diff options
author | Sathya Perla <sathyap@serverengines.com> | 2009-06-30 21:06:07 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-07-03 23:09:45 -0400 |
commit | c001c213b109c8baeeb6d012b422bf059b18368f (patch) | |
tree | eb9c551c9f84fe1a7fbaa8d15866200aa76e98f1 | |
parent | 7d3cabbcc86f7f69c47cb20c23ee84350ae6cfbb (diff) |
be2net: fix spurious interrupt handling in intx mode
Occasionally we may see an interrupt without an event in the eq.
In intx, we currently see the event queue and return IRQ_NONE causing
a the irq to be disabled ("no one cared".) Instead, read the CEV_ISR
reg to check the existence of the interrupt.
Signed-off-by: Sathya Perla <sathyap@serverengines.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/benet/be_hw.h | 4 | ||||
-rw-r--r-- | drivers/net/benet/be_main.c | 16 |
2 files changed, 13 insertions, 7 deletions
diff --git a/drivers/net/benet/be_hw.h b/drivers/net/benet/be_hw.h index b02e805c1db3..29c33c709c6d 100644 --- a/drivers/net/benet/be_hw.h +++ b/drivers/net/benet/be_hw.h | |||
@@ -55,6 +55,10 @@ | |||
55 | #define MEMBAR_CTRL_INT_CTRL_PFUNC_MASK 0x7 /* bits 26 - 28 */ | 55 | #define MEMBAR_CTRL_INT_CTRL_PFUNC_MASK 0x7 /* bits 26 - 28 */ |
56 | #define MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT 26 | 56 | #define MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT 26 |
57 | 57 | ||
58 | /********* ISR0 Register offset **********/ | ||
59 | #define CEV_ISR0_OFFSET 0xC18 | ||
60 | #define CEV_ISR_SIZE 4 | ||
61 | |||
58 | /********* Event Q door bell *************/ | 62 | /********* Event Q door bell *************/ |
59 | #define DB_EQ_OFFSET DB_CQ_OFFSET | 63 | #define DB_EQ_OFFSET DB_CQ_OFFSET |
60 | #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ | 64 | #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ |
diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c index 308eb09ca56b..c43f6a119295 100644 --- a/drivers/net/benet/be_main.c +++ b/drivers/net/benet/be_main.c | |||
@@ -1274,15 +1274,17 @@ static irqreturn_t be_intx(int irq, void *dev) | |||
1274 | { | 1274 | { |
1275 | struct be_adapter *adapter = dev; | 1275 | struct be_adapter *adapter = dev; |
1276 | struct be_ctrl_info *ctrl = &adapter->ctrl; | 1276 | struct be_ctrl_info *ctrl = &adapter->ctrl; |
1277 | int rx, tx; | 1277 | int isr; |
1278 | 1278 | ||
1279 | tx = event_handle(ctrl, &adapter->tx_eq); | 1279 | isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET + |
1280 | rx = event_handle(ctrl, &adapter->rx_eq); | 1280 | ctrl->pci_func * CEV_ISR_SIZE); |
1281 | if (!isr) | ||
1282 | return IRQ_NONE; | ||
1281 | 1283 | ||
1282 | if (rx || tx) | 1284 | event_handle(ctrl, &adapter->tx_eq); |
1283 | return IRQ_HANDLED; | 1285 | event_handle(ctrl, &adapter->rx_eq); |
1284 | else | 1286 | |
1285 | return IRQ_NONE; | 1287 | return IRQ_HANDLED; |
1286 | } | 1288 | } |
1287 | 1289 | ||
1288 | static irqreturn_t be_msix_rx(int irq, void *dev) | 1290 | static irqreturn_t be_msix_rx(int irq, void *dev) |