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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2013-03-28 07:48:26 -0400
committerDavid S. Miller <davem@davemloft.net>2013-03-29 15:31:30 -0400
commitc0013f6f8bbcb7605d591431444780d636dbe223 (patch)
tree20ca5394858a33f61dbbd28129a4af703920030e
parent91f3e7b17412d42e933949a9c297072b13a04d41 (diff)
sh_eth: move data from header file to driver
The driver's header file contains initialized register offset tables which (as any data definitions), of course, have no business being there. Move them to the driver's body, somewhat beautifying the initializers, while at it... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/renesas/sh_eth.c218
-rw-r--r--drivers/net/ethernet/renesas/sh_eth.h219
2 files changed, 218 insertions, 219 deletions
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index 3703a29022b6..13abe917cbdf 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -49,6 +49,224 @@
49 NETIF_MSG_RX_ERR| \ 49 NETIF_MSG_RX_ERR| \
50 NETIF_MSG_TX_ERR) 50 NETIF_MSG_TX_ERR)
51 51
52static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
53 [EDSR] = 0x0000,
54 [EDMR] = 0x0400,
55 [EDTRR] = 0x0408,
56 [EDRRR] = 0x0410,
57 [EESR] = 0x0428,
58 [EESIPR] = 0x0430,
59 [TDLAR] = 0x0010,
60 [TDFAR] = 0x0014,
61 [TDFXR] = 0x0018,
62 [TDFFR] = 0x001c,
63 [RDLAR] = 0x0030,
64 [RDFAR] = 0x0034,
65 [RDFXR] = 0x0038,
66 [RDFFR] = 0x003c,
67 [TRSCER] = 0x0438,
68 [RMFCR] = 0x0440,
69 [TFTR] = 0x0448,
70 [FDR] = 0x0450,
71 [RMCR] = 0x0458,
72 [RPADIR] = 0x0460,
73 [FCFTR] = 0x0468,
74 [CSMR] = 0x04E4,
75
76 [ECMR] = 0x0500,
77 [ECSR] = 0x0510,
78 [ECSIPR] = 0x0518,
79 [PIR] = 0x0520,
80 [PSR] = 0x0528,
81 [PIPR] = 0x052c,
82 [RFLR] = 0x0508,
83 [APR] = 0x0554,
84 [MPR] = 0x0558,
85 [PFTCR] = 0x055c,
86 [PFRCR] = 0x0560,
87 [TPAUSER] = 0x0564,
88 [GECMR] = 0x05b0,
89 [BCULR] = 0x05b4,
90 [MAHR] = 0x05c0,
91 [MALR] = 0x05c8,
92 [TROCR] = 0x0700,
93 [CDCR] = 0x0708,
94 [LCCR] = 0x0710,
95 [CEFCR] = 0x0740,
96 [FRECR] = 0x0748,
97 [TSFRCR] = 0x0750,
98 [TLFRCR] = 0x0758,
99 [RFCR] = 0x0760,
100 [CERCR] = 0x0768,
101 [CEECR] = 0x0770,
102 [MAFCR] = 0x0778,
103 [RMII_MII] = 0x0790,
104
105 [ARSTR] = 0x0000,
106 [TSU_CTRST] = 0x0004,
107 [TSU_FWEN0] = 0x0010,
108 [TSU_FWEN1] = 0x0014,
109 [TSU_FCM] = 0x0018,
110 [TSU_BSYSL0] = 0x0020,
111 [TSU_BSYSL1] = 0x0024,
112 [TSU_PRISL0] = 0x0028,
113 [TSU_PRISL1] = 0x002c,
114 [TSU_FWSL0] = 0x0030,
115 [TSU_FWSL1] = 0x0034,
116 [TSU_FWSLC] = 0x0038,
117 [TSU_QTAG0] = 0x0040,
118 [TSU_QTAG1] = 0x0044,
119 [TSU_FWSR] = 0x0050,
120 [TSU_FWINMK] = 0x0054,
121 [TSU_ADQT0] = 0x0048,
122 [TSU_ADQT1] = 0x004c,
123 [TSU_VTAG0] = 0x0058,
124 [TSU_VTAG1] = 0x005c,
125 [TSU_ADSBSY] = 0x0060,
126 [TSU_TEN] = 0x0064,
127 [TSU_POST1] = 0x0070,
128 [TSU_POST2] = 0x0074,
129 [TSU_POST3] = 0x0078,
130 [TSU_POST4] = 0x007c,
131 [TSU_ADRH0] = 0x0100,
132 [TSU_ADRL0] = 0x0104,
133 [TSU_ADRH31] = 0x01f8,
134 [TSU_ADRL31] = 0x01fc,
135
136 [TXNLCR0] = 0x0080,
137 [TXALCR0] = 0x0084,
138 [RXNLCR0] = 0x0088,
139 [RXALCR0] = 0x008c,
140 [FWNLCR0] = 0x0090,
141 [FWALCR0] = 0x0094,
142 [TXNLCR1] = 0x00a0,
143 [TXALCR1] = 0x00a0,
144 [RXNLCR1] = 0x00a8,
145 [RXALCR1] = 0x00ac,
146 [FWNLCR1] = 0x00b0,
147 [FWALCR1] = 0x00b4,
148};
149
150static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
151 [ECMR] = 0x0100,
152 [RFLR] = 0x0108,
153 [ECSR] = 0x0110,
154 [ECSIPR] = 0x0118,
155 [PIR] = 0x0120,
156 [PSR] = 0x0128,
157 [RDMLR] = 0x0140,
158 [IPGR] = 0x0150,
159 [APR] = 0x0154,
160 [MPR] = 0x0158,
161 [TPAUSER] = 0x0164,
162 [RFCF] = 0x0160,
163 [TPAUSECR] = 0x0168,
164 [BCFRR] = 0x016c,
165 [MAHR] = 0x01c0,
166 [MALR] = 0x01c8,
167 [TROCR] = 0x01d0,
168 [CDCR] = 0x01d4,
169 [LCCR] = 0x01d8,
170 [CNDCR] = 0x01dc,
171 [CEFCR] = 0x01e4,
172 [FRECR] = 0x01e8,
173 [TSFRCR] = 0x01ec,
174 [TLFRCR] = 0x01f0,
175 [RFCR] = 0x01f4,
176 [MAFCR] = 0x01f8,
177 [RTRATE] = 0x01fc,
178
179 [EDMR] = 0x0000,
180 [EDTRR] = 0x0008,
181 [EDRRR] = 0x0010,
182 [TDLAR] = 0x0018,
183 [RDLAR] = 0x0020,
184 [EESR] = 0x0028,
185 [EESIPR] = 0x0030,
186 [TRSCER] = 0x0038,
187 [RMFCR] = 0x0040,
188 [TFTR] = 0x0048,
189 [FDR] = 0x0050,
190 [RMCR] = 0x0058,
191 [TFUCR] = 0x0064,
192 [RFOCR] = 0x0068,
193 [FCFTR] = 0x0070,
194 [RPADIR] = 0x0078,
195 [TRIMD] = 0x007c,
196 [RBWAR] = 0x00c8,
197 [RDFAR] = 0x00cc,
198 [TBRAR] = 0x00d4,
199 [TDFAR] = 0x00d8,
200};
201
202static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
203 [ECMR] = 0x0160,
204 [ECSR] = 0x0164,
205 [ECSIPR] = 0x0168,
206 [PIR] = 0x016c,
207 [MAHR] = 0x0170,
208 [MALR] = 0x0174,
209 [RFLR] = 0x0178,
210 [PSR] = 0x017c,
211 [TROCR] = 0x0180,
212 [CDCR] = 0x0184,
213 [LCCR] = 0x0188,
214 [CNDCR] = 0x018c,
215 [CEFCR] = 0x0194,
216 [FRECR] = 0x0198,
217 [TSFRCR] = 0x019c,
218 [TLFRCR] = 0x01a0,
219 [RFCR] = 0x01a4,
220 [MAFCR] = 0x01a8,
221 [IPGR] = 0x01b4,
222 [APR] = 0x01b8,
223 [MPR] = 0x01bc,
224 [TPAUSER] = 0x01c4,
225 [BCFR] = 0x01cc,
226
227 [ARSTR] = 0x0000,
228 [TSU_CTRST] = 0x0004,
229 [TSU_FWEN0] = 0x0010,
230 [TSU_FWEN1] = 0x0014,
231 [TSU_FCM] = 0x0018,
232 [TSU_BSYSL0] = 0x0020,
233 [TSU_BSYSL1] = 0x0024,
234 [TSU_PRISL0] = 0x0028,
235 [TSU_PRISL1] = 0x002c,
236 [TSU_FWSL0] = 0x0030,
237 [TSU_FWSL1] = 0x0034,
238 [TSU_FWSLC] = 0x0038,
239 [TSU_QTAGM0] = 0x0040,
240 [TSU_QTAGM1] = 0x0044,
241 [TSU_ADQT0] = 0x0048,
242 [TSU_ADQT1] = 0x004c,
243 [TSU_FWSR] = 0x0050,
244 [TSU_FWINMK] = 0x0054,
245 [TSU_ADSBSY] = 0x0060,
246 [TSU_TEN] = 0x0064,
247 [TSU_POST1] = 0x0070,
248 [TSU_POST2] = 0x0074,
249 [TSU_POST3] = 0x0078,
250 [TSU_POST4] = 0x007c,
251
252 [TXNLCR0] = 0x0080,
253 [TXALCR0] = 0x0084,
254 [RXNLCR0] = 0x0088,
255 [RXALCR0] = 0x008c,
256 [FWNLCR0] = 0x0090,
257 [FWALCR0] = 0x0094,
258 [TXNLCR1] = 0x00a0,
259 [TXALCR1] = 0x00a0,
260 [RXNLCR1] = 0x00a8,
261 [RXALCR1] = 0x00ac,
262 [FWNLCR1] = 0x00b0,
263 [FWALCR1] = 0x00b4,
264
265 [TSU_ADRH0] = 0x0100,
266 [TSU_ADRL0] = 0x0104,
267 [TSU_ADRL31] = 0x01fc,
268};
269
52#if defined(CONFIG_CPU_SUBTYPE_SH7734) || \ 270#if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
53 defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 271 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
54 defined(CONFIG_ARCH_R8A7740) 272 defined(CONFIG_ARCH_R8A7740)
diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
index bae84fd2e73a..e5292973900b 100644
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
@@ -156,225 +156,6 @@ enum {
156 SH_ETH_MAX_REGISTER_OFFSET, 156 SH_ETH_MAX_REGISTER_OFFSET,
157}; 157};
158 158
159static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [ECSR] = 0x0510,
185 [ECSIPR] = 0x0518,
186 [PIR] = 0x0520,
187 [PSR] = 0x0528,
188 [PIPR] = 0x052c,
189 [RFLR] = 0x0508,
190 [APR] = 0x0554,
191 [MPR] = 0x0558,
192 [PFTCR] = 0x055c,
193 [PFRCR] = 0x0560,
194 [TPAUSER] = 0x0564,
195 [GECMR] = 0x05b0,
196 [BCULR] = 0x05b4,
197 [MAHR] = 0x05c0,
198 [MALR] = 0x05c8,
199 [TROCR] = 0x0700,
200 [CDCR] = 0x0708,
201 [LCCR] = 0x0710,
202 [CEFCR] = 0x0740,
203 [FRECR] = 0x0748,
204 [TSFRCR] = 0x0750,
205 [TLFRCR] = 0x0758,
206 [RFCR] = 0x0760,
207 [CERCR] = 0x0768,
208 [CEECR] = 0x0770,
209 [MAFCR] = 0x0778,
210 [RMII_MII] = 0x0790,
211
212 [ARSTR] = 0x0000,
213 [TSU_CTRST] = 0x0004,
214 [TSU_FWEN0] = 0x0010,
215 [TSU_FWEN1] = 0x0014,
216 [TSU_FCM] = 0x0018,
217 [TSU_BSYSL0] = 0x0020,
218 [TSU_BSYSL1] = 0x0024,
219 [TSU_PRISL0] = 0x0028,
220 [TSU_PRISL1] = 0x002c,
221 [TSU_FWSL0] = 0x0030,
222 [TSU_FWSL1] = 0x0034,
223 [TSU_FWSLC] = 0x0038,
224 [TSU_QTAG0] = 0x0040,
225 [TSU_QTAG1] = 0x0044,
226 [TSU_FWSR] = 0x0050,
227 [TSU_FWINMK] = 0x0054,
228 [TSU_ADQT0] = 0x0048,
229 [TSU_ADQT1] = 0x004c,
230 [TSU_VTAG0] = 0x0058,
231 [TSU_VTAG1] = 0x005c,
232 [TSU_ADSBSY] = 0x0060,
233 [TSU_TEN] = 0x0064,
234 [TSU_POST1] = 0x0070,
235 [TSU_POST2] = 0x0074,
236 [TSU_POST3] = 0x0078,
237 [TSU_POST4] = 0x007c,
238 [TSU_ADRH0] = 0x0100,
239 [TSU_ADRL0] = 0x0104,
240 [TSU_ADRH31] = 0x01f8,
241 [TSU_ADRL31] = 0x01fc,
242
243 [TXNLCR0] = 0x0080,
244 [TXALCR0] = 0x0084,
245 [RXNLCR0] = 0x0088,
246 [RXALCR0] = 0x008c,
247 [FWNLCR0] = 0x0090,
248 [FWALCR0] = 0x0094,
249 [TXNLCR1] = 0x00a0,
250 [TXALCR1] = 0x00a0,
251 [RXNLCR1] = 0x00a8,
252 [RXALCR1] = 0x00ac,
253 [FWNLCR1] = 0x00b0,
254 [FWALCR1] = 0x00b4,
255};
256
257static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
258 [ECMR] = 0x0100,
259 [RFLR] = 0x0108,
260 [ECSR] = 0x0110,
261 [ECSIPR] = 0x0118,
262 [PIR] = 0x0120,
263 [PSR] = 0x0128,
264 [RDMLR] = 0x0140,
265 [IPGR] = 0x0150,
266 [APR] = 0x0154,
267 [MPR] = 0x0158,
268 [TPAUSER] = 0x0164,
269 [RFCF] = 0x0160,
270 [TPAUSECR] = 0x0168,
271 [BCFRR] = 0x016c,
272 [MAHR] = 0x01c0,
273 [MALR] = 0x01c8,
274 [TROCR] = 0x01d0,
275 [CDCR] = 0x01d4,
276 [LCCR] = 0x01d8,
277 [CNDCR] = 0x01dc,
278 [CEFCR] = 0x01e4,
279 [FRECR] = 0x01e8,
280 [TSFRCR] = 0x01ec,
281 [TLFRCR] = 0x01f0,
282 [RFCR] = 0x01f4,
283 [MAFCR] = 0x01f8,
284 [RTRATE] = 0x01fc,
285
286 [EDMR] = 0x0000,
287 [EDTRR] = 0x0008,
288 [EDRRR] = 0x0010,
289 [TDLAR] = 0x0018,
290 [RDLAR] = 0x0020,
291 [EESR] = 0x0028,
292 [EESIPR] = 0x0030,
293 [TRSCER] = 0x0038,
294 [RMFCR] = 0x0040,
295 [TFTR] = 0x0048,
296 [FDR] = 0x0050,
297 [RMCR] = 0x0058,
298 [TFUCR] = 0x0064,
299 [RFOCR] = 0x0068,
300 [FCFTR] = 0x0070,
301 [RPADIR] = 0x0078,
302 [TRIMD] = 0x007c,
303 [RBWAR] = 0x00c8,
304 [RDFAR] = 0x00cc,
305 [TBRAR] = 0x00d4,
306 [TDFAR] = 0x00d8,
307};
308
309static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
310 [ECMR] = 0x0160,
311 [ECSR] = 0x0164,
312 [ECSIPR] = 0x0168,
313 [PIR] = 0x016c,
314 [MAHR] = 0x0170,
315 [MALR] = 0x0174,
316 [RFLR] = 0x0178,
317 [PSR] = 0x017c,
318 [TROCR] = 0x0180,
319 [CDCR] = 0x0184,
320 [LCCR] = 0x0188,
321 [CNDCR] = 0x018c,
322 [CEFCR] = 0x0194,
323 [FRECR] = 0x0198,
324 [TSFRCR] = 0x019c,
325 [TLFRCR] = 0x01a0,
326 [RFCR] = 0x01a4,
327 [MAFCR] = 0x01a8,
328 [IPGR] = 0x01b4,
329 [APR] = 0x01b8,
330 [MPR] = 0x01bc,
331 [TPAUSER] = 0x01c4,
332 [BCFR] = 0x01cc,
333
334 [ARSTR] = 0x0000,
335 [TSU_CTRST] = 0x0004,
336 [TSU_FWEN0] = 0x0010,
337 [TSU_FWEN1] = 0x0014,
338 [TSU_FCM] = 0x0018,
339 [TSU_BSYSL0] = 0x0020,
340 [TSU_BSYSL1] = 0x0024,
341 [TSU_PRISL0] = 0x0028,
342 [TSU_PRISL1] = 0x002c,
343 [TSU_FWSL0] = 0x0030,
344 [TSU_FWSL1] = 0x0034,
345 [TSU_FWSLC] = 0x0038,
346 [TSU_QTAGM0] = 0x0040,
347 [TSU_QTAGM1] = 0x0044,
348 [TSU_ADQT0] = 0x0048,
349 [TSU_ADQT1] = 0x004c,
350 [TSU_FWSR] = 0x0050,
351 [TSU_FWINMK] = 0x0054,
352 [TSU_ADSBSY] = 0x0060,
353 [TSU_TEN] = 0x0064,
354 [TSU_POST1] = 0x0070,
355 [TSU_POST2] = 0x0074,
356 [TSU_POST3] = 0x0078,
357 [TSU_POST4] = 0x007c,
358
359 [TXNLCR0] = 0x0080,
360 [TXALCR0] = 0x0084,
361 [RXNLCR0] = 0x0088,
362 [RXALCR0] = 0x008c,
363 [FWNLCR0] = 0x0090,
364 [FWALCR0] = 0x0094,
365 [TXNLCR1] = 0x00a0,
366 [TXALCR1] = 0x00a0,
367 [RXNLCR1] = 0x00a8,
368 [RXALCR1] = 0x00ac,
369 [FWNLCR1] = 0x00b0,
370 [FWALCR1] = 0x00b4,
371
372 [TSU_ADRH0] = 0x0100,
373 [TSU_ADRL0] = 0x0104,
374 [TSU_ADRL31] = 0x01fc,
375
376};
377
378/* Driver's parameters */ 159/* Driver's parameters */
379#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 160#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380#define SH4_SKB_RX_ALIGN 32 161#define SH4_SKB_RX_ALIGN 32
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