ARM: vexpress: Add Device Tree for V2P-CA5s core tile

This patch adds Device Tree file for the CoreTile Express A5x2 (V2P-CA5s). Signed-off-by: Pawel Moll <pawel.moll@arm.com>
author: Pawel Moll <pawel.moll@arm.com> 2011-12-09 13:41:27 -0500
committer: Pawel Moll <pawel.moll@arm.com> 2012-02-24 04:18:20 -0500
commit: bfd5200c16637552979e5cc082eb29d759d894bf (patch)
tree: ae833031c8d598414b2b73da6283b711cba1444b
parent: 6a3719562b69ffdfc36e829e19b35fda6ab19ca6 (diff)
2 files changed, 164 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 000000000000..6905e66d4748
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,162 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+/dts-v1/;
+/ {
+        model = "V2P-CA5s";
+        arm,hbi = <0x225>;
+        compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        chosen { };
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+                i2c0 = &v2m_i2c_dvi;
+                i2c1 = &v2m_i2c_pcie;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a5";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a5";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>;
+        };
+        hdlcd@2a110000 {
+                compatible = "arm,hdlcd";
+                reg = <0x2a110000 0x1000>;
+                interrupts = <0 85 4>;
+        };
+        memory-controller@2a150000 {
+                compatible = "arm,pl341", "arm,primecell";
+                reg = <0x2a150000 0x1000>;
+        };
+        memory-controller@2a190000 {
+                compatible = "arm,pl354", "arm,primecell";
+                reg = <0x2a190000 0x1000>;
+                interrupts = <0 86 4>,
+                             <0 87 4>;
+        };
+        scu@2c000000 {
+                compatible = "arm,cortex-a5-scu";
+                reg = <0x2c000000 0x58>;
+        };
+        timer@2c000600 {
+                compatible = "arm,cortex-a5-twd-timer";
+                reg = <0x2c000600 0x38>;
+                interrupts = <1 2 0x304>,
+                             <1 3 0x304>;
+        };
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x2c001000 0x1000>,
+                      <0x2c000100 0x100>;
+        };
+        L2: cache-controller@2c0f0000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x2c0f0000 0x1000>;
+                interrupts = <0 84 4>;
+                cache-level = <2>;
+        };
+        pmu {
+                compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
+                interrupts = <0 68 4>,
+                             <0 69 4>;
+        };
+        motherboard {
+                ranges = <0 0 0x08000000 0x04000000>,
+                         <1 0 0x14000000 0x04000000>,
+                         <2 0 0x18000000 0x04000000>,
+                         <3 0 0x1c000000 0x04000000>,
+                         <4 0 0x0c000000 0x04000000>,
+                         <5 0 0x10000000 0x04000000>;
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+        };
+};
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index c6dd8918b9ed..5e2177eb3fe0 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -3,3 +3,5 @@
   zreladdr-y   += 0x60008000
 params_phys-y   := 0x60000100
 initrd_phys-y   := 0x60800000
+dtb-$(CONFIG_ARCH_VEXPRESS_DT)  += vexpress-v2p-ca5s.dtb
author	Pawel Moll <pawel.moll@arm.com>	2011-12-09 13:41:27 -0500
committer	Pawel Moll <pawel.moll@arm.com>	2012-02-24 04:18:20 -0500
commit	bfd5200c16637552979e5cc082eb29d759d894bf (patch)
tree	ae833031c8d598414b2b73da6283b711cba1444b
parent	6a3719562b69ffdfc36e829e19b35fda6ab19ca6 (diff)

diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts new file mode 100644 index 000000000000..6905e66d4748 --- /dev/null +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,162 @@
		1	/*
		2	* ARM Ltd. Versatile Express
		3	*
		4	* CoreTile Express A5x2
		5	* Cortex-A5 MPCore (V2P-CA5s)
		6	*
		7	* HBI-0225B
		8	*/
		9
		10	/dts-v1/;
		11
		12	/ {
		13	model = "V2P-CA5s";
		14	arm,hbi = <0x225>;
		15	compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
		16	interrupt-parent = <&gic>;
		17	#address-cells = <1>;
		18	#size-cells = <1>;
		19
		20	chosen { };
		21
		22	aliases {
		23	serial0 = &v2m_serial0;
		24	serial1 = &v2m_serial1;
		25	serial2 = &v2m_serial2;
		26	serial3 = &v2m_serial3;
		27	i2c0 = &v2m_i2c_dvi;
		28	i2c1 = &v2m_i2c_pcie;
		29	};
		30
		31	cpus {
		32	#address-cells = <1>;
		33	#size-cells = <0>;
		34
		35	cpu@0 {
		36	device_type = "cpu";
		37	compatible = "arm,cortex-a5";
		38	reg = <0>;
		39	next-level-cache = <&L2>;
		40	};
		41
		42	cpu@1 {
		43	device_type = "cpu";
		44	compatible = "arm,cortex-a5";
		45	reg = <1>;
		46	next-level-cache = <&L2>;
		47	};
		48	};
		49
		50	memory@80000000 {
		51	device_type = "memory";
		52	reg = <0x80000000 0x40000000>;
		53	};
		54
		55	hdlcd@2a110000 {
		56	compatible = "arm,hdlcd";
		57	reg = <0x2a110000 0x1000>;
		58	interrupts = <0 85 4>;
		59	};
		60
		61	memory-controller@2a150000 {
		62	compatible = "arm,pl341", "arm,primecell";
		63	reg = <0x2a150000 0x1000>;
		64	};
		65
		66	memory-controller@2a190000 {
		67	compatible = "arm,pl354", "arm,primecell";
		68	reg = <0x2a190000 0x1000>;
		69	interrupts = <0 86 4>,
		70	<0 87 4>;
		71	};
		72
		73	scu@2c000000 {
		74	compatible = "arm,cortex-a5-scu";
		75	reg = <0x2c000000 0x58>;
		76	};
		77
		78	timer@2c000600 {
		79	compatible = "arm,cortex-a5-twd-timer";
		80	reg = <0x2c000600 0x38>;
		81	interrupts = <1 2 0x304>,
		82	<1 3 0x304>;
		83	};
		84
		85	gic: interrupt-controller@2c001000 {
		86	compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic";
		87	#interrupt-cells = <3>;
		88	#address-cells = <0>;
		89	interrupt-controller;
		90	reg = <0x2c001000 0x1000>,
		91	<0x2c000100 0x100>;
		92	};
		93
		94	L2: cache-controller@2c0f0000 {
		95	compatible = "arm,pl310-cache";
		96	reg = <0x2c0f0000 0x1000>;
		97	interrupts = <0 84 4>;
		98	cache-level = <2>;
		99	};
		100
		101	pmu {
		102	compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
		103	interrupts = <0 68 4>,
		104	<0 69 4>;
		105	};
		106
		107	motherboard {
		108	ranges = <0 0 0x08000000 0x04000000>,
		109	<1 0 0x14000000 0x04000000>,
		110	<2 0 0x18000000 0x04000000>,
		111	<3 0 0x1c000000 0x04000000>,
		112	<4 0 0x0c000000 0x04000000>,
		113	<5 0 0x10000000 0x04000000>;
		114
		115	interrupt-map-mask = <0 0 63>;
		116	interrupt-map = <0 0 0 &gic 0 0 4>,
		117	<0 0 1 &gic 0 1 4>,
		118	<0 0 2 &gic 0 2 4>,
		119	<0 0 3 &gic 0 3 4>,
		120	<0 0 4 &gic 0 4 4>,
		121	<0 0 5 &gic 0 5 4>,
		122	<0 0 6 &gic 0 6 4>,
		123	<0 0 7 &gic 0 7 4>,
		124	<0 0 8 &gic 0 8 4>,
		125	<0 0 9 &gic 0 9 4>,
		126	<0 0 10 &gic 0 10 4>,
		127	<0 0 11 &gic 0 11 4>,
		128	<0 0 12 &gic 0 12 4>,
		129	<0 0 13 &gic 0 13 4>,
		130	<0 0 14 &gic 0 14 4>,
		131	<0 0 15 &gic 0 15 4>,
		132	<0 0 16 &gic 0 16 4>,
		133	<0 0 17 &gic 0 17 4>,
		134	<0 0 18 &gic 0 18 4>,
		135	<0 0 19 &gic 0 19 4>,
		136	<0 0 20 &gic 0 20 4>,
		137	<0 0 21 &gic 0 21 4>,
		138	<0 0 22 &gic 0 22 4>,
		139	<0 0 23 &gic 0 23 4>,
		140	<0 0 24 &gic 0 24 4>,
		141	<0 0 25 &gic 0 25 4>,
		142	<0 0 26 &gic 0 26 4>,
		143	<0 0 27 &gic 0 27 4>,
		144	<0 0 28 &gic 0 28 4>,
		145	<0 0 29 &gic 0 29 4>,
		146	<0 0 30 &gic 0 30 4>,
		147	<0 0 31 &gic 0 31 4>,
		148	<0 0 32 &gic 0 32 4>,
		149	<0 0 33 &gic 0 33 4>,
		150	<0 0 34 &gic 0 34 4>,
		151	<0 0 35 &gic 0 35 4>,
		152	<0 0 36 &gic 0 36 4>,
		153	<0 0 37 &gic 0 37 4>,
		154	<0 0 38 &gic 0 38 4>,
		155	<0 0 39 &gic 0 39 4>,
		156	<0 0 40 &gic 0 40 4>,
		157	<0 0 41 &gic 0 41 4>,
		158	<0 0 42 &gic 0 42 4>;
		159	};
		160	};
		161
		162	/include/ "vexpress-v2m-rs1.dtsi"


diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot index c6dd8918b9ed..5e2177eb3fe0 100644 --- a/arch/arm/mach-vexpress/Makefile.boot +++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -3,3 +3,5 @@
3	zreladdr-y += 0x60008000	3	zreladdr-y += 0x60008000
4	params_phys-y := 0x60000100	4	params_phys-y := 0x60000100
5	initrd_phys-y := 0x60800000	5	initrd_phys-y := 0x60800000
		6
		7	dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb