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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-02-06 03:55:58 -0500
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-02-18 10:53:37 -0500
commitbf6534a180d6d596521b0bfa6de29da5e18314a6 (patch)
treeb242fff5bb0993c718fe6a6daa21935d003efb91
parent7902763e4a4d04a96406447f935a8f676e73e0ce (diff)
ARM: sunxi: dt: Convert to the new clock compatibles
Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi60
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi48
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi48
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi10
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi54
5 files changed, 110 insertions, 110 deletions
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index b268f68cf8fa..5b18f7d94853 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -60,7 +60,7 @@
60 60
61 osc24M: clk@01c20050 { 61 osc24M: clk@01c20050 {
62 #clock-cells = <0>; 62 #clock-cells = <0>;
63 compatible = "allwinner,sun4i-osc-clk"; 63 compatible = "allwinner,sun4i-a10-osc-clk";
64 reg = <0x01c20050 0x4>; 64 reg = <0x01c20050 0x4>;
65 clock-frequency = <24000000>; 65 clock-frequency = <24000000>;
66 clock-output-names = "osc24M"; 66 clock-output-names = "osc24M";
@@ -75,7 +75,7 @@
75 75
76 pll1: clk@01c20000 { 76 pll1: clk@01c20000 {
77 #clock-cells = <0>; 77 #clock-cells = <0>;
78 compatible = "allwinner,sun4i-pll1-clk"; 78 compatible = "allwinner,sun4i-a10-pll1-clk";
79 reg = <0x01c20000 0x4>; 79 reg = <0x01c20000 0x4>;
80 clocks = <&osc24M>; 80 clocks = <&osc24M>;
81 clock-output-names = "pll1"; 81 clock-output-names = "pll1";
@@ -83,7 +83,7 @@
83 83
84 pll4: clk@01c20018 { 84 pll4: clk@01c20018 {
85 #clock-cells = <0>; 85 #clock-cells = <0>;
86 compatible = "allwinner,sun4i-pll1-clk"; 86 compatible = "allwinner,sun4i-a10-pll1-clk";
87 reg = <0x01c20018 0x4>; 87 reg = <0x01c20018 0x4>;
88 clocks = <&osc24M>; 88 clocks = <&osc24M>;
89 clock-output-names = "pll4"; 89 clock-output-names = "pll4";
@@ -91,7 +91,7 @@
91 91
92 pll5: clk@01c20020 { 92 pll5: clk@01c20020 {
93 #clock-cells = <1>; 93 #clock-cells = <1>;
94 compatible = "allwinner,sun4i-pll5-clk"; 94 compatible = "allwinner,sun4i-a10-pll5-clk";
95 reg = <0x01c20020 0x4>; 95 reg = <0x01c20020 0x4>;
96 clocks = <&osc24M>; 96 clocks = <&osc24M>;
97 clock-output-names = "pll5_ddr", "pll5_other"; 97 clock-output-names = "pll5_ddr", "pll5_other";
@@ -99,7 +99,7 @@
99 99
100 pll6: clk@01c20028 { 100 pll6: clk@01c20028 {
101 #clock-cells = <1>; 101 #clock-cells = <1>;
102 compatible = "allwinner,sun4i-pll6-clk"; 102 compatible = "allwinner,sun4i-a10-pll6-clk";
103 reg = <0x01c20028 0x4>; 103 reg = <0x01c20028 0x4>;
104 clocks = <&osc24M>; 104 clocks = <&osc24M>;
105 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 105 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -108,7 +108,7 @@
108 /* dummy is 200M */ 108 /* dummy is 200M */
109 cpu: cpu@01c20054 { 109 cpu: cpu@01c20054 {
110 #clock-cells = <0>; 110 #clock-cells = <0>;
111 compatible = "allwinner,sun4i-cpu-clk"; 111 compatible = "allwinner,sun4i-a10-cpu-clk";
112 reg = <0x01c20054 0x4>; 112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 113 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
114 clock-output-names = "cpu"; 114 clock-output-names = "cpu";
@@ -116,7 +116,7 @@
116 116
117 axi: axi@01c20054 { 117 axi: axi@01c20054 {
118 #clock-cells = <0>; 118 #clock-cells = <0>;
119 compatible = "allwinner,sun4i-axi-clk"; 119 compatible = "allwinner,sun4i-a10-axi-clk";
120 reg = <0x01c20054 0x4>; 120 reg = <0x01c20054 0x4>;
121 clocks = <&cpu>; 121 clocks = <&cpu>;
122 clock-output-names = "axi"; 122 clock-output-names = "axi";
@@ -124,7 +124,7 @@
124 124
125 axi_gates: clk@01c2005c { 125 axi_gates: clk@01c2005c {
126 #clock-cells = <1>; 126 #clock-cells = <1>;
127 compatible = "allwinner,sun4i-axi-gates-clk"; 127 compatible = "allwinner,sun4i-a10-axi-gates-clk";
128 reg = <0x01c2005c 0x4>; 128 reg = <0x01c2005c 0x4>;
129 clocks = <&axi>; 129 clocks = <&axi>;
130 clock-output-names = "axi_dram"; 130 clock-output-names = "axi_dram";
@@ -132,7 +132,7 @@
132 132
133 ahb: ahb@01c20054 { 133 ahb: ahb@01c20054 {
134 #clock-cells = <0>; 134 #clock-cells = <0>;
135 compatible = "allwinner,sun4i-ahb-clk"; 135 compatible = "allwinner,sun4i-a10-ahb-clk";
136 reg = <0x01c20054 0x4>; 136 reg = <0x01c20054 0x4>;
137 clocks = <&axi>; 137 clocks = <&axi>;
138 clock-output-names = "ahb"; 138 clock-output-names = "ahb";
@@ -140,7 +140,7 @@
140 140
141 ahb_gates: clk@01c20060 { 141 ahb_gates: clk@01c20060 {
142 #clock-cells = <1>; 142 #clock-cells = <1>;
143 compatible = "allwinner,sun4i-ahb-gates-clk"; 143 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
144 reg = <0x01c20060 0x8>; 144 reg = <0x01c20060 0x8>;
145 clocks = <&ahb>; 145 clocks = <&ahb>;
146 clock-output-names = "ahb_usb0", "ahb_ehci0", 146 clock-output-names = "ahb_usb0", "ahb_ehci0",
@@ -158,7 +158,7 @@
158 158
159 apb0: apb0@01c20054 { 159 apb0: apb0@01c20054 {
160 #clock-cells = <0>; 160 #clock-cells = <0>;
161 compatible = "allwinner,sun4i-apb0-clk"; 161 compatible = "allwinner,sun4i-a10-apb0-clk";
162 reg = <0x01c20054 0x4>; 162 reg = <0x01c20054 0x4>;
163 clocks = <&ahb>; 163 clocks = <&ahb>;
164 clock-output-names = "apb0"; 164 clock-output-names = "apb0";
@@ -166,7 +166,7 @@
166 166
167 apb0_gates: clk@01c20068 { 167 apb0_gates: clk@01c20068 {
168 #clock-cells = <1>; 168 #clock-cells = <1>;
169 compatible = "allwinner,sun4i-apb0-gates-clk"; 169 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
170 reg = <0x01c20068 0x4>; 170 reg = <0x01c20068 0x4>;
171 clocks = <&apb0>; 171 clocks = <&apb0>;
172 clock-output-names = "apb0_codec", "apb0_spdif", 172 clock-output-names = "apb0_codec", "apb0_spdif",
@@ -176,7 +176,7 @@
176 176
177 apb1_mux: apb1_mux@01c20058 { 177 apb1_mux: apb1_mux@01c20058 {
178 #clock-cells = <0>; 178 #clock-cells = <0>;
179 compatible = "allwinner,sun4i-apb1-mux-clk"; 179 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
180 reg = <0x01c20058 0x4>; 180 reg = <0x01c20058 0x4>;
181 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 181 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
182 clock-output-names = "apb1_mux"; 182 clock-output-names = "apb1_mux";
@@ -184,7 +184,7 @@
184 184
185 apb1: apb1@01c20058 { 185 apb1: apb1@01c20058 {
186 #clock-cells = <0>; 186 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-apb1-clk"; 187 compatible = "allwinner,sun4i-a10-apb1-clk";
188 reg = <0x01c20058 0x4>; 188 reg = <0x01c20058 0x4>;
189 clocks = <&apb1_mux>; 189 clocks = <&apb1_mux>;
190 clock-output-names = "apb1"; 190 clock-output-names = "apb1";
@@ -192,7 +192,7 @@
192 192
193 apb1_gates: clk@01c2006c { 193 apb1_gates: clk@01c2006c {
194 #clock-cells = <1>; 194 #clock-cells = <1>;
195 compatible = "allwinner,sun4i-apb1-gates-clk"; 195 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
196 reg = <0x01c2006c 0x4>; 196 reg = <0x01c2006c 0x4>;
197 clocks = <&apb1>; 197 clocks = <&apb1>;
198 clock-output-names = "apb1_i2c0", "apb1_i2c1", 198 clock-output-names = "apb1_i2c0", "apb1_i2c1",
@@ -205,7 +205,7 @@
205 205
206 nand_clk: clk@01c20080 { 206 nand_clk: clk@01c20080 {
207 #clock-cells = <0>; 207 #clock-cells = <0>;
208 compatible = "allwinner,sun4i-mod0-clk"; 208 compatible = "allwinner,sun4i-a10-mod0-clk";
209 reg = <0x01c20080 0x4>; 209 reg = <0x01c20080 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "nand"; 211 clock-output-names = "nand";
@@ -213,7 +213,7 @@
213 213
214 ms_clk: clk@01c20084 { 214 ms_clk: clk@01c20084 {
215 #clock-cells = <0>; 215 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-mod0-clk"; 216 compatible = "allwinner,sun4i-a10-mod0-clk";
217 reg = <0x01c20084 0x4>; 217 reg = <0x01c20084 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "ms"; 219 clock-output-names = "ms";
@@ -221,7 +221,7 @@
221 221
222 mmc0_clk: clk@01c20088 { 222 mmc0_clk: clk@01c20088 {
223 #clock-cells = <0>; 223 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-mod0-clk"; 224 compatible = "allwinner,sun4i-a10-mod0-clk";
225 reg = <0x01c20088 0x4>; 225 reg = <0x01c20088 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "mmc0"; 227 clock-output-names = "mmc0";
@@ -229,7 +229,7 @@
229 229
230 mmc1_clk: clk@01c2008c { 230 mmc1_clk: clk@01c2008c {
231 #clock-cells = <0>; 231 #clock-cells = <0>;
232 compatible = "allwinner,sun4i-mod0-clk"; 232 compatible = "allwinner,sun4i-a10-mod0-clk";
233 reg = <0x01c2008c 0x4>; 233 reg = <0x01c2008c 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "mmc1"; 235 clock-output-names = "mmc1";
@@ -237,7 +237,7 @@
237 237
238 mmc2_clk: clk@01c20090 { 238 mmc2_clk: clk@01c20090 {
239 #clock-cells = <0>; 239 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-mod0-clk"; 240 compatible = "allwinner,sun4i-a10-mod0-clk";
241 reg = <0x01c20090 0x4>; 241 reg = <0x01c20090 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "mmc2"; 243 clock-output-names = "mmc2";
@@ -245,7 +245,7 @@
245 245
246 mmc3_clk: clk@01c20094 { 246 mmc3_clk: clk@01c20094 {
247 #clock-cells = <0>; 247 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-mod0-clk"; 248 compatible = "allwinner,sun4i-a10-mod0-clk";
249 reg = <0x01c20094 0x4>; 249 reg = <0x01c20094 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "mmc3"; 251 clock-output-names = "mmc3";
@@ -253,7 +253,7 @@
253 253
254 ts_clk: clk@01c20098 { 254 ts_clk: clk@01c20098 {
255 #clock-cells = <0>; 255 #clock-cells = <0>;
256 compatible = "allwinner,sun4i-mod0-clk"; 256 compatible = "allwinner,sun4i-a10-mod0-clk";
257 reg = <0x01c20098 0x4>; 257 reg = <0x01c20098 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ts"; 259 clock-output-names = "ts";
@@ -261,7 +261,7 @@
261 261
262 ss_clk: clk@01c2009c { 262 ss_clk: clk@01c2009c {
263 #clock-cells = <0>; 263 #clock-cells = <0>;
264 compatible = "allwinner,sun4i-mod0-clk"; 264 compatible = "allwinner,sun4i-a10-mod0-clk";
265 reg = <0x01c2009c 0x4>; 265 reg = <0x01c2009c 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "ss"; 267 clock-output-names = "ss";
@@ -269,7 +269,7 @@
269 269
270 spi0_clk: clk@01c200a0 { 270 spi0_clk: clk@01c200a0 {
271 #clock-cells = <0>; 271 #clock-cells = <0>;
272 compatible = "allwinner,sun4i-mod0-clk"; 272 compatible = "allwinner,sun4i-a10-mod0-clk";
273 reg = <0x01c200a0 0x4>; 273 reg = <0x01c200a0 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "spi0"; 275 clock-output-names = "spi0";
@@ -277,7 +277,7 @@
277 277
278 spi1_clk: clk@01c200a4 { 278 spi1_clk: clk@01c200a4 {
279 #clock-cells = <0>; 279 #clock-cells = <0>;
280 compatible = "allwinner,sun4i-mod0-clk"; 280 compatible = "allwinner,sun4i-a10-mod0-clk";
281 reg = <0x01c200a4 0x4>; 281 reg = <0x01c200a4 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "spi1"; 283 clock-output-names = "spi1";
@@ -285,7 +285,7 @@
285 285
286 spi2_clk: clk@01c200a8 { 286 spi2_clk: clk@01c200a8 {
287 #clock-cells = <0>; 287 #clock-cells = <0>;
288 compatible = "allwinner,sun4i-mod0-clk"; 288 compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c200a8 0x4>; 289 reg = <0x01c200a8 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "spi2"; 291 clock-output-names = "spi2";
@@ -293,7 +293,7 @@
293 293
294 pata_clk: clk@01c200ac { 294 pata_clk: clk@01c200ac {
295 #clock-cells = <0>; 295 #clock-cells = <0>;
296 compatible = "allwinner,sun4i-mod0-clk"; 296 compatible = "allwinner,sun4i-a10-mod0-clk";
297 reg = <0x01c200ac 0x4>; 297 reg = <0x01c200ac 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "pata"; 299 clock-output-names = "pata";
@@ -301,7 +301,7 @@
301 301
302 ir0_clk: clk@01c200b0 { 302 ir0_clk: clk@01c200b0 {
303 #clock-cells = <0>; 303 #clock-cells = <0>;
304 compatible = "allwinner,sun4i-mod0-clk"; 304 compatible = "allwinner,sun4i-a10-mod0-clk";
305 reg = <0x01c200b0 0x4>; 305 reg = <0x01c200b0 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "ir0"; 307 clock-output-names = "ir0";
@@ -309,7 +309,7 @@
309 309
310 ir1_clk: clk@01c200b4 { 310 ir1_clk: clk@01c200b4 {
311 #clock-cells = <0>; 311 #clock-cells = <0>;
312 compatible = "allwinner,sun4i-mod0-clk"; 312 compatible = "allwinner,sun4i-a10-mod0-clk";
313 reg = <0x01c200b4 0x4>; 313 reg = <0x01c200b4 0x4>;
314 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 314 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
315 clock-output-names = "ir1"; 315 clock-output-names = "ir1";
@@ -326,7 +326,7 @@
326 326
327 spi3_clk: clk@01c200d4 { 327 spi3_clk: clk@01c200d4 {
328 #clock-cells = <0>; 328 #clock-cells = <0>;
329 compatible = "allwinner,sun4i-mod0-clk"; 329 compatible = "allwinner,sun4i-a10-mod0-clk";
330 reg = <0x01c200d4 0x4>; 330 reg = <0x01c200d4 0x4>;
331 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 331 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
332 clock-output-names = "spi3"; 332 clock-output-names = "spi3";
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 0e0da137279f..9cbd88421dbc 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -53,7 +53,7 @@
53 53
54 osc24M: clk@01c20050 { 54 osc24M: clk@01c20050 {
55 #clock-cells = <0>; 55 #clock-cells = <0>;
56 compatible = "allwinner,sun4i-osc-clk"; 56 compatible = "allwinner,sun4i-a10-osc-clk";
57 reg = <0x01c20050 0x4>; 57 reg = <0x01c20050 0x4>;
58 clock-frequency = <24000000>; 58 clock-frequency = <24000000>;
59 clock-output-names = "osc24M"; 59 clock-output-names = "osc24M";
@@ -68,7 +68,7 @@
68 68
69 pll1: clk@01c20000 { 69 pll1: clk@01c20000 {
70 #clock-cells = <0>; 70 #clock-cells = <0>;
71 compatible = "allwinner,sun4i-pll1-clk"; 71 compatible = "allwinner,sun4i-a10-pll1-clk";
72 reg = <0x01c20000 0x4>; 72 reg = <0x01c20000 0x4>;
73 clocks = <&osc24M>; 73 clocks = <&osc24M>;
74 clock-output-names = "pll1"; 74 clock-output-names = "pll1";
@@ -76,7 +76,7 @@
76 76
77 pll4: clk@01c20018 { 77 pll4: clk@01c20018 {
78 #clock-cells = <0>; 78 #clock-cells = <0>;
79 compatible = "allwinner,sun4i-pll1-clk"; 79 compatible = "allwinner,sun4i-a10-pll1-clk";
80 reg = <0x01c20018 0x4>; 80 reg = <0x01c20018 0x4>;
81 clocks = <&osc24M>; 81 clocks = <&osc24M>;
82 clock-output-names = "pll4"; 82 clock-output-names = "pll4";
@@ -84,7 +84,7 @@
84 84
85 pll5: clk@01c20020 { 85 pll5: clk@01c20020 {
86 #clock-cells = <1>; 86 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll5-clk"; 87 compatible = "allwinner,sun4i-a10-pll5-clk";
88 reg = <0x01c20020 0x4>; 88 reg = <0x01c20020 0x4>;
89 clocks = <&osc24M>; 89 clocks = <&osc24M>;
90 clock-output-names = "pll5_ddr", "pll5_other"; 90 clock-output-names = "pll5_ddr", "pll5_other";
@@ -92,7 +92,7 @@
92 92
93 pll6: clk@01c20028 { 93 pll6: clk@01c20028 {
94 #clock-cells = <1>; 94 #clock-cells = <1>;
95 compatible = "allwinner,sun4i-pll6-clk"; 95 compatible = "allwinner,sun4i-a10-pll6-clk";
96 reg = <0x01c20028 0x4>; 96 reg = <0x01c20028 0x4>;
97 clocks = <&osc24M>; 97 clocks = <&osc24M>;
98 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 98 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -101,7 +101,7 @@
101 /* dummy is 200M */ 101 /* dummy is 200M */
102 cpu: cpu@01c20054 { 102 cpu: cpu@01c20054 {
103 #clock-cells = <0>; 103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-cpu-clk"; 104 compatible = "allwinner,sun4i-a10-cpu-clk";
105 reg = <0x01c20054 0x4>; 105 reg = <0x01c20054 0x4>;
106 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 106 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
107 clock-output-names = "cpu"; 107 clock-output-names = "cpu";
@@ -109,7 +109,7 @@
109 109
110 axi: axi@01c20054 { 110 axi: axi@01c20054 {
111 #clock-cells = <0>; 111 #clock-cells = <0>;
112 compatible = "allwinner,sun4i-axi-clk"; 112 compatible = "allwinner,sun4i-a10-axi-clk";
113 reg = <0x01c20054 0x4>; 113 reg = <0x01c20054 0x4>;
114 clocks = <&cpu>; 114 clocks = <&cpu>;
115 clock-output-names = "axi"; 115 clock-output-names = "axi";
@@ -117,7 +117,7 @@
117 117
118 axi_gates: clk@01c2005c { 118 axi_gates: clk@01c2005c {
119 #clock-cells = <1>; 119 #clock-cells = <1>;
120 compatible = "allwinner,sun4i-axi-gates-clk"; 120 compatible = "allwinner,sun4i-a10-axi-gates-clk";
121 reg = <0x01c2005c 0x4>; 121 reg = <0x01c2005c 0x4>;
122 clocks = <&axi>; 122 clocks = <&axi>;
123 clock-output-names = "axi_dram"; 123 clock-output-names = "axi_dram";
@@ -125,7 +125,7 @@
125 125
126 ahb: ahb@01c20054 { 126 ahb: ahb@01c20054 {
127 #clock-cells = <0>; 127 #clock-cells = <0>;
128 compatible = "allwinner,sun4i-ahb-clk"; 128 compatible = "allwinner,sun4i-a10-ahb-clk";
129 reg = <0x01c20054 0x4>; 129 reg = <0x01c20054 0x4>;
130 clocks = <&axi>; 130 clocks = <&axi>;
131 clock-output-names = "ahb"; 131 clock-output-names = "ahb";
@@ -147,7 +147,7 @@
147 147
148 apb0: apb0@01c20054 { 148 apb0: apb0@01c20054 {
149 #clock-cells = <0>; 149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-apb0-clk"; 150 compatible = "allwinner,sun4i-a10-apb0-clk";
151 reg = <0x01c20054 0x4>; 151 reg = <0x01c20054 0x4>;
152 clocks = <&ahb>; 152 clocks = <&ahb>;
153 clock-output-names = "apb0"; 153 clock-output-names = "apb0";
@@ -164,7 +164,7 @@
164 164
165 apb1_mux: apb1_mux@01c20058 { 165 apb1_mux: apb1_mux@01c20058 {
166 #clock-cells = <0>; 166 #clock-cells = <0>;
167 compatible = "allwinner,sun4i-apb1-mux-clk"; 167 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
168 reg = <0x01c20058 0x4>; 168 reg = <0x01c20058 0x4>;
169 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 169 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
170 clock-output-names = "apb1_mux"; 170 clock-output-names = "apb1_mux";
@@ -172,7 +172,7 @@
172 172
173 apb1: apb1@01c20058 { 173 apb1: apb1@01c20058 {
174 #clock-cells = <0>; 174 #clock-cells = <0>;
175 compatible = "allwinner,sun4i-apb1-clk"; 175 compatible = "allwinner,sun4i-a10-apb1-clk";
176 reg = <0x01c20058 0x4>; 176 reg = <0x01c20058 0x4>;
177 clocks = <&apb1_mux>; 177 clocks = <&apb1_mux>;
178 clock-output-names = "apb1"; 178 clock-output-names = "apb1";
@@ -190,7 +190,7 @@
190 190
191 nand_clk: clk@01c20080 { 191 nand_clk: clk@01c20080 {
192 #clock-cells = <0>; 192 #clock-cells = <0>;
193 compatible = "allwinner,sun4i-mod0-clk"; 193 compatible = "allwinner,sun4i-a10-mod0-clk";
194 reg = <0x01c20080 0x4>; 194 reg = <0x01c20080 0x4>;
195 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 195 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
196 clock-output-names = "nand"; 196 clock-output-names = "nand";
@@ -198,7 +198,7 @@
198 198
199 ms_clk: clk@01c20084 { 199 ms_clk: clk@01c20084 {
200 #clock-cells = <0>; 200 #clock-cells = <0>;
201 compatible = "allwinner,sun4i-mod0-clk"; 201 compatible = "allwinner,sun4i-a10-mod0-clk";
202 reg = <0x01c20084 0x4>; 202 reg = <0x01c20084 0x4>;
203 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 203 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
204 clock-output-names = "ms"; 204 clock-output-names = "ms";
@@ -206,7 +206,7 @@
206 206
207 mmc0_clk: clk@01c20088 { 207 mmc0_clk: clk@01c20088 {
208 #clock-cells = <0>; 208 #clock-cells = <0>;
209 compatible = "allwinner,sun4i-mod0-clk"; 209 compatible = "allwinner,sun4i-a10-mod0-clk";
210 reg = <0x01c20088 0x4>; 210 reg = <0x01c20088 0x4>;
211 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 211 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
212 clock-output-names = "mmc0"; 212 clock-output-names = "mmc0";
@@ -214,7 +214,7 @@
214 214
215 mmc1_clk: clk@01c2008c { 215 mmc1_clk: clk@01c2008c {
216 #clock-cells = <0>; 216 #clock-cells = <0>;
217 compatible = "allwinner,sun4i-mod0-clk"; 217 compatible = "allwinner,sun4i-a10-mod0-clk";
218 reg = <0x01c2008c 0x4>; 218 reg = <0x01c2008c 0x4>;
219 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 219 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
220 clock-output-names = "mmc1"; 220 clock-output-names = "mmc1";
@@ -222,7 +222,7 @@
222 222
223 mmc2_clk: clk@01c20090 { 223 mmc2_clk: clk@01c20090 {
224 #clock-cells = <0>; 224 #clock-cells = <0>;
225 compatible = "allwinner,sun4i-mod0-clk"; 225 compatible = "allwinner,sun4i-a10-mod0-clk";
226 reg = <0x01c20090 0x4>; 226 reg = <0x01c20090 0x4>;
227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
228 clock-output-names = "mmc2"; 228 clock-output-names = "mmc2";
@@ -230,7 +230,7 @@
230 230
231 ts_clk: clk@01c20098 { 231 ts_clk: clk@01c20098 {
232 #clock-cells = <0>; 232 #clock-cells = <0>;
233 compatible = "allwinner,sun4i-mod0-clk"; 233 compatible = "allwinner,sun4i-a10-mod0-clk";
234 reg = <0x01c20098 0x4>; 234 reg = <0x01c20098 0x4>;
235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
236 clock-output-names = "ts"; 236 clock-output-names = "ts";
@@ -238,7 +238,7 @@
238 238
239 ss_clk: clk@01c2009c { 239 ss_clk: clk@01c2009c {
240 #clock-cells = <0>; 240 #clock-cells = <0>;
241 compatible = "allwinner,sun4i-mod0-clk"; 241 compatible = "allwinner,sun4i-a10-mod0-clk";
242 reg = <0x01c2009c 0x4>; 242 reg = <0x01c2009c 0x4>;
243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
244 clock-output-names = "ss"; 244 clock-output-names = "ss";
@@ -246,7 +246,7 @@
246 246
247 spi0_clk: clk@01c200a0 { 247 spi0_clk: clk@01c200a0 {
248 #clock-cells = <0>; 248 #clock-cells = <0>;
249 compatible = "allwinner,sun4i-mod0-clk"; 249 compatible = "allwinner,sun4i-a10-mod0-clk";
250 reg = <0x01c200a0 0x4>; 250 reg = <0x01c200a0 0x4>;
251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
252 clock-output-names = "spi0"; 252 clock-output-names = "spi0";
@@ -254,7 +254,7 @@
254 254
255 spi1_clk: clk@01c200a4 { 255 spi1_clk: clk@01c200a4 {
256 #clock-cells = <0>; 256 #clock-cells = <0>;
257 compatible = "allwinner,sun4i-mod0-clk"; 257 compatible = "allwinner,sun4i-a10-mod0-clk";
258 reg = <0x01c200a4 0x4>; 258 reg = <0x01c200a4 0x4>;
259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
260 clock-output-names = "spi1"; 260 clock-output-names = "spi1";
@@ -262,7 +262,7 @@
262 262
263 spi2_clk: clk@01c200a8 { 263 spi2_clk: clk@01c200a8 {
264 #clock-cells = <0>; 264 #clock-cells = <0>;
265 compatible = "allwinner,sun4i-mod0-clk"; 265 compatible = "allwinner,sun4i-a10-mod0-clk";
266 reg = <0x01c200a8 0x4>; 266 reg = <0x01c200a8 0x4>;
267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
268 clock-output-names = "spi2"; 268 clock-output-names = "spi2";
@@ -270,7 +270,7 @@
270 270
271 ir0_clk: clk@01c200b0 { 271 ir0_clk: clk@01c200b0 {
272 #clock-cells = <0>; 272 #clock-cells = <0>;
273 compatible = "allwinner,sun4i-mod0-clk"; 273 compatible = "allwinner,sun4i-a10-mod0-clk";
274 reg = <0x01c200b0 0x4>; 274 reg = <0x01c200b0 0x4>;
275 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 275 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
276 clock-output-names = "ir0"; 276 clock-output-names = "ir0";
@@ -287,7 +287,7 @@
287 287
288 mbus_clk: clk@01c2015c { 288 mbus_clk: clk@01c2015c {
289 #clock-cells = <0>; 289 #clock-cells = <0>;
290 compatible = "allwinner,sun4i-mod0-clk"; 290 compatible = "allwinner,sun4i-a10-mod0-clk";
291 reg = <0x01c2015c 0x4>; 291 reg = <0x01c2015c 0x4>;
292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
293 clock-output-names = "mbus"; 293 clock-output-names = "mbus";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index b1468b3c7c57..6caf65dbf187 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -54,7 +54,7 @@
54 54
55 osc24M: clk@01c20050 { 55 osc24M: clk@01c20050 {
56 #clock-cells = <0>; 56 #clock-cells = <0>;
57 compatible = "allwinner,sun4i-osc-clk"; 57 compatible = "allwinner,sun4i-a10-osc-clk";
58 reg = <0x01c20050 0x4>; 58 reg = <0x01c20050 0x4>;
59 clock-frequency = <24000000>; 59 clock-frequency = <24000000>;
60 clock-output-names = "osc24M"; 60 clock-output-names = "osc24M";
@@ -69,7 +69,7 @@
69 69
70 pll1: clk@01c20000 { 70 pll1: clk@01c20000 {
71 #clock-cells = <0>; 71 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 72 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20000 0x4>; 73 reg = <0x01c20000 0x4>;
74 clocks = <&osc24M>; 74 clocks = <&osc24M>;
75 clock-output-names = "pll1"; 75 clock-output-names = "pll1";
@@ -77,7 +77,7 @@
77 77
78 pll4: clk@01c20018 { 78 pll4: clk@01c20018 {
79 #clock-cells = <0>; 79 #clock-cells = <0>;
80 compatible = "allwinner,sun4i-pll1-clk"; 80 compatible = "allwinner,sun4i-a10-pll1-clk";
81 reg = <0x01c20018 0x4>; 81 reg = <0x01c20018 0x4>;
82 clocks = <&osc24M>; 82 clocks = <&osc24M>;
83 clock-output-names = "pll4"; 83 clock-output-names = "pll4";
@@ -85,7 +85,7 @@
85 85
86 pll5: clk@01c20020 { 86 pll5: clk@01c20020 {
87 #clock-cells = <1>; 87 #clock-cells = <1>;
88 compatible = "allwinner,sun4i-pll5-clk"; 88 compatible = "allwinner,sun4i-a10-pll5-clk";
89 reg = <0x01c20020 0x4>; 89 reg = <0x01c20020 0x4>;
90 clocks = <&osc24M>; 90 clocks = <&osc24M>;
91 clock-output-names = "pll5_ddr", "pll5_other"; 91 clock-output-names = "pll5_ddr", "pll5_other";
@@ -93,7 +93,7 @@
93 93
94 pll6: clk@01c20028 { 94 pll6: clk@01c20028 {
95 #clock-cells = <1>; 95 #clock-cells = <1>;
96 compatible = "allwinner,sun4i-pll6-clk"; 96 compatible = "allwinner,sun4i-a10-pll6-clk";
97 reg = <0x01c20028 0x4>; 97 reg = <0x01c20028 0x4>;
98 clocks = <&osc24M>; 98 clocks = <&osc24M>;
99 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 99 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -102,7 +102,7 @@
102 /* dummy is 200M */ 102 /* dummy is 200M */
103 cpu: cpu@01c20054 { 103 cpu: cpu@01c20054 {
104 #clock-cells = <0>; 104 #clock-cells = <0>;
105 compatible = "allwinner,sun4i-cpu-clk"; 105 compatible = "allwinner,sun4i-a10-cpu-clk";
106 reg = <0x01c20054 0x4>; 106 reg = <0x01c20054 0x4>;
107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
108 clock-output-names = "cpu"; 108 clock-output-names = "cpu";
@@ -110,7 +110,7 @@
110 110
111 axi: axi@01c20054 { 111 axi: axi@01c20054 {
112 #clock-cells = <0>; 112 #clock-cells = <0>;
113 compatible = "allwinner,sun4i-axi-clk"; 113 compatible = "allwinner,sun4i-a10-axi-clk";
114 reg = <0x01c20054 0x4>; 114 reg = <0x01c20054 0x4>;
115 clocks = <&cpu>; 115 clocks = <&cpu>;
116 clock-output-names = "axi"; 116 clock-output-names = "axi";
@@ -118,7 +118,7 @@
118 118
119 axi_gates: clk@01c2005c { 119 axi_gates: clk@01c2005c {
120 #clock-cells = <1>; 120 #clock-cells = <1>;
121 compatible = "allwinner,sun4i-axi-gates-clk"; 121 compatible = "allwinner,sun4i-a10-axi-gates-clk";
122 reg = <0x01c2005c 0x4>; 122 reg = <0x01c2005c 0x4>;
123 clocks = <&axi>; 123 clocks = <&axi>;
124 clock-output-names = "axi_dram"; 124 clock-output-names = "axi_dram";
@@ -126,7 +126,7 @@
126 126
127 ahb: ahb@01c20054 { 127 ahb: ahb@01c20054 {
128 #clock-cells = <0>; 128 #clock-cells = <0>;
129 compatible = "allwinner,sun4i-ahb-clk"; 129 compatible = "allwinner,sun4i-a10-ahb-clk";
130 reg = <0x01c20054 0x4>; 130 reg = <0x01c20054 0x4>;
131 clocks = <&axi>; 131 clocks = <&axi>;
132 clock-output-names = "ahb"; 132 clock-output-names = "ahb";
@@ -147,7 +147,7 @@
147 147
148 apb0: apb0@01c20054 { 148 apb0: apb0@01c20054 {
149 #clock-cells = <0>; 149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-apb0-clk"; 150 compatible = "allwinner,sun4i-a10-apb0-clk";
151 reg = <0x01c20054 0x4>; 151 reg = <0x01c20054 0x4>;
152 clocks = <&ahb>; 152 clocks = <&ahb>;
153 clock-output-names = "apb0"; 153 clock-output-names = "apb0";
@@ -163,7 +163,7 @@
163 163
164 apb1_mux: apb1_mux@01c20058 { 164 apb1_mux: apb1_mux@01c20058 {
165 #clock-cells = <0>; 165 #clock-cells = <0>;
166 compatible = "allwinner,sun4i-apb1-mux-clk"; 166 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
167 reg = <0x01c20058 0x4>; 167 reg = <0x01c20058 0x4>;
168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
169 clock-output-names = "apb1_mux"; 169 clock-output-names = "apb1_mux";
@@ -171,7 +171,7 @@
171 171
172 apb1: apb1@01c20058 { 172 apb1: apb1@01c20058 {
173 #clock-cells = <0>; 173 #clock-cells = <0>;
174 compatible = "allwinner,sun4i-apb1-clk"; 174 compatible = "allwinner,sun4i-a10-apb1-clk";
175 reg = <0x01c20058 0x4>; 175 reg = <0x01c20058 0x4>;
176 clocks = <&apb1_mux>; 176 clocks = <&apb1_mux>;
177 clock-output-names = "apb1"; 177 clock-output-names = "apb1";
@@ -188,7 +188,7 @@
188 188
189 nand_clk: clk@01c20080 { 189 nand_clk: clk@01c20080 {
190 #clock-cells = <0>; 190 #clock-cells = <0>;
191 compatible = "allwinner,sun4i-mod0-clk"; 191 compatible = "allwinner,sun4i-a10-mod0-clk";
192 reg = <0x01c20080 0x4>; 192 reg = <0x01c20080 0x4>;
193 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 193 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
194 clock-output-names = "nand"; 194 clock-output-names = "nand";
@@ -196,7 +196,7 @@
196 196
197 ms_clk: clk@01c20084 { 197 ms_clk: clk@01c20084 {
198 #clock-cells = <0>; 198 #clock-cells = <0>;
199 compatible = "allwinner,sun4i-mod0-clk"; 199 compatible = "allwinner,sun4i-a10-mod0-clk";
200 reg = <0x01c20084 0x4>; 200 reg = <0x01c20084 0x4>;
201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
202 clock-output-names = "ms"; 202 clock-output-names = "ms";
@@ -204,7 +204,7 @@
204 204
205 mmc0_clk: clk@01c20088 { 205 mmc0_clk: clk@01c20088 {
206 #clock-cells = <0>; 206 #clock-cells = <0>;
207 compatible = "allwinner,sun4i-mod0-clk"; 207 compatible = "allwinner,sun4i-a10-mod0-clk";
208 reg = <0x01c20088 0x4>; 208 reg = <0x01c20088 0x4>;
209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
210 clock-output-names = "mmc0"; 210 clock-output-names = "mmc0";
@@ -212,7 +212,7 @@
212 212
213 mmc1_clk: clk@01c2008c { 213 mmc1_clk: clk@01c2008c {
214 #clock-cells = <0>; 214 #clock-cells = <0>;
215 compatible = "allwinner,sun4i-mod0-clk"; 215 compatible = "allwinner,sun4i-a10-mod0-clk";
216 reg = <0x01c2008c 0x4>; 216 reg = <0x01c2008c 0x4>;
217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
218 clock-output-names = "mmc1"; 218 clock-output-names = "mmc1";
@@ -220,7 +220,7 @@
220 220
221 mmc2_clk: clk@01c20090 { 221 mmc2_clk: clk@01c20090 {
222 #clock-cells = <0>; 222 #clock-cells = <0>;
223 compatible = "allwinner,sun4i-mod0-clk"; 223 compatible = "allwinner,sun4i-a10-mod0-clk";
224 reg = <0x01c20090 0x4>; 224 reg = <0x01c20090 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
226 clock-output-names = "mmc2"; 226 clock-output-names = "mmc2";
@@ -228,7 +228,7 @@
228 228
229 ts_clk: clk@01c20098 { 229 ts_clk: clk@01c20098 {
230 #clock-cells = <0>; 230 #clock-cells = <0>;
231 compatible = "allwinner,sun4i-mod0-clk"; 231 compatible = "allwinner,sun4i-a10-mod0-clk";
232 reg = <0x01c20098 0x4>; 232 reg = <0x01c20098 0x4>;
233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
234 clock-output-names = "ts"; 234 clock-output-names = "ts";
@@ -236,7 +236,7 @@
236 236
237 ss_clk: clk@01c2009c { 237 ss_clk: clk@01c2009c {
238 #clock-cells = <0>; 238 #clock-cells = <0>;
239 compatible = "allwinner,sun4i-mod0-clk"; 239 compatible = "allwinner,sun4i-a10-mod0-clk";
240 reg = <0x01c2009c 0x4>; 240 reg = <0x01c2009c 0x4>;
241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
242 clock-output-names = "ss"; 242 clock-output-names = "ss";
@@ -244,7 +244,7 @@
244 244
245 spi0_clk: clk@01c200a0 { 245 spi0_clk: clk@01c200a0 {
246 #clock-cells = <0>; 246 #clock-cells = <0>;
247 compatible = "allwinner,sun4i-mod0-clk"; 247 compatible = "allwinner,sun4i-a10-mod0-clk";
248 reg = <0x01c200a0 0x4>; 248 reg = <0x01c200a0 0x4>;
249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 clock-output-names = "spi0"; 250 clock-output-names = "spi0";
@@ -252,7 +252,7 @@
252 252
253 spi1_clk: clk@01c200a4 { 253 spi1_clk: clk@01c200a4 {
254 #clock-cells = <0>; 254 #clock-cells = <0>;
255 compatible = "allwinner,sun4i-mod0-clk"; 255 compatible = "allwinner,sun4i-a10-mod0-clk";
256 reg = <0x01c200a4 0x4>; 256 reg = <0x01c200a4 0x4>;
257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
258 clock-output-names = "spi1"; 258 clock-output-names = "spi1";
@@ -260,7 +260,7 @@
260 260
261 spi2_clk: clk@01c200a8 { 261 spi2_clk: clk@01c200a8 {
262 #clock-cells = <0>; 262 #clock-cells = <0>;
263 compatible = "allwinner,sun4i-mod0-clk"; 263 compatible = "allwinner,sun4i-a10-mod0-clk";
264 reg = <0x01c200a8 0x4>; 264 reg = <0x01c200a8 0x4>;
265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
266 clock-output-names = "spi2"; 266 clock-output-names = "spi2";
@@ -268,7 +268,7 @@
268 268
269 ir0_clk: clk@01c200b0 { 269 ir0_clk: clk@01c200b0 {
270 #clock-cells = <0>; 270 #clock-cells = <0>;
271 compatible = "allwinner,sun4i-mod0-clk"; 271 compatible = "allwinner,sun4i-a10-mod0-clk";
272 reg = <0x01c200b0 0x4>; 272 reg = <0x01c200b0 0x4>;
273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
274 clock-output-names = "ir0"; 274 clock-output-names = "ir0";
@@ -285,7 +285,7 @@
285 285
286 mbus_clk: clk@01c2015c { 286 mbus_clk: clk@01c2015c {
287 #clock-cells = <0>; 287 #clock-cells = <0>;
288 compatible = "allwinner,sun4i-mod0-clk"; 288 compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c2015c 0x4>; 289 reg = <0x01c2015c 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "mbus"; 291 clock-output-names = "mbus";
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index d3f19951d501..af6f87c4e1c7 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -95,7 +95,7 @@
95 95
96 cpu: cpu@01c20050 { 96 cpu: cpu@01c20050 {
97 #clock-cells = <0>; 97 #clock-cells = <0>;
98 compatible = "allwinner,sun4i-cpu-clk"; 98 compatible = "allwinner,sun4i-a10-cpu-clk";
99 reg = <0x01c20050 0x4>; 99 reg = <0x01c20050 0x4>;
100 100
101 /* 101 /*
@@ -110,7 +110,7 @@
110 110
111 axi: axi@01c20050 { 111 axi: axi@01c20050 {
112 #clock-cells = <0>; 112 #clock-cells = <0>;
113 compatible = "allwinner,sun4i-axi-clk"; 113 compatible = "allwinner,sun4i-a10-axi-clk";
114 reg = <0x01c20050 0x4>; 114 reg = <0x01c20050 0x4>;
115 clocks = <&cpu>; 115 clocks = <&cpu>;
116 clock-output-names = "axi"; 116 clock-output-names = "axi";
@@ -126,7 +126,7 @@
126 126
127 ahb1: ahb1@01c20054 { 127 ahb1: ahb1@01c20054 {
128 #clock-cells = <0>; 128 #clock-cells = <0>;
129 compatible = "allwinner,sun4i-ahb-clk"; 129 compatible = "allwinner,sun4i-a10-ahb-clk";
130 reg = <0x01c20054 0x4>; 130 reg = <0x01c20054 0x4>;
131 clocks = <&ahb1_mux>; 131 clocks = <&ahb1_mux>;
132 clock-output-names = "ahb1"; 132 clock-output-names = "ahb1";
@@ -155,7 +155,7 @@
155 155
156 apb1: apb1@01c20054 { 156 apb1: apb1@01c20054 {
157 #clock-cells = <0>; 157 #clock-cells = <0>;
158 compatible = "allwinner,sun4i-apb0-clk"; 158 compatible = "allwinner,sun4i-a10-apb0-clk";
159 reg = <0x01c20054 0x4>; 159 reg = <0x01c20054 0x4>;
160 clocks = <&ahb1>; 160 clocks = <&ahb1>;
161 clock-output-names = "apb1"; 161 clock-output-names = "apb1";
@@ -173,7 +173,7 @@
173 173
174 apb2_mux: apb2_mux@01c20058 { 174 apb2_mux: apb2_mux@01c20058 {
175 #clock-cells = <0>; 175 #clock-cells = <0>;
176 compatible = "allwinner,sun4i-apb1-mux-clk"; 176 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
177 reg = <0x01c20058 0x4>; 177 reg = <0x01c20058 0x4>;
178 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 178 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
179 clock-output-names = "apb2_mux"; 179 clock-output-names = "apb2_mux";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 25ba9fa99c5d..bc528de39f8e 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -64,7 +64,7 @@
64 64
65 osc24M: clk@01c20050 { 65 osc24M: clk@01c20050 {
66 #clock-cells = <0>; 66 #clock-cells = <0>;
67 compatible = "allwinner,sun4i-osc-clk"; 67 compatible = "allwinner,sun4i-a10-osc-clk";
68 reg = <0x01c20050 0x4>; 68 reg = <0x01c20050 0x4>;
69 clock-frequency = <24000000>; 69 clock-frequency = <24000000>;
70 clock-output-names = "osc24M"; 70 clock-output-names = "osc24M";
@@ -79,7 +79,7 @@
79 79
80 pll1: clk@01c20000 { 80 pll1: clk@01c20000 {
81 #clock-cells = <0>; 81 #clock-cells = <0>;
82 compatible = "allwinner,sun4i-pll1-clk"; 82 compatible = "allwinner,sun4i-a10-pll1-clk";
83 reg = <0x01c20000 0x4>; 83 reg = <0x01c20000 0x4>;
84 clocks = <&osc24M>; 84 clocks = <&osc24M>;
85 clock-output-names = "pll1"; 85 clock-output-names = "pll1";
@@ -87,7 +87,7 @@
87 87
88 pll4: clk@01c20018 { 88 pll4: clk@01c20018 {
89 #clock-cells = <0>; 89 #clock-cells = <0>;
90 compatible = "allwinner,sun4i-pll1-clk"; 90 compatible = "allwinner,sun4i-a10-pll1-clk";
91 reg = <0x01c20018 0x4>; 91 reg = <0x01c20018 0x4>;
92 clocks = <&osc24M>; 92 clocks = <&osc24M>;
93 clock-output-names = "pll4"; 93 clock-output-names = "pll4";
@@ -95,7 +95,7 @@
95 95
96 pll5: clk@01c20020 { 96 pll5: clk@01c20020 {
97 #clock-cells = <1>; 97 #clock-cells = <1>;
98 compatible = "allwinner,sun4i-pll5-clk"; 98 compatible = "allwinner,sun4i-a10-pll5-clk";
99 reg = <0x01c20020 0x4>; 99 reg = <0x01c20020 0x4>;
100 clocks = <&osc24M>; 100 clocks = <&osc24M>;
101 clock-output-names = "pll5_ddr", "pll5_other"; 101 clock-output-names = "pll5_ddr", "pll5_other";
@@ -103,7 +103,7 @@
103 103
104 pll6: clk@01c20028 { 104 pll6: clk@01c20028 {
105 #clock-cells = <1>; 105 #clock-cells = <1>;
106 compatible = "allwinner,sun4i-pll6-clk"; 106 compatible = "allwinner,sun4i-a10-pll6-clk";
107 reg = <0x01c20028 0x4>; 107 reg = <0x01c20028 0x4>;
108 clocks = <&osc24M>; 108 clocks = <&osc24M>;
109 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 109 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -111,7 +111,7 @@
111 111
112 cpu: cpu@01c20054 { 112 cpu: cpu@01c20054 {
113 #clock-cells = <0>; 113 #clock-cells = <0>;
114 compatible = "allwinner,sun4i-cpu-clk"; 114 compatible = "allwinner,sun4i-a10-cpu-clk";
115 reg = <0x01c20054 0x4>; 115 reg = <0x01c20054 0x4>;
116 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; 116 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
117 clock-output-names = "cpu"; 117 clock-output-names = "cpu";
@@ -119,7 +119,7 @@
119 119
120 axi: axi@01c20054 { 120 axi: axi@01c20054 {
121 #clock-cells = <0>; 121 #clock-cells = <0>;
122 compatible = "allwinner,sun4i-axi-clk"; 122 compatible = "allwinner,sun4i-a10-axi-clk";
123 reg = <0x01c20054 0x4>; 123 reg = <0x01c20054 0x4>;
124 clocks = <&cpu>; 124 clocks = <&cpu>;
125 clock-output-names = "axi"; 125 clock-output-names = "axi";
@@ -127,7 +127,7 @@
127 127
128 ahb: ahb@01c20054 { 128 ahb: ahb@01c20054 {
129 #clock-cells = <0>; 129 #clock-cells = <0>;
130 compatible = "allwinner,sun4i-ahb-clk"; 130 compatible = "allwinner,sun4i-a10-ahb-clk";
131 reg = <0x01c20054 0x4>; 131 reg = <0x01c20054 0x4>;
132 clocks = <&axi>; 132 clocks = <&axi>;
133 clock-output-names = "ahb"; 133 clock-output-names = "ahb";
@@ -155,7 +155,7 @@
155 155
156 apb0: apb0@01c20054 { 156 apb0: apb0@01c20054 {
157 #clock-cells = <0>; 157 #clock-cells = <0>;
158 compatible = "allwinner,sun4i-apb0-clk"; 158 compatible = "allwinner,sun4i-a10-apb0-clk";
159 reg = <0x01c20054 0x4>; 159 reg = <0x01c20054 0x4>;
160 clocks = <&ahb>; 160 clocks = <&ahb>;
161 clock-output-names = "apb0"; 161 clock-output-names = "apb0";
@@ -174,7 +174,7 @@
174 174
175 apb1_mux: apb1_mux@01c20058 { 175 apb1_mux: apb1_mux@01c20058 {
176 #clock-cells = <0>; 176 #clock-cells = <0>;
177 compatible = "allwinner,sun4i-apb1-mux-clk"; 177 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
178 reg = <0x01c20058 0x4>; 178 reg = <0x01c20058 0x4>;
179 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 179 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
180 clock-output-names = "apb1_mux"; 180 clock-output-names = "apb1_mux";
@@ -182,7 +182,7 @@
182 182
183 apb1: apb1@01c20058 { 183 apb1: apb1@01c20058 {
184 #clock-cells = <0>; 184 #clock-cells = <0>;
185 compatible = "allwinner,sun4i-apb1-clk"; 185 compatible = "allwinner,sun4i-a10-apb1-clk";
186 reg = <0x01c20058 0x4>; 186 reg = <0x01c20058 0x4>;
187 clocks = <&apb1_mux>; 187 clocks = <&apb1_mux>;
188 clock-output-names = "apb1"; 188 clock-output-names = "apb1";
@@ -203,7 +203,7 @@
203 203
204 nand_clk: clk@01c20080 { 204 nand_clk: clk@01c20080 {
205 #clock-cells = <0>; 205 #clock-cells = <0>;
206 compatible = "allwinner,sun4i-mod0-clk"; 206 compatible = "allwinner,sun4i-a10-mod0-clk";
207 reg = <0x01c20080 0x4>; 207 reg = <0x01c20080 0x4>;
208 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 208 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
209 clock-output-names = "nand"; 209 clock-output-names = "nand";
@@ -211,7 +211,7 @@
211 211
212 ms_clk: clk@01c20084 { 212 ms_clk: clk@01c20084 {
213 #clock-cells = <0>; 213 #clock-cells = <0>;
214 compatible = "allwinner,sun4i-mod0-clk"; 214 compatible = "allwinner,sun4i-a10-mod0-clk";
215 reg = <0x01c20084 0x4>; 215 reg = <0x01c20084 0x4>;
216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
217 clock-output-names = "ms"; 217 clock-output-names = "ms";
@@ -219,7 +219,7 @@
219 219
220 mmc0_clk: clk@01c20088 { 220 mmc0_clk: clk@01c20088 {
221 #clock-cells = <0>; 221 #clock-cells = <0>;
222 compatible = "allwinner,sun4i-mod0-clk"; 222 compatible = "allwinner,sun4i-a10-mod0-clk";
223 reg = <0x01c20088 0x4>; 223 reg = <0x01c20088 0x4>;
224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
225 clock-output-names = "mmc0"; 225 clock-output-names = "mmc0";
@@ -227,7 +227,7 @@
227 227
228 mmc1_clk: clk@01c2008c { 228 mmc1_clk: clk@01c2008c {
229 #clock-cells = <0>; 229 #clock-cells = <0>;
230 compatible = "allwinner,sun4i-mod0-clk"; 230 compatible = "allwinner,sun4i-a10-mod0-clk";
231 reg = <0x01c2008c 0x4>; 231 reg = <0x01c2008c 0x4>;
232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
233 clock-output-names = "mmc1"; 233 clock-output-names = "mmc1";
@@ -235,7 +235,7 @@
235 235
236 mmc2_clk: clk@01c20090 { 236 mmc2_clk: clk@01c20090 {
237 #clock-cells = <0>; 237 #clock-cells = <0>;
238 compatible = "allwinner,sun4i-mod0-clk"; 238 compatible = "allwinner,sun4i-a10-mod0-clk";
239 reg = <0x01c20090 0x4>; 239 reg = <0x01c20090 0x4>;
240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
241 clock-output-names = "mmc2"; 241 clock-output-names = "mmc2";
@@ -243,7 +243,7 @@
243 243
244 mmc3_clk: clk@01c20094 { 244 mmc3_clk: clk@01c20094 {
245 #clock-cells = <0>; 245 #clock-cells = <0>;
246 compatible = "allwinner,sun4i-mod0-clk"; 246 compatible = "allwinner,sun4i-a10-mod0-clk";
247 reg = <0x01c20094 0x4>; 247 reg = <0x01c20094 0x4>;
248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
249 clock-output-names = "mmc3"; 249 clock-output-names = "mmc3";
@@ -251,7 +251,7 @@
251 251
252 ts_clk: clk@01c20098 { 252 ts_clk: clk@01c20098 {
253 #clock-cells = <0>; 253 #clock-cells = <0>;
254 compatible = "allwinner,sun4i-mod0-clk"; 254 compatible = "allwinner,sun4i-a10-mod0-clk";
255 reg = <0x01c20098 0x4>; 255 reg = <0x01c20098 0x4>;
256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
257 clock-output-names = "ts"; 257 clock-output-names = "ts";
@@ -259,7 +259,7 @@
259 259
260 ss_clk: clk@01c2009c { 260 ss_clk: clk@01c2009c {
261 #clock-cells = <0>; 261 #clock-cells = <0>;
262 compatible = "allwinner,sun4i-mod0-clk"; 262 compatible = "allwinner,sun4i-a10-mod0-clk";
263 reg = <0x01c2009c 0x4>; 263 reg = <0x01c2009c 0x4>;
264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265 clock-output-names = "ss"; 265 clock-output-names = "ss";
@@ -267,7 +267,7 @@
267 267
268 spi0_clk: clk@01c200a0 { 268 spi0_clk: clk@01c200a0 {
269 #clock-cells = <0>; 269 #clock-cells = <0>;
270 compatible = "allwinner,sun4i-mod0-clk"; 270 compatible = "allwinner,sun4i-a10-mod0-clk";
271 reg = <0x01c200a0 0x4>; 271 reg = <0x01c200a0 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "spi0"; 273 clock-output-names = "spi0";
@@ -275,7 +275,7 @@
275 275
276 spi1_clk: clk@01c200a4 { 276 spi1_clk: clk@01c200a4 {
277 #clock-cells = <0>; 277 #clock-cells = <0>;
278 compatible = "allwinner,sun4i-mod0-clk"; 278 compatible = "allwinner,sun4i-a10-mod0-clk";
279 reg = <0x01c200a4 0x4>; 279 reg = <0x01c200a4 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "spi1"; 281 clock-output-names = "spi1";
@@ -283,7 +283,7 @@
283 283
284 spi2_clk: clk@01c200a8 { 284 spi2_clk: clk@01c200a8 {
285 #clock-cells = <0>; 285 #clock-cells = <0>;
286 compatible = "allwinner,sun4i-mod0-clk"; 286 compatible = "allwinner,sun4i-a10-mod0-clk";
287 reg = <0x01c200a8 0x4>; 287 reg = <0x01c200a8 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "spi2"; 289 clock-output-names = "spi2";
@@ -291,7 +291,7 @@
291 291
292 pata_clk: clk@01c200ac { 292 pata_clk: clk@01c200ac {
293 #clock-cells = <0>; 293 #clock-cells = <0>;
294 compatible = "allwinner,sun4i-mod0-clk"; 294 compatible = "allwinner,sun4i-a10-mod0-clk";
295 reg = <0x01c200ac 0x4>; 295 reg = <0x01c200ac 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "pata"; 297 clock-output-names = "pata";
@@ -299,7 +299,7 @@
299 299
300 ir0_clk: clk@01c200b0 { 300 ir0_clk: clk@01c200b0 {
301 #clock-cells = <0>; 301 #clock-cells = <0>;
302 compatible = "allwinner,sun4i-mod0-clk"; 302 compatible = "allwinner,sun4i-a10-mod0-clk";
303 reg = <0x01c200b0 0x4>; 303 reg = <0x01c200b0 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "ir0"; 305 clock-output-names = "ir0";
@@ -307,7 +307,7 @@
307 307
308 ir1_clk: clk@01c200b4 { 308 ir1_clk: clk@01c200b4 {
309 #clock-cells = <0>; 309 #clock-cells = <0>;
310 compatible = "allwinner,sun4i-mod0-clk"; 310 compatible = "allwinner,sun4i-a10-mod0-clk";
311 reg = <0x01c200b4 0x4>; 311 reg = <0x01c200b4 0x4>;
312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313 clock-output-names = "ir1"; 313 clock-output-names = "ir1";
@@ -324,7 +324,7 @@
324 324
325 spi3_clk: clk@01c200d4 { 325 spi3_clk: clk@01c200d4 {
326 #clock-cells = <0>; 326 #clock-cells = <0>;
327 compatible = "allwinner,sun4i-mod0-clk"; 327 compatible = "allwinner,sun4i-a10-mod0-clk";
328 reg = <0x01c200d4 0x4>; 328 reg = <0x01c200d4 0x4>;
329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
330 clock-output-names = "spi3"; 330 clock-output-names = "spi3";
@@ -332,7 +332,7 @@
332 332
333 mbus_clk: clk@01c2015c { 333 mbus_clk: clk@01c2015c {
334 #clock-cells = <0>; 334 #clock-cells = <0>;
335 compatible = "allwinner,sun4i-mod0-clk"; 335 compatible = "allwinner,sun4i-a10-mod0-clk";
336 reg = <0x01c2015c 0x4>; 336 reg = <0x01c2015c 0x4>;
337 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; 337 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
338 clock-output-names = "mbus"; 338 clock-output-names = "mbus";
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 23:18:23 -0500