diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2014-07-10 15:31:18 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-10 16:30:27 -0400 |
commit | bf225f20d51fb1b77d47fce0628159a3eda027b9 (patch) | |
tree | 7b70655f06122d2b7f00b5324792ffef0d283c20 | |
parent | 755f68f4f32fc690957cfc94a19fff3139958299 (diff) |
drm/i915: Move RPS evaluation interval counters to i915->rps
Place the RPS counters inside the RPS struct.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 18 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 32 |
2 files changed, 23 insertions, 27 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 647ea67d0b1d..263a8799eb59 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -902,10 +902,10 @@ struct vlv_s0ix_state { | |||
902 | u32 clock_gate_dis2; | 902 | u32 clock_gate_dis2; |
903 | }; | 903 | }; |
904 | 904 | ||
905 | struct intel_rps_ei_calc { | 905 | struct intel_rps_ei { |
906 | u32 cz_ts_ei; | 906 | u32 cz_clock; |
907 | u32 render_ei_c0; | 907 | u32 render_c0; |
908 | u32 media_ei_c0; | 908 | u32 media_c0; |
909 | }; | 909 | }; |
910 | 910 | ||
911 | struct intel_gen6_power_mgmt { | 911 | struct intel_gen6_power_mgmt { |
@@ -940,6 +940,9 @@ struct intel_gen6_power_mgmt { | |||
940 | bool enabled; | 940 | bool enabled; |
941 | struct delayed_work delayed_resume_work; | 941 | struct delayed_work delayed_resume_work; |
942 | 942 | ||
943 | /* manual wa residency calculations */ | ||
944 | struct intel_rps_ei up_ei, down_ei; | ||
945 | |||
943 | /* | 946 | /* |
944 | * Protects RPS/RC6 register access and PCU communication. | 947 | * Protects RPS/RC6 register access and PCU communication. |
945 | * Must be taken after struct_mutex if nested. | 948 | * Must be taken after struct_mutex if nested. |
@@ -1534,13 +1537,6 @@ struct drm_i915_private { | |||
1534 | /* gen6+ rps state */ | 1537 | /* gen6+ rps state */ |
1535 | struct intel_gen6_power_mgmt rps; | 1538 | struct intel_gen6_power_mgmt rps; |
1536 | 1539 | ||
1537 | /* rps wa up ei calculation */ | ||
1538 | struct intel_rps_ei_calc rps_up_ei; | ||
1539 | |||
1540 | /* rps wa down ei calculation */ | ||
1541 | struct intel_rps_ei_calc rps_down_ei; | ||
1542 | |||
1543 | |||
1544 | /* ilk-only ips/rps state. Everything in here is protected by the global | 1540 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1545 | * mchdev_lock in intel_pm.c */ | 1541 | * mchdev_lock in intel_pm.c */ |
1546 | struct intel_ilk_power_mgmt ips; | 1542 | struct intel_ilk_power_mgmt ips; |
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 0b4a8ed76a54..30fd63708b1a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -1273,7 +1273,7 @@ static void notify_ring(struct drm_device *dev, | |||
1273 | } | 1273 | } |
1274 | 1274 | ||
1275 | static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, | 1275 | static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, |
1276 | struct intel_rps_ei_calc *rps_ei) | 1276 | struct intel_rps_ei *rps_ei) |
1277 | { | 1277 | { |
1278 | u32 cz_ts, cz_freq_khz; | 1278 | u32 cz_ts, cz_freq_khz; |
1279 | u32 render_count, media_count; | 1279 | u32 render_count, media_count; |
@@ -1286,22 +1286,22 @@ static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, | |||
1286 | render_count = I915_READ(VLV_RENDER_C0_COUNT_REG); | 1286 | render_count = I915_READ(VLV_RENDER_C0_COUNT_REG); |
1287 | media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG); | 1287 | media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG); |
1288 | 1288 | ||
1289 | if (rps_ei->cz_ts_ei == 0) { | 1289 | if (rps_ei->cz_clock == 0) { |
1290 | rps_ei->cz_ts_ei = cz_ts; | 1290 | rps_ei->cz_clock = cz_ts; |
1291 | rps_ei->render_ei_c0 = render_count; | 1291 | rps_ei->render_c0 = render_count; |
1292 | rps_ei->media_ei_c0 = media_count; | 1292 | rps_ei->media_c0 = media_count; |
1293 | 1293 | ||
1294 | return dev_priv->rps.cur_freq; | 1294 | return dev_priv->rps.cur_freq; |
1295 | } | 1295 | } |
1296 | 1296 | ||
1297 | elapsed_time = cz_ts - rps_ei->cz_ts_ei; | 1297 | elapsed_time = cz_ts - rps_ei->cz_clock; |
1298 | rps_ei->cz_ts_ei = cz_ts; | 1298 | rps_ei->cz_clock = cz_ts; |
1299 | 1299 | ||
1300 | elapsed_render = render_count - rps_ei->render_ei_c0; | 1300 | elapsed_render = render_count - rps_ei->render_c0; |
1301 | rps_ei->render_ei_c0 = render_count; | 1301 | rps_ei->render_c0 = render_count; |
1302 | 1302 | ||
1303 | elapsed_media = media_count - rps_ei->media_ei_c0; | 1303 | elapsed_media = media_count - rps_ei->media_c0; |
1304 | rps_ei->media_ei_c0 = media_count; | 1304 | rps_ei->media_c0 = media_count; |
1305 | 1305 | ||
1306 | /* Convert all the counters into common unit of milli sec */ | 1306 | /* Convert all the counters into common unit of milli sec */ |
1307 | elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC; | 1307 | elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC; |
@@ -1337,9 +1337,9 @@ static u32 vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv) | |||
1337 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | 1337 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
1338 | 1338 | ||
1339 | 1339 | ||
1340 | if (dev_priv->rps_up_ei.cz_ts_ei == 0) { | 1340 | if (dev_priv->rps.up_ei.cz_clock == 0) { |
1341 | vlv_c0_residency(dev_priv, &dev_priv->rps_up_ei); | 1341 | vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei); |
1342 | vlv_c0_residency(dev_priv, &dev_priv->rps_down_ei); | 1342 | vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei); |
1343 | return dev_priv->rps.cur_freq; | 1343 | return dev_priv->rps.cur_freq; |
1344 | } | 1344 | } |
1345 | 1345 | ||
@@ -1354,10 +1354,10 @@ static u32 vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv) | |||
1354 | dev_priv->rps.ei_interrupt_count = 0; | 1354 | dev_priv->rps.ei_interrupt_count = 0; |
1355 | 1355 | ||
1356 | residency_C0_down = vlv_c0_residency(dev_priv, | 1356 | residency_C0_down = vlv_c0_residency(dev_priv, |
1357 | &dev_priv->rps_down_ei); | 1357 | &dev_priv->rps.down_ei); |
1358 | } else { | 1358 | } else { |
1359 | residency_C0_up = vlv_c0_residency(dev_priv, | 1359 | residency_C0_up = vlv_c0_residency(dev_priv, |
1360 | &dev_priv->rps_up_ei); | 1360 | &dev_priv->rps.up_ei); |
1361 | } | 1361 | } |
1362 | 1362 | ||
1363 | new_delay = dev_priv->rps.cur_freq; | 1363 | new_delay = dev_priv->rps.cur_freq; |