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authorArchit Taneja <archit@ti.com>2013-09-12 08:37:49 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2013-10-09 05:42:23 -0400
commitbdb8bfc652543dc392caa66343fe32cf66c4095b (patch)
tree9221d7863bb4c4511b99c7b5cb26ccb394c47506
parent275cfa1a9d43f00d1ae59f36fa0c3ed7f941b369 (diff)
omapdss: HDMI: Clean up the header files
Keep only OMAP4 HDMI core block related structs and enums in ti_hdmi_4xxx_ip.h, move the rest to ti_hdmi.h. This holds all library specific data which will be shared between OMAP4 and OMAP5/DRA7x HDMI encoder drivers. Move the duplicate register read/write/wait_for_bit_change functions in the hdmi library files to ti_hdmi.h Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat
-rw-r--r--drivers/video/omap2/dss/hdmi_phy.c31
-rw-r--r--drivers/video/omap2/dss/hdmi_pll.c31
-rw-r--r--drivers/video/omap2/dss/hdmi_wp.c31
-rw-r--r--drivers/video/omap2/dss/ti_hdmi.h170
-rw-r--r--drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c31
-rw-r--r--drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h141
6 files changed, 171 insertions, 264 deletions
diff --git a/drivers/video/omap2/dss/hdmi_phy.c b/drivers/video/omap2/dss/hdmi_phy.c
index 48bdba8d7031..29f7552b4b9a 100644
--- a/drivers/video/omap2/dss/hdmi_phy.c
+++ b/drivers/video/omap2/dss/hdmi_phy.c
@@ -9,7 +9,6 @@
9 */ 9 */
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/err.h> 12#include <linux/err.h>
14#include <linux/io.h> 13#include <linux/io.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
@@ -17,40 +16,10 @@
17 16
18#include "dss.h" 17#include "dss.h"
19#include "ti_hdmi.h" 18#include "ti_hdmi.h"
20#include "ti_hdmi_4xxx_ip.h"
21 19
22#define HDMI_IRQ_LINK_CONNECT (1 << 25) 20#define HDMI_IRQ_LINK_CONNECT (1 << 25)
23#define HDMI_IRQ_LINK_DISCONNECT (1 << 26) 21#define HDMI_IRQ_LINK_DISCONNECT (1 << 26)
24 22
25static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,
26 u32 val)
27{
28 __raw_writel(val, base_addr + idx);
29}
30
31static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)
32{
33 return __raw_readl(base_addr + idx);
34}
35
36#define REG_FLD_MOD(base, idx, val, start, end) \
37 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
38 val, start, end))
39#define REG_GET(base, idx, start, end) \
40 FLD_GET(hdmi_read_reg(base, idx), start, end)
41
42static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
43 const u16 idx, int b2, int b1, u32 val)
44{
45 u32 t = 0;
46 while (val != REG_GET(base_addr, idx, b2, b1)) {
47 udelay(1);
48 if (t++ > 10000)
49 return !val;
50 }
51 return val;
52}
53
54void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s) 23void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)
55{ 24{
56#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\ 25#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
diff --git a/drivers/video/omap2/dss/hdmi_pll.c b/drivers/video/omap2/dss/hdmi_pll.c
index e12fa6ada58f..6e187e63daae 100644
--- a/drivers/video/omap2/dss/hdmi_pll.c
+++ b/drivers/video/omap2/dss/hdmi_pll.c
@@ -10,7 +10,6 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/err.h> 13#include <linux/err.h>
15#include <linux/io.h> 14#include <linux/io.h>
16#include <linux/platform_device.h> 15#include <linux/platform_device.h>
@@ -18,40 +17,10 @@
18 17
19#include "dss.h" 18#include "dss.h"
20#include "ti_hdmi.h" 19#include "ti_hdmi.h"
21#include "ti_hdmi_4xxx_ip.h"
22 20
23#define HDMI_DEFAULT_REGN 16 21#define HDMI_DEFAULT_REGN 16
24#define HDMI_DEFAULT_REGM2 1 22#define HDMI_DEFAULT_REGM2 1
25 23
26static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,
27 u32 val)
28{
29 __raw_writel(val, base_addr + idx);
30}
31
32static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)
33{
34 return __raw_readl(base_addr + idx);
35}
36
37#define REG_FLD_MOD(base, idx, val, start, end) \
38 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
39 val, start, end))
40#define REG_GET(base, idx, start, end) \
41 FLD_GET(hdmi_read_reg(base, idx), start, end)
42
43static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
44 const u16 idx, int b2, int b1, u32 val)
45{
46 u32 t = 0;
47 while (val != REG_GET(base_addr, idx, b2, b1)) {
48 udelay(1);
49 if (t++ > 10000)
50 return !val;
51 }
52 return val;
53}
54
55void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) 24void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
56{ 25{
57#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ 26#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
diff --git a/drivers/video/omap2/dss/hdmi_wp.c b/drivers/video/omap2/dss/hdmi_wp.c
index 1b6dbe1095a7..93039ea970f0 100644
--- a/drivers/video/omap2/dss/hdmi_wp.c
+++ b/drivers/video/omap2/dss/hdmi_wp.c
@@ -9,7 +9,6 @@
9 */ 9 */
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/err.h> 12#include <linux/err.h>
14#include <linux/io.h> 13#include <linux/io.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
@@ -17,36 +16,6 @@
17 16
18#include "dss.h" 17#include "dss.h"
19#include "ti_hdmi.h" 18#include "ti_hdmi.h"
20#include "ti_hdmi_4xxx_ip.h"
21
22static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,
23 u32 val)
24{
25 __raw_writel(val, base_addr + idx);
26}
27
28static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)
29{
30 return __raw_readl(base_addr + idx);
31}
32
33#define REG_FLD_MOD(base, idx, val, start, end) \
34 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
35 val, start, end))
36#define REG_GET(base, idx, start, end) \
37 FLD_GET(hdmi_read_reg(base, idx), start, end)
38
39static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
40 const u16 idx, int b2, int b1, u32 val)
41{
42 u32 t = 0;
43 while (val != REG_GET(base_addr, idx, b2, b1)) {
44 udelay(1);
45 if (t++ > 10000)
46 return !val;
47 }
48 return val;
49}
50 19
51void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) 20void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
52{ 21{
diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h
index 107a6061a800..cf096fdb9183 100644
--- a/drivers/video/omap2/dss/ti_hdmi.h
+++ b/drivers/video/omap2/dss/ti_hdmi.h
@@ -21,7 +21,52 @@
21#ifndef _TI_HDMI_H 21#ifndef _TI_HDMI_H
22#define _TI_HDMI_H 22#define _TI_HDMI_H
23 23
24#include <linux/delay.h>
25#include <linux/io.h>
24#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <video/omapdss.h>
28
29#include "dss.h"
30
31/* HDMI Wrapper */
32
33#define HDMI_WP_REVISION 0x0
34#define HDMI_WP_SYSCONFIG 0x10
35#define HDMI_WP_IRQSTATUS_RAW 0x24
36#define HDMI_WP_IRQSTATUS 0x28
37#define HDMI_WP_IRQENABLE_SET 0x2C
38#define HDMI_WP_IRQENABLE_CLR 0x30
39#define HDMI_WP_IRQWAKEEN 0x34
40#define HDMI_WP_PWR_CTRL 0x40
41#define HDMI_WP_DEBOUNCE 0x44
42#define HDMI_WP_VIDEO_CFG 0x50
43#define HDMI_WP_VIDEO_SIZE 0x60
44#define HDMI_WP_VIDEO_TIMING_H 0x68
45#define HDMI_WP_VIDEO_TIMING_V 0x6C
46#define HDMI_WP_WP_CLK 0x70
47#define HDMI_WP_AUDIO_CFG 0x80
48#define HDMI_WP_AUDIO_CFG2 0x84
49#define HDMI_WP_AUDIO_CTRL 0x88
50#define HDMI_WP_AUDIO_DATA 0x8C
51
52/* HDMI PLL */
53
54#define PLLCTRL_PLL_CONTROL 0x0
55#define PLLCTRL_PLL_STATUS 0x4
56#define PLLCTRL_PLL_GO 0x8
57#define PLLCTRL_CFG1 0xC
58#define PLLCTRL_CFG2 0x10
59#define PLLCTRL_CFG3 0x14
60#define PLLCTRL_SSC_CFG1 0x18
61#define PLLCTRL_SSC_CFG2 0x1C
62#define PLLCTRL_CFG4 0x20
63
64/* HDMI PHY */
65
66#define HDMI_TXPHY_TX_CTRL 0x0
67#define HDMI_TXPHY_DIGITAL_CTRL 0x4
68#define HDMI_TXPHY_POWER_CTRL 0x8
69#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
25 70
26enum hdmi_pll_pwr { 71enum hdmi_pll_pwr {
27 HDMI_PLLPWRCMD_ALLOFF = 0, 72 HDMI_PLLPWRCMD_ALLOFF = 0,
@@ -98,6 +143,75 @@ enum hdmi_audio_blk_strt_end_sig {
98 HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1 143 HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
99}; 144};
100 145
146enum hdmi_core_audio_layout {
147 HDMI_AUDIO_LAYOUT_2CH = 0,
148 HDMI_AUDIO_LAYOUT_8CH = 1
149};
150
151enum hdmi_core_cts_mode {
152 HDMI_AUDIO_CTS_MODE_HW = 0,
153 HDMI_AUDIO_CTS_MODE_SW = 1
154};
155
156enum hdmi_audio_mclk_mode {
157 HDMI_AUDIO_MCLK_128FS = 0,
158 HDMI_AUDIO_MCLK_256FS = 1,
159 HDMI_AUDIO_MCLK_384FS = 2,
160 HDMI_AUDIO_MCLK_512FS = 3,
161 HDMI_AUDIO_MCLK_768FS = 4,
162 HDMI_AUDIO_MCLK_1024FS = 5,
163 HDMI_AUDIO_MCLK_1152FS = 6,
164 HDMI_AUDIO_MCLK_192FS = 7
165};
166
167/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
168enum hdmi_core_infoframe {
169 HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
170 HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
171 HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
172 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
173 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1,
174 HDMI_INFOFRAME_AVI_DB1B_NO = 0,
175 HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
176 HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
177 HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
178 HDMI_INFOFRAME_AVI_DB1S_0 = 0,
179 HDMI_INFOFRAME_AVI_DB1S_1 = 1,
180 HDMI_INFOFRAME_AVI_DB1S_2 = 2,
181 HDMI_INFOFRAME_AVI_DB2C_NO = 0,
182 HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
183 HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
184 HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
185 HDMI_INFOFRAME_AVI_DB2M_NO = 0,
186 HDMI_INFOFRAME_AVI_DB2M_43 = 1,
187 HDMI_INFOFRAME_AVI_DB2M_169 = 2,
188 HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
189 HDMI_INFOFRAME_AVI_DB2R_43 = 9,
190 HDMI_INFOFRAME_AVI_DB2R_169 = 10,
191 HDMI_INFOFRAME_AVI_DB2R_149 = 11,
192 HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
193 HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
194 HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
195 HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
196 HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
197 HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
198 HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
199 HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
200 HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
201 HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
202 HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
203 HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
204 HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
205 HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
206 HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
207 HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
208 HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
209 HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
210 HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
211 HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
212 HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
213};
214
101struct hdmi_cm { 215struct hdmi_cm {
102 int code; 216 int code;
103 int mode; 217 int mode;
@@ -143,6 +257,33 @@ struct hdmi_audio_dma {
143 u16 fifo_threshold; 257 u16 fifo_threshold;
144}; 258};
145 259
260struct hdmi_core_audio_i2s_config {
261 u8 in_length_bits;
262 u8 justification;
263 u8 sck_edge_mode;
264 u8 vbit;
265 u8 direction;
266 u8 shift;
267 u8 active_sds;
268};
269
270struct hdmi_core_audio_config {
271 struct hdmi_core_audio_i2s_config i2s_cfg;
272 struct snd_aes_iec958 *iec60958_cfg;
273 bool fs_override;
274 u32 n;
275 u32 cts;
276 u32 aud_par_busclk;
277 enum hdmi_core_audio_layout layout;
278 enum hdmi_core_cts_mode cts_mode;
279 bool use_mclk;
280 enum hdmi_audio_mclk_mode mclk_mode;
281 bool en_acr_pkt;
282 bool en_dsd_audio;
283 bool en_parallel_aud_input;
284 bool en_spdif;
285};
286
146/* 287/*
147 * Refer to section 8.2 in HDMI 1.3 specification for 288 * Refer to section 8.2 in HDMI 1.3 specification for
148 * details about infoframe databytes 289 * details about infoframe databytes
@@ -206,6 +347,35 @@ struct hdmi_core_data {
206 struct hdmi_core_infoframe_avi avi_cfg; 347 struct hdmi_core_infoframe_avi avi_cfg;
207}; 348};
208 349
350static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,
351 u32 val)
352{
353 __raw_writel(val, base_addr + idx);
354}
355
356static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)
357{
358 return __raw_readl(base_addr + idx);
359}
360
361#define REG_FLD_MOD(base, idx, val, start, end) \
362 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
363 val, start, end))
364#define REG_GET(base, idx, start, end) \
365 FLD_GET(hdmi_read_reg(base, idx), start, end)
366
367static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
368 const u16 idx, int b2, int b1, u32 val)
369{
370 u32 t = 0;
371 while (val != REG_GET(base_addr, idx, b2, b1)) {
372 udelay(1);
373 if (t++ > 10000)
374 return !val;
375 }
376 return val;
377}
378
209/* HDMI wrapper funcs */ 379/* HDMI wrapper funcs */
210int hdmi_wp_video_start(struct hdmi_wp_data *wp); 380int hdmi_wp_video_start(struct hdmi_wp_data *wp);
211void hdmi_wp_video_stop(struct hdmi_wp_data *wp); 381void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index 4ac9e0af7ca6..93a99fd080af 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -35,41 +35,10 @@
35#endif 35#endif
36 36
37#include "ti_hdmi_4xxx_ip.h" 37#include "ti_hdmi_4xxx_ip.h"
38#include "dss.h"
39#include "dss_features.h" 38#include "dss_features.h"
40 39
41#define HDMI_CORE_AV 0x500 40#define HDMI_CORE_AV 0x500
42 41
43static inline void hdmi_write_reg(void __iomem *base_addr,
44 const u16 idx, u32 val)
45{
46 __raw_writel(val, base_addr + idx);
47}
48
49static inline u32 hdmi_read_reg(void __iomem *base_addr,
50 const u16 idx)
51{
52 return __raw_readl(base_addr + idx);
53}
54
55#define REG_FLD_MOD(base, idx, val, start, end) \
56 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
57 val, start, end))
58#define REG_GET(base, idx, start, end) \
59 FLD_GET(hdmi_read_reg(base, idx), start, end)
60
61static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
62 const u16 idx, int b2, int b1, u32 val)
63{
64 u32 t = 0;
65 while (val != REG_GET(base_addr, idx, b2, b1)) {
66 udelay(1);
67 if (t++ > 10000)
68 return !val;
69 }
70 return val;
71}
72
73static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core) 42static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core)
74{ 43{
75 return core->base + HDMI_CORE_AV; 44 return core->base + HDMI_CORE_AV;
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index b9bb30004703..78319ff0b227 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -21,32 +21,9 @@
21#ifndef _HDMI_TI_4xxx_H_ 21#ifndef _HDMI_TI_4xxx_H_
22#define _HDMI_TI_4xxx_H_ 22#define _HDMI_TI_4xxx_H_
23 23
24#include <linux/string.h>
25#include <video/omapdss.h>
26#include "ti_hdmi.h" 24#include "ti_hdmi.h"
27 25
28/* HDMI Wrapper */ 26/* OMAP4 HDMI IP Core System */
29
30#define HDMI_WP_REVISION 0x0
31#define HDMI_WP_SYSCONFIG 0x10
32#define HDMI_WP_IRQSTATUS_RAW 0x24
33#define HDMI_WP_IRQSTATUS 0x28
34#define HDMI_WP_IRQENABLE_SET 0x2C
35#define HDMI_WP_IRQENABLE_CLR 0x30
36#define HDMI_WP_IRQWAKEEN 0x34
37#define HDMI_WP_PWR_CTRL 0x40
38#define HDMI_WP_DEBOUNCE 0x44
39#define HDMI_WP_VIDEO_CFG 0x50
40#define HDMI_WP_VIDEO_SIZE 0x60
41#define HDMI_WP_VIDEO_TIMING_H 0x68
42#define HDMI_WP_VIDEO_TIMING_V 0x6C
43#define HDMI_WP_WP_CLK 0x70
44#define HDMI_WP_AUDIO_CFG 0x80
45#define HDMI_WP_AUDIO_CFG2 0x84
46#define HDMI_WP_AUDIO_CTRL 0x88
47#define HDMI_WP_AUDIO_DATA 0x8C
48
49/* HDMI IP Core System */
50 27
51#define HDMI_CORE_SYS_VND_IDL 0x0 28#define HDMI_CORE_SYS_VND_IDL 0x0
52#define HDMI_CORE_SYS_DEV_IDL 0x8 29#define HDMI_CORE_SYS_DEV_IDL 0x8
@@ -207,25 +184,6 @@
207#define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31 184#define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31
208#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31 185#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31
209 186
210/* PLL */
211
212#define PLLCTRL_PLL_CONTROL 0x0
213#define PLLCTRL_PLL_STATUS 0x4
214#define PLLCTRL_PLL_GO 0x8
215#define PLLCTRL_CFG1 0xC
216#define PLLCTRL_CFG2 0x10
217#define PLLCTRL_CFG3 0x14
218#define PLLCTRL_SSC_CFG1 0x18
219#define PLLCTRL_SSC_CFG2 0x1C
220#define PLLCTRL_CFG4 0x20
221
222/* HDMI PHY */
223
224#define HDMI_TXPHY_TX_CTRL 0x0
225#define HDMI_TXPHY_DIGITAL_CTRL 0x4
226#define HDMI_TXPHY_POWER_CTRL 0x8
227#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
228
229enum hdmi_core_inputbus_width { 187enum hdmi_core_inputbus_width {
230 HDMI_INPUT_8BIT = 0, 188 HDMI_INPUT_8BIT = 0,
231 HDMI_INPUT_10BIT = 1, 189 HDMI_INPUT_10BIT = 1,
@@ -268,64 +226,6 @@ enum hdmi_core_packet_ctrl {
268 HDMI_PACKETREPEATOFF = 0 226 HDMI_PACKETREPEATOFF = 0
269}; 227};
270 228
271/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
272enum hdmi_core_infoframe {
273 HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
274 HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
275 HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
276 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
277 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1,
278 HDMI_INFOFRAME_AVI_DB1B_NO = 0,
279 HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
280 HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
281 HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
282 HDMI_INFOFRAME_AVI_DB1S_0 = 0,
283 HDMI_INFOFRAME_AVI_DB1S_1 = 1,
284 HDMI_INFOFRAME_AVI_DB1S_2 = 2,
285 HDMI_INFOFRAME_AVI_DB2C_NO = 0,
286 HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
287 HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
288 HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
289 HDMI_INFOFRAME_AVI_DB2M_NO = 0,
290 HDMI_INFOFRAME_AVI_DB2M_43 = 1,
291 HDMI_INFOFRAME_AVI_DB2M_169 = 2,
292 HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
293 HDMI_INFOFRAME_AVI_DB2R_43 = 9,
294 HDMI_INFOFRAME_AVI_DB2R_169 = 10,
295 HDMI_INFOFRAME_AVI_DB2R_149 = 11,
296 HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
297 HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
298 HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
299 HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
300 HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
301 HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
302 HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
303 HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
304 HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
305 HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
306 HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
307 HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
308 HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
309 HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
310 HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
311 HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
312 HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
313 HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
314 HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
315 HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
316 HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
317};
318
319enum hdmi_core_audio_layout {
320 HDMI_AUDIO_LAYOUT_2CH = 0,
321 HDMI_AUDIO_LAYOUT_8CH = 1
322};
323
324enum hdmi_core_cts_mode {
325 HDMI_AUDIO_CTS_MODE_HW = 0,
326 HDMI_AUDIO_CTS_MODE_SW = 1
327};
328
329enum hdmi_audio_i2s_config { 229enum hdmi_audio_i2s_config {
330 HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0, 230 HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
331 HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1, 231 HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
@@ -341,17 +241,6 @@ enum hdmi_audio_i2s_config {
341 HDMI_AUDIO_I2S_SD3_EN = 1 << 3, 241 HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
342}; 242};
343 243
344enum hdmi_audio_mclk_mode {
345 HDMI_AUDIO_MCLK_128FS = 0,
346 HDMI_AUDIO_MCLK_256FS = 1,
347 HDMI_AUDIO_MCLK_384FS = 2,
348 HDMI_AUDIO_MCLK_512FS = 3,
349 HDMI_AUDIO_MCLK_768FS = 4,
350 HDMI_AUDIO_MCLK_1024FS = 5,
351 HDMI_AUDIO_MCLK_1152FS = 6,
352 HDMI_AUDIO_MCLK_192FS = 7
353};
354
355struct hdmi_core_video_config { 244struct hdmi_core_video_config {
356 enum hdmi_core_inputbus_width ip_bus_width; 245 enum hdmi_core_inputbus_width ip_bus_width;
357 enum hdmi_core_dither_trunc op_dither_truc; 246 enum hdmi_core_dither_trunc op_dither_truc;
@@ -372,34 +261,6 @@ struct hdmi_core_packet_enable_repeat {
372 u32 generic_pkt_repeat; 261 u32 generic_pkt_repeat;
373}; 262};
374 263
375
376struct hdmi_core_audio_i2s_config {
377 u8 in_length_bits;
378 u8 justification;
379 u8 sck_edge_mode;
380 u8 vbit;
381 u8 direction;
382 u8 shift;
383 u8 active_sds;
384};
385
386struct hdmi_core_audio_config {
387 struct hdmi_core_audio_i2s_config i2s_cfg;
388 struct snd_aes_iec958 *iec60958_cfg;
389 bool fs_override;
390 u32 n;
391 u32 cts;
392 u32 aud_par_busclk;
393 enum hdmi_core_audio_layout layout;
394 enum hdmi_core_cts_mode cts_mode;
395 bool use_mclk;
396 enum hdmi_audio_mclk_mode mclk_mode;
397 bool en_acr_pkt;
398 bool en_dsd_audio;
399 bool en_parallel_aud_input;
400 bool en_spdif;
401};
402
403int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len); 264int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len);
404void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 265void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
405 struct hdmi_config *cfg); 266 struct hdmi_config *cfg);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 08:36:52 -0400