aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorShun Fu <fushun@gmail.com>2012-09-23 10:16:14 -0400
committerJames Bottomley <JBottomley@Parallels.com>2012-10-07 06:34:36 -0400
commitbd756ddea18e02ccea8b29496b2fe3bd91af8eb7 (patch)
tree55fbeff97cf94eefd19b9d18ccbc5b969cc56133
parent08bc166d0f2985046f2f6b6f7a1f69c2b2599865 (diff)
[SCSI] mvumi: Add support for Marvell SAS/SATA RAID-on-Chip(ROC) 88RC9580
[jejb: fix up for spelling correction patch] Signed-off-by: Shun Fu <fushun@marvell.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat
-rw-r--r--drivers/scsi/mvumi.c1093
-rw-r--r--drivers/scsi/mvumi.h235
2 files changed, 1068 insertions, 260 deletions
diff --git a/drivers/scsi/mvumi.c b/drivers/scsi/mvumi.c
index 783edc7c6b98..c585a925b3cd 100644
--- a/drivers/scsi/mvumi.c
+++ b/drivers/scsi/mvumi.c
@@ -35,10 +35,12 @@
35#include <linux/io.h> 35#include <linux/io.h>
36#include <scsi/scsi.h> 36#include <scsi/scsi.h>
37#include <scsi/scsi_cmnd.h> 37#include <scsi/scsi_cmnd.h>
38#include <scsi/scsi_device.h>
38#include <scsi/scsi_host.h> 39#include <scsi/scsi_host.h>
39#include <scsi/scsi_transport.h> 40#include <scsi/scsi_transport.h>
40#include <scsi/scsi_eh.h> 41#include <scsi/scsi_eh.h>
41#include <linux/uaccess.h> 42#include <linux/uaccess.h>
43#include <linux/kthread.h>
42 44
43#include "mvumi.h" 45#include "mvumi.h"
44 46
@@ -48,6 +50,7 @@ MODULE_DESCRIPTION("Marvell UMI Driver");
48 50
49static DEFINE_PCI_DEVICE_TABLE(mvumi_pci_table) = { 51static DEFINE_PCI_DEVICE_TABLE(mvumi_pci_table) = {
50 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_2, PCI_DEVICE_ID_MARVELL_MV9143) }, 52 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_2, PCI_DEVICE_ID_MARVELL_MV9143) },
53 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_2, PCI_DEVICE_ID_MARVELL_MV9580) },
51 { 0 } 54 { 0 }
52}; 55};
53 56
@@ -118,7 +121,7 @@ static int mvumi_map_pci_addr(struct pci_dev *dev, void **addr_array)
118static struct mvumi_res *mvumi_alloc_mem_resource(struct mvumi_hba *mhba, 121static struct mvumi_res *mvumi_alloc_mem_resource(struct mvumi_hba *mhba,
119 enum resource_type type, unsigned int size) 122 enum resource_type type, unsigned int size)
120{ 123{
121 struct mvumi_res *res = kzalloc(sizeof(*res), GFP_KERNEL); 124 struct mvumi_res *res = kzalloc(sizeof(*res), GFP_ATOMIC);
122 125
123 if (!res) { 126 if (!res) {
124 dev_err(&mhba->pdev->dev, 127 dev_err(&mhba->pdev->dev,
@@ -128,7 +131,7 @@ static struct mvumi_res *mvumi_alloc_mem_resource(struct mvumi_hba *mhba,
128 131
129 switch (type) { 132 switch (type) {
130 case RESOURCE_CACHED_MEMORY: 133 case RESOURCE_CACHED_MEMORY:
131 res->virt_addr = kzalloc(size, GFP_KERNEL); 134 res->virt_addr = kzalloc(size, GFP_ATOMIC);
132 if (!res->virt_addr) { 135 if (!res->virt_addr) {
133 dev_err(&mhba->pdev->dev, 136 dev_err(&mhba->pdev->dev,
134 "unable to allocate memory,size = %d.\n", size); 137 "unable to allocate memory,size = %d.\n", size);
@@ -222,11 +225,11 @@ static int mvumi_make_sgl(struct mvumi_hba *mhba, struct scsi_cmnd *scmd,
222 m_sg->baseaddr_l = cpu_to_le32(lower_32_bits(busaddr)); 225 m_sg->baseaddr_l = cpu_to_le32(lower_32_bits(busaddr));
223 m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(busaddr)); 226 m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(busaddr));
224 m_sg->flags = 0; 227 m_sg->flags = 0;
225 m_sg->size = cpu_to_le32(sg_dma_len(&sg[i])); 228 sgd_setsz(mhba, m_sg, cpu_to_le32(sg_dma_len(&sg[i])));
226 if ((i + 1) == *sg_count) 229 if ((i + 1) == *sg_count)
227 m_sg->flags |= SGD_EOT; 230 m_sg->flags |= 1U << mhba->eot_flag;
228 231
229 m_sg++; 232 sgd_inc(mhba, m_sg);
230 } 233 }
231 } else { 234 } else {
232 scmd->SCp.dma_handle = scsi_bufflen(scmd) ? 235 scmd->SCp.dma_handle = scsi_bufflen(scmd) ?
@@ -237,8 +240,8 @@ static int mvumi_make_sgl(struct mvumi_hba *mhba, struct scsi_cmnd *scmd,
237 busaddr = scmd->SCp.dma_handle; 240 busaddr = scmd->SCp.dma_handle;
238 m_sg->baseaddr_l = cpu_to_le32(lower_32_bits(busaddr)); 241 m_sg->baseaddr_l = cpu_to_le32(lower_32_bits(busaddr));
239 m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(busaddr)); 242 m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(busaddr));
240 m_sg->flags = SGD_EOT; 243 m_sg->flags = 1U << mhba->eot_flag;
241 m_sg->size = cpu_to_le32(scsi_bufflen(scmd)); 244 sgd_setsz(mhba, m_sg, cpu_to_le32(scsi_bufflen(scmd)));
242 *sg_count = 1; 245 *sg_count = 1;
243 } 246 }
244 247
@@ -267,8 +270,8 @@ static int mvumi_internal_cmd_sgl(struct mvumi_hba *mhba, struct mvumi_cmd *cmd,
267 270
268 m_sg->baseaddr_l = cpu_to_le32(lower_32_bits(phy_addr)); 271 m_sg->baseaddr_l = cpu_to_le32(lower_32_bits(phy_addr));
269 m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(phy_addr)); 272 m_sg->baseaddr_h = cpu_to_le32(upper_32_bits(phy_addr));
270 m_sg->flags = SGD_EOT; 273 m_sg->flags = 1U << mhba->eot_flag;
271 m_sg->size = cpu_to_le32(size); 274 sgd_setsz(mhba, m_sg, cpu_to_le32(size));
272 275
273 return 0; 276 return 0;
274} 277}
@@ -285,7 +288,8 @@ static struct mvumi_cmd *mvumi_create_internal_cmd(struct mvumi_hba *mhba,
285 } 288 }
286 INIT_LIST_HEAD(&cmd->queue_pointer); 289 INIT_LIST_HEAD(&cmd->queue_pointer);
287 290
288 cmd->frame = kzalloc(mhba->ib_max_size, GFP_KERNEL); 291 cmd->frame = pci_alloc_consistent(mhba->pdev,
292 mhba->ib_max_size, &cmd->frame_phys);
289 if (!cmd->frame) { 293 if (!cmd->frame) {
290 dev_err(&mhba->pdev->dev, "failed to allocate memory for FW" 294 dev_err(&mhba->pdev->dev, "failed to allocate memory for FW"
291 " frame,size = %d.\n", mhba->ib_max_size); 295 " frame,size = %d.\n", mhba->ib_max_size);
@@ -297,7 +301,8 @@ static struct mvumi_cmd *mvumi_create_internal_cmd(struct mvumi_hba *mhba,
297 if (mvumi_internal_cmd_sgl(mhba, cmd, buf_size)) { 301 if (mvumi_internal_cmd_sgl(mhba, cmd, buf_size)) {
298 dev_err(&mhba->pdev->dev, "failed to allocate memory" 302 dev_err(&mhba->pdev->dev, "failed to allocate memory"
299 " for internal frame\n"); 303 " for internal frame\n");
300 kfree(cmd->frame); 304 pci_free_consistent(mhba->pdev, mhba->ib_max_size,
305 cmd->frame, cmd->frame_phys);
301 kfree(cmd); 306 kfree(cmd);
302 return NULL; 307 return NULL;
303 } 308 }
@@ -317,7 +322,7 @@ static void mvumi_delete_internal_cmd(struct mvumi_hba *mhba,
317 if (cmd && cmd->frame) { 322 if (cmd && cmd->frame) {
318 if (cmd->frame->sg_counts) { 323 if (cmd->frame->sg_counts) {
319 m_sg = (struct mvumi_sgl *) &cmd->frame->payload[0]; 324 m_sg = (struct mvumi_sgl *) &cmd->frame->payload[0];
320 size = m_sg->size; 325 sgd_getsz(mhba, m_sg, size);
321 326
322 phy_addr = (dma_addr_t) m_sg->baseaddr_l | 327 phy_addr = (dma_addr_t) m_sg->baseaddr_l |
323 (dma_addr_t) ((m_sg->baseaddr_h << 16) << 16); 328 (dma_addr_t) ((m_sg->baseaddr_h << 16) << 16);
@@ -325,7 +330,8 @@ static void mvumi_delete_internal_cmd(struct mvumi_hba *mhba,
325 pci_free_consistent(mhba->pdev, size, cmd->data_buf, 330 pci_free_consistent(mhba->pdev, size, cmd->data_buf,
326 phy_addr); 331 phy_addr);
327 } 332 }
328 kfree(cmd->frame); 333 pci_free_consistent(mhba->pdev, mhba->ib_max_size,
334 cmd->frame, cmd->frame_phys);
329 kfree(cmd); 335 kfree(cmd);
330 } 336 }
331} 337}
@@ -374,7 +380,8 @@ static void mvumi_free_cmds(struct mvumi_hba *mhba)
374 cmd = list_first_entry(&mhba->cmd_pool, struct mvumi_cmd, 380 cmd = list_first_entry(&mhba->cmd_pool, struct mvumi_cmd,
375 queue_pointer); 381 queue_pointer);
376 list_del(&cmd->queue_pointer); 382 list_del(&cmd->queue_pointer);
377 kfree(cmd->frame); 383 if (!(mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC))
384 kfree(cmd->frame);
378 kfree(cmd); 385 kfree(cmd);
379 } 386 }
380} 387}
@@ -396,7 +403,12 @@ static int mvumi_alloc_cmds(struct mvumi_hba *mhba)
396 403
397 INIT_LIST_HEAD(&cmd->queue_pointer); 404 INIT_LIST_HEAD(&cmd->queue_pointer);
398 list_add_tail(&cmd->queue_pointer, &mhba->cmd_pool); 405 list_add_tail(&cmd->queue_pointer, &mhba->cmd_pool);
399 cmd->frame = kzalloc(mhba->ib_max_size, GFP_KERNEL); 406 if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC) {
407 cmd->frame = mhba->ib_frame + i * mhba->ib_max_size;
408 cmd->frame_phys = mhba->ib_frame_phys
409 + i * mhba->ib_max_size;
410 } else
411 cmd->frame = kzalloc(mhba->ib_max_size, GFP_KERNEL);
400 if (!cmd->frame) 412 if (!cmd->frame)
401 goto err_exit; 413 goto err_exit;
402 } 414 }
@@ -409,48 +421,71 @@ err_exit:
409 cmd = list_first_entry(&mhba->cmd_pool, struct mvumi_cmd, 421 cmd = list_first_entry(&mhba->cmd_pool, struct mvumi_cmd,
410 queue_pointer); 422 queue_pointer);
411 list_del(&cmd->queue_pointer); 423 list_del(&cmd->queue_pointer);
412 kfree(cmd->frame); 424 if (!(mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC))
425 kfree(cmd->frame);
413 kfree(cmd); 426 kfree(cmd);
414 } 427 }
415 return -ENOMEM; 428 return -ENOMEM;
416} 429}
417 430
418static int mvumi_get_ib_list_entry(struct mvumi_hba *mhba, void **ib_entry) 431static unsigned int mvumi_check_ib_list_9143(struct mvumi_hba *mhba)
419{ 432{
420 unsigned int ib_rp_reg, cur_ib_entry; 433 unsigned int ib_rp_reg;
434 struct mvumi_hw_regs *regs = mhba->regs;
435
436 ib_rp_reg = ioread32(mhba->regs->inb_read_pointer);
421 437
438 if (unlikely(((ib_rp_reg & regs->cl_slot_num_mask) ==
439 (mhba->ib_cur_slot & regs->cl_slot_num_mask)) &&
440 ((ib_rp_reg & regs->cl_pointer_toggle)
441 != (mhba->ib_cur_slot & regs->cl_pointer_toggle)))) {
442 dev_warn(&mhba->pdev->dev, "no free slot to use.\n");
443 return 0;
444 }
422 if (atomic_read(&mhba->fw_outstanding) >= mhba->max_io) { 445 if (atomic_read(&mhba->fw_outstanding) >= mhba->max_io) {
423 dev_warn(&mhba->pdev->dev, "firmware io overflow.\n"); 446 dev_warn(&mhba->pdev->dev, "firmware io overflow.\n");
424 return -1; 447 return 0;
448 } else {
449 return mhba->max_io - atomic_read(&mhba->fw_outstanding);
425 } 450 }
426 ib_rp_reg = ioread32(mhba->mmio + CLA_INB_READ_POINTER); 451}
427 452
428 if (unlikely(((ib_rp_reg & CL_SLOT_NUM_MASK) == 453static unsigned int mvumi_check_ib_list_9580(struct mvumi_hba *mhba)
429 (mhba->ib_cur_slot & CL_SLOT_NUM_MASK)) && 454{
430 ((ib_rp_reg & CL_POINTER_TOGGLE) != 455 unsigned int count;
431 (mhba->ib_cur_slot & CL_POINTER_TOGGLE)))) { 456 if (atomic_read(&mhba->fw_outstanding) >= (mhba->max_io - 1))
432 dev_warn(&mhba->pdev->dev, "no free slot to use.\n"); 457 return 0;
433 return -1; 458 count = ioread32(mhba->ib_shadow);
434 } 459 if (count == 0xffff)
460 return 0;
461 return count;
462}
463
464static void mvumi_get_ib_list_entry(struct mvumi_hba *mhba, void **ib_entry)
465{
466 unsigned int cur_ib_entry;
435 467
436 cur_ib_entry = mhba->ib_cur_slot & CL_SLOT_NUM_MASK; 468 cur_ib_entry = mhba->ib_cur_slot & mhba->regs->cl_slot_num_mask;
437 cur_ib_entry++; 469 cur_ib_entry++;
438 if (cur_ib_entry >= mhba->list_num_io) { 470 if (cur_ib_entry >= mhba->list_num_io) {
439 cur_ib_entry -= mhba->list_num_io; 471 cur_ib_entry -= mhba->list_num_io;
440 mhba->ib_cur_slot ^= CL_POINTER_TOGGLE; 472 mhba->ib_cur_slot ^= mhba->regs->cl_pointer_toggle;
473 }
474 mhba->ib_cur_slot &= ~mhba->regs->cl_slot_num_mask;
475 mhba->ib_cur_slot |= (cur_ib_entry & mhba->regs->cl_slot_num_mask);
476 if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC) {
477 *ib_entry = mhba->ib_list + cur_ib_entry *
478 sizeof(struct mvumi_dyn_list_entry);
479 } else {
480 *ib_entry = mhba->ib_list + cur_ib_entry * mhba->ib_max_size;
441 } 481 }
442 mhba->ib_cur_slot &= ~CL_SLOT_NUM_MASK;
443 mhba->ib_cur_slot |= (cur_ib_entry & CL_SLOT_NUM_MASK);
444 *ib_entry = mhba->ib_list + cur_ib_entry * mhba->ib_max_size;
445 atomic_inc(&mhba->fw_outstanding); 482 atomic_inc(&mhba->fw_outstanding);
446
447 return 0;
448} 483}
449 484
450static void mvumi_send_ib_list_entry(struct mvumi_hba *mhba) 485static void mvumi_send_ib_list_entry(struct mvumi_hba *mhba)
451{ 486{
452 iowrite32(0xfff, mhba->ib_shadow); 487 iowrite32(0xffff, mhba->ib_shadow);
453 iowrite32(mhba->ib_cur_slot, mhba->mmio + CLA_INB_WRITE_POINTER); 488 iowrite32(mhba->ib_cur_slot, mhba->regs->inb_write_pointer);
454} 489}
455 490
456static char mvumi_check_ob_frame(struct mvumi_hba *mhba, 491static char mvumi_check_ob_frame(struct mvumi_hba *mhba,
@@ -480,31 +515,59 @@ static char mvumi_check_ob_frame(struct mvumi_hba *mhba,
480 return 0; 515 return 0;
481} 516}
482 517
483static void mvumi_receive_ob_list_entry(struct mvumi_hba *mhba) 518static int mvumi_check_ob_list_9143(struct mvumi_hba *mhba,
519 unsigned int *cur_obf, unsigned int *assign_obf_end)
484{ 520{
485 unsigned int ob_write_reg, ob_write_shadow_reg; 521 unsigned int ob_write, ob_write_shadow;
486 unsigned int cur_obf, assign_obf_end, i; 522 struct mvumi_hw_regs *regs = mhba->regs;
487 struct mvumi_ob_data *ob_data;
488 struct mvumi_rsp_frame *p_outb_frame;
489 523
490 do { 524 do {
491 ob_write_reg = ioread32(mhba->mmio + CLA_OUTB_COPY_POINTER); 525 ob_write = ioread32(regs->outb_copy_pointer);
492 ob_write_shadow_reg = ioread32(mhba->ob_shadow); 526 ob_write_shadow = ioread32(mhba->ob_shadow);
493 } while ((ob_write_reg & CL_SLOT_NUM_MASK) != ob_write_shadow_reg); 527 } while ((ob_write & regs->cl_slot_num_mask) != ob_write_shadow);
494 528
495 cur_obf = mhba->ob_cur_slot & CL_SLOT_NUM_MASK; 529 *cur_obf = mhba->ob_cur_slot & mhba->regs->cl_slot_num_mask;
496 assign_obf_end = ob_write_reg & CL_SLOT_NUM_MASK; 530 *assign_obf_end = ob_write & mhba->regs->cl_slot_num_mask;
497 531
498 if ((ob_write_reg & CL_POINTER_TOGGLE) != 532 if ((ob_write & regs->cl_pointer_toggle) !=
499 (mhba->ob_cur_slot & CL_POINTER_TOGGLE)) { 533 (mhba->ob_cur_slot & regs->cl_pointer_toggle)) {
500 assign_obf_end += mhba->list_num_io; 534 *assign_obf_end += mhba->list_num_io;
501 } 535 }
536 return 0;
537}
538
539static int mvumi_check_ob_list_9580(struct mvumi_hba *mhba,
540 unsigned int *cur_obf, unsigned int *assign_obf_end)
541{
542 unsigned int ob_write;
543 struct mvumi_hw_regs *regs = mhba->regs;
544
545 ob_write = ioread32(regs->outb_read_pointer);
546 ob_write = ioread32(regs->outb_copy_pointer);
547 *cur_obf = mhba->ob_cur_slot & mhba->regs->cl_slot_num_mask;
548 *assign_obf_end = ob_write & mhba->regs->cl_slot_num_mask;
549 if (*assign_obf_end < *cur_obf)
550 *assign_obf_end += mhba->list_num_io;
551 else if (*assign_obf_end == *cur_obf)
552 return -1;
553 return 0;
554}
555
556static void mvumi_receive_ob_list_entry(struct mvumi_hba *mhba)
557{
558 unsigned int cur_obf, assign_obf_end, i;
559 struct mvumi_ob_data *ob_data;
560 struct mvumi_rsp_frame *p_outb_frame;
561 struct mvumi_hw_regs *regs = mhba->regs;
562
563 if (mhba->instancet->check_ob_list(mhba, &cur_obf, &assign_obf_end))
564 return;
502 565
503 for (i = (assign_obf_end - cur_obf); i != 0; i--) { 566 for (i = (assign_obf_end - cur_obf); i != 0; i--) {
504 cur_obf++; 567 cur_obf++;
505 if (cur_obf >= mhba->list_num_io) { 568 if (cur_obf >= mhba->list_num_io) {
506 cur_obf -= mhba->list_num_io; 569 cur_obf -= mhba->list_num_io;
507 mhba->ob_cur_slot ^= CL_POINTER_TOGGLE; 570 mhba->ob_cur_slot ^= regs->cl_pointer_toggle;
508 } 571 }
509 572
510 p_outb_frame = mhba->ob_list + cur_obf * mhba->ob_max_size; 573 p_outb_frame = mhba->ob_list + cur_obf * mhba->ob_max_size;
@@ -528,7 +591,7 @@ static void mvumi_receive_ob_list_entry(struct mvumi_hba *mhba)
528 ob_data = NULL; 591 ob_data = NULL;
529 if (cur_obf == 0) { 592 if (cur_obf == 0) {
530 cur_obf = mhba->list_num_io - 1; 593 cur_obf = mhba->list_num_io - 1;
531 mhba->ob_cur_slot ^= CL_POINTER_TOGGLE; 594 mhba->ob_cur_slot ^= regs->cl_pointer_toggle;
532 } else 595 } else
533 cur_obf -= 1; 596 cur_obf -= 1;
534 break; 597 break;
@@ -539,18 +602,20 @@ static void mvumi_receive_ob_list_entry(struct mvumi_hba *mhba)
539 602
540 list_add_tail(&ob_data->list, &mhba->free_ob_list); 603 list_add_tail(&ob_data->list, &mhba->free_ob_list);
541 } 604 }
542 mhba->ob_cur_slot &= ~CL_SLOT_NUM_MASK; 605 mhba->ob_cur_slot &= ~regs->cl_slot_num_mask;
543 mhba->ob_cur_slot |= (cur_obf & CL_SLOT_NUM_MASK); 606 mhba->ob_cur_slot |= (cur_obf & regs->cl_slot_num_mask);
544 iowrite32(mhba->ob_cur_slot, mhba->mmio + CLA_OUTB_READ_POINTER); 607 iowrite32(mhba->ob_cur_slot, regs->outb_read_pointer);
545} 608}
546 609
547static void mvumi_reset(void *regs) 610static void mvumi_reset(struct mvumi_hba *mhba)
548{ 611{
549 iowrite32(0, regs + CPU_ENPOINTA_MASK_REG); 612 struct mvumi_hw_regs *regs = mhba->regs;
550 if (ioread32(regs + CPU_ARM_TO_PCIEA_MSG1) != HANDSHAKE_DONESTATE) 613
614 iowrite32(0, regs->enpointa_mask_reg);
615 if (ioread32(regs->arm_to_pciea_msg1) != HANDSHAKE_DONESTATE)
551 return; 616 return;
552 617
553 iowrite32(DRBL_SOFT_RESET, regs + CPU_PCIEA_TO_ARM_DRBL_REG); 618 iowrite32(DRBL_SOFT_RESET, regs->pciea_to_arm_drbl_reg);
554} 619}
555 620
556static unsigned char mvumi_start(struct mvumi_hba *mhba); 621static unsigned char mvumi_start(struct mvumi_hba *mhba);
@@ -558,7 +623,7 @@ static unsigned char mvumi_start(struct mvumi_hba *mhba);
558static int mvumi_wait_for_outstanding(struct mvumi_hba *mhba) 623static int mvumi_wait_for_outstanding(struct mvumi_hba *mhba)
559{ 624{
560 mhba->fw_state = FW_STATE_ABORT; 625 mhba->fw_state = FW_STATE_ABORT;
561 mvumi_reset(mhba->mmio); 626 mvumi_reset(mhba);
562 627
563 if (mvumi_start(mhba)) 628 if (mvumi_start(mhba))
564 return FAILED; 629 return FAILED;
@@ -566,6 +631,98 @@ static int mvumi_wait_for_outstanding(struct mvumi_hba *mhba)
566 return SUCCESS; 631 return SUCCESS;
567} 632}
568 633
634static int mvumi_wait_for_fw(struct mvumi_hba *mhba)
635{
636 struct mvumi_hw_regs *regs = mhba->regs;
637 u32 tmp;
638 unsigned long before;
639 before = jiffies;
640
641 iowrite32(0, regs->enpointa_mask_reg);
642 tmp = ioread32(regs->arm_to_pciea_msg1);
643 while (tmp != HANDSHAKE_READYSTATE) {
644 iowrite32(DRBL_MU_RESET, regs->pciea_to_arm_drbl_reg);
645 if (time_after(jiffies, before + FW_MAX_DELAY * HZ)) {
646 dev_err(&mhba->pdev->dev,
647 "FW reset failed [0x%x].\n", tmp);
648 return FAILED;
649 }
650
651 msleep(500);
652 rmb();
653 tmp = ioread32(regs->arm_to_pciea_msg1);
654 }
655
656 return SUCCESS;
657}
658
659static void mvumi_backup_bar_addr(struct mvumi_hba *mhba)
660{
661 unsigned char i;
662
663 for (i = 0; i < MAX_BASE_ADDRESS; i++) {
664 pci_read_config_dword(mhba->pdev, 0x10 + i * 4,
665 &mhba->pci_base[i]);
666 }
667}
668
669static void mvumi_restore_bar_addr(struct mvumi_hba *mhba)
670{
671 unsigned char i;
672
673 for (i = 0; i < MAX_BASE_ADDRESS; i++) {
674 if (mhba->pci_base[i])
675 pci_write_config_dword(mhba->pdev, 0x10 + i * 4,
676 mhba->pci_base[i]);
677 }
678}
679
680static unsigned int mvumi_pci_set_master(struct pci_dev *pdev)
681{
682 unsigned int ret = 0;
683 pci_set_master(pdev);
684
685 if (IS_DMA64) {
686 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
687 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
688 } else
689 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
690
691 return ret;
692}
693
694static int mvumi_reset_host_9580(struct mvumi_hba *mhba)
695{
696 mhba->fw_state = FW_STATE_ABORT;
697
698 iowrite32(0, mhba->regs->reset_enable);
699 iowrite32(0xf, mhba->regs->reset_request);
700
701 iowrite32(0x10, mhba->regs->reset_enable);
702 iowrite32(0x10, mhba->regs->reset_request);
703 msleep(100);
704 pci_disable_device(mhba->pdev);
705
706 if (pci_enable_device(mhba->pdev)) {
707 dev_err(&mhba->pdev->dev, "enable device failed\n");
708 return FAILED;
709 }
710 if (mvumi_pci_set_master(mhba->pdev)) {
711 dev_err(&mhba->pdev->dev, "set master failed\n");
712 return FAILED;
713 }
714 mvumi_restore_bar_addr(mhba);
715 if (mvumi_wait_for_fw(mhba) == FAILED)
716 return FAILED;
717
718 return mvumi_wait_for_outstanding(mhba);
719}
720
721static int mvumi_reset_host_9143(struct mvumi_hba *mhba)
722{
723 return mvumi_wait_for_outstanding(mhba);
724}
725
569static int mvumi_host_reset(struct scsi_cmnd *scmd) 726static int mvumi_host_reset(struct scsi_cmnd *scmd)
570{ 727{
571 struct mvumi_hba *mhba; 728 struct mvumi_hba *mhba;
@@ -575,7 +732,7 @@ static int mvumi_host_reset(struct scsi_cmnd *scmd)
575 scmd_printk(KERN_NOTICE, scmd, "RESET -%ld cmd=%x retries=%x\n", 732 scmd_printk(KERN_NOTICE, scmd, "RESET -%ld cmd=%x retries=%x\n",
576 scmd->serial_number, scmd->cmnd[0], scmd->retries); 733 scmd->serial_number, scmd->cmnd[0], scmd->retries);
577 734
578 return mvumi_wait_for_outstanding(mhba); 735 return mhba->instancet->reset_host(mhba);
579} 736}
580 737
581static int mvumi_issue_blocked_cmd(struct mvumi_hba *mhba, 738static int mvumi_issue_blocked_cmd(struct mvumi_hba *mhba,
@@ -628,7 +785,9 @@ static void mvumi_release_fw(struct mvumi_hba *mhba)
628 mvumi_free_cmds(mhba); 785 mvumi_free_cmds(mhba);
629 mvumi_release_mem_resource(mhba); 786 mvumi_release_mem_resource(mhba);
630 mvumi_unmap_pci_addr(mhba->pdev, mhba->base_addr); 787 mvumi_unmap_pci_addr(mhba->pdev, mhba->base_addr);
631 kfree(mhba->handshake_page); 788 pci_free_consistent(mhba->pdev, HSP_MAX_SIZE,
789 mhba->handshake_page, mhba->handshake_page_phys);
790 kfree(mhba->regs);
632 pci_release_regions(mhba->pdev); 791 pci_release_regions(mhba->pdev);
633} 792}
634 793
@@ -665,6 +824,7 @@ get_cmd: cmd = mvumi_create_internal_cmd(mhba, 0);
665 frame->cdb_length = MAX_COMMAND_SIZE; 824 frame->cdb_length = MAX_COMMAND_SIZE;
666 memset(frame->cdb, 0, MAX_COMMAND_SIZE); 825 memset(frame->cdb, 0, MAX_COMMAND_SIZE);
667 frame->cdb[0] = SCSI_CMD_MARVELL_SPECIFIC; 826 frame->cdb[0] = SCSI_CMD_MARVELL_SPECIFIC;
827 frame->cdb[1] = CDB_CORE_MODULE;
668 frame->cdb[2] = CDB_CORE_SHUTDOWN; 828 frame->cdb[2] = CDB_CORE_SHUTDOWN;
669 829
670 mvumi_issue_blocked_cmd(mhba, cmd); 830 mvumi_issue_blocked_cmd(mhba, cmd);
@@ -695,7 +855,7 @@ mvumi_calculate_checksum(struct mvumi_hs_header *p_header,
695 return ret; 855 return ret;
696} 856}
697 857
698void mvumi_hs_build_page(struct mvumi_hba *mhba, 858static void mvumi_hs_build_page(struct mvumi_hba *mhba,
699 struct mvumi_hs_header *hs_header) 859 struct mvumi_hs_header *hs_header)
700{ 860{
701 struct mvumi_hs_page2 *hs_page2; 861 struct mvumi_hs_page2 *hs_page2;
@@ -710,6 +870,8 @@ void mvumi_hs_build_page(struct mvumi_hba *mhba,
710 hs_header->frame_length = sizeof(*hs_page2) - 4; 870 hs_header->frame_length = sizeof(*hs_page2) - 4;
711 memset(hs_header->frame_content, 0, hs_header->frame_length); 871 memset(hs_header->frame_content, 0, hs_header->frame_length);
712 hs_page2->host_type = 3; /* 3 mean linux*/ 872 hs_page2->host_type = 3; /* 3 mean linux*/
873 if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC)
874 hs_page2->host_cap = 0x08;/* host dynamic source mode */
713 hs_page2->host_ver.ver_major = VER_MAJOR; 875 hs_page2->host_ver.ver_major = VER_MAJOR;
714 hs_page2->host_ver.ver_minor = VER_MINOR; 876 hs_page2->host_ver.ver_minor = VER_MINOR;
715 hs_page2->host_ver.ver_oem = VER_OEM; 877 hs_page2->host_ver.ver_oem = VER_OEM;
@@ -745,8 +907,18 @@ void mvumi_hs_build_page(struct mvumi_hba *mhba,
745 hs_page4->ob_baseaddr_h = upper_32_bits(mhba->ob_list_phys); 907 hs_page4->ob_baseaddr_h = upper_32_bits(mhba->ob_list_phys);
746 hs_page4->ib_entry_size = mhba->ib_max_size_setting; 908 hs_page4->ib_entry_size = mhba->ib_max_size_setting;
747 hs_page4->ob_entry_size = mhba->ob_max_size_setting; 909 hs_page4->ob_entry_size = mhba->ob_max_size_setting;
748 hs_page4->ob_depth = mhba->list_num_io; 910 if (mhba->hba_capability
749 hs_page4->ib_depth = mhba->list_num_io; 911 & HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF) {
912 hs_page4->ob_depth = find_first_bit((unsigned long *)
913 &mhba->list_num_io,
914 BITS_PER_LONG);
915 hs_page4->ib_depth = find_first_bit((unsigned long *)
916 &mhba->list_num_io,
917 BITS_PER_LONG);
918 } else {
919 hs_page4->ob_depth = (u8) mhba->list_num_io;
920 hs_page4->ib_depth = (u8) mhba->list_num_io;
921 }
750 hs_header->checksum = mvumi_calculate_checksum(hs_header, 922 hs_header->checksum = mvumi_calculate_checksum(hs_header,
751 hs_header->frame_length); 923 hs_header->frame_length);
752 break; 924 break;
@@ -774,8 +946,11 @@ static int mvumi_init_data(struct mvumi_hba *mhba)
774 return 0; 946 return 0;
775 947
776 tmp_size = mhba->ib_max_size * mhba->max_io; 948 tmp_size = mhba->ib_max_size * mhba->max_io;
949 if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC)
950 tmp_size += sizeof(struct mvumi_dyn_list_entry) * mhba->max_io;
951
777 tmp_size += 128 + mhba->ob_max_size * mhba->max_io; 952 tmp_size += 128 + mhba->ob_max_size * mhba->max_io;
778 tmp_size += 8 + sizeof(u32) + 16; 953 tmp_size += 8 + sizeof(u32)*2 + 16;
779 954
780 res_mgnt = mvumi_alloc_mem_resource(mhba, 955 res_mgnt = mvumi_alloc_mem_resource(mhba,
781 RESOURCE_UNCACHED_MEMORY, tmp_size); 956 RESOURCE_UNCACHED_MEMORY, tmp_size);
@@ -793,24 +968,41 @@ static int mvumi_init_data(struct mvumi_hba *mhba)
793 v += offset; 968 v += offset;
794 mhba->ib_list = v; 969 mhba->ib_list = v;
795 mhba->ib_list_phys = p; 970 mhba->ib_list_phys = p;
971 if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC) {
972 v += sizeof(struct mvumi_dyn_list_entry) * mhba->max_io;
973 p += sizeof(struct mvumi_dyn_list_entry) * mhba->max_io;
974 mhba->ib_frame = v;
975 mhba->ib_frame_phys = p;
976 }
796 v += mhba->ib_max_size * mhba->max_io; 977 v += mhba->ib_max_size * mhba->max_io;
797 p += mhba->ib_max_size * mhba->max_io; 978 p += mhba->ib_max_size * mhba->max_io;
979
798 /* ib shadow */ 980 /* ib shadow */
799 offset = round_up(p, 8) - p; 981 offset = round_up(p, 8) - p;
800 p += offset; 982 p += offset;
801 v += offset; 983 v += offset;
802 mhba->ib_shadow = v; 984 mhba->ib_shadow = v;
803 mhba->ib_shadow_phys = p; 985 mhba->ib_shadow_phys = p;
804 p += sizeof(u32); 986 p += sizeof(u32)*2;
805 v += sizeof(u32); 987 v += sizeof(u32)*2;
806 /* ob shadow */ 988 /* ob shadow */
807 offset = round_up(p, 8) - p; 989 if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9580) {
808 p += offset; 990 offset = round_up(p, 8) - p;
809 v += offset; 991 p += offset;
810 mhba->ob_shadow = v; 992 v += offset;
811 mhba->ob_shadow_phys = p; 993 mhba->ob_shadow = v;
812 p += 8; 994 mhba->ob_shadow_phys = p;
813 v += 8; 995 p += 8;
996 v += 8;
997 } else {
998 offset = round_up(p, 4) - p;
999 p += offset;
1000 v += offset;
1001 mhba->ob_shadow = v;
1002 mhba->ob_shadow_phys = p;
1003 p += 4;
1004 v += 4;
1005 }
814 1006
815 /* ob list */ 1007 /* ob list */
816 offset = round_up(p, 128) - p; 1008 offset = round_up(p, 128) - p;
@@ -902,6 +1094,12 @@ static int mvumi_hs_process_page(struct mvumi_hba *mhba,
902 dev_dbg(&mhba->pdev->dev, "FW version:%d\n", 1094 dev_dbg(&mhba->pdev->dev, "FW version:%d\n",
903 hs_page1->fw_ver.ver_build); 1095 hs_page1->fw_ver.ver_build);
904 1096
1097 if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG)
1098 mhba->eot_flag = 22;
1099 else
1100 mhba->eot_flag = 27;
1101 if (mhba->hba_capability & HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF)
1102 mhba->list_num_io = 1 << hs_page1->cl_inout_list_depth;
905 break; 1103 break;
906 default: 1104 default:
907 dev_err(&mhba->pdev->dev, "handshake: page code error\n"); 1105 dev_err(&mhba->pdev->dev, "handshake: page code error\n");
@@ -923,12 +1121,12 @@ static int mvumi_handshake(struct mvumi_hba *mhba)
923{ 1121{
924 unsigned int hs_state, tmp, hs_fun; 1122 unsigned int hs_state, tmp, hs_fun;
925 struct mvumi_hs_header *hs_header; 1123 struct mvumi_hs_header *hs_header;
926 void *regs = mhba->mmio; 1124 struct mvumi_hw_regs *regs = mhba->regs;
927 1125
928 if (mhba->fw_state == FW_STATE_STARTING) 1126 if (mhba->fw_state == FW_STATE_STARTING)
929 hs_state = HS_S_START; 1127 hs_state = HS_S_START;
930 else { 1128 else {
931 tmp = ioread32(regs + CPU_ARM_TO_PCIEA_MSG0); 1129 tmp = ioread32(regs->arm_to_pciea_msg0);
932 hs_state = HS_GET_STATE(tmp); 1130 hs_state = HS_GET_STATE(tmp);
933 dev_dbg(&mhba->pdev->dev, "handshake state[0x%x].\n", hs_state); 1131 dev_dbg(&mhba->pdev->dev, "handshake state[0x%x].\n", hs_state);
934 if (HS_GET_STATUS(tmp) != HS_STATUS_OK) { 1132 if (HS_GET_STATUS(tmp) != HS_STATUS_OK) {
@@ -943,21 +1141,20 @@ static int mvumi_handshake(struct mvumi_hba *mhba)
943 mhba->fw_state = FW_STATE_HANDSHAKING; 1141 mhba->fw_state = FW_STATE_HANDSHAKING;
944 HS_SET_STATUS(hs_fun, HS_STATUS_OK); 1142 HS_SET_STATUS(hs_fun, HS_STATUS_OK);
945 HS_SET_STATE(hs_fun, HS_S_RESET); 1143 HS_SET_STATE(hs_fun, HS_S_RESET);
946 iowrite32(HANDSHAKE_SIGNATURE, regs + CPU_PCIEA_TO_ARM_MSG1); 1144 iowrite32(HANDSHAKE_SIGNATURE, regs->pciea_to_arm_msg1);
947 iowrite32(hs_fun, regs + CPU_PCIEA_TO_ARM_MSG0); 1145 iowrite32(hs_fun, regs->pciea_to_arm_msg0);
948 iowrite32(DRBL_HANDSHAKE, regs + CPU_PCIEA_TO_ARM_DRBL_REG); 1146 iowrite32(DRBL_HANDSHAKE, regs->pciea_to_arm_drbl_reg);
949 break; 1147 break;
950 1148
951 case HS_S_RESET: 1149 case HS_S_RESET:
952 iowrite32(lower_32_bits(mhba->handshake_page_phys), 1150 iowrite32(lower_32_bits(mhba->handshake_page_phys),
953 regs + CPU_PCIEA_TO_ARM_MSG1); 1151 regs->pciea_to_arm_msg1);
954 iowrite32(upper_32_bits(mhba->handshake_page_phys), 1152 iowrite32(upper_32_bits(mhba->handshake_page_phys),
955 regs + CPU_ARM_TO_PCIEA_MSG1); 1153 regs->arm_to_pciea_msg1);
956 HS_SET_STATUS(hs_fun, HS_STATUS_OK); 1154 HS_SET_STATUS(hs_fun, HS_STATUS_OK);
957 HS_SET_STATE(hs_fun, HS_S_PAGE_ADDR); 1155 HS_SET_STATE(hs_fun, HS_S_PAGE_ADDR);
958 iowrite32(hs_fun, regs + CPU_PCIEA_TO_ARM_MSG0); 1156 iowrite32(hs_fun, regs->pciea_to_arm_msg0);
959 iowrite32(DRBL_HANDSHAKE, regs + CPU_PCIEA_TO_ARM_DRBL_REG); 1157 iowrite32(DRBL_HANDSHAKE, regs->pciea_to_arm_drbl_reg);
960
961 break; 1158 break;
962 1159
963 case HS_S_PAGE_ADDR: 1160 case HS_S_PAGE_ADDR:
@@ -997,30 +1194,37 @@ static int mvumi_handshake(struct mvumi_hba *mhba)
997 HS_SET_STATE(hs_fun, HS_S_END); 1194 HS_SET_STATE(hs_fun, HS_S_END);
998 1195
999 HS_SET_STATUS(hs_fun, HS_STATUS_OK); 1196 HS_SET_STATUS(hs_fun, HS_STATUS_OK);
1000 iowrite32(hs_fun, regs + CPU_PCIEA_TO_ARM_MSG0); 1197 iowrite32(hs_fun, regs->pciea_to_arm_msg0);
1001 iowrite32(DRBL_HANDSHAKE, regs + CPU_PCIEA_TO_ARM_DRBL_REG); 1198 iowrite32(DRBL_HANDSHAKE, regs->pciea_to_arm_drbl_reg);
1002 break; 1199 break;
1003 1200
1004 case HS_S_END: 1201 case HS_S_END:
1005 /* Set communication list ISR */ 1202 /* Set communication list ISR */
1006 tmp = ioread32(regs + CPU_ENPOINTA_MASK_REG); 1203 tmp = ioread32(regs->enpointa_mask_reg);
1007 tmp |= INT_MAP_COMAOUT | INT_MAP_COMAERR; 1204 tmp |= regs->int_comaout | regs->int_comaerr;
1008 iowrite32(tmp, regs + CPU_ENPOINTA_MASK_REG); 1205 iowrite32(tmp, regs->enpointa_mask_reg);
1009 iowrite32(mhba->list_num_io, mhba->ib_shadow); 1206 iowrite32(mhba->list_num_io, mhba->ib_shadow);
1010 /* Set InBound List Available count shadow */ 1207 /* Set InBound List Available count shadow */
1011 iowrite32(lower_32_bits(mhba->ib_shadow_phys), 1208 iowrite32(lower_32_bits(mhba->ib_shadow_phys),
1012 regs + CLA_INB_AVAL_COUNT_BASEL); 1209 regs->inb_aval_count_basel);
1013 iowrite32(upper_32_bits(mhba->ib_shadow_phys), 1210 iowrite32(upper_32_bits(mhba->ib_shadow_phys),
1014 regs + CLA_INB_AVAL_COUNT_BASEH); 1211 regs->inb_aval_count_baseh);
1015 1212
1016 /* Set OutBound List Available count shadow */ 1213 if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9143) {
1017 iowrite32((mhba->list_num_io-1) | CL_POINTER_TOGGLE, 1214 /* Set OutBound List Available count shadow */
1018 mhba->ob_shadow); 1215 iowrite32((mhba->list_num_io-1) |
1019 iowrite32(lower_32_bits(mhba->ob_shadow_phys), regs + 0x5B0); 1216 regs->cl_pointer_toggle,
1020 iowrite32(upper_32_bits(mhba->ob_shadow_phys), regs + 0x5B4); 1217 mhba->ob_shadow);
1218 iowrite32(lower_32_bits(mhba->ob_shadow_phys),
1219 regs->outb_copy_basel);
1220 iowrite32(upper_32_bits(mhba->ob_shadow_phys),
1221 regs->outb_copy_baseh);
1222 }
1021 1223
1022 mhba->ib_cur_slot = (mhba->list_num_io - 1) | CL_POINTER_TOGGLE; 1224 mhba->ib_cur_slot = (mhba->list_num_io - 1) |
1023 mhba->ob_cur_slot = (mhba->list_num_io - 1) | CL_POINTER_TOGGLE; 1225 regs->cl_pointer_toggle;
1226 mhba->ob_cur_slot = (mhba->list_num_io - 1) |
1227 regs->cl_pointer_toggle;
1024 mhba->fw_state = FW_STATE_STARTED; 1228 mhba->fw_state = FW_STATE_STARTED;
1025 1229
1026 break; 1230 break;
@@ -1040,7 +1244,7 @@ static unsigned char mvumi_handshake_event(struct mvumi_hba *mhba)
1040 before = jiffies; 1244 before = jiffies;
1041 mvumi_handshake(mhba); 1245 mvumi_handshake(mhba);
1042 do { 1246 do {
1043 isr_status = mhba->instancet->read_fw_status_reg(mhba->mmio); 1247 isr_status = mhba->instancet->read_fw_status_reg(mhba);
1044 1248
1045 if (mhba->fw_state == FW_STATE_STARTED) 1249 if (mhba->fw_state == FW_STATE_STARTED)
1046 return 0; 1250 return 0;
@@ -1062,16 +1266,15 @@ static unsigned char mvumi_handshake_event(struct mvumi_hba *mhba)
1062 1266
1063static unsigned char mvumi_check_handshake(struct mvumi_hba *mhba) 1267static unsigned char mvumi_check_handshake(struct mvumi_hba *mhba)
1064{ 1268{
1065 void *regs = mhba->mmio;
1066 unsigned int tmp; 1269 unsigned int tmp;
1067 unsigned long before; 1270 unsigned long before;
1068 1271
1069 before = jiffies; 1272 before = jiffies;
1070 tmp = ioread32(regs + CPU_ARM_TO_PCIEA_MSG1); 1273 tmp = ioread32(mhba->regs->arm_to_pciea_msg1);
1071 while ((tmp != HANDSHAKE_READYSTATE) && (tmp != HANDSHAKE_DONESTATE)) { 1274 while ((tmp != HANDSHAKE_READYSTATE) && (tmp != HANDSHAKE_DONESTATE)) {
1072 if (tmp != HANDSHAKE_READYSTATE) 1275 if (tmp != HANDSHAKE_READYSTATE)
1073 iowrite32(DRBL_MU_RESET, 1276 iowrite32(DRBL_MU_RESET,
1074 regs + CPU_PCIEA_TO_ARM_DRBL_REG); 1277 mhba->regs->pciea_to_arm_drbl_reg);
1075 if (time_after(jiffies, before + FW_MAX_DELAY * HZ)) { 1278 if (time_after(jiffies, before + FW_MAX_DELAY * HZ)) {
1076 dev_err(&mhba->pdev->dev, 1279 dev_err(&mhba->pdev->dev,
1077 "invalid signature [0x%x].\n", tmp); 1280 "invalid signature [0x%x].\n", tmp);
@@ -1079,7 +1282,7 @@ static unsigned char mvumi_check_handshake(struct mvumi_hba *mhba)
1079 } 1282 }
1080 usleep_range(1000, 2000); 1283 usleep_range(1000, 2000);
1081 rmb(); 1284 rmb();
1082 tmp = ioread32(regs + CPU_ARM_TO_PCIEA_MSG1); 1285 tmp = ioread32(mhba->regs->arm_to_pciea_msg1);
1083 } 1286 }
1084 1287
1085 mhba->fw_state = FW_STATE_STARTING; 1288 mhba->fw_state = FW_STATE_STARTING;
@@ -1100,15 +1303,17 @@ static unsigned char mvumi_check_handshake(struct mvumi_hba *mhba)
1100 1303
1101static unsigned char mvumi_start(struct mvumi_hba *mhba) 1304static unsigned char mvumi_start(struct mvumi_hba *mhba)
1102{ 1305{
1103 void *regs = mhba->mmio;
1104 unsigned int tmp; 1306 unsigned int tmp;
1307 struct mvumi_hw_regs *regs = mhba->regs;
1308
1105 /* clear Door bell */ 1309 /* clear Door bell */
1106 tmp = ioread32(regs + CPU_ARM_TO_PCIEA_DRBL_REG); 1310 tmp = ioread32(regs->arm_to_pciea_drbl_reg);
1107 iowrite32(tmp, regs + CPU_ARM_TO_PCIEA_DRBL_REG); 1311 iowrite32(tmp, regs->arm_to_pciea_drbl_reg);
1108 1312
1109 iowrite32(0x3FFFFFFF, regs + CPU_ARM_TO_PCIEA_MASK_REG); 1313 iowrite32(regs->int_drbl_int_mask, regs->arm_to_pciea_mask_reg);
1110 tmp = ioread32(regs + CPU_ENPOINTA_MASK_REG) | INT_MAP_DL_CPU2PCIEA; 1314 tmp = ioread32(regs->enpointa_mask_reg) | regs->int_dl_cpu2pciea;
1111 iowrite32(tmp, regs + CPU_ENPOINTA_MASK_REG); 1315 iowrite32(tmp, regs->enpointa_mask_reg);
1316 msleep(100);
1112 if (mvumi_check_handshake(mhba)) 1317 if (mvumi_check_handshake(mhba))
1113 return -1; 1318 return -1;
1114 1319
@@ -1166,6 +1371,7 @@ static void mvumi_complete_cmd(struct mvumi_hba *mhba, struct mvumi_cmd *cmd,
1166 cmd->scmd->scsi_done(scmd); 1371 cmd->scmd->scsi_done(scmd);
1167 mvumi_return_cmd(mhba, cmd); 1372 mvumi_return_cmd(mhba, cmd);
1168} 1373}
1374
1169static void mvumi_complete_internal_cmd(struct mvumi_hba *mhba, 1375static void mvumi_complete_internal_cmd(struct mvumi_hba *mhba,
1170 struct mvumi_cmd *cmd, 1376 struct mvumi_cmd *cmd,
1171 struct mvumi_rsp_frame *ob_frame) 1377 struct mvumi_rsp_frame *ob_frame)
@@ -1210,6 +1416,304 @@ static void mvumi_show_event(struct mvumi_hba *mhba,
1210 } 1416 }
1211} 1417}
1212 1418
1419static int mvumi_handle_hotplug(struct mvumi_hba *mhba, u16 devid, int status)
1420{
1421 struct scsi_device *sdev;
1422 int ret = -1;
1423
1424 if (status == DEVICE_OFFLINE) {
1425 sdev = scsi_device_lookup(mhba->shost, 0, devid, 0);
1426 if (sdev) {
1427 dev_dbg(&mhba->pdev->dev, "remove disk %d-%d-%d.\n", 0,
1428 sdev->id, 0);
1429 scsi_remove_device(sdev);
1430 scsi_device_put(sdev);
1431 ret = 0;
1432 } else
1433 dev_err(&mhba->pdev->dev, " no disk[%d] to remove\n",
1434 devid);
1435 } else if (status == DEVICE_ONLINE) {
1436 sdev = scsi_device_lookup(mhba->shost, 0, devid, 0);
1437 if (!sdev) {
1438 scsi_add_device(mhba->shost, 0, devid, 0);
1439 dev_dbg(&mhba->pdev->dev, " add disk %d-%d-%d.\n", 0,
1440 devid, 0);
1441 ret = 0;
1442 } else {
1443 dev_err(&mhba->pdev->dev, " don't add disk %d-%d-%d.\n",
1444 0, devid, 0);
1445 scsi_device_put(sdev);
1446 }
1447 }
1448 return ret;
1449}
1450
1451static u64 mvumi_inquiry(struct mvumi_hba *mhba,
1452 unsigned int id, struct mvumi_cmd *cmd)
1453{
1454 struct mvumi_msg_frame *frame;
1455 u64 wwid = 0;
1456 int cmd_alloc = 0;
1457 int data_buf_len = 64;
1458
1459 if (!cmd) {
1460 cmd = mvumi_create_internal_cmd(mhba, data_buf_len);
1461 if (cmd)
1462 cmd_alloc = 1;
1463 else
1464 return 0;
1465 } else {
1466 memset(cmd->data_buf, 0, data_buf_len);
1467 }
1468 cmd->scmd = NULL;
1469 cmd->cmd_status = REQ_STATUS_PENDING;
1470 atomic_set(&cmd->sync_cmd, 0);
1471 frame = cmd->frame;
1472 frame->device_id = (u16) id;
1473 frame->cmd_flag = CMD_FLAG_DATA_IN;
1474 frame->req_function = CL_FUN_SCSI_CMD;
1475 frame->cdb_length = 6;
1476 frame->data_transfer_length = MVUMI_INQUIRY_LENGTH;
1477 memset(frame->cdb, 0, frame->cdb_length);
1478 frame->cdb[0] = INQUIRY;
1479 frame->cdb[4] = frame->data_transfer_length;
1480
1481 mvumi_issue_blocked_cmd(mhba, cmd);
1482
1483 if (cmd->cmd_status == SAM_STAT_GOOD) {
1484 if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9143)
1485 wwid = id + 1;
1486 else
1487 memcpy((void *)&wwid,
1488 (cmd->data_buf + MVUMI_INQUIRY_UUID_OFF),
1489 MVUMI_INQUIRY_UUID_LEN);
1490 dev_dbg(&mhba->pdev->dev,
1491 "inquiry device(0:%d:0) wwid(%llx)\n", id, wwid);
1492 } else {
1493 wwid = 0;
1494 }
1495 if (cmd_alloc)
1496 mvumi_delete_internal_cmd(mhba, cmd);
1497
1498 return wwid;
1499}
1500
1501static void mvumi_detach_devices(struct mvumi_hba *mhba)
1502{
1503 struct mvumi_device *mv_dev = NULL , *dev_next;
1504 struct scsi_device *sdev = NULL;
1505
1506 mutex_lock(&mhba->device_lock);
1507
1508 /* detach Hard Disk */
1509 list_for_each_entry_safe(mv_dev, dev_next,
1510 &mhba->shost_dev_list, list) {
1511 mvumi_handle_hotplug(mhba, mv_dev->id, DEVICE_OFFLINE);
1512 list_del_init(&mv_dev->list);
1513 dev_dbg(&mhba->pdev->dev, "release device(0:%d:0) wwid(%llx)\n",
1514 mv_dev->id, mv_dev->wwid);
1515 kfree(mv_dev);
1516 }
1517 list_for_each_entry_safe(mv_dev, dev_next, &mhba->mhba_dev_list, list) {
1518 list_del_init(&mv_dev->list);
1519 dev_dbg(&mhba->pdev->dev, "release device(0:%d:0) wwid(%llx)\n",
1520 mv_dev->id, mv_dev->wwid);
1521 kfree(mv_dev);
1522 }
1523
1524 /* detach virtual device */
1525 if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9580)
1526 sdev = scsi_device_lookup(mhba->shost, 0,
1527 mhba->max_target_id - 1, 0);
1528
1529 if (sdev) {
1530 scsi_remove_device(sdev);
1531 scsi_device_put(sdev);
1532 }
1533
1534 mutex_unlock(&mhba->device_lock);
1535}
1536
1537static void mvumi_rescan_devices(struct mvumi_hba *mhba, int id)
1538{
1539 struct scsi_device *sdev;
1540
1541 sdev = scsi_device_lookup(mhba->shost, 0, id, 0);
1542 if (sdev) {
1543 scsi_rescan_device(&sdev->sdev_gendev);
1544 scsi_device_put(sdev);
1545 }
1546}
1547
1548static int mvumi_match_devices(struct mvumi_hba *mhba, int id, u64 wwid)
1549{
1550 struct mvumi_device *mv_dev = NULL;
1551
1552 list_for_each_entry(mv_dev, &mhba->shost_dev_list, list) {
1553 if (mv_dev->wwid == wwid) {
1554 if (mv_dev->id != id) {
1555 dev_err(&mhba->pdev->dev,
1556 "%s has same wwid[%llx] ,"
1557 " but different id[%d %d]\n",
1558 __func__, mv_dev->wwid, mv_dev->id, id);
1559 return -1;
1560 } else {
1561 if (mhba->pdev->device ==
1562 PCI_DEVICE_ID_MARVELL_MV9143)
1563 mvumi_rescan_devices(mhba, id);
1564 return 1;
1565 }
1566 }
1567 }
1568 return 0;
1569}
1570
1571static void mvumi_remove_devices(struct mvumi_hba *mhba, int id)
1572{
1573 struct mvumi_device *mv_dev = NULL, *dev_next;
1574
1575 list_for_each_entry_safe(mv_dev, dev_next,
1576 &mhba->shost_dev_list, list) {
1577 if (mv_dev->id == id) {
1578 dev_dbg(&mhba->pdev->dev,
1579 "detach device(0:%d:0) wwid(%llx) from HOST\n",
1580 mv_dev->id, mv_dev->wwid);
1581 mvumi_handle_hotplug(mhba, mv_dev->id, DEVICE_OFFLINE);
1582 list_del_init(&mv_dev->list);
1583 kfree(mv_dev);
1584 }
1585 }
1586}
1587
1588static int mvumi_probe_devices(struct mvumi_hba *mhba)
1589{
1590 int id, maxid;
1591 u64 wwid = 0;
1592 struct mvumi_device *mv_dev = NULL;
1593 struct mvumi_cmd *cmd = NULL;
1594 int found = 0;
1595
1596 cmd = mvumi_create_internal_cmd(mhba, 64);
1597 if (!cmd)
1598 return -1;
1599
1600 if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9143)
1601 maxid = mhba->max_target_id;
1602 else
1603 maxid = mhba->max_target_id - 1;
1604
1605 for (id = 0; id < maxid; id++) {
1606 wwid = mvumi_inquiry(mhba, id, cmd);
1607 if (!wwid) {
1608 /* device no response, remove it */
1609 mvumi_remove_devices(mhba, id);
1610 } else {
1611 /* device response, add it */
1612 found = mvumi_match_devices(mhba, id, wwid);
1613 if (!found) {
1614 mvumi_remove_devices(mhba, id);
1615 mv_dev = kzalloc(sizeof(struct mvumi_device),
1616 GFP_KERNEL);
1617 if (!mv_dev) {
1618 dev_err(&mhba->pdev->dev,
1619 "%s alloc mv_dev failed\n",
1620 __func__);
1621 continue;
1622 }
1623 mv_dev->id = id;
1624 mv_dev->wwid = wwid;
1625 mv_dev->sdev = NULL;
1626 INIT_LIST_HEAD(&mv_dev->list);
1627 list_add_tail(&mv_dev->list,
1628 &mhba->mhba_dev_list);
1629 dev_dbg(&mhba->pdev->dev,
1630 "probe a new device(0:%d:0)"
1631 " wwid(%llx)\n", id, mv_dev->wwid);
1632 } else if (found == -1)
1633 return -1;
1634 else
1635 continue;
1636 }
1637 }
1638
1639 if (cmd)
1640 mvumi_delete_internal_cmd(mhba, cmd);
1641
1642 return 0;
1643}
1644
1645static int mvumi_rescan_bus(void *data)
1646{
1647 int ret = 0;
1648 struct mvumi_hba *mhba = (struct mvumi_hba *) data;
1649 struct mvumi_device *mv_dev = NULL , *dev_next;
1650
1651 while (!kthread_should_stop()) {
1652
1653 set_current_state(TASK_INTERRUPTIBLE);
1654 if (!atomic_read(&mhba->pnp_count))
1655 schedule();
1656 msleep(1000);
1657 atomic_set(&mhba->pnp_count, 0);
1658 __set_current_state(TASK_RUNNING);
1659
1660 mutex_lock(&mhba->device_lock);
1661 ret = mvumi_probe_devices(mhba);
1662 if (!ret) {
1663 list_for_each_entry_safe(mv_dev, dev_next,
1664 &mhba->mhba_dev_list, list) {
1665 if (mvumi_handle_hotplug(mhba, mv_dev->id,
1666 DEVICE_ONLINE)) {
1667 dev_err(&mhba->pdev->dev,
1668 "%s add device(0:%d:0) failed"
1669 "wwid(%llx) has exist\n",
1670 __func__,
1671 mv_dev->id, mv_dev->wwid);
1672 list_del_init(&mv_dev->list);
1673 kfree(mv_dev);
1674 } else {
1675 list_move_tail(&mv_dev->list,
1676 &mhba->shost_dev_list);
1677 }
1678 }
1679 }
1680 mutex_unlock(&mhba->device_lock);
1681 }
1682 return 0;
1683}
1684
1685static void mvumi_proc_msg(struct mvumi_hba *mhba,
1686 struct mvumi_hotplug_event *param)
1687{
1688 u16 size = param->size;
1689 const unsigned long *ar_bitmap;
1690 const unsigned long *re_bitmap;
1691 int index;
1692
1693 if (mhba->fw_flag & MVUMI_FW_ATTACH) {
1694 index = -1;
1695 ar_bitmap = (const unsigned long *) param->bitmap;
1696 re_bitmap = (const unsigned long *) &param->bitmap[size >> 3];
1697
1698 mutex_lock(&mhba->sas_discovery_mutex);
1699 do {
1700 index = find_next_zero_bit(ar_bitmap, size, index + 1);
1701 if (index >= size)
1702 break;
1703 mvumi_handle_hotplug(mhba, index, DEVICE_ONLINE);
1704 } while (1);
1705
1706 index = -1;
1707 do {
1708 index = find_next_zero_bit(re_bitmap, size, index + 1);
1709 if (index >= size)
1710 break;
1711 mvumi_handle_hotplug(mhba, index, DEVICE_OFFLINE);
1712 } while (1);
1713 mutex_unlock(&mhba->sas_discovery_mutex);
1714 }
1715}
1716
1213static void mvumi_notification(struct mvumi_hba *mhba, u8 msg, void *buffer) 1717static void mvumi_notification(struct mvumi_hba *mhba, u8 msg, void *buffer)
1214{ 1718{
1215 if (msg == APICDB1_EVENT_GETEVENT) { 1719 if (msg == APICDB1_EVENT_GETEVENT) {
@@ -1227,6 +1731,8 @@ static void mvumi_notification(struct mvumi_hba *mhba, u8 msg, void *buffer)
1227 param = &er->events[i]; 1731 param = &er->events[i];
1228 mvumi_show_event(mhba, param); 1732 mvumi_show_event(mhba, param);
1229 } 1733 }
1734 } else if (msg == APICDB1_HOST_GETEVENT) {
1735 mvumi_proc_msg(mhba, buffer);
1230 } 1736 }
1231} 1737}
1232 1738
@@ -1271,17 +1777,27 @@ static void mvumi_scan_events(struct work_struct *work)
1271 kfree(mu_ev); 1777 kfree(mu_ev);
1272} 1778}
1273 1779
1274static void mvumi_launch_events(struct mvumi_hba *mhba, u8 msg) 1780static void mvumi_launch_events(struct mvumi_hba *mhba, u32 isr_status)
1275{ 1781{
1276 struct mvumi_events_wq *mu_ev; 1782 struct mvumi_events_wq *mu_ev;
1277 1783
1278 mu_ev = kzalloc(sizeof(*mu_ev), GFP_ATOMIC); 1784 while (isr_status & (DRBL_BUS_CHANGE | DRBL_EVENT_NOTIFY)) {
1279 if (mu_ev) { 1785 if (isr_status & DRBL_BUS_CHANGE) {
1280 INIT_WORK(&mu_ev->work_q, mvumi_scan_events); 1786 atomic_inc(&mhba->pnp_count);
1281 mu_ev->mhba = mhba; 1787 wake_up_process(mhba->dm_thread);
1282 mu_ev->event = msg; 1788 isr_status &= ~(DRBL_BUS_CHANGE);
1283 mu_ev->param = NULL; 1789 continue;
1284 schedule_work(&mu_ev->work_q); 1790 }
1791
1792 mu_ev = kzalloc(sizeof(*mu_ev), GFP_ATOMIC);
1793 if (mu_ev) {
1794 INIT_WORK(&mu_ev->work_q, mvumi_scan_events);
1795 mu_ev->mhba = mhba;
1796 mu_ev->event = APICDB1_EVENT_GETEVENT;
1797 isr_status &= ~(DRBL_EVENT_NOTIFY);
1798 mu_ev->param = NULL;
1799 schedule_work(&mu_ev->work_q);
1800 }
1285 } 1801 }
1286} 1802}
1287 1803
@@ -1322,16 +1838,17 @@ static irqreturn_t mvumi_isr_handler(int irq, void *devp)
1322 return IRQ_NONE; 1838 return IRQ_NONE;
1323 } 1839 }
1324 1840
1325 if (mhba->global_isr & INT_MAP_DL_CPU2PCIEA) { 1841 if (mhba->global_isr & mhba->regs->int_dl_cpu2pciea) {
1842 if (mhba->isr_status & (DRBL_BUS_CHANGE | DRBL_EVENT_NOTIFY))
1843 mvumi_launch_events(mhba, mhba->isr_status);
1326 if (mhba->isr_status & DRBL_HANDSHAKE_ISR) { 1844 if (mhba->isr_status & DRBL_HANDSHAKE_ISR) {
1327 dev_warn(&mhba->pdev->dev, "enter handshake again!\n"); 1845 dev_warn(&mhba->pdev->dev, "enter handshake again!\n");
1328 mvumi_handshake(mhba); 1846 mvumi_handshake(mhba);
1329 } 1847 }
1330 if (mhba->isr_status & DRBL_EVENT_NOTIFY) 1848
1331 mvumi_launch_events(mhba, APICDB1_EVENT_GETEVENT);
1332 } 1849 }
1333 1850
1334 if (mhba->global_isr & INT_MAP_COMAOUT) 1851 if (mhba->global_isr & mhba->regs->int_comaout)
1335 mvumi_receive_ob_list_entry(mhba); 1852 mvumi_receive_ob_list_entry(mhba);
1336 1853
1337 mhba->global_isr = 0; 1854 mhba->global_isr = 0;
@@ -1358,8 +1875,7 @@ static enum mvumi_qc_result mvumi_send_command(struct mvumi_hba *mhba,
1358 dev_dbg(&mhba->pdev->dev, "no free tag.\n"); 1875 dev_dbg(&mhba->pdev->dev, "no free tag.\n");
1359 return MV_QUEUE_COMMAND_RESULT_NO_RESOURCE; 1876 return MV_QUEUE_COMMAND_RESULT_NO_RESOURCE;
1360 } 1877 }
1361 if (mvumi_get_ib_list_entry(mhba, &ib_entry)) 1878 mvumi_get_ib_list_entry(mhba, &ib_entry);
1362 return MV_QUEUE_COMMAND_RESULT_NO_RESOURCE;
1363 1879
1364 cmd->frame->tag = tag_get_one(mhba, &mhba->tag_pool); 1880 cmd->frame->tag = tag_get_one(mhba, &mhba->tag_pool);
1365 cmd->frame->request_id = mhba->io_seq++; 1881 cmd->frame->request_id = mhba->io_seq++;
@@ -1367,21 +1883,35 @@ static enum mvumi_qc_result mvumi_send_command(struct mvumi_hba *mhba,
1367 mhba->tag_cmd[cmd->frame->tag] = cmd; 1883 mhba->tag_cmd[cmd->frame->tag] = cmd;
1368 frame_len = sizeof(*ib_frame) - 4 + 1884 frame_len = sizeof(*ib_frame) - 4 +
1369 ib_frame->sg_counts * sizeof(struct mvumi_sgl); 1885 ib_frame->sg_counts * sizeof(struct mvumi_sgl);
1370 memcpy(ib_entry, ib_frame, frame_len); 1886 if (mhba->hba_capability & HS_CAPABILITY_SUPPORT_DYN_SRC) {
1887 struct mvumi_dyn_list_entry *dle;
1888 dle = ib_entry;
1889 dle->src_low_addr =
1890 cpu_to_le32(lower_32_bits(cmd->frame_phys));
1891 dle->src_high_addr =
1892 cpu_to_le32(upper_32_bits(cmd->frame_phys));
1893 dle->if_length = (frame_len >> 2) & 0xFFF;
1894 } else {
1895 memcpy(ib_entry, ib_frame, frame_len);
1896 }
1371 return MV_QUEUE_COMMAND_RESULT_SENT; 1897 return MV_QUEUE_COMMAND_RESULT_SENT;
1372} 1898}
1373 1899
1374static void mvumi_fire_cmd(struct mvumi_hba *mhba, struct mvumi_cmd *cmd) 1900static void mvumi_fire_cmd(struct mvumi_hba *mhba, struct mvumi_cmd *cmd)
1375{ 1901{
1376 unsigned short num_of_cl_sent = 0; 1902 unsigned short num_of_cl_sent = 0;
1903 unsigned int count;
1377 enum mvumi_qc_result result; 1904 enum mvumi_qc_result result;
1378 1905
1379 if (cmd) 1906 if (cmd)
1380 list_add_tail(&cmd->queue_pointer, &mhba->waiting_req_list); 1907 list_add_tail(&cmd->queue_pointer, &mhba->waiting_req_list);
1908 count = mhba->instancet->check_ib_list(mhba);
1909 if (list_empty(&mhba->waiting_req_list) || !count)
1910 return;
1381 1911
1382 while (!list_empty(&mhba->waiting_req_list)) { 1912 do {
1383 cmd = list_first_entry(&mhba->waiting_req_list, 1913 cmd = list_first_entry(&mhba->waiting_req_list,
1384 struct mvumi_cmd, queue_pointer); 1914 struct mvumi_cmd, queue_pointer);
1385 list_del_init(&cmd->queue_pointer); 1915 list_del_init(&cmd->queue_pointer);
1386 result = mvumi_send_command(mhba, cmd); 1916 result = mvumi_send_command(mhba, cmd);
1387 switch (result) { 1917 switch (result) {
@@ -1395,65 +1925,77 @@ static void mvumi_fire_cmd(struct mvumi_hba *mhba, struct mvumi_cmd *cmd)
1395 1925
1396 return; 1926 return;
1397 } 1927 }
1398 } 1928 } while (!list_empty(&mhba->waiting_req_list) && count--);
1929
1399 if (num_of_cl_sent > 0) 1930 if (num_of_cl_sent > 0)
1400 mvumi_send_ib_list_entry(mhba); 1931 mvumi_send_ib_list_entry(mhba);
1401} 1932}
1402 1933
1403/** 1934/**
1404 * mvumi_enable_intr - Enables interrupts 1935 * mvumi_enable_intr - Enables interrupts
1405 * @regs: FW register set 1936 * @mhba: Adapter soft state
1406 */ 1937 */
1407static void mvumi_enable_intr(void *regs) 1938static void mvumi_enable_intr(struct mvumi_hba *mhba)
1408{ 1939{
1409 unsigned int mask; 1940 unsigned int mask;
1941 struct mvumi_hw_regs *regs = mhba->regs;
1410 1942
1411 iowrite32(0x3FFFFFFF, regs + CPU_ARM_TO_PCIEA_MASK_REG); 1943 iowrite32(regs->int_drbl_int_mask, regs->arm_to_pciea_mask_reg);
1412 mask = ioread32(regs + CPU_ENPOINTA_MASK_REG); 1944 mask = ioread32(regs->enpointa_mask_reg);
1413 mask |= INT_MAP_DL_CPU2PCIEA | INT_MAP_COMAOUT | INT_MAP_COMAERR; 1945 mask |= regs->int_dl_cpu2pciea | regs->int_comaout | regs->int_comaerr;
1414 iowrite32(mask, regs + CPU_ENPOINTA_MASK_REG); 1946 iowrite32(mask, regs->enpointa_mask_reg);
1415} 1947}
1416 1948
1417/** 1949/**
1418 * mvumi_disable_intr -Disables interrupt 1950 * mvumi_disable_intr -Disables interrupt
1419 * @regs: FW register set 1951 * @mhba: Adapter soft state
1420 */ 1952 */
1421static void mvumi_disable_intr(void *regs) 1953static void mvumi_disable_intr(struct mvumi_hba *mhba)
1422{ 1954{
1423 unsigned int mask; 1955 unsigned int mask;
1956 struct mvumi_hw_regs *regs = mhba->regs;
1424 1957
1425 iowrite32(0, regs + CPU_ARM_TO_PCIEA_MASK_REG); 1958 iowrite32(0, regs->arm_to_pciea_mask_reg);
1426 mask = ioread32(regs + CPU_ENPOINTA_MASK_REG); 1959 mask = ioread32(regs->enpointa_mask_reg);
1427 mask &= ~(INT_MAP_DL_CPU2PCIEA | INT_MAP_COMAOUT | INT_MAP_COMAERR); 1960 mask &= ~(regs->int_dl_cpu2pciea | regs->int_comaout |
1428 iowrite32(mask, regs + CPU_ENPOINTA_MASK_REG); 1961 regs->int_comaerr);
1962 iowrite32(mask, regs->enpointa_mask_reg);
1429} 1963}
1430 1964
1431static int mvumi_clear_intr(void *extend) 1965static int mvumi_clear_intr(void *extend)
1432{ 1966{
1433 struct mvumi_hba *mhba = (struct mvumi_hba *) extend; 1967 struct mvumi_hba *mhba = (struct mvumi_hba *) extend;
1434 unsigned int status, isr_status = 0, tmp = 0; 1968 unsigned int status, isr_status = 0, tmp = 0;
1435 void *regs = mhba->mmio; 1969 struct mvumi_hw_regs *regs = mhba->regs;
1436 1970
1437 status = ioread32(regs + CPU_MAIN_INT_CAUSE_REG); 1971 status = ioread32(regs->main_int_cause_reg);
1438 if (!(status & INT_MAP_MU) || status == 0xFFFFFFFF) 1972 if (!(status & regs->int_mu) || status == 0xFFFFFFFF)
1439 return 1; 1973 return 1;
1440 if (unlikely(status & INT_MAP_COMAERR)) { 1974 if (unlikely(status & regs->int_comaerr)) {
1441 tmp = ioread32(regs + CLA_ISR_CAUSE); 1975 tmp = ioread32(regs->outb_isr_cause);
1442 if (tmp & (CLIC_IN_ERR_IRQ | CLIC_OUT_ERR_IRQ)) 1976 if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9580) {
1443 iowrite32(tmp & (CLIC_IN_ERR_IRQ | CLIC_OUT_ERR_IRQ), 1977 if (tmp & regs->clic_out_err) {
1444 regs + CLA_ISR_CAUSE); 1978 iowrite32(tmp & regs->clic_out_err,
1445 status ^= INT_MAP_COMAERR; 1979 regs->outb_isr_cause);
1980 }
1981 } else {
1982 if (tmp & (regs->clic_in_err | regs->clic_out_err))
1983 iowrite32(tmp & (regs->clic_in_err |
1984 regs->clic_out_err),
1985 regs->outb_isr_cause);
1986 }
1987 status ^= mhba->regs->int_comaerr;
1446 /* inbound or outbound parity error, command will timeout */ 1988 /* inbound or outbound parity error, command will timeout */
1447 } 1989 }
1448 if (status & INT_MAP_COMAOUT) { 1990 if (status & regs->int_comaout) {
1449 tmp = ioread32(regs + CLA_ISR_CAUSE); 1991 tmp = ioread32(regs->outb_isr_cause);
1450 if (tmp & CLIC_OUT_IRQ) 1992 if (tmp & regs->clic_irq)
1451 iowrite32(tmp & CLIC_OUT_IRQ, regs + CLA_ISR_CAUSE); 1993 iowrite32(tmp & regs->clic_irq, regs->outb_isr_cause);
1452 } 1994 }
1453 if (status & INT_MAP_DL_CPU2PCIEA) { 1995 if (status & regs->int_dl_cpu2pciea) {
1454 isr_status = ioread32(regs + CPU_ARM_TO_PCIEA_DRBL_REG); 1996 isr_status = ioread32(regs->arm_to_pciea_drbl_reg);
1455 if (isr_status) 1997 if (isr_status)
1456 iowrite32(isr_status, regs + CPU_ARM_TO_PCIEA_DRBL_REG); 1998 iowrite32(isr_status, regs->arm_to_pciea_drbl_reg);
1457 } 1999 }
1458 2000
1459 mhba->global_isr = status; 2001 mhba->global_isr = status;
@@ -1464,24 +2006,38 @@ static int mvumi_clear_intr(void *extend)
1464 2006
1465/** 2007/**
1466 * mvumi_read_fw_status_reg - returns the current FW status value 2008 * mvumi_read_fw_status_reg - returns the current FW status value
1467 * @regs: FW register set 2009 * @mhba: Adapter soft state
1468 */ 2010 */
1469static unsigned int mvumi_read_fw_status_reg(void *regs) 2011static unsigned int mvumi_read_fw_status_reg(struct mvumi_hba *mhba)
1470{ 2012{
1471 unsigned int status; 2013 unsigned int status;
1472 2014
1473 status = ioread32(regs + CPU_ARM_TO_PCIEA_DRBL_REG); 2015 status = ioread32(mhba->regs->arm_to_pciea_drbl_reg);
1474 if (status) 2016 if (status)
1475 iowrite32(status, regs + CPU_ARM_TO_PCIEA_DRBL_REG); 2017 iowrite32(status, mhba->regs->arm_to_pciea_drbl_reg);
1476 return status; 2018 return status;
1477} 2019}
1478 2020
1479static struct mvumi_instance_template mvumi_instance_template = { 2021static struct mvumi_instance_template mvumi_instance_9143 = {
1480 .fire_cmd = mvumi_fire_cmd, 2022 .fire_cmd = mvumi_fire_cmd,
1481 .enable_intr = mvumi_enable_intr, 2023 .enable_intr = mvumi_enable_intr,
1482 .disable_intr = mvumi_disable_intr, 2024 .disable_intr = mvumi_disable_intr,
1483 .clear_intr = mvumi_clear_intr, 2025 .clear_intr = mvumi_clear_intr,
1484 .read_fw_status_reg = mvumi_read_fw_status_reg, 2026 .read_fw_status_reg = mvumi_read_fw_status_reg,
2027 .check_ib_list = mvumi_check_ib_list_9143,
2028 .check_ob_list = mvumi_check_ob_list_9143,
2029 .reset_host = mvumi_reset_host_9143,
2030};
2031
2032static struct mvumi_instance_template mvumi_instance_9580 = {
2033 .fire_cmd = mvumi_fire_cmd,
2034 .enable_intr = mvumi_enable_intr,
2035 .disable_intr = mvumi_disable_intr,
2036 .clear_intr = mvumi_clear_intr,
2037 .read_fw_status_reg = mvumi_read_fw_status_reg,
2038 .check_ib_list = mvumi_check_ib_list_9580,
2039 .check_ob_list = mvumi_check_ob_list_9580,
2040 .reset_host = mvumi_reset_host_9580,
1485}; 2041};
1486 2042
1487static int mvumi_slave_configure(struct scsi_device *sdev) 2043static int mvumi_slave_configure(struct scsi_device *sdev)
@@ -1681,6 +2237,124 @@ static struct scsi_transport_template mvumi_transport_template = {
1681 .eh_timed_out = mvumi_timed_out, 2237 .eh_timed_out = mvumi_timed_out,
1682}; 2238};
1683 2239
2240static int mvumi_cfg_hw_reg(struct mvumi_hba *mhba)
2241{
2242 void *base = NULL;
2243 struct mvumi_hw_regs *regs;
2244
2245 switch (mhba->pdev->device) {
2246 case PCI_DEVICE_ID_MARVELL_MV9143:
2247 mhba->mmio = mhba->base_addr[0];
2248 base = mhba->mmio;
2249 if (!mhba->regs) {
2250 mhba->regs = kzalloc(sizeof(*regs), GFP_KERNEL);
2251 if (mhba->regs == NULL)
2252 return -ENOMEM;
2253 }
2254 regs = mhba->regs;
2255
2256 /* For Arm */
2257 regs->ctrl_sts_reg = base + 0x20104;
2258 regs->rstoutn_mask_reg = base + 0x20108;
2259 regs->sys_soft_rst_reg = base + 0x2010C;
2260 regs->main_int_cause_reg = base + 0x20200;
2261 regs->enpointa_mask_reg = base + 0x2020C;
2262 regs->rstoutn_en_reg = base + 0xF1400;
2263 /* For Doorbell */
2264 regs->pciea_to_arm_drbl_reg = base + 0x20400;
2265 regs->arm_to_pciea_drbl_reg = base + 0x20408;
2266 regs->arm_to_pciea_mask_reg = base + 0x2040C;
2267 regs->pciea_to_arm_msg0 = base + 0x20430;
2268 regs->pciea_to_arm_msg1 = base + 0x20434;
2269 regs->arm_to_pciea_msg0 = base + 0x20438;
2270 regs->arm_to_pciea_msg1 = base + 0x2043C;
2271
2272 /* For Message Unit */
2273
2274 regs->inb_aval_count_basel = base + 0x508;
2275 regs->inb_aval_count_baseh = base + 0x50C;
2276 regs->inb_write_pointer = base + 0x518;
2277 regs->inb_read_pointer = base + 0x51C;
2278 regs->outb_coal_cfg = base + 0x568;
2279 regs->outb_copy_basel = base + 0x5B0;
2280 regs->outb_copy_baseh = base + 0x5B4;
2281 regs->outb_copy_pointer = base + 0x544;
2282 regs->outb_read_pointer = base + 0x548;
2283 regs->outb_isr_cause = base + 0x560;
2284 regs->outb_coal_cfg = base + 0x568;
2285 /* Bit setting for HW */
2286 regs->int_comaout = 1 << 8;
2287 regs->int_comaerr = 1 << 6;
2288 regs->int_dl_cpu2pciea = 1 << 1;
2289 regs->cl_pointer_toggle = 1 << 12;
2290 regs->clic_irq = 1 << 1;
2291 regs->clic_in_err = 1 << 8;
2292 regs->clic_out_err = 1 << 12;
2293 regs->cl_slot_num_mask = 0xFFF;
2294 regs->int_drbl_int_mask = 0x3FFFFFFF;
2295 regs->int_mu = regs->int_dl_cpu2pciea | regs->int_comaout |
2296 regs->int_comaerr;
2297 break;
2298 case PCI_DEVICE_ID_MARVELL_MV9580:
2299 mhba->mmio = mhba->base_addr[2];
2300 base = mhba->mmio;
2301 if (!mhba->regs) {
2302 mhba->regs = kzalloc(sizeof(*regs), GFP_KERNEL);
2303 if (mhba->regs == NULL)
2304 return -ENOMEM;
2305 }
2306 regs = mhba->regs;
2307 /* For Arm */
2308 regs->ctrl_sts_reg = base + 0x20104;
2309 regs->rstoutn_mask_reg = base + 0x1010C;
2310 regs->sys_soft_rst_reg = base + 0x10108;
2311 regs->main_int_cause_reg = base + 0x10200;
2312 regs->enpointa_mask_reg = base + 0x1020C;
2313 regs->rstoutn_en_reg = base + 0xF1400;
2314
2315 /* For Doorbell */
2316 regs->pciea_to_arm_drbl_reg = base + 0x10460;
2317 regs->arm_to_pciea_drbl_reg = base + 0x10480;
2318 regs->arm_to_pciea_mask_reg = base + 0x10484;
2319 regs->pciea_to_arm_msg0 = base + 0x10400;
2320 regs->pciea_to_arm_msg1 = base + 0x10404;
2321 regs->arm_to_pciea_msg0 = base + 0x10420;
2322 regs->arm_to_pciea_msg1 = base + 0x10424;
2323
2324 /* For reset*/
2325 regs->reset_request = base + 0x10108;
2326 regs->reset_enable = base + 0x1010c;
2327
2328 /* For Message Unit */
2329 regs->inb_aval_count_basel = base + 0x4008;
2330 regs->inb_aval_count_baseh = base + 0x400C;
2331 regs->inb_write_pointer = base + 0x4018;
2332 regs->inb_read_pointer = base + 0x401C;
2333 regs->outb_copy_basel = base + 0x4058;
2334 regs->outb_copy_baseh = base + 0x405C;
2335 regs->outb_copy_pointer = base + 0x406C;
2336 regs->outb_read_pointer = base + 0x4070;
2337 regs->outb_coal_cfg = base + 0x4080;
2338 regs->outb_isr_cause = base + 0x4088;
2339 /* Bit setting for HW */
2340 regs->int_comaout = 1 << 4;
2341 regs->int_dl_cpu2pciea = 1 << 12;
2342 regs->int_comaerr = 1 << 29;
2343 regs->cl_pointer_toggle = 1 << 14;
2344 regs->cl_slot_num_mask = 0x3FFF;
2345 regs->clic_irq = 1 << 0;
2346 regs->clic_out_err = 1 << 1;
2347 regs->int_drbl_int_mask = 0x3FFFFFFF;
2348 regs->int_mu = regs->int_dl_cpu2pciea | regs->int_comaout;
2349 break;
2350 default:
2351 return -1;
2352 break;
2353 }
2354
2355 return 0;
2356}
2357
1684/** 2358/**
1685 * mvumi_init_fw - Initializes the FW 2359 * mvumi_init_fw - Initializes the FW
1686 * @mhba: Adapter soft state 2360 * @mhba: Adapter soft state
@@ -1699,15 +2373,18 @@ static int mvumi_init_fw(struct mvumi_hba *mhba)
1699 if (ret) 2373 if (ret)
1700 goto fail_ioremap; 2374 goto fail_ioremap;
1701 2375
1702 mhba->mmio = mhba->base_addr[0];
1703
1704 switch (mhba->pdev->device) { 2376 switch (mhba->pdev->device) {
1705 case PCI_DEVICE_ID_MARVELL_MV9143: 2377 case PCI_DEVICE_ID_MARVELL_MV9143:
1706 mhba->instancet = &mvumi_instance_template; 2378 mhba->instancet = &mvumi_instance_9143;
1707 mhba->io_seq = 0; 2379 mhba->io_seq = 0;
1708 mhba->max_sge = MVUMI_MAX_SG_ENTRY; 2380 mhba->max_sge = MVUMI_MAX_SG_ENTRY;
1709 mhba->request_id_enabled = 1; 2381 mhba->request_id_enabled = 1;
1710 break; 2382 break;
2383 case PCI_DEVICE_ID_MARVELL_MV9580:
2384 mhba->instancet = &mvumi_instance_9580;
2385 mhba->io_seq = 0;
2386 mhba->max_sge = MVUMI_MAX_SG_ENTRY;
2387 break;
1711 default: 2388 default:
1712 dev_err(&mhba->pdev->dev, "device 0x%x not supported!\n", 2389 dev_err(&mhba->pdev->dev, "device 0x%x not supported!\n",
1713 mhba->pdev->device); 2390 mhba->pdev->device);
@@ -1717,15 +2394,21 @@ static int mvumi_init_fw(struct mvumi_hba *mhba)
1717 } 2394 }
1718 dev_dbg(&mhba->pdev->dev, "device id : %04X is found.\n", 2395 dev_dbg(&mhba->pdev->dev, "device id : %04X is found.\n",
1719 mhba->pdev->device); 2396 mhba->pdev->device);
1720 2397 ret = mvumi_cfg_hw_reg(mhba);
1721 mhba->handshake_page = kzalloc(HSP_MAX_SIZE, GFP_KERNEL); 2398 if (ret) {
2399 dev_err(&mhba->pdev->dev,
2400 "failed to allocate memory for reg\n");
2401 ret = -ENOMEM;
2402 goto fail_alloc_mem;
2403 }
2404 mhba->handshake_page = pci_alloc_consistent(mhba->pdev, HSP_MAX_SIZE,
2405 &mhba->handshake_page_phys);
1722 if (!mhba->handshake_page) { 2406 if (!mhba->handshake_page) {
1723 dev_err(&mhba->pdev->dev, 2407 dev_err(&mhba->pdev->dev,
1724 "failed to allocate memory for handshake\n"); 2408 "failed to allocate memory for handshake\n");
1725 ret = -ENOMEM; 2409 ret = -ENOMEM;
1726 goto fail_alloc_mem; 2410 goto fail_alloc_page;
1727 } 2411 }
1728 mhba->handshake_page_phys = virt_to_phys(mhba->handshake_page);
1729 2412
1730 if (mvumi_start(mhba)) { 2413 if (mvumi_start(mhba)) {
1731 ret = -EINVAL; 2414 ret = -EINVAL;
@@ -1739,7 +2422,10 @@ static int mvumi_init_fw(struct mvumi_hba *mhba)
1739 2422
1740fail_ready_state: 2423fail_ready_state:
1741 mvumi_release_mem_resource(mhba); 2424 mvumi_release_mem_resource(mhba);
1742 kfree(mhba->handshake_page); 2425 pci_free_consistent(mhba->pdev, HSP_MAX_SIZE,
2426 mhba->handshake_page, mhba->handshake_page_phys);
2427fail_alloc_page:
2428 kfree(mhba->regs);
1743fail_alloc_mem: 2429fail_alloc_mem:
1744 mvumi_unmap_pci_addr(mhba->pdev, mhba->base_addr); 2430 mvumi_unmap_pci_addr(mhba->pdev, mhba->base_addr);
1745fail_ioremap: 2431fail_ioremap:
@@ -1755,6 +2441,7 @@ fail_ioremap:
1755static int mvumi_io_attach(struct mvumi_hba *mhba) 2441static int mvumi_io_attach(struct mvumi_hba *mhba)
1756{ 2442{
1757 struct Scsi_Host *host = mhba->shost; 2443 struct Scsi_Host *host = mhba->shost;
2444 struct scsi_device *sdev = NULL;
1758 int ret; 2445 int ret;
1759 unsigned int max_sg = (mhba->ib_max_size + 4 - 2446 unsigned int max_sg = (mhba->ib_max_size + 4 -
1760 sizeof(struct mvumi_msg_frame)) / sizeof(struct mvumi_sgl); 2447 sizeof(struct mvumi_msg_frame)) / sizeof(struct mvumi_sgl);
@@ -1764,7 +2451,7 @@ static int mvumi_io_attach(struct mvumi_hba *mhba)
1764 host->can_queue = (mhba->max_io - 1) ? (mhba->max_io - 1) : 1; 2451 host->can_queue = (mhba->max_io - 1) ? (mhba->max_io - 1) : 1;
1765 host->sg_tablesize = mhba->max_sge > max_sg ? max_sg : mhba->max_sge; 2452 host->sg_tablesize = mhba->max_sge > max_sg ? max_sg : mhba->max_sge;
1766 host->max_sectors = mhba->max_transfer_size / 512; 2453 host->max_sectors = mhba->max_transfer_size / 512;
1767 host->cmd_per_lun = (mhba->max_io - 1) ? (mhba->max_io - 1) : 1; 2454 host->cmd_per_lun = (mhba->max_io - 1) ? (mhba->max_io - 1) : 1;
1768 host->max_id = mhba->max_target_id; 2455 host->max_id = mhba->max_target_id;
1769 host->max_cmd_len = MAX_COMMAND_SIZE; 2456 host->max_cmd_len = MAX_COMMAND_SIZE;
1770 host->transportt = &mvumi_transport_template; 2457 host->transportt = &mvumi_transport_template;
@@ -1775,9 +2462,43 @@ static int mvumi_io_attach(struct mvumi_hba *mhba)
1775 return ret; 2462 return ret;
1776 } 2463 }
1777 mhba->fw_flag |= MVUMI_FW_ATTACH; 2464 mhba->fw_flag |= MVUMI_FW_ATTACH;
1778 scsi_scan_host(host);
1779 2465
2466 mutex_lock(&mhba->sas_discovery_mutex);
2467 if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9580)
2468 ret = scsi_add_device(host, 0, mhba->max_target_id - 1, 0);
2469 else
2470 ret = 0;
2471 if (ret) {
2472 dev_err(&mhba->pdev->dev, "add virtual device failed\n");
2473 mutex_unlock(&mhba->sas_discovery_mutex);
2474 goto fail_add_device;
2475 }
2476
2477 mhba->dm_thread = kthread_create(mvumi_rescan_bus,
2478 mhba, "mvumi_scanthread");
2479 if (IS_ERR(mhba->dm_thread)) {
2480 dev_err(&mhba->pdev->dev,
2481 "failed to create device scan thread\n");
2482 mutex_unlock(&mhba->sas_discovery_mutex);
2483 goto fail_create_thread;
2484 }
2485 atomic_set(&mhba->pnp_count, 1);
2486 wake_up_process(mhba->dm_thread);
2487
2488 mutex_unlock(&mhba->sas_discovery_mutex);
1780 return 0; 2489 return 0;
2490
2491fail_create_thread:
2492 if (mhba->pdev->device == PCI_DEVICE_ID_MARVELL_MV9580)
2493 sdev = scsi_device_lookup(mhba->shost, 0,
2494 mhba->max_target_id - 1, 0);
2495 if (sdev) {
2496 scsi_remove_device(sdev);
2497 scsi_device_put(sdev);
2498 }
2499fail_add_device:
2500 scsi_remove_host(mhba->shost);
2501 return ret;
1781} 2502}
1782 2503
1783/** 2504/**
@@ -1828,8 +2549,12 @@ static int __devinit mvumi_probe_one(struct pci_dev *pdev,
1828 INIT_LIST_HEAD(&mhba->free_ob_list); 2549 INIT_LIST_HEAD(&mhba->free_ob_list);
1829 INIT_LIST_HEAD(&mhba->res_list); 2550 INIT_LIST_HEAD(&mhba->res_list);
1830 INIT_LIST_HEAD(&mhba->waiting_req_list); 2551 INIT_LIST_HEAD(&mhba->waiting_req_list);
2552 mutex_init(&mhba->device_lock);
2553 INIT_LIST_HEAD(&mhba->mhba_dev_list);
2554 INIT_LIST_HEAD(&mhba->shost_dev_list);
1831 atomic_set(&mhba->fw_outstanding, 0); 2555 atomic_set(&mhba->fw_outstanding, 0);
1832 init_waitqueue_head(&mhba->int_cmd_wait_q); 2556 init_waitqueue_head(&mhba->int_cmd_wait_q);
2557 mutex_init(&mhba->sas_discovery_mutex);
1833 2558
1834 mhba->pdev = pdev; 2559 mhba->pdev = pdev;
1835 mhba->shost = host; 2560 mhba->shost = host;
@@ -1845,19 +2570,22 @@ static int __devinit mvumi_probe_one(struct pci_dev *pdev,
1845 dev_err(&pdev->dev, "failed to register IRQ\n"); 2570 dev_err(&pdev->dev, "failed to register IRQ\n");
1846 goto fail_init_irq; 2571 goto fail_init_irq;
1847 } 2572 }
1848 mhba->instancet->enable_intr(mhba->mmio); 2573
2574 mhba->instancet->enable_intr(mhba);
1849 pci_set_drvdata(pdev, mhba); 2575 pci_set_drvdata(pdev, mhba);
1850 2576
1851 ret = mvumi_io_attach(mhba); 2577 ret = mvumi_io_attach(mhba);
1852 if (ret) 2578 if (ret)
1853 goto fail_io_attach; 2579 goto fail_io_attach;
2580
2581 mvumi_backup_bar_addr(mhba);
1854 dev_dbg(&pdev->dev, "probe mvumi driver successfully.\n"); 2582 dev_dbg(&pdev->dev, "probe mvumi driver successfully.\n");
1855 2583
1856 return 0; 2584 return 0;
1857 2585
1858fail_io_attach: 2586fail_io_attach:
1859 pci_set_drvdata(pdev, NULL); 2587 pci_set_drvdata(pdev, NULL);
1860 mhba->instancet->disable_intr(mhba->mmio); 2588 mhba->instancet->disable_intr(mhba);
1861 free_irq(mhba->pdev->irq, mhba); 2589 free_irq(mhba->pdev->irq, mhba);
1862fail_init_irq: 2590fail_init_irq:
1863 mvumi_release_fw(mhba); 2591 mvumi_release_fw(mhba);
@@ -1877,11 +2605,17 @@ static void mvumi_detach_one(struct pci_dev *pdev)
1877 struct mvumi_hba *mhba; 2605 struct mvumi_hba *mhba;
1878 2606
1879 mhba = pci_get_drvdata(pdev); 2607 mhba = pci_get_drvdata(pdev);
2608 if (mhba->dm_thread) {
2609 kthread_stop(mhba->dm_thread);
2610 mhba->dm_thread = NULL;
2611 }
2612
2613 mvumi_detach_devices(mhba);
1880 host = mhba->shost; 2614 host = mhba->shost;
1881 scsi_remove_host(mhba->shost); 2615 scsi_remove_host(mhba->shost);
1882 mvumi_flush_cache(mhba); 2616 mvumi_flush_cache(mhba);
1883 2617
1884 mhba->instancet->disable_intr(mhba->mmio); 2618 mhba->instancet->disable_intr(mhba);
1885 free_irq(mhba->pdev->irq, mhba); 2619 free_irq(mhba->pdev->irq, mhba);
1886 mvumi_release_fw(mhba); 2620 mvumi_release_fw(mhba);
1887 scsi_host_put(host); 2621 scsi_host_put(host);
@@ -1909,7 +2643,7 @@ static int mvumi_suspend(struct pci_dev *pdev, pm_message_t state)
1909 mvumi_flush_cache(mhba); 2643 mvumi_flush_cache(mhba);
1910 2644
1911 pci_set_drvdata(pdev, mhba); 2645 pci_set_drvdata(pdev, mhba);
1912 mhba->instancet->disable_intr(mhba->mmio); 2646 mhba->instancet->disable_intr(mhba);
1913 free_irq(mhba->pdev->irq, mhba); 2647 free_irq(mhba->pdev->irq, mhba);
1914 mvumi_unmap_pci_addr(pdev, mhba->base_addr); 2648 mvumi_unmap_pci_addr(pdev, mhba->base_addr);
1915 pci_release_regions(pdev); 2649 pci_release_regions(pdev);
@@ -1956,8 +2690,13 @@ static int mvumi_resume(struct pci_dev *pdev)
1956 if (ret) 2690 if (ret)
1957 goto release_regions; 2691 goto release_regions;
1958 2692
2693 if (mvumi_cfg_hw_reg(mhba)) {
2694 ret = -EINVAL;
2695 goto unmap_pci_addr;
2696 }
2697
1959 mhba->mmio = mhba->base_addr[0]; 2698 mhba->mmio = mhba->base_addr[0];
1960 mvumi_reset(mhba->mmio); 2699 mvumi_reset(mhba);
1961 2700
1962 if (mvumi_start(mhba)) { 2701 if (mvumi_start(mhba)) {
1963 ret = -EINVAL; 2702 ret = -EINVAL;
@@ -1970,7 +2709,7 @@ static int mvumi_resume(struct pci_dev *pdev)
1970 dev_err(&pdev->dev, "failed to register IRQ\n"); 2709 dev_err(&pdev->dev, "failed to register IRQ\n");
1971 goto unmap_pci_addr; 2710 goto unmap_pci_addr;
1972 } 2711 }
1973 mhba->instancet->enable_intr(mhba->mmio); 2712 mhba->instancet->enable_intr(mhba);
1974 2713
1975 return 0; 2714 return 0;
1976 2715
diff --git a/drivers/scsi/mvumi.h b/drivers/scsi/mvumi.h
index 10b9237566f0..e360135fd1bd 100644
--- a/drivers/scsi/mvumi.h
+++ b/drivers/scsi/mvumi.h
@@ -34,51 +34,87 @@
34#define MV_DRIVER_NAME "mvumi" 34#define MV_DRIVER_NAME "mvumi"
35#define PCI_VENDOR_ID_MARVELL_2 0x1b4b 35#define PCI_VENDOR_ID_MARVELL_2 0x1b4b
36#define PCI_DEVICE_ID_MARVELL_MV9143 0x9143 36#define PCI_DEVICE_ID_MARVELL_MV9143 0x9143
37#define PCI_DEVICE_ID_MARVELL_MV9580 0x9580
37 38
38#define MVUMI_INTERNAL_CMD_WAIT_TIME 45 39#define MVUMI_INTERNAL_CMD_WAIT_TIME 45
40#define MVUMI_INQUIRY_LENGTH 44
41#define MVUMI_INQUIRY_UUID_OFF 36
42#define MVUMI_INQUIRY_UUID_LEN 8
39 43
40#define IS_DMA64 (sizeof(dma_addr_t) == 8) 44#define IS_DMA64 (sizeof(dma_addr_t) == 8)
41 45
42enum mvumi_qc_result { 46enum mvumi_qc_result {
43 MV_QUEUE_COMMAND_RESULT_SENT = 0, 47 MV_QUEUE_COMMAND_RESULT_SENT = 0,
44 MV_QUEUE_COMMAND_RESULT_NO_RESOURCE, 48 MV_QUEUE_COMMAND_RESULT_NO_RESOURCE,
45}; 49};
46 50
47enum { 51struct mvumi_hw_regs {
48 /*******************************************/ 52 /* For CPU */
49 53 void *main_int_cause_reg;
50 /* ARM Mbus Registers Map */ 54 void *enpointa_mask_reg;
51 55 void *enpointb_mask_reg;
52 /*******************************************/ 56 void *rstoutn_en_reg;
53 CPU_MAIN_INT_CAUSE_REG = 0x20200, 57 void *ctrl_sts_reg;
54 CPU_MAIN_IRQ_MASK_REG = 0x20204, 58 void *rstoutn_mask_reg;
55 CPU_MAIN_FIQ_MASK_REG = 0x20208, 59 void *sys_soft_rst_reg;
56 CPU_ENPOINTA_MASK_REG = 0x2020C, 60
57 CPU_ENPOINTB_MASK_REG = 0x20210, 61 /* For Doorbell */
58 62 void *pciea_to_arm_drbl_reg;
59 INT_MAP_COMAERR = 1 << 6, 63 void *arm_to_pciea_drbl_reg;
60 INT_MAP_COMAIN = 1 << 7, 64 void *arm_to_pciea_mask_reg;
61 INT_MAP_COMAOUT = 1 << 8, 65 void *pciea_to_arm_msg0;
62 INT_MAP_COMBERR = 1 << 9, 66 void *pciea_to_arm_msg1;
63 INT_MAP_COMBIN = 1 << 10, 67 void *arm_to_pciea_msg0;
64 INT_MAP_COMBOUT = 1 << 11, 68 void *arm_to_pciea_msg1;
65 69
66 INT_MAP_COMAINT = (INT_MAP_COMAOUT | INT_MAP_COMAERR), 70 /* reset register */
67 INT_MAP_COMBINT = (INT_MAP_COMBOUT | INT_MAP_COMBIN | INT_MAP_COMBERR), 71 void *reset_request;
68 72 void *reset_enable;
69 INT_MAP_DL_PCIEA2CPU = 1 << 0, 73
70 INT_MAP_DL_CPU2PCIEA = 1 << 1, 74 /* For Message Unit */
71 75 void *inb_list_basel;
72 /***************************************/ 76 void *inb_list_baseh;
77 void *inb_aval_count_basel;
78 void *inb_aval_count_baseh;
79 void *inb_write_pointer;
80 void *inb_read_pointer;
81 void *outb_list_basel;
82 void *outb_list_baseh;
83 void *outb_copy_basel;
84 void *outb_copy_baseh;
85 void *outb_copy_pointer;
86 void *outb_read_pointer;
87 void *inb_isr_cause;
88 void *outb_isr_cause;
89 void *outb_coal_cfg;
90 void *outb_coal_timeout;
91
92 /* Bit setting for HW */
93 u32 int_comaout;
94 u32 int_comaerr;
95 u32 int_dl_cpu2pciea;
96 u32 int_mu;
97 u32 int_drbl_int_mask;
98 u32 int_main_int_mask;
99 u32 cl_pointer_toggle;
100 u32 cl_slot_num_mask;
101 u32 clic_irq;
102 u32 clic_in_err;
103 u32 clic_out_err;
104};
73 105
74 /* ARM Doorbell Registers Map */ 106struct mvumi_dyn_list_entry {
107 u32 src_low_addr;
108 u32 src_high_addr;
109 u32 if_length;
110 u32 reserve;
111};
75 112
76 /***************************************/ 113#define SCSI_CMD_MARVELL_SPECIFIC 0xE1
77 CPU_PCIEA_TO_ARM_DRBL_REG = 0x20400, 114#define CDB_CORE_MODULE 0x1
78 CPU_PCIEA_TO_ARM_MASK_REG = 0x20404, 115#define CDB_CORE_SHUTDOWN 0xB
79 CPU_ARM_TO_PCIEA_DRBL_REG = 0x20408,
80 CPU_ARM_TO_PCIEA_MASK_REG = 0x2040C,
81 116
117enum {
82 DRBL_HANDSHAKE = 1 << 0, 118 DRBL_HANDSHAKE = 1 << 0,
83 DRBL_SOFT_RESET = 1 << 1, 119 DRBL_SOFT_RESET = 1 << 1,
84 DRBL_BUS_CHANGE = 1 << 2, 120 DRBL_BUS_CHANGE = 1 << 2,
@@ -86,46 +122,6 @@ enum {
86 DRBL_MU_RESET = 1 << 4, 122 DRBL_MU_RESET = 1 << 4,
87 DRBL_HANDSHAKE_ISR = DRBL_HANDSHAKE, 123 DRBL_HANDSHAKE_ISR = DRBL_HANDSHAKE,
88 124
89 CPU_PCIEA_TO_ARM_MSG0 = 0x20430,
90 CPU_PCIEA_TO_ARM_MSG1 = 0x20434,
91 CPU_ARM_TO_PCIEA_MSG0 = 0x20438,
92 CPU_ARM_TO_PCIEA_MSG1 = 0x2043C,
93
94 /*******************************************/
95
96 /* ARM Communication List Registers Map */
97
98 /*******************************************/
99 CLA_INB_LIST_BASEL = 0x500,
100 CLA_INB_LIST_BASEH = 0x504,
101 CLA_INB_AVAL_COUNT_BASEL = 0x508,
102 CLA_INB_AVAL_COUNT_BASEH = 0x50C,
103 CLA_INB_DESTI_LIST_BASEL = 0x510,
104 CLA_INB_DESTI_LIST_BASEH = 0x514,
105 CLA_INB_WRITE_POINTER = 0x518,
106 CLA_INB_READ_POINTER = 0x51C,
107
108 CLA_OUTB_LIST_BASEL = 0x530,
109 CLA_OUTB_LIST_BASEH = 0x534,
110 CLA_OUTB_SOURCE_LIST_BASEL = 0x538,
111 CLA_OUTB_SOURCE_LIST_BASEH = 0x53C,
112 CLA_OUTB_COPY_POINTER = 0x544,
113 CLA_OUTB_READ_POINTER = 0x548,
114
115 CLA_ISR_CAUSE = 0x560,
116 CLA_ISR_MASK = 0x564,
117
118 INT_MAP_MU = (INT_MAP_DL_CPU2PCIEA | INT_MAP_COMAINT),
119
120 CL_POINTER_TOGGLE = 1 << 12,
121
122 CLIC_IN_IRQ = 1 << 0,
123 CLIC_OUT_IRQ = 1 << 1,
124 CLIC_IN_ERR_IRQ = 1 << 8,
125 CLIC_OUT_ERR_IRQ = 1 << 12,
126
127 CL_SLOT_NUM_MASK = 0xFFF,
128
129 /* 125 /*
130 * Command flag is the flag for the CDB command itself 126 * Command flag is the flag for the CDB command itself
131 */ 127 */
@@ -137,15 +133,23 @@ enum {
137 CMD_FLAG_DATA_IN = 1 << 3, 133 CMD_FLAG_DATA_IN = 1 << 3,
138 /* 1-host write data */ 134 /* 1-host write data */
139 CMD_FLAG_DATA_OUT = 1 << 4, 135 CMD_FLAG_DATA_OUT = 1 << 4,
140 136 CMD_FLAG_PRDT_IN_HOST = 1 << 5,
141 SCSI_CMD_MARVELL_SPECIFIC = 0xE1,
142 CDB_CORE_SHUTDOWN = 0xB,
143}; 137};
144 138
145#define APICDB0_EVENT 0xF4 139#define APICDB0_EVENT 0xF4
146#define APICDB1_EVENT_GETEVENT 0 140#define APICDB1_EVENT_GETEVENT 0
141#define APICDB1_HOST_GETEVENT 1
147#define MAX_EVENTS_RETURNED 6 142#define MAX_EVENTS_RETURNED 6
148 143
144#define DEVICE_OFFLINE 0
145#define DEVICE_ONLINE 1
146
147struct mvumi_hotplug_event {
148 u16 size;
149 u8 dummy[2];
150 u8 bitmap[0];
151};
152
149struct mvumi_driver_event { 153struct mvumi_driver_event {
150 u32 time_stamp; 154 u32 time_stamp;
151 u32 sequence_no; 155 u32 sequence_no;
@@ -172,8 +176,14 @@ struct mvumi_events_wq {
172 void *param; 176 void *param;
173}; 177};
174 178
179#define HS_CAPABILITY_SUPPORT_COMPACT_SG (1U << 4)
180#define HS_CAPABILITY_SUPPORT_PRD_HOST (1U << 5)
181#define HS_CAPABILITY_SUPPORT_DYN_SRC (1U << 6)
182#define HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF (1U << 14)
183
175#define MVUMI_MAX_SG_ENTRY 32 184#define MVUMI_MAX_SG_ENTRY 32
176#define SGD_EOT (1L << 27) 185#define SGD_EOT (1L << 27)
186#define SGD_EOT_CP (1L << 22)
177 187
178struct mvumi_sgl { 188struct mvumi_sgl {
179 u32 baseaddr_l; 189 u32 baseaddr_l;
@@ -181,6 +191,39 @@ struct mvumi_sgl {
181 u32 flags; 191 u32 flags;
182 u32 size; 192 u32 size;
183}; 193};
194struct mvumi_compact_sgl {
195 u32 baseaddr_l;
196 u32 baseaddr_h;
197 u32 flags;
198};
199
200#define GET_COMPACT_SGD_SIZE(sgd) \
201 ((((struct mvumi_compact_sgl *)(sgd))->flags) & 0x3FFFFFL)
202
203#define SET_COMPACT_SGD_SIZE(sgd, sz) do { \
204 (((struct mvumi_compact_sgl *)(sgd))->flags) &= ~0x3FFFFFL; \
205 (((struct mvumi_compact_sgl *)(sgd))->flags) |= (sz); \
206} while (0)
207#define sgd_getsz(_mhba, sgd, sz) do { \
208 if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
209 (sz) = GET_COMPACT_SGD_SIZE(sgd); \
210 else \
211 (sz) = (sgd)->size; \
212} while (0)
213
214#define sgd_setsz(_mhba, sgd, sz) do { \
215 if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
216 SET_COMPACT_SGD_SIZE(sgd, sz); \
217 else \
218 (sgd)->size = (sz); \
219} while (0)
220
221#define sgd_inc(_mhba, sgd) do { \
222 if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
223 sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 12); \
224 else \
225 sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 16); \
226} while (0)
184 227
185struct mvumi_res { 228struct mvumi_res {
186 struct list_head entry; 229 struct list_head entry;
@@ -197,7 +240,7 @@ enum resource_type {
197}; 240};
198 241
199struct mvumi_sense_data { 242struct mvumi_sense_data {
200 u8 error_eode:7; 243 u8 error_code:7;
201 u8 valid:1; 244 u8 valid:1;
202 u8 segment_number; 245 u8 segment_number;
203 u8 sense_key:4; 246 u8 sense_key:4;
@@ -220,6 +263,7 @@ struct mvumi_sense_data {
220struct mvumi_cmd { 263struct mvumi_cmd {
221 struct list_head queue_pointer; 264 struct list_head queue_pointer;
222 struct mvumi_msg_frame *frame; 265 struct mvumi_msg_frame *frame;
266 dma_addr_t frame_phys;
223 struct scsi_cmnd *scmd; 267 struct scsi_cmnd *scmd;
224 atomic_t sync_cmd; 268 atomic_t sync_cmd;
225 void *data_buf; 269 void *data_buf;
@@ -393,7 +437,8 @@ struct mvumi_hs_page2 {
393 u16 frame_length; 437 u16 frame_length;
394 438
395 u8 host_type; 439 u8 host_type;
396 u8 reserved[3]; 440 u8 host_cap;
441 u8 reserved[2];
397 struct version_info host_ver; 442 struct version_info host_ver;
398 u32 system_io_bus; 443 u32 system_io_bus;
399 u32 slot_number; 444 u32 slot_number;
@@ -435,8 +480,17 @@ struct mvumi_tag {
435 unsigned short size; 480 unsigned short size;
436}; 481};
437 482
483struct mvumi_device {
484 struct list_head list;
485 struct scsi_device *sdev;
486 u64 wwid;
487 u8 dev_type;
488 int id;
489};
490
438struct mvumi_hba { 491struct mvumi_hba {
439 void *base_addr[MAX_BASE_ADDRESS]; 492 void *base_addr[MAX_BASE_ADDRESS];
493 u32 pci_base[MAX_BASE_ADDRESS];
440 void *mmio; 494 void *mmio;
441 struct list_head cmd_pool; 495 struct list_head cmd_pool;
442 struct Scsi_Host *shost; 496 struct Scsi_Host *shost;
@@ -449,6 +503,9 @@ struct mvumi_hba {
449 void *ib_list; 503 void *ib_list;
450 dma_addr_t ib_list_phys; 504 dma_addr_t ib_list_phys;
451 505
506 void *ib_frame;
507 dma_addr_t ib_frame_phys;
508
452 void *ob_list; 509 void *ob_list;
453 dma_addr_t ob_list_phys; 510 dma_addr_t ob_list_phys;
454 511
@@ -477,12 +534,14 @@ struct mvumi_hba {
477 unsigned char hba_total_pages; 534 unsigned char hba_total_pages;
478 unsigned char fw_flag; 535 unsigned char fw_flag;
479 unsigned char request_id_enabled; 536 unsigned char request_id_enabled;
537 unsigned char eot_flag;
480 unsigned short hba_capability; 538 unsigned short hba_capability;
481 unsigned short io_seq; 539 unsigned short io_seq;
482 540
483 unsigned int ib_cur_slot; 541 unsigned int ib_cur_slot;
484 unsigned int ob_cur_slot; 542 unsigned int ob_cur_slot;
485 unsigned int fw_state; 543 unsigned int fw_state;
544 struct mutex sas_discovery_mutex;
486 545
487 struct list_head ob_data_list; 546 struct list_head ob_data_list;
488 struct list_head free_ob_list; 547 struct list_head free_ob_list;
@@ -491,14 +550,24 @@ struct mvumi_hba {
491 550
492 struct mvumi_tag tag_pool; 551 struct mvumi_tag tag_pool;
493 struct mvumi_cmd **tag_cmd; 552 struct mvumi_cmd **tag_cmd;
553 struct mvumi_hw_regs *regs;
554 struct mutex device_lock;
555 struct list_head mhba_dev_list;
556 struct list_head shost_dev_list;
557 struct task_struct *dm_thread;
558 atomic_t pnp_count;
494}; 559};
495 560
496struct mvumi_instance_template { 561struct mvumi_instance_template {
497 void (*fire_cmd)(struct mvumi_hba *, struct mvumi_cmd *); 562 void (*fire_cmd) (struct mvumi_hba *, struct mvumi_cmd *);
498 void (*enable_intr)(void *) ; 563 void (*enable_intr) (struct mvumi_hba *);
499 void (*disable_intr)(void *); 564 void (*disable_intr) (struct mvumi_hba *);
500 int (*clear_intr)(void *); 565 int (*clear_intr) (void *);
501 unsigned int (*read_fw_status_reg)(void *); 566 unsigned int (*read_fw_status_reg) (struct mvumi_hba *);
567 unsigned int (*check_ib_list) (struct mvumi_hba *);
568 int (*check_ob_list) (struct mvumi_hba *, unsigned int *,
569 unsigned int *);
570 int (*reset_host) (struct mvumi_hba *);
502}; 571};
503 572
504extern struct timezone sys_tz; 573extern struct timezone sys_tz;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 05:41:04 -0500