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authorLinus Torvalds <torvalds@linux-foundation.org>2014-06-03 14:20:32 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-06-03 14:20:32 -0400
commitbd698cf6595b079ce36423e8c7eb4a69a31b1733 (patch)
tree3a5dfaa971670445eb16ab854ef31962860d8aad
parentf456205265a61f1d649f8378eceaa163850cba4e (diff)
parent29c7f1f53bfb3770bdb65a9e79064a963dd40621 (diff)
Merge tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next
Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.16 development cycle: - Antoine Tenart made the get_group_pins() vtable entry optional. - Antoine also provides an entirely new driver for the Marvell Berlin SoC. This is unrelated to the existing MVEBU hardware driver and warrants its own separate driver. - reflected from the GPIO subsystem there is a number of refactorings to make pin control drivers with gpiochips use the new gpiolib irqchip helpers. The following drivers were converted to use the new infrastructure: * ST Microelectronics STiH416 and friends * The Atmel AT91 * The CSR SiRF (Prima2) * The Qualcomm MSM series - massive improvements in the Qualcomm MSM driver from Bjorn Andersson, Andy Gross and Kumar Gala. Among those new support for the IPQ8064 and MSM8x74 SoC variants. - support for the Freescale i.MX6 SoloX SoC variant. - massive improvements in the Allwinner sunxi driver from Boris Brezillon, Maxime Ripard and Chen-Yu Tsai. - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto, Wolfram Sang and Magnus Damm. - Cleanups and refactorings of the nVidia Tegra driver from Stepgen Warren. - the Exynos driver now supports the Exynos3250 SoC. - Intel BayTrail updates from Jin Yao, Mika Westerberg. - the MVEBU driver now supports the Orion5x SoC variants, which is part of the effort of getting rid of the old Marvell kludges in arch/arm/mach-orion5x - Rockchip driver updates from Heiko Stuebner. - a ton of cleanups and janitorial patches from Axel Lin. - some minor fixes and improvements here and there" * tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits) pinctrl: sirf: fix a bad conflict resolution pinctrl: msm: Add more MSM8X74 pin definitions pinctrl: qcom: ipq8064: Fix naming convention pinctrl: msm: Add missing sdc1 and sdc3 groups pinctrl: sirf: switch to using allocated state container pinctrl: Enable "power-source" to be extracted from DT files pinctrl: sunxi: create irq/pin mapping during init pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy pinctrl: berlin: Use devm_ioremap_resource() pinctrl: sirf: fix typo for GPIO bank number pinctrl: sunxi: depend on RESET_CONTROLLER pinctrl: sunxi: fix pin numbers passed to register offset helpers pinctrl: add pinctrl driver for imx6sx pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs pinctrl: msm: switch to using generic GPIO irqchip helpers pinctrl: sunxi: Fix multiple registration issue pinctrl: sunxi: Fix recursive dependency pinctrl: berlin: add the BG2CD pinctrl driver pinctrl: berlin: add the BG2 pinctrl driver pinctrl: berlin: add the BG2Q pinctrl driver ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt9
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt36
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt91
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt88
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt95
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt22
-rw-r--r--Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt28
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--drivers/acpi/acpi_lpss.c1
-rw-r--r--drivers/pinctrl/Kconfig39
-rw-r--r--drivers/pinctrl/Makefile6
-rw-r--r--drivers/pinctrl/berlin/Kconfig20
-rw-r--r--drivers/pinctrl/berlin/Makefile4
-rw-r--r--drivers/pinctrl/berlin/berlin-bg2.c274
-rw-r--r--drivers/pinctrl/berlin/berlin-bg2cd.c217
-rw-r--r--drivers/pinctrl/berlin/berlin-bg2q.c436
-rw-r--r--drivers/pinctrl/berlin/berlin.c348
-rw-r--r--drivers/pinctrl/berlin/berlin.h61
-rw-r--r--drivers/pinctrl/core.c17
-rw-r--r--drivers/pinctrl/mvebu/Kconfig4
-rw-r--r--drivers/pinctrl/mvebu/Makefile1
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-orion.c261
-rw-r--r--drivers/pinctrl/pinconf-generic.c4
-rw-r--r--drivers/pinctrl/pinctrl-adi2.c2
-rw-r--r--drivers/pinctrl/pinctrl-apq8064.c613
-rw-r--r--drivers/pinctrl/pinctrl-at91.c129
-rw-r--r--drivers/pinctrl/pinctrl-baytrail.c68
-rw-r--r--drivers/pinctrl/pinctrl-exynos.c67
-rw-r--r--drivers/pinctrl/pinctrl-imx.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx6sx.c407
-rw-r--r--drivers/pinctrl/pinctrl-ipq8064.c653
-rw-r--r--drivers/pinctrl/pinctrl-lantiq.h1
-rw-r--r--drivers/pinctrl/pinctrl-msm.c103
-rw-r--r--drivers/pinctrl/pinctrl-msm.h3
-rw-r--r--drivers/pinctrl/pinctrl-msm8x74.c680
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c221
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c2
-rw-r--r--drivers/pinctrl/pinctrl-samsung.h1
-rw-r--r--drivers/pinctrl/pinctrl-st.c130
-rw-r--r--drivers/pinctrl/pinctrl-sunxi-pins.h3863
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.h548
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c49
-rw-r--r--drivers/pinctrl/pinctrl-tegra.h133
-rw-r--r--drivers/pinctrl/pinctrl-tegra114.c412
-rw-r--r--drivers/pinctrl/pinctrl-tegra124.c520
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c244
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c551
-rw-r--r--drivers/pinctrl/pinmux.c23
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c3
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c138
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c412
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c2
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h5
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c350
-rw-r--r--drivers/pinctrl/sunxi/Kconfig36
-rw-r--r--drivers/pinctrl/sunxi/Makefile10
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c1039
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c690
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c411
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c141
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c865
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c1065
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c (renamed from drivers/pinctrl/pinctrl-sunxi.c)145
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.h258
66 files changed, 10872 insertions, 6190 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index dff0e5f995e2..d8d065608ec0 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -6,8 +6,13 @@ the first two functions being GPIO in and out. The configuration on
6the pins includes drive strength and pull-up. 6the pins includes drive strength and pull-up.
7 7
8Required properties: 8Required properties:
9- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are: 9- compatible: Should be one of the followings (depending on you SoC):
10 sun5i-a13. 10 "allwinner,sun4i-a10-pinctrl"
11 "allwinner,sun5i-a10s-pinctrl"
12 "allwinner,sun5i-a13-pinctrl"
13 "allwinner,sun6i-a31-pinctrl"
14 "allwinner,sun6i-a31-r-pinctrl"
15 "allwinner,sun7i-a20-pinctrl"
11- reg: Should contain the register physical address and length for the 16- reg: Should contain the register physical address and length for the
12 pin controller. 17 pin controller.
13 18
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
new file mode 100644
index 000000000000..b1b595220f1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
@@ -0,0 +1,36 @@
1* Freescale i.MX6 SoloX IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx6sx-iomuxc"
8- fsl,pins: each entry consists of 6 integers and represents the mux and config
9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
10 input_val> are specified using a PIN_FUNC_ID macro, which can be found in
11 imx6sx-pinfunc.h under device tree source folder. The last integer CONFIG is
12 the pad setting value like pull-up on this pin. Please refer to i.MX6 SoloX
13 Reference Manual for detailed CONFIG settings.
14
15CONFIG bits definition:
16PAD_CTL_HYS (1 << 16)
17PAD_CTL_PUS_100K_DOWN (0 << 14)
18PAD_CTL_PUS_47K_UP (1 << 14)
19PAD_CTL_PUS_100K_UP (2 << 14)
20PAD_CTL_PUS_22K_UP (3 << 14)
21PAD_CTL_PUE (1 << 13)
22PAD_CTL_PKE (1 << 12)
23PAD_CTL_ODE (1 << 11)
24PAD_CTL_SPEED_LOW (0 << 6)
25PAD_CTL_SPEED_MED (1 << 6)
26PAD_CTL_SPEED_HIGH (3 << 6)
27PAD_CTL_DSE_DISABLE (0 << 3)
28PAD_CTL_DSE_260ohm (1 << 3)
29PAD_CTL_DSE_130ohm (2 << 3)
30PAD_CTL_DSE_87ohm (3 << 3)
31PAD_CTL_DSE_65ohm (4 << 3)
32PAD_CTL_DSE_52ohm (5 << 3)
33PAD_CTL_DSE_43ohm (6 << 3)
34PAD_CTL_DSE_37ohm (7 << 3)
35PAD_CTL_SRE_FAST (1 << 0)
36PAD_CTL_SRE_SLOW (0 << 0)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
new file mode 100644
index 000000000000..27570a3a1741
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
@@ -0,0 +1,91 @@
1* Marvell Orion SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
8 "marvell,88f5281-pinctrl"
9
10- reg: two register areas, the first one describing the first two
11 contiguous MPP registers, and the second one describing the single
12 final MPP register, separated from the previous one.
13
14Available mpp pins/groups and functions:
15Note: brackets (x) are not part of the mpp name for marvell,function and given
16only for more detailed description in this document.
17
18* Marvell Orion 88f5181l
19
20name pins functions
21================================================================================
22mpp0 0 pcie(rstout), pci(req2), gpio
23mpp1 1 gpio, pci(gnt2)
24mpp2 2 gpio, pci(req3), pci-1(pme)
25mpp3 3 gpio, pci(gnt3)
26mpp4 4 gpio, pci(req4)
27mpp5 5 gpio, pci(gnt4)
28mpp6 6 gpio, pci(req5), pci-1(clk)
29mpp7 7 gpio, pci(gnt5), pci-1(clk)
30mpp8 8 gpio, ge(col)
31mpp9 9 gpio, ge(rxerr)
32mpp10 10 gpio, ge(crs)
33mpp11 11 gpio, ge(txerr)
34mpp12 12 gpio, ge(txd4)
35mpp13 13 gpio, ge(txd5)
36mpp14 14 gpio, ge(txd6)
37mpp15 15 gpio, ge(txd7)
38mpp16 16 ge(rxd4)
39mpp17 17 ge(rxd5)
40mpp18 18 ge(rxd6)
41mpp19 19 ge(rxd7)
42
43* Marvell Orion 88f5182
44
45name pins functions
46================================================================================
47mpp0 0 pcie(rstout), pci(req2), gpio
48mpp1 1 gpio, pci(gnt2)
49mpp2 2 gpio, pci(req3), pci-1(pme)
50mpp3 3 gpio, pci(gnt3)
51mpp4 4 gpio, pci(req4), bootnand(re), sata0(prsnt)
52mpp5 5 gpio, pci(gnt4), bootnand(we), sata1(prsnt)
53mpp6 6 gpio, pci(req5), nand(re0), sata0(act)
54mpp7 7 gpio, pci(gnt5), nand(we0), sata1(act)
55mpp8 8 gpio, ge(col)
56mpp9 9 gpio, ge(rxerr)
57mpp10 10 gpio, ge(crs)
58mpp11 11 gpio, ge(txerr)
59mpp12 12 gpio, ge(txd4), nand(re1), sata0(ledprsnt)
60mpp13 13 gpio, ge(txd5), nand(we1), sata1(ledprsnt)
61mpp14 14 gpio, ge(txd6), nand(re2), sata0(ledact)
62mpp15 15 gpio, ge(txd7), nand(we2), sata1(ledact)
63mpp16 16 uart1(rxd), ge(rxd4), gpio
64mpp17 17 uart1(txd), ge(rxd5), gpio
65mpp18 18 uart1(cts), ge(rxd6), gpio
66mpp19 19 uart1(rts), ge(rxd7), gpio
67
68* Marvell Orion 88f5281
69
70name pins functions
71================================================================================
72mpp0 0 pcie(rstout), pci(req2), gpio
73mpp1 1 gpio, pci(gnt2)
74mpp2 2 gpio, pci(req3), pci(pme)
75mpp3 3 gpio, pci(gnt3)
76mpp4 4 gpio, pci(req4), bootnand(re)
77mpp5 5 gpio, pci(gnt4), bootnand(we)
78mpp6 6 gpio, pci(req5), nand(re0)
79mpp7 7 gpio, pci(gnt5), nand(we0)
80mpp8 8 gpio, ge(col)
81mpp9 9 gpio, ge(rxerr)
82mpp10 10 gpio, ge(crs)
83mpp11 11 gpio, ge(txerr)
84mpp12 12 gpio, ge(txd4), nand(re1)
85mpp13 13 gpio, ge(txd5), nand(we1)
86mpp14 14 gpio, ge(txd6), nand(re2)
87mpp15 15 gpio, ge(txd7), nand(we2)
88mpp16 16 uart1(rxd), ge(rxd4)
89mpp17 17 uart1(txd), ge(rxd5)
90mpp18 18 uart1(cts), ge(rxd6)
91mpp19 19 uart1(rts), ge(rxd7)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
index 4414163e76d2..fa40a177164c 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -156,6 +156,7 @@ input-disable - disable input on pin (no effect on output)
156input-schmitt-enable - enable schmitt-trigger mode 156input-schmitt-enable - enable schmitt-trigger mode
157input-schmitt-disable - disable schmitt-trigger mode 157input-schmitt-disable - disable schmitt-trigger mode
158input-debounce - debounce mode with debound time X 158input-debounce - debounce mode with debound time X
159power-source - select between different power supplies
159low-power-enable - enable low power mode 160low-power-enable - enable low power mode
160low-power-disable - disable low power mode 161low-power-disable - disable low power mode
161output-low - set the pin to output mode with low level 162output-low - set the pin to output mode with low level
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
new file mode 100644
index 000000000000..7181f925acaa
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
@@ -0,0 +1,88 @@
1Qualcomm APQ8064 TLMM block
2
3Required properties:
4- compatible: "qcom,apq8064-pinctrl"
5- reg: Should be the base address and length of the TLMM block.
6- interrupts: Should be the parent IRQ of the TLMM block.
7- interrupt-controller: Marks the device node as an interrupt controller.
8- #interrupt-cells: Should be two.
9- gpio-controller: Marks the device node as a GPIO controller.
10- #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
12 second cell is used for optional parameters.
13
14Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
15a general description of GPIO and interrupt bindings.
16
17Please refer to pinctrl-bindings.txt in this directory for details of the
18common pinctrl bindings used by client devices, including the meaning of the
19phrase "pin configuration node".
20
21Qualcomm's pin configuration nodes act as a container for an abitrary number of
22subnodes. Each of these subnodes represents some desired configuration for a
23pin, a group, or a list of pins or groups. This configuration can include the
24mux function to select on those pin(s)/group(s), and various pin configuration
25parameters, such as pull-up, drive strength, etc.
26
27The name of each subnode is not important; all subnodes should be enumerated
28and processed purely based on their content.
29
30Each subnode only affects those parameters that are explicitly listed. In
31other words, a subnode that lists a mux function but no pin configuration
32parameters implies no information about any pin configuration parameters.
33Similarly, a pin subnode that describes a pullup parameter implies no
34information about e.g. the mux function.
35
36
37The following generic properties as defined in pinctrl-bindings.txt are valid
38to specify in a pin configuration subnode:
39
40 pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,
41 output-low, output-high.
42
43Non-empty subnodes must specify the 'pins' property.
44
45Valid values for pins are:
46 gpio0-gpio89
47
48Valid values for function are:
49 cam_mclk, codec_mic_i2s, codec_spkr_i2s, gsbi1, gsbi2, gsbi3, gsbi4,
50 gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
51 gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
52 gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
53 riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,
54
55Example:
56
57 msmgpio: pinctrl@800000 {
58 compatible = "qcom,apq8064-pinctrl";
59 reg = <0x800000 0x4000>;
60
61 gpio-controller;
62 #gpio-cells = <2>;
63 interrupt-controller;
64 #interrupt-cells = <2>;
65 interrupts = <0 32 0x4>;
66
67 pinctrl-names = "default";
68 pinctrl-0 = <&gsbi5_uart_default>;
69
70 gsbi5_uart_default: gsbi5_uart_default {
71 mux {
72 pins = "gpio51", "gpio52";
73 function = "gsbi5";
74 };
75
76 tx {
77 pins = "gpio51";
78 drive-strength = <4>;
79 bias-disable;
80 };
81
82 rx {
83 pins = "gpio52";
84 drive-strength = <2>;
85 bias-pull-up;
86 };
87 };
88 };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
new file mode 100644
index 000000000000..e0d35a40981b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
@@ -0,0 +1,95 @@
1Qualcomm IPQ8064 TLMM block
2
3Required properties:
4- compatible: "qcom,ipq8064-pinctrl"
5- reg: Should be the base address and length of the TLMM block.
6- interrupts: Should be the parent IRQ of the TLMM block.
7- interrupt-controller: Marks the device node as an interrupt controller.
8- #interrupt-cells: Should be two.
9- gpio-controller: Marks the device node as a GPIO controller.
10- #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
12 second cell is used for optional parameters.
13
14Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
15a general description of GPIO and interrupt bindings.
16
17Please refer to pinctrl-bindings.txt in this directory for details of the
18common pinctrl bindings used by client devices, including the meaning of the
19phrase "pin configuration node".
20
21Qualcomm's pin configuration nodes act as a container for an abitrary number of
22subnodes. Each of these subnodes represents some desired configuration for a
23pin, a group, or a list of pins or groups. This configuration can include the
24mux function to select on those pin(s)/group(s), and various pin configuration
25parameters, such as pull-up, drive strength, etc.
26
27The name of each subnode is not important; all subnodes should be enumerated
28and processed purely based on their content.
29
30Each subnode only affects those parameters that are explicitly listed. In
31other words, a subnode that lists a mux function but no pin configuration
32parameters implies no information about any pin configuration parameters.
33Similarly, a pin subnode that describes a pullup parameter implies no
34information about e.g. the mux function.
35
36
37The following generic properties as defined in pinctrl-bindings.txt are valid
38to specify in a pin configuration subnode:
39
40 pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,
41 output-low, output-high.
42
43Non-empty subnodes must specify the 'pins' property.
44
45Valid values for qcom,pins are:
46 gpio0-gpio68
47 Supports mux, bias, and drive-strength
48
49 sdc3_clk, sdc3_cmd, sdc3_data
50 Supports bias and drive-strength
51
52
53Valid values for function are:
54 mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gsbi1, gsbi2, gsbi4, gsbi5,
55 gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
56 spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
57 pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
58 pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
59 pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
60 pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold
61
62Example:
63
64 pinmux: pinctrl@800000 {
65 compatible = "qcom,ipq8064-pinctrl";
66 reg = <0x800000 0x4000>;
67
68 gpio-controller;
69 #gpio-cells = <2>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
72 interrupts = <0 32 0x4>;
73
74 pinctrl-names = "default";
75 pinctrl-0 = <&gsbi5_uart_default>;
76
77 gsbi5_uart_default: gsbi5_uart_default {
78 mux {
79 pins = "gpio18", "gpio19";
80 function = "gsbi5";
81 };
82
83 tx {
84 pins = "gpio18";
85 drive-strength = <4>;
86 bias-disable;
87 };
88
89 rx {
90 pins = "gpio19";
91 drive-strength = <2>;
92 bias-pull-up;
93 };
94 };
95 };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
index 9fb89e3f61ea..73262b575dfc 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
@@ -50,7 +50,27 @@ Valid values for pins are:
50 Supports bias and drive-strength 50 Supports bias and drive-strength
51 51
52Valid values for function are: 52Valid values for function are:
53 blsp_i2c2, blsp_i2c6, blsp_i2c11, blsp_spi1, blsp_uart2, blsp_uart8, slimbus 53 cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
54 blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1,
55 blsp_uim2, blsp_uart2, blsp_i2c2, blsp_spi2,
56 blsp_uim3, blsp_uart3, blsp_i2c3, blsp_spi3,
57 blsp_uim4, blsp_uart4, blsp_i2c4, blsp_spi4,
58 blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5,
59 blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6,
60 blsp_uim7, blsp_uart7, blsp_i2c7, blsp_spi7,
61 blsp_uim8, blsp_uart8, blsp_i2c8, blsp_spi8,
62 blsp_uim9, blsp_uart9, blsp_i2c9, blsp_spi9,
63 blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10,
64 blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11,
65 blsp_uim12, blsp_uart12, blsp_i2c12, blsp_spi12,
66 blsp_spi1_cs1, blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2
67 blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
68 sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0, cci_timer1,
69 cci_timer2, cci_timer3, cci_async_in0, cci_async_in1, cci_async_in2,
70 cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc,
71 hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk,
72 gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s,
73 ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus
54 74
55 (Note that this is not yet the complete list of functions) 75 (Note that this is not yet the complete list of functions)
56 76
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index f378d342aae4..cefef741a40b 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -21,13 +21,23 @@ defined as gpio sub-nodes of the pinmux controller.
21Required properties for iomux controller: 21Required properties for iomux controller:
22 - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" 22 - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
23 "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" 23 "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
24 - rockchip,grf: phandle referencing a syscon providing the
25 "general register files"
26
27Optional properties for iomux controller:
28 - rockchip,pmu: phandle referencing a syscon providing the pmu registers
29 as some SoCs carry parts of the iomux controller registers there.
30 Required for at least rk3188 and rk3288.
31
32Deprecated properties for iomux controller:
24 - reg: first element is the general register space of the iomux controller 33 - reg: first element is the general register space of the iomux controller
25 second element is the separate pull register space of the rk3188 34 It should be large enough to contain also separate pull registers.
35 second element is the separate pull register space of the rk3188.
36 Use rockchip,grf and rockchip,pmu described above instead.
26 37
27Required properties for gpio sub nodes: 38Required properties for gpio sub nodes:
28 - compatible: "rockchip,gpio-bank", "rockchip,rk3188-gpio-bank0" 39 - compatible: "rockchip,gpio-bank", "rockchip,rk3188-gpio-bank0"
29 - reg: register of the gpio bank (different than the iomux registerset) 40 - reg: register of the gpio bank (different than the iomux registerset)
30 second element: separate pull register for rk3188 bank0
31 - interrupts: base interrupt of the gpio bank in the interrupt controller 41 - interrupts: base interrupt of the gpio bank in the interrupt controller
32 - clocks: clock that drives this bank 42 - clocks: clock that drives this bank
33 - gpio-controller: identifies the node as a gpio controller and pin bank. 43 - gpio-controller: identifies the node as a gpio controller and pin bank.
@@ -39,6 +49,10 @@ Required properties for gpio sub nodes:
39 cells should use the standard two-cell scheme described in 49 cells should use the standard two-cell scheme described in
40 bindings/interrupt-controller/interrupts.txt 50 bindings/interrupt-controller/interrupts.txt
41 51
52Deprecated properties for gpio sub nodes:
53 - reg: second element: separate pull register for rk3188 bank0, use
54 rockchip,pmu described above instead
55
42Required properties for pin configuration node: 56Required properties for pin configuration node:
43 - rockchip,pins: 3 integers array, represents a group of pins mux and config 57 - rockchip,pins: 3 integers array, represents a group of pins mux and config
44 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. 58 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
@@ -54,7 +68,8 @@ Examples:
54 68
55pinctrl@20008000 { 69pinctrl@20008000 {
56 compatible = "rockchip,rk3066a-pinctrl"; 70 compatible = "rockchip,rk3066a-pinctrl";
57 reg = <0x20008000 0x150>; 71 rockchip,grf = <&grf>;
72
58 #address-cells = <1>; 73 #address-cells = <1>;
59 #size-cells = <1>; 74 #size-cells = <1>;
60 ranges; 75 ranges;
@@ -103,16 +118,15 @@ Example for rk3188:
103 118
104 pinctrl@20008000 { 119 pinctrl@20008000 {
105 compatible = "rockchip,rk3188-pinctrl"; 120 compatible = "rockchip,rk3188-pinctrl";
106 reg = <0x20008000 0xa0>, 121 rockchip,grf = <&grf>;
107 <0x20008164 0x1a0>; 122 rockchip,pmu = <&pmu>;
108 #address-cells = <1>; 123 #address-cells = <1>;
109 #size-cells = <1>; 124 #size-cells = <1>;
110 ranges; 125 ranges;
111 126
112 gpio0: gpio0@0x2000a000 { 127 gpio0: gpio0@0x2000a000 {
113 compatible = "rockchip,rk3188-gpio-bank0"; 128 compatible = "rockchip,rk3188-gpio-bank0";
114 reg = <0x2000a000 0x100>, 129 reg = <0x2000a000 0x100>;
115 <0x20004064 0x8>;
116 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 130 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&clk_gates8 9>; 131 clocks = <&clk_gates8 9>;
118 132
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 201f5e105484..071dce78959a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1629,9 +1629,9 @@ config ARCH_NR_GPIO
1629 int 1629 int
1630 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1630 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1631 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX 1631 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1632 default 416 if ARCH_SUNXI
1632 default 392 if ARCH_U8500 1633 default 392 if ARCH_U8500
1633 default 352 if ARCH_VT8500 1634 default 352 if ARCH_VT8500
1634 default 288 if ARCH_SUNXI
1635 default 264 if MACH_H4700 1635 default 264 if MACH_H4700
1636 default 0 1636 default 0
1637 help 1637 help
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index 69e29f409d4c..d79c6d7f598e 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -180,6 +180,7 @@ static const struct acpi_device_id acpi_lpss_device_ids[] = {
180 { "80860F14", (unsigned long)&byt_sdio_dev_desc }, 180 { "80860F14", (unsigned long)&byt_sdio_dev_desc },
181 { "80860F41", (unsigned long)&byt_i2c_dev_desc }, 181 { "80860F41", (unsigned long)&byt_i2c_dev_desc },
182 { "INT33B2", }, 182 { "INT33B2", },
183 { "INT33FC", },
183 184
184 { "INT3430", (unsigned long)&lpt_dev_desc }, 185 { "INT3430", (unsigned long)&lpt_dev_desc },
185 { "INT3431", (unsigned long)&lpt_dev_desc }, 186 { "INT3431", (unsigned long)&lpt_dev_desc },
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e00c02d0a094..0042ccb46b9a 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -84,6 +84,9 @@ config PINCTRL_AT91
84 depends on ARCH_AT91 84 depends on ARCH_AT91
85 select PINMUX 85 select PINMUX
86 select PINCONF 86 select PINCONF
87 select GPIOLIB
88 select OF_GPIO
89 select GPIOLIB_IRQCHIP
87 help 90 help
88 Say Y here to enable the at91 pinctrl driver 91 Say Y here to enable the at91 pinctrl driver
89 92
@@ -185,6 +188,13 @@ config PINCTRL_IMX6SL
185 help 188 help
186 Say Y here to enable the imx6sl pinctrl driver 189 Say Y here to enable the imx6sl pinctrl driver
187 190
191config PINCTRL_IMX6SX
192 bool "IMX6SX pinctrl driver"
193 depends on SOC_IMX6SX
194 select PINCTRL_IMX
195 help
196 Say Y here to enable the imx6sx pinctrl driver
197
188config PINCTRL_VF610 198config PINCTRL_VF610
189 bool "Freescale Vybrid VF610 pinctrl driver" 199 bool "Freescale Vybrid VF610 pinctrl driver"
190 depends on SOC_VF610 200 depends on SOC_VF610
@@ -221,10 +231,27 @@ config PINCTRL_MSM
221 select PINMUX 231 select PINMUX
222 select PINCONF 232 select PINCONF
223 select GENERIC_PINCONF 233 select GENERIC_PINCONF
234 select GPIOLIB_IRQCHIP
235
236config PINCTRL_APQ8064
237 tristate "Qualcomm APQ8064 pin controller driver"
238 depends on GPIOLIB && OF
239 select PINCTRL_MSM
240 help
241 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
242 Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
243
244config PINCTRL_IPQ8064
245 tristate "Qualcomm IPQ8064 pin controller driver"
246 depends on GPIOLIB && OF
247 select PINCTRL_MSM
248 help
249 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
250 Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
224 251
225config PINCTRL_MSM8X74 252config PINCTRL_MSM8X74
226 tristate "Qualcomm 8x74 pin controller driver" 253 tristate "Qualcomm 8x74 pin controller driver"
227 depends on GPIOLIB && OF 254 depends on GPIOLIB && OF && (ARCH_QCOM || COMPILE_TEST)
228 select PINCTRL_MSM 255 select PINCTRL_MSM
229 help 256 help
230 This is the pinctrl, pinmux, pinconf and gpiolib driver for the 257 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@@ -256,6 +283,7 @@ config PINCTRL_ROCKCHIP
256 select PINMUX 283 select PINMUX
257 select GENERIC_PINCONF 284 select GENERIC_PINCONF
258 select GENERIC_IRQ_CHIP 285 select GENERIC_IRQ_CHIP
286 select MFD_SYSCON
259 287
260config PINCTRL_SINGLE 288config PINCTRL_SINGLE
261 tristate "One-register-per-pin type device tree based pinctrl driver" 289 tristate "One-register-per-pin type device tree based pinctrl driver"
@@ -270,17 +298,14 @@ config PINCTRL_SIRF
270 bool "CSR SiRFprimaII/SiRFmarco pin controller driver" 298 bool "CSR SiRFprimaII/SiRFmarco pin controller driver"
271 depends on ARCH_SIRF 299 depends on ARCH_SIRF
272 select PINMUX 300 select PINMUX
273 301 select GPIOLIB_IRQCHIP
274config PINCTRL_SUNXI
275 bool
276 select PINMUX
277 select GENERIC_PINCONF
278 302
279config PINCTRL_ST 303config PINCTRL_ST
280 bool 304 bool
281 depends on OF 305 depends on OF
282 select PINMUX 306 select PINMUX
283 select PINCONF 307 select PINCONF
308 select GPIOLIB_IRQCHIP
284 309
285config PINCTRL_TEGRA 310config PINCTRL_TEGRA
286 bool 311 bool
@@ -368,9 +393,11 @@ config PINCTRL_S3C64XX
368 depends on ARCH_S3C64XX 393 depends on ARCH_S3C64XX
369 select PINCTRL_SAMSUNG 394 select PINCTRL_SAMSUNG
370 395
396source "drivers/pinctrl/berlin/Kconfig"
371source "drivers/pinctrl/mvebu/Kconfig" 397source "drivers/pinctrl/mvebu/Kconfig"
372source "drivers/pinctrl/sh-pfc/Kconfig" 398source "drivers/pinctrl/sh-pfc/Kconfig"
373source "drivers/pinctrl/spear/Kconfig" 399source "drivers/pinctrl/spear/Kconfig"
400source "drivers/pinctrl/sunxi/Kconfig"
374source "drivers/pinctrl/vt8500/Kconfig" 401source "drivers/pinctrl/vt8500/Kconfig"
375 402
376config PINCTRL_XWAY 403config PINCTRL_XWAY
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6d3fd62b9ae8..c4b5d405b8f5 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -32,12 +32,15 @@ obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
32obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o 32obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
33obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o 33obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
34obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o 34obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
35obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
35obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 36obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
36obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o 37obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
37obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 38obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
38obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o 39obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
39obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o 40obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
40obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o 41obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
42obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
43obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
41obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o 44obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
42obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o 45obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
43obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o 46obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
@@ -47,7 +50,6 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
47obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o 50obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
48obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 51obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
49obj-$(CONFIG_PINCTRL_SIRF) += sirf/ 52obj-$(CONFIG_PINCTRL_SIRF) += sirf/
50obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o
51obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o 53obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
52obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o 54obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
53obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o 55obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
@@ -68,8 +70,10 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
68obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o 70obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
69obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o 71obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
70 72
73obj-$(CONFIG_ARCH_BERLIN) += berlin/
71obj-$(CONFIG_PLAT_ORION) += mvebu/ 74obj-$(CONFIG_PLAT_ORION) += mvebu/
72obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ 75obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
73obj-$(CONFIG_SUPERH) += sh-pfc/ 76obj-$(CONFIG_SUPERH) += sh-pfc/
74obj-$(CONFIG_PLAT_SPEAR) += spear/ 77obj-$(CONFIG_PLAT_SPEAR) += spear/
75obj-$(CONFIG_ARCH_VT8500) += vt8500/ 78obj-$(CONFIG_ARCH_VT8500) += vt8500/
79obj-$(CONFIG_ARCH_SUNXI) += sunxi/
diff --git a/drivers/pinctrl/berlin/Kconfig b/drivers/pinctrl/berlin/Kconfig
new file mode 100644
index 000000000000..b18322bc7bf9
--- /dev/null
+++ b/drivers/pinctrl/berlin/Kconfig
@@ -0,0 +1,20 @@
1if ARCH_BERLIN
2
3config PINCTRL_BERLIN
4 bool
5 select PINMUX
6 select REGMAP_MMIO
7
8config PINCTRL_BERLIN_BG2
9 bool
10 select PINCTRL_BERLIN
11
12config PINCTRL_BERLIN_BG2CD
13 bool
14 select PINCTRL_BERLIN
15
16config PINCTRL_BERLIN_BG2Q
17 bool
18 select PINCTRL_BERLIN
19
20endif
diff --git a/drivers/pinctrl/berlin/Makefile b/drivers/pinctrl/berlin/Makefile
new file mode 100644
index 000000000000..deb0c6baf316
--- /dev/null
+++ b/drivers/pinctrl/berlin/Makefile
@@ -0,0 +1,4 @@
1obj-$(CONFIG_PINCTRL_BERLIN) += berlin.o
2obj-$(CONFIG_PINCTRL_BERLIN_BG2) += berlin-bg2.o
3obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o
4obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o
diff --git a/drivers/pinctrl/berlin/berlin-bg2.c b/drivers/pinctrl/berlin/berlin-bg2.c
new file mode 100644
index 000000000000..dcd4f6a4fc50
--- /dev/null
+++ b/drivers/pinctrl/berlin/berlin-bg2.c
@@ -0,0 +1,274 @@
1/*
2 * Marvell Berlin BG2 pinctrl driver.
3 *
4 * Copyright (C) 2014 Marvell Technology Group Ltd.
5 *
6 * Antoine Ténart <antoine.tenart@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17
18#include "berlin.h"
19
20static const struct berlin_desc_group berlin2_soc_pinctrl_groups[] = {
21 /* G */
22 BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00,
23 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
24 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
25 BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01,
26 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
27 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
28 BERLIN_PINCTRL_FUNCTION(0x2, "usb1")),
29 BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02,
30 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
31 BERLIN_PINCTRL_FUNCTION(0x1, "spi1"),
32 BERLIN_PINCTRL_FUNCTION(0x2, "pwm"),
33 BERLIN_PINCTRL_FUNCTION(0x3, "i2s0")),
34 BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04,
35 BERLIN_PINCTRL_FUNCTION(0x0, "soc"),
36 BERLIN_PINCTRL_FUNCTION(0x1, "spi1"),
37 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
38 BERLIN_PINCTRL_FUNCTION(0x3, "i2s1")),
39 BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06,
40 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
41 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
42 BERLIN_PINCTRL_FUNCTION(0x2, "pwm")),
43 BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08,
44 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
45 BERLIN_PINCTRL_FUNCTION(0x1, "sts1"),
46 BERLIN_PINCTRL_FUNCTION(0x2, "et"),
47 /*
48 * Mode 0x3 mux i2s2 mclk *and* i2s3 mclk:
49 * add two functions so it can be used with other groups
50 * within the same subnode in the device tree
51 */
52 BERLIN_PINCTRL_FUNCTION(0x3, "i2s2"),
53 BERLIN_PINCTRL_FUNCTION(0x3, "i2s3")),
54 BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b,
55 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
56 BERLIN_PINCTRL_FUNCTION(0x1, "sts0"),
57 BERLIN_PINCTRL_FUNCTION(0x2, "et")),
58 BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x0d,
59 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
60 BERLIN_PINCTRL_FUNCTION(0x1, "sts0"),
61 BERLIN_PINCTRL_FUNCTION(0x2, "et"),
62 BERLIN_PINCTRL_FUNCTION(0x3, "vdac")),
63 BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10,
64 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
65 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
66 BERLIN_PINCTRL_FUNCTION(0x2, "et"),
67 BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"),
68 BERLIN_PINCTRL_FUNCTION(0x4, "sata_dbg"),
69 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
70 BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13,
71 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
72 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
73 BERLIN_PINCTRL_FUNCTION(0x2, "et"),
74 BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"),
75 BERLIN_PINCTRL_FUNCTION(0x4, "sata_dbg"),
76 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
77 BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16,
78 BERLIN_PINCTRL_FUNCTION(0x0, "soc"),
79 BERLIN_PINCTRL_FUNCTION(0x1, "twsi0"),
80 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
81 BERLIN_PINCTRL_FUNCTION(0x3, "ptp")),
82 BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18,
83 BERLIN_PINCTRL_FUNCTION(0x0, "soc"),
84 BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"),
85 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
86 BERLIN_PINCTRL_FUNCTION(0x3, "eddc")),
87 BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a,
88 BERLIN_PINCTRL_FUNCTION(0x0, "sts2"),
89 BERLIN_PINCTRL_FUNCTION(0x1, "sata"),
90 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"),
91 BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"),
92 BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
93 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
94 BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x00,
95 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
96 BERLIN_PINCTRL_FUNCTION(0x1, "sata"),
97 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"),
98 BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"),
99 BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
100 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
101 BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x03,
102 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
103 BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04,
104 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
105 BERLIN_PINCTRL_FUNCTION(0x2, "et"),
106 BERLIN_PINCTRL_FUNCTION(0x3, "osco")),
107 BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x06,
108 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
109 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
110 BERLIN_PINCTRL_FUNCTION(0x2, "fp")),
111 BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x09,
112 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
113 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
114 BERLIN_PINCTRL_FUNCTION(0x2, "fp")),
115 BERLIN_PINCTRL_GROUP("G18", 0x04, 0x1, 0x0c,
116 BERLIN_PINCTRL_FUNCTION(0x0, "pll"),
117 BERLIN_PINCTRL_FUNCTION(0x1, "i2s0")),
118 BERLIN_PINCTRL_GROUP("G19", 0x04, 0x1, 0x0d,
119 BERLIN_PINCTRL_FUNCTION(0x0, "i2s0"),
120 BERLIN_PINCTRL_FUNCTION(0x1, "pwm")),
121 BERLIN_PINCTRL_GROUP("G20", 0x04, 0x1, 0x0e,
122 BERLIN_PINCTRL_FUNCTION(0x0, "spdif"),
123 BERLIN_PINCTRL_FUNCTION(0x1, "arc")),
124 BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x0f,
125 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
126 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
127 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
128 BERLIN_PINCTRL_FUNCTION(0x3, "adac_dbg"),
129 BERLIN_PINCTRL_FUNCTION(0x4, "pdm_a"), /* gpio17..19,pdm */
130 BERLIN_PINCTRL_FUNCTION(0x7, "pdm_b")), /* gpio12..14,pdm */
131 BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x12,
132 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
133 BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
134 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
135 BERLIN_PINCTRL_FUNCTION(0x3, "twsi0"),
136 BERLIN_PINCTRL_FUNCTION(0x4, "pwm")),
137 BERLIN_PINCTRL_GROUP("G23", 0x04, 0x3, 0x15,
138 BERLIN_PINCTRL_FUNCTION(0x0, "vclki"),
139 BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
140 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
141 BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"),
142 BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
143 BERLIN_PINCTRL_FUNCTION(0x7, "pdm")),
144 BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18,
145 BERLIN_PINCTRL_FUNCTION(0x0, "i2s2"),
146 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1")),
147 BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a,
148 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
149 BERLIN_PINCTRL_FUNCTION(0x1, "nand"),
150 BERLIN_PINCTRL_FUNCTION(0x2, "i2s2")),
151 BERLIN_PINCTRL_GROUP("G26", 0x04, 0x1, 0x1c,
152 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
153 BERLIN_PINCTRL_FUNCTION(0x1, "emmc")),
154 BERLIN_PINCTRL_GROUP("G27", 0x04, 0x1, 0x1d,
155 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
156 BERLIN_PINCTRL_FUNCTION(0x1, "nand")),
157 BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e,
158 BERLIN_PINCTRL_FUNCTION(0x0, "dvo"),
159 BERLIN_PINCTRL_FUNCTION(0x2, "sp")),
160};
161
162static const struct berlin_desc_group berlin2_sysmgr_pinctrl_groups[] = {
163 /* GSM */
164 BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
165 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
166 BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
167 BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
168 BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
169 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
170 BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
171 BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
172 BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
173 BERLIN_PINCTRL_FUNCTION(0x0, "twsi2"),
174 BERLIN_PINCTRL_FUNCTION(0x1, "spi2")),
175 BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
176 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
177 BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* CTS/RTS */
178 BERLIN_PINCTRL_FUNCTION(0x2, "uart2"), /* RX/TX */
179 BERLIN_PINCTRL_FUNCTION(0x3, "twsi2")),
180 BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x2, 0x08,
181 BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */
182 BERLIN_PINCTRL_FUNCTION(0x1, "irda0")),
183 BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x2, 0x0a,
184 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
185 BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RX/TX */
186 BERLIN_PINCTRL_FUNCTION(0x2, "irda1"),
187 BERLIN_PINCTRL_FUNCTION(0x3, "twsi3")),
188 BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c,
189 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
190 BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
191 BERLIN_PINCTRL_FUNCTION(0x1, "clki")),
192 BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0e,
193 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
194 BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
195 BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0f,
196 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
197 BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
198 BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x10,
199 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
200 BERLIN_PINCTRL_FUNCTION(0x1, "led")),
201 BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x11,
202 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
203 BERLIN_PINCTRL_FUNCTION(0x1, "led")),
204 BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x12,
205 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
206 BERLIN_PINCTRL_FUNCTION(0x1, "led")),
207};
208
209static const struct berlin_pinctrl_desc berlin2_soc_pinctrl_data = {
210 .groups = berlin2_soc_pinctrl_groups,
211 .ngroups = ARRAY_SIZE(berlin2_soc_pinctrl_groups),
212};
213
214static const struct berlin_pinctrl_desc berlin2_sysmgr_pinctrl_data = {
215 .groups = berlin2_sysmgr_pinctrl_groups,
216 .ngroups = ARRAY_SIZE(berlin2_sysmgr_pinctrl_groups),
217};
218
219static const struct of_device_id berlin2_pinctrl_match[] = {
220 {
221 .compatible = "marvell,berlin2-chip-ctrl",
222 .data = &berlin2_soc_pinctrl_data
223 },
224 {
225 .compatible = "marvell,berlin2-system-ctrl",
226 .data = &berlin2_sysmgr_pinctrl_data
227 },
228 {}
229};
230MODULE_DEVICE_TABLE(of, berlin2_pinctrl_match);
231
232static int berlin2_pinctrl_probe(struct platform_device *pdev)
233{
234 const struct of_device_id *match =
235 of_match_device(berlin2_pinctrl_match, &pdev->dev);
236 struct regmap_config *rmconfig;
237 struct regmap *regmap;
238 struct resource *res;
239 void __iomem *base;
240
241 rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL);
242 if (!rmconfig)
243 return -ENOMEM;
244
245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
246 base = devm_ioremap_resource(&pdev->dev, res);
247 if (IS_ERR(base))
248 return PTR_ERR(base);
249
250 rmconfig->reg_bits = 32,
251 rmconfig->val_bits = 32,
252 rmconfig->reg_stride = 4,
253 rmconfig->max_register = resource_size(res);
254
255 regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig);
256 if (IS_ERR(regmap))
257 return PTR_ERR(regmap);
258
259 return berlin_pinctrl_probe(pdev, match->data);
260}
261
262static struct platform_driver berlin2_pinctrl_driver = {
263 .probe = berlin2_pinctrl_probe,
264 .driver = {
265 .name = "berlin-bg2-pinctrl",
266 .owner = THIS_MODULE,
267 .of_match_table = berlin2_pinctrl_match,
268 },
269};
270module_platform_driver(berlin2_pinctrl_driver);
271
272MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
273MODULE_DESCRIPTION("Marvell Berlin BG2 pinctrl driver");
274MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c
new file mode 100644
index 000000000000..89d585ef7da7
--- /dev/null
+++ b/drivers/pinctrl/berlin/berlin-bg2cd.c
@@ -0,0 +1,217 @@
1/*
2 * Marvell Berlin BG2CD pinctrl driver.
3 *
4 * Copyright (C) 2014 Marvell Technology Group Ltd.
5 *
6 * Antoine Ténart <antoine.tenart@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17
18#include "berlin.h"
19
20static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = {
21 /* G */
22 BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00,
23 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
24 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
25 BERLIN_PINCTRL_FUNCTION(0x2, "led"),
26 BERLIN_PINCTRL_FUNCTION(0x3, "pwm")),
27 BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01,
28 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
29 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
30 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
31 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
32 BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02,
33 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
34 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
35 BERLIN_PINCTRL_FUNCTION(0x2, "fe"),
36 BERLIN_PINCTRL_FUNCTION(0x3, "pll"),
37 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
38 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
39 BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04,
40 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
41 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
42 BERLIN_PINCTRL_FUNCTION(0x2, "twsi2"),
43 BERLIN_PINCTRL_FUNCTION(0x3, "pll"),
44 BERLIN_PINCTRL_FUNCTION(0x4, "fe"),
45 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
46 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
47 BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06,
48 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
49 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
50 BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"),
51 BERLIN_PINCTRL_FUNCTION(0x3, "pll"),
52 BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
53 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
54 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
55 BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08,
56 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
57 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
58 BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"),
59 BERLIN_PINCTRL_FUNCTION(0x3, "arc"),
60 BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
61 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
62 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
63 BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b,
64 BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */
65 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
66 BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x0d,
67 BERLIN_PINCTRL_FUNCTION(0x0, "eddc"),
68 BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"),
69 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
70 BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10,
71 BERLIN_PINCTRL_FUNCTION(0x0, "ss0"),
72 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
73 BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13,
74 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
75 BERLIN_PINCTRL_FUNCTION(0x1, "spi1"),
76 BERLIN_PINCTRL_FUNCTION(0x2, "twsi0")),
77 BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16,
78 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
79 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
80 BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18,
81 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
82 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
83 BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a,
84 BERLIN_PINCTRL_FUNCTION(0x0, "usb1"),
85 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
86 BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x00,
87 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
88 BERLIN_PINCTRL_FUNCTION(0x1, "usb0_dbg"),
89 BERLIN_PINCTRL_FUNCTION(0x2, "usb1_dbg")),
90 BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x03,
91 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
92 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
93 BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04,
94 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
95 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
96 BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x06,
97 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
98 BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x09,
99 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
100 BERLIN_PINCTRL_GROUP("G18", 0x04, 0x1, 0x0c,
101 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
102 BERLIN_PINCTRL_GROUP("G19", 0x04, 0x1, 0x0d,
103 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
104 BERLIN_PINCTRL_GROUP("G20", 0x04, 0x1, 0x0e,
105 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
106 BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x0f,
107 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
108 BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x12,
109 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
110 BERLIN_PINCTRL_GROUP("G23", 0x04, 0x3, 0x15,
111 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
112 BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18,
113 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
114 BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a,
115 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
116 BERLIN_PINCTRL_GROUP("G26", 0x04, 0x1, 0x1c,
117 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
118 BERLIN_PINCTRL_GROUP("G27", 0x04, 0x1, 0x1d,
119 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
120 BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e,
121 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
122};
123
124static const struct berlin_desc_group berlin2cd_sysmgr_pinctrl_groups[] = {
125 /* GSM */
126 BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
127 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
128 BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
129 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
130 BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
131 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
132 BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
133 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
134 BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x2, 0x08,
135 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
136 BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x2, 0x0a,
137 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
138 BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c,
139 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
140 BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0e,
141 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
142 BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0f,
143 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
144 BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x10,
145 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
146 BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x11,
147 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
148 BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x12,
149 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
150};
151
152static const struct berlin_pinctrl_desc berlin2cd_soc_pinctrl_data = {
153 .groups = berlin2cd_soc_pinctrl_groups,
154 .ngroups = ARRAY_SIZE(berlin2cd_soc_pinctrl_groups),
155};
156
157static const struct berlin_pinctrl_desc berlin2cd_sysmgr_pinctrl_data = {
158 .groups = berlin2cd_sysmgr_pinctrl_groups,
159 .ngroups = ARRAY_SIZE(berlin2cd_sysmgr_pinctrl_groups),
160};
161
162static const struct of_device_id berlin2cd_pinctrl_match[] = {
163 {
164 .compatible = "marvell,berlin2cd-chip-ctrl",
165 .data = &berlin2cd_soc_pinctrl_data
166 },
167 {
168 .compatible = "marvell,berlin2cd-system-ctrl",
169 .data = &berlin2cd_sysmgr_pinctrl_data
170 },
171 {}
172};
173MODULE_DEVICE_TABLE(of, berlin2cd_pinctrl_match);
174
175static int berlin2cd_pinctrl_probe(struct platform_device *pdev)
176{
177 const struct of_device_id *match =
178 of_match_device(berlin2cd_pinctrl_match, &pdev->dev);
179 struct regmap_config *rmconfig;
180 struct regmap *regmap;
181 struct resource *res;
182 void __iomem *base;
183
184 rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL);
185 if (!rmconfig)
186 return -ENOMEM;
187
188 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
189 base = devm_ioremap_resource(&pdev->dev, res);
190 if (IS_ERR(base))
191 return PTR_ERR(base);
192
193 rmconfig->reg_bits = 32,
194 rmconfig->val_bits = 32,
195 rmconfig->reg_stride = 4,
196 rmconfig->max_register = resource_size(res);
197
198 regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig);
199 if (IS_ERR(regmap))
200 return PTR_ERR(regmap);
201
202 return berlin_pinctrl_probe(pdev, match->data);
203}
204
205static struct platform_driver berlin2cd_pinctrl_driver = {
206 .probe = berlin2cd_pinctrl_probe,
207 .driver = {
208 .name = "berlin-bg2cd-pinctrl",
209 .owner = THIS_MODULE,
210 .of_match_table = berlin2cd_pinctrl_match,
211 },
212};
213module_platform_driver(berlin2cd_pinctrl_driver);
214
215MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
216MODULE_DESCRIPTION("Marvell Berlin BG2CD pinctrl driver");
217MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/berlin/berlin-bg2q.c b/drivers/pinctrl/berlin/berlin-bg2q.c
new file mode 100644
index 000000000000..9fcf9836045c
--- /dev/null
+++ b/drivers/pinctrl/berlin/berlin-bg2q.c
@@ -0,0 +1,436 @@
1/*
2 * Marvell Berlin BG2Q pinctrl driver
3 *
4 * Copyright (C) 2014 Marvell Technology Group Ltd.
5 *
6 * Antoine Ténart <antoine.tenart@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17
18#include "berlin.h"
19
20static const struct berlin_desc_group berlin2q_soc_pinctrl_groups[] = {
21 /* G */
22 BERLIN_PINCTRL_GROUP("G0", 0x18, 0x3, 0x00,
23 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
24 BERLIN_PINCTRL_FUNCTION(0x1, "mmc"),
25 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
26 BERLIN_PINCTRL_GROUP("G1", 0x18, 0x3, 0x03,
27 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
28 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
29 BERLIN_PINCTRL_GROUP("G2", 0x18, 0x3, 0x06,
30 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
31 BERLIN_PINCTRL_FUNCTION(0x2, "arc"),
32 BERLIN_PINCTRL_FUNCTION(0x3, "lvds")),
33 BERLIN_PINCTRL_GROUP("G3", 0x18, 0x3, 0x09,
34 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
35 BERLIN_PINCTRL_FUNCTION(0x2, "i2s2"),
36 BERLIN_PINCTRL_FUNCTION(0x3, "lvds")),
37 BERLIN_PINCTRL_GROUP("G4", 0x18, 0x3, 0x0c,
38 BERLIN_PINCTRL_FUNCTION(0x0, "pll"),
39 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
40 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
41 BERLIN_PINCTRL_FUNCTION(0x3, "gpio"),
42 BERLIN_PINCTRL_FUNCTION(0x5, "sata_dbg"),
43 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
44 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
45 BERLIN_PINCTRL_GROUP("G5", 0x18, 0x3, 0x0f,
46 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
47 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
48 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
49 BERLIN_PINCTRL_FUNCTION(0x5, "sata_dbg"),
50 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
51 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
52 BERLIN_PINCTRL_GROUP("G6", 0x18, 0x3, 0x12,
53 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
54 BERLIN_PINCTRL_FUNCTION(0x1, "twsi0"),
55 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
56 BERLIN_PINCTRL_GROUP("G7", 0x18, 0x3, 0x15,
57 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
58 BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"),
59 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
60 BERLIN_PINCTRL_FUNCTION(0x3, "eddc")),
61 BERLIN_PINCTRL_GROUP("G8", 0x18, 0x3, 0x18,
62 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
63 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
64 BERLIN_PINCTRL_GROUP("G9", 0x18, 0x3, 0x1b,
65 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"),
66 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
67 BERLIN_PINCTRL_FUNCTION(0x5, "sata")),
68 BERLIN_PINCTRL_GROUP("G10", 0x1c, 0x3, 0x00,
69 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
70 BERLIN_PINCTRL_FUNCTION(0x1, "spi1"),
71 BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"),
72 BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
73 BERLIN_PINCTRL_FUNCTION(0x5, "sata")),
74 BERLIN_PINCTRL_GROUP("G11", 0x1c, 0x3, 0x03,
75 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
76 BERLIN_PINCTRL_FUNCTION(0x1, "spi1"),
77 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
78 BERLIN_PINCTRL_FUNCTION(0x3, "i2s1"),
79 BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
80 BERLIN_PINCTRL_FUNCTION(0x5, "sata")),
81 BERLIN_PINCTRL_GROUP("G12", 0x1c, 0x3, 0x06,
82 BERLIN_PINCTRL_FUNCTION(0x0, "agc"),
83 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
84 BERLIN_PINCTRL_GROUP("G13", 0x1c, 0x3, 0x09,
85 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
86 BERLIN_PINCTRL_FUNCTION(0x1, "sts1"),
87 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
88 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
89 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
90 BERLIN_PINCTRL_GROUP("G14", 0x1c, 0x3, 0x0c,
91 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
92 BERLIN_PINCTRL_FUNCTION(0x1, "sts0"),
93 BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
94 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
95 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
96 BERLIN_PINCTRL_GROUP("G15", 0x1c, 0x3, 0x0f,
97 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
98 BERLIN_PINCTRL_FUNCTION(0x1, "sts0"),
99 BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
100 BERLIN_PINCTRL_FUNCTION(0x5, "vdac"),
101 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
102 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
103 BERLIN_PINCTRL_GROUP("G16", 0x1c, 0x3, 0x12,
104 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
105 BERLIN_PINCTRL_FUNCTION(0x1, "sts0"),
106 BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
107 BERLIN_PINCTRL_FUNCTION(0x5, "osco"),
108 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
109 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
110 BERLIN_PINCTRL_GROUP("G17", 0x1c, 0x3, 0x15,
111 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
112 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
113 BERLIN_PINCTRL_FUNCTION(0x3, "spdif"),
114 BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
115 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
116 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
117 BERLIN_PINCTRL_GROUP("G18", 0x1c, 0x3, 0x18,
118 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
119 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
120 BERLIN_PINCTRL_FUNCTION(0x3, "i2s2"),
121 BERLIN_PINCTRL_FUNCTION(0x4, "sts1")),
122 BERLIN_PINCTRL_GROUP("G19", 0x1c, 0x3, 0x1b,
123 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
124 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
125 BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"),
126 BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
127 BERLIN_PINCTRL_FUNCTION(0x5, "osco")),
128 BERLIN_PINCTRL_GROUP("G20", 0x20, 0x3, 0x00,
129 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
130 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
131 BERLIN_PINCTRL_FUNCTION(0x3, "demod"),
132 /*
133 * Mode 0x4 mux usb2_dbg *and* usb3_dbg:
134 * add two functions so it can be used with other groups
135 * within the same subnode in the device tree
136 */
137 BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg"),
138 BERLIN_PINCTRL_FUNCTION(0x4, "usb3_dbg")),
139 BERLIN_PINCTRL_GROUP("G21", 0x20, 0x3, 0x03,
140 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
141 BERLIN_PINCTRL_FUNCTION(0x1, "sts2"),
142 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
143 BERLIN_PINCTRL_FUNCTION(0x3, "demod")),
144 BERLIN_PINCTRL_GROUP("G22", 0x20, 0x3, 0x06,
145 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
146 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
147 BERLIN_PINCTRL_GROUP("G23", 0x20, 0x3, 0x09,
148 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
149 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
150 BERLIN_PINCTRL_FUNCTION(0x3, "avif"),
151 BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")),
152 BERLIN_PINCTRL_GROUP("G24", 0x20, 0x3, 0x0c,
153 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
154 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
155 BERLIN_PINCTRL_FUNCTION(0x3, "demod"),
156 BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")),
157 BERLIN_PINCTRL_GROUP("G25", 0x20, 0x3, 0x0f,
158 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
159 BERLIN_PINCTRL_FUNCTION(0x1, "vga"),
160 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
161 BERLIN_PINCTRL_FUNCTION(0x3, "avif"),
162 BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")),
163 BERLIN_PINCTRL_GROUP("G26", 0x20, 0x3, 0x12,
164 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
165 BERLIN_PINCTRL_FUNCTION(0x1, "lvds"),
166 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
167 BERLIN_PINCTRL_GROUP("G27", 0x20, 0x3, 0x15,
168 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
169 BERLIN_PINCTRL_FUNCTION(0x1, "agc"),
170 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
171 BERLIN_PINCTRL_GROUP("G28", 0x20, 0x3, 0x18,
172 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
173 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
174 BERLIN_PINCTRL_FUNCTION(0x3, "avif"),
175 BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")),
176 BERLIN_PINCTRL_GROUP("G29", 0x20, 0x3, 0x1b,
177 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
178 BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"),
179 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
180 BERLIN_PINCTRL_GROUP("G30", 0x24, 0x3, 0x00,
181 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
182 BERLIN_PINCTRL_FUNCTION(0x1, "scrd1"),
183 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
184 BERLIN_PINCTRL_GROUP("G31", 0x24, 0x3, 0x03,
185 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
186 BERLIN_PINCTRL_FUNCTION(0x1, "sd1"),
187 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
188 BERLIN_PINCTRL_GROUP("G32", 0x24, 0x3, 0x06,
189 BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
190 BERLIN_PINCTRL_FUNCTION(0x1, "sd1"),
191 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
192 /* GAV */
193 BERLIN_PINCTRL_GROUP("GAV0", 0x24, 0x3, 0x09,
194 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
195 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
196 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
197 BERLIN_PINCTRL_FUNCTION(0x4, "lvds")),
198 BERLIN_PINCTRL_GROUP("GAV1", 0x24, 0x3, 0x0c,
199 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
200 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
201 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
202 BERLIN_PINCTRL_FUNCTION(0x4, "vga")),
203 BERLIN_PINCTRL_GROUP("GAV2", 0x24, 0x3, 0x0f,
204 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
205 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
206 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
207 BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"),
208 BERLIN_PINCTRL_FUNCTION(0x4, "pdm"),
209 BERLIN_PINCTRL_FUNCTION(0x6, "adac")),
210 BERLIN_PINCTRL_GROUP("GAV3", 0x24, 0x3, 0x12,
211 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
212 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
213 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
214 BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"),
215 BERLIN_PINCTRL_FUNCTION(0x6, "adac")),
216 BERLIN_PINCTRL_GROUP("GAV4", 0x24, 0x3, 0x15,
217 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
218 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
219 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
220 BERLIN_PINCTRL_FUNCTION(0x4, "i2s1"),
221 BERLIN_PINCTRL_FUNCTION(0x6, "adac")),
222 BERLIN_PINCTRL_GROUP("GAV5", 0x24, 0x3, 0x18,
223 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
224 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
225 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
226 BERLIN_PINCTRL_FUNCTION(0x4, "spdif")),
227 BERLIN_PINCTRL_GROUP("GAV6", 0x24, 0x3, 0x1b,
228 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
229 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
230 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
231 BERLIN_PINCTRL_FUNCTION(0x4, "i2s2")),
232 BERLIN_PINCTRL_GROUP("GAV7", 0x28, 0x3, 0x00,
233 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
234 BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
235 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
236 BERLIN_PINCTRL_FUNCTION(0x4, "i2s3")),
237 BERLIN_PINCTRL_GROUP("GAV8", 0x28, 0x3, 0x03,
238 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
239 BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
240 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
241 BERLIN_PINCTRL_FUNCTION(0x4, "pwm")),
242 BERLIN_PINCTRL_GROUP("GAV9", 0x28, 0x3, 0x06,
243 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
244 BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
245 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
246 BERLIN_PINCTRL_FUNCTION(0x4, "pwm")),
247 BERLIN_PINCTRL_GROUP("GAV10", 0x28, 0x3, 0x09,
248 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
249 BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
250 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
251 BERLIN_PINCTRL_FUNCTION(0x4, "agc")),
252 BERLIN_PINCTRL_GROUP("GAV11", 0x28, 0x3, 0x0c,
253 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
254 BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
255 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
256 BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"),
257 BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
258 BERLIN_PINCTRL_FUNCTION(0x5, "vclki")),
259 BERLIN_PINCTRL_GROUP("GAV12", 0x28, 0x3, 0x0f,
260 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
261 BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"),
262 BERLIN_PINCTRL_FUNCTION(0x2, "i2s1")),
263 BERLIN_PINCTRL_GROUP("GAV13", 0x28, 0x3, 0x12,
264 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
265 BERLIN_PINCTRL_FUNCTION(0x1, "i2s2")),
266 BERLIN_PINCTRL_GROUP("GAV14", 0x28, 0x3, 0x15,
267 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
268 BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"),
269 BERLIN_PINCTRL_FUNCTION(0x2, "i2s1")),
270 BERLIN_PINCTRL_GROUP("GAV15", 0x28, 0x3, 0x18,
271 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
272 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"),
273 BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")),
274 BERLIN_PINCTRL_GROUP("GAV16", 0x28, 0x3, 0x1b,
275 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
276 BERLIN_PINCTRL_FUNCTION(0x1, "i2s0"),
277 BERLIN_PINCTRL_FUNCTION(0x2, "i2s1"),
278 BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"),
279 BERLIN_PINCTRL_FUNCTION(0x5, "pdm"),
280 BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")),
281 BERLIN_PINCTRL_GROUP("GAV17", 0x2c, 0x3, 0x00,
282 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
283 BERLIN_PINCTRL_FUNCTION(0x1, "i2s0"),
284 BERLIN_PINCTRL_FUNCTION(0x2, "i2s1"),
285 BERLIN_PINCTRL_FUNCTION(0x3, "pwm"),
286 BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"),
287 BERLIN_PINCTRL_FUNCTION(0x5, "pdm"),
288 BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")),
289 BERLIN_PINCTRL_GROUP("GAV18", 0x2c, 0x3, 0x03,
290 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
291 BERLIN_PINCTRL_FUNCTION(0x1, "spdif"),
292 BERLIN_PINCTRL_FUNCTION(0x2, "arc")),
293 BERLIN_PINCTRL_GROUP("GAV19", 0x2c, 0x3, 0x06,
294 BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
295 BERLIN_PINCTRL_FUNCTION(0x1, "spdif"),
296 BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"),
297 BERLIN_PINCTRL_FUNCTION(0x5, "pdm")),
298};
299
300static const struct berlin_desc_group berlin2q_sysmgr_pinctrl_groups[] = {
301 /* GSM */
302 BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
303 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
304 BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
305 BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
306 BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
307 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
308 BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
309 BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
310 BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
311 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
312 BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
313 BERLIN_PINCTRL_FUNCTION(0x2, "eddc")),
314 BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
315 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
316 BERLIN_PINCTRL_FUNCTION(0x1, "spi2"),
317 BERLIN_PINCTRL_FUNCTION(0x2, "eddc")),
318 BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x1, 0x08,
319 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
320 BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
321 BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x1, 0x09,
322 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
323 BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
324 BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x1, 0x0a,
325 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
326 BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
327 BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0b,
328 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
329 BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
330 BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0c,
331 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
332 BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
333 BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x0d,
334 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
335 BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
336 BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x0e,
337 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
338 BERLIN_PINCTRL_FUNCTION(0x1, "led")),
339 BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x0f,
340 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
341 BERLIN_PINCTRL_FUNCTION(0x1, "led")),
342 BERLIN_PINCTRL_GROUP("GSM12", 0x40, 0x2, 0x10,
343 BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */
344 BERLIN_PINCTRL_FUNCTION(0x1, "irda0"),
345 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
346 BERLIN_PINCTRL_GROUP("GSM13", 0x40, 0x2, 0x12,
347 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
348 BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* CTS/RTS */
349 BERLIN_PINCTRL_FUNCTION(0x2, "uart1"), /* RX/TX */
350 BERLIN_PINCTRL_FUNCTION(0x3, "twsi2")),
351 BERLIN_PINCTRL_GROUP("GSM14", 0x40, 0x2, 0x14,
352 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
353 BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RX/TX */
354 BERLIN_PINCTRL_FUNCTION(0x2, "irda1"),
355 BERLIN_PINCTRL_FUNCTION(0x3, "twsi3")),
356 BERLIN_PINCTRL_GROUP("GSM15", 0x40, 0x2, 0x16,
357 BERLIN_PINCTRL_FUNCTION(0x0, "pwr"),
358 BERLIN_PINCTRL_FUNCTION(0x1, "led"),
359 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
360 BERLIN_PINCTRL_GROUP("GSM16", 0x40, 0x1, 0x18,
361 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
362 BERLIN_PINCTRL_FUNCTION(0x1, "eddc")),
363 BERLIN_PINCTRL_GROUP("GSM17", 0x40, 0x1, 0x19,
364 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
365 BERLIN_PINCTRL_FUNCTION(0x1, "eddc")),
366 BERLIN_PINCTRL_GROUP("GSM18", 0x40, 0x1, 0x1a,
367 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
368 BERLIN_PINCTRL_FUNCTION(0x1, "eddc")),
369};
370
371static const struct berlin_pinctrl_desc berlin2q_soc_pinctrl_data = {
372 .groups = berlin2q_soc_pinctrl_groups,
373 .ngroups = ARRAY_SIZE(berlin2q_soc_pinctrl_groups),
374};
375
376static const struct berlin_pinctrl_desc berlin2q_sysmgr_pinctrl_data = {
377 .groups = berlin2q_sysmgr_pinctrl_groups,
378 .ngroups = ARRAY_SIZE(berlin2q_sysmgr_pinctrl_groups),
379};
380
381static const struct of_device_id berlin2q_pinctrl_match[] = {
382 {
383 .compatible = "marvell,berlin2q-chip-ctrl",
384 .data = &berlin2q_soc_pinctrl_data,
385 },
386 {
387 .compatible = "marvell,berlin2q-system-ctrl",
388 .data = &berlin2q_sysmgr_pinctrl_data,
389 },
390 {}
391};
392MODULE_DEVICE_TABLE(of, berlin2q_pinctrl_match);
393
394static int berlin2q_pinctrl_probe(struct platform_device *pdev)
395{
396 const struct of_device_id *match =
397 of_match_device(berlin2q_pinctrl_match, &pdev->dev);
398 struct regmap_config *rmconfig;
399 struct regmap *regmap;
400 struct resource *res;
401 void __iomem *base;
402
403 rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL);
404 if (!rmconfig)
405 return -ENOMEM;
406
407 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
408 base = devm_ioremap_resource(&pdev->dev, res);
409 if (IS_ERR(base))
410 return PTR_ERR(base);
411
412 rmconfig->reg_bits = 32,
413 rmconfig->val_bits = 32,
414 rmconfig->reg_stride = 4,
415 rmconfig->max_register = resource_size(res);
416
417 regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig);
418 if (IS_ERR(regmap))
419 return PTR_ERR(regmap);
420
421 return berlin_pinctrl_probe(pdev, match->data);
422}
423
424static struct platform_driver berlin2q_pinctrl_driver = {
425 .probe = berlin2q_pinctrl_probe,
426 .driver = {
427 .name = "berlin-bg2q-pinctrl",
428 .owner = THIS_MODULE,
429 .of_match_table = berlin2q_pinctrl_match,
430 },
431};
432module_platform_driver(berlin2q_pinctrl_driver);
433
434MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
435MODULE_DESCRIPTION("Marvell Berlin BG2Q pinctrl driver");
436MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
new file mode 100644
index 000000000000..edf5d2fd2b22
--- /dev/null
+++ b/drivers/pinctrl/berlin/berlin.c
@@ -0,0 +1,348 @@
1/*
2 * Marvell Berlin SoC pinctrl core driver
3 *
4 * Copyright (C) 2014 Marvell Technology Group Ltd.
5 *
6 * Antoine Ténart <antoine.tenart@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_device.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>
23
24#include "../core.h"
25#include "../pinctrl-utils.h"
26#include "berlin.h"
27
28struct berlin_pinctrl {
29 struct regmap *regmap;
30 struct device *dev;
31 const struct berlin_pinctrl_desc *desc;
32 struct berlin_pinctrl_function *functions;
33 unsigned nfunctions;
34 struct pinctrl_dev *pctrl_dev;
35};
36
37static int berlin_pinctrl_get_group_count(struct pinctrl_dev *pctrl_dev)
38{
39 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
40
41 return pctrl->desc->ngroups;
42}
43
44static const char *berlin_pinctrl_get_group_name(struct pinctrl_dev *pctrl_dev,
45 unsigned group)
46{
47 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
48
49 return pctrl->desc->groups[group].name;
50}
51
52static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
53 struct device_node *node,
54 struct pinctrl_map **map,
55 unsigned *num_maps)
56{
57 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
58 struct property *prop;
59 const char *function_name, *group_name;
60 unsigned reserved_maps = 0;
61 int ret, ngroups;
62
63 *map = NULL;
64 *num_maps = 0;
65
66 ret = of_property_read_string(node, "function", &function_name);
67 if (ret) {
68 dev_err(pctrl->dev,
69 "missing function property in node %s\n",
70 node->name);
71 return -EINVAL;
72 }
73
74 ngroups = of_property_count_strings(node, "groups");
75 if (ngroups < 0) {
76 dev_err(pctrl->dev,
77 "missing groups property in node %s\n",
78 node->name);
79 return -EINVAL;
80 }
81
82 ret = pinctrl_utils_reserve_map(pctrl_dev, map, &reserved_maps,
83 num_maps, ngroups);
84 if (ret) {
85 dev_err(pctrl->dev, "can't reserve map: %d\n", ret);
86 return ret;
87 }
88
89 of_property_for_each_string(node, "groups", prop, group_name) {
90 ret = pinctrl_utils_add_map_mux(pctrl_dev, map, &reserved_maps,
91 num_maps, group_name,
92 function_name);
93 if (ret) {
94 dev_err(pctrl->dev, "can't add map: %d\n", ret);
95 return ret;
96 }
97 }
98
99 return 0;
100}
101
102static void berlin_pinctrl_dt_free_map(struct pinctrl_dev *pctrl_dev,
103 struct pinctrl_map *map,
104 unsigned nmaps)
105{
106 int i;
107
108 for (i = 0; i < nmaps; i++) {
109 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) {
110 kfree(map[i].data.mux.group);
111
112 /* a function can be applied to multiple groups */
113 if (i == 0)
114 kfree(map[i].data.mux.function);
115 }
116 }
117
118 kfree(map);
119}
120
121static const struct pinctrl_ops berlin_pinctrl_ops = {
122 .get_groups_count = &berlin_pinctrl_get_group_count,
123 .get_group_name = &berlin_pinctrl_get_group_name,
124 .dt_node_to_map = &berlin_pinctrl_dt_node_to_map,
125 .dt_free_map = &berlin_pinctrl_dt_free_map,
126};
127
128static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev)
129{
130 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
131
132 return pctrl->nfunctions;
133}
134
135static const char *berlin_pinmux_get_function_name(struct pinctrl_dev *pctrl_dev,
136 unsigned function)
137{
138 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
139
140 return pctrl->functions[function].name;
141}
142
143static int berlin_pinmux_get_function_groups(struct pinctrl_dev *pctrl_dev,
144 unsigned function,
145 const char * const **groups,
146 unsigned * const num_groups)
147{
148 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
149
150 *groups = pctrl->functions[function].groups;
151 *num_groups = pctrl->functions[function].ngroups;
152
153 return 0;
154}
155
156static struct berlin_desc_function *
157berlin_pinctrl_find_function_by_name(struct berlin_pinctrl *pctrl,
158 const struct berlin_desc_group *group,
159 const char *fname)
160{
161 struct berlin_desc_function *function = group->functions;
162
163 while (function->name) {
164 if (!strcmp(function->name, fname))
165 return function;
166
167 function++;
168 }
169
170 return NULL;
171}
172
173static int berlin_pinmux_enable(struct pinctrl_dev *pctrl_dev,
174 unsigned function,
175 unsigned group)
176{
177 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
178 const struct berlin_desc_group *group_desc = pctrl->desc->groups + group;
179 struct berlin_pinctrl_function *func = pctrl->functions + function;
180 struct berlin_desc_function *function_desc =
181 berlin_pinctrl_find_function_by_name(pctrl, group_desc,
182 func->name);
183 u32 mask, val;
184
185 if (!function_desc)
186 return -EINVAL;
187
188 mask = GENMASK(group_desc->lsb + group_desc->bit_width - 1,
189 group_desc->lsb);
190 val = function_desc->muxval << group_desc->lsb;
191 regmap_update_bits(pctrl->regmap, group_desc->offset, mask, val);
192
193 return 0;
194}
195
196static const struct pinmux_ops berlin_pinmux_ops = {
197 .get_functions_count = &berlin_pinmux_get_functions_count,
198 .get_function_name = &berlin_pinmux_get_function_name,
199 .get_function_groups = &berlin_pinmux_get_function_groups,
200 .enable = &berlin_pinmux_enable,
201};
202
203static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl,
204 const char *name)
205{
206 struct berlin_pinctrl_function *function = pctrl->functions;
207
208 while (function->name) {
209 if (!strcmp(function->name, name)) {
210 function->ngroups++;
211 return -EEXIST;
212 }
213 function++;
214 }
215
216 function->name = name;
217 function->ngroups = 1;
218
219 pctrl->nfunctions++;
220
221 return 0;
222}
223
224static int berlin_pinctrl_build_state(struct platform_device *pdev)
225{
226 struct berlin_pinctrl *pctrl = platform_get_drvdata(pdev);
227 struct berlin_desc_group const *desc_group;
228 struct berlin_desc_function const *desc_function;
229 int i, max_functions = 0;
230
231 pctrl->nfunctions = 0;
232
233 for (i = 0; i < pctrl->desc->ngroups; i++) {
234 desc_group = pctrl->desc->groups + i;
235 /* compute the maxiumum number of functions a group can have */
236 max_functions += 1 << (desc_group->bit_width + 1);
237 }
238
239 /* we will reallocate later */
240 pctrl->functions = devm_kzalloc(&pdev->dev,
241 max_functions * sizeof(*pctrl->functions),
242 GFP_KERNEL);
243 if (!pctrl->functions)
244 return -ENOMEM;
245
246 /* register all functions */
247 for (i = 0; i < pctrl->desc->ngroups; i++) {
248 desc_group = pctrl->desc->groups + i;
249 desc_function = desc_group->functions;
250
251 while (desc_function->name) {
252 berlin_pinctrl_add_function(pctrl, desc_function->name);
253 desc_function++;
254 }
255 }
256
257 pctrl->functions = krealloc(pctrl->functions,
258 pctrl->nfunctions * sizeof(*pctrl->functions),
259 GFP_KERNEL);
260
261 /* map functions to theirs groups */
262 for (i = 0; i < pctrl->desc->ngroups; i++) {
263 desc_group = pctrl->desc->groups + i;
264 desc_function = desc_group->functions;
265
266 while (desc_function->name) {
267 struct berlin_pinctrl_function
268 *function = pctrl->functions;
269 const char **groups;
270 bool found = false;
271
272 while (function->name) {
273 if (!strcmp(desc_function->name, function->name)) {
274 found = true;
275 break;
276 }
277 function++;
278 }
279
280 if (!found)
281 return -EINVAL;
282
283 if (!function->groups) {
284 function->groups =
285 devm_kzalloc(&pdev->dev,
286 function->ngroups * sizeof(char *),
287 GFP_KERNEL);
288
289 if (!function->groups)
290 return -ENOMEM;
291 }
292
293 groups = function->groups;
294 while (*groups)
295 groups++;
296
297 *groups = desc_group->name;
298
299 desc_function++;
300 }
301 }
302
303 return 0;
304}
305
306static struct pinctrl_desc berlin_pctrl_desc = {
307 .name = "berlin-pinctrl",
308 .pctlops = &berlin_pinctrl_ops,
309 .pmxops = &berlin_pinmux_ops,
310 .owner = THIS_MODULE,
311};
312
313int berlin_pinctrl_probe(struct platform_device *pdev,
314 const struct berlin_pinctrl_desc *desc)
315{
316 struct device *dev = &pdev->dev;
317 struct berlin_pinctrl *pctrl;
318 struct regmap *regmap;
319 int ret;
320
321 regmap = dev_get_regmap(&pdev->dev, NULL);
322 if (!regmap)
323 return PTR_ERR(regmap);
324
325 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
326 if (!pctrl)
327 return -ENOMEM;
328
329 platform_set_drvdata(pdev, pctrl);
330
331 pctrl->regmap = regmap;
332 pctrl->dev = &pdev->dev;
333 pctrl->desc = desc;
334
335 ret = berlin_pinctrl_build_state(pdev);
336 if (ret) {
337 dev_err(dev, "cannot build driver state: %d\n", ret);
338 return ret;
339 }
340
341 pctrl->pctrl_dev = pinctrl_register(&berlin_pctrl_desc, dev, pctrl);
342 if (!pctrl->pctrl_dev) {
343 dev_err(dev, "failed to register pinctrl driver\n");
344 return -EINVAL;
345 }
346
347 return 0;
348}
diff --git a/drivers/pinctrl/berlin/berlin.h b/drivers/pinctrl/berlin/berlin.h
new file mode 100644
index 000000000000..e1aa84145194
--- /dev/null
+++ b/drivers/pinctrl/berlin/berlin.h
@@ -0,0 +1,61 @@
1/*
2 * Marvell Berlin SoC pinctrl driver.
3 *
4 * Copyright (C) 2014 Marvell Technology Group Ltd.
5 *
6 * Antoine Ténart <antoine.tenart@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_BERLIN_H
14#define __PINCTRL_BERLIN_H
15
16struct berlin_desc_function {
17 const char *name;
18 u8 muxval;
19};
20
21struct berlin_desc_group {
22 const char *name;
23 u8 offset;
24 u8 bit_width;
25 u8 lsb;
26 struct berlin_desc_function *functions;
27};
28
29struct berlin_pinctrl_desc {
30 const struct berlin_desc_group *groups;
31 unsigned ngroups;
32};
33
34struct berlin_pinctrl_function {
35 const char *name;
36 const char **groups;
37 unsigned ngroups;
38};
39
40#define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \
41 { \
42 .name = _name, \
43 .offset = _offset, \
44 .bit_width = _width, \
45 .lsb = _lsb, \
46 .functions = (struct berlin_desc_function[]){ \
47 __VA_ARGS__, { } }, \
48 }
49
50#define BERLIN_PINCTRL_FUNCTION(_muxval, _name) \
51 { \
52 .name = _name, \
53 .muxval = _muxval, \
54 }
55
56#define BERLIN_PINCTRL_FUNCTION_UNKNOWN {}
57
58int berlin_pinctrl_probe(struct platform_device *pdev,
59 const struct berlin_pinctrl_desc *desc);
60
61#endif /* __PINCTRL_BERLIN_H */
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index c0fe6091566a..e09474ecde23 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -468,6 +468,9 @@ int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, const char *pin_group,
468 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 468 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
469 int gs; 469 int gs;
470 470
471 if (!pctlops->get_group_pins)
472 return -EINVAL;
473
471 gs = pinctrl_get_group_selector(pctldev, pin_group); 474 gs = pinctrl_get_group_selector(pctldev, pin_group);
472 if (gs < 0) 475 if (gs < 0)
473 return gs; 476 return gs;
@@ -1362,15 +1365,16 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
1362 1365
1363 seq_puts(s, "registered pin groups:\n"); 1366 seq_puts(s, "registered pin groups:\n");
1364 while (selector < ngroups) { 1367 while (selector < ngroups) {
1365 const unsigned *pins; 1368 const unsigned *pins = NULL;
1366 unsigned num_pins; 1369 unsigned num_pins = 0;
1367 const char *gname = ops->get_group_name(pctldev, selector); 1370 const char *gname = ops->get_group_name(pctldev, selector);
1368 const char *pname; 1371 const char *pname;
1369 int ret; 1372 int ret = 0;
1370 int i; 1373 int i;
1371 1374
1372 ret = ops->get_group_pins(pctldev, selector, 1375 if (ops->get_group_pins)
1373 &pins, &num_pins); 1376 ret = ops->get_group_pins(pctldev, selector,
1377 &pins, &num_pins);
1374 if (ret) 1378 if (ret)
1375 seq_printf(s, "%s [ERROR GETTING PINS]\n", 1379 seq_printf(s, "%s [ERROR GETTING PINS]\n",
1376 gname); 1380 gname);
@@ -1694,8 +1698,7 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
1694 1698
1695 if (!ops || 1699 if (!ops ||
1696 !ops->get_groups_count || 1700 !ops->get_groups_count ||
1697 !ops->get_group_name || 1701 !ops->get_group_name)
1698 !ops->get_group_pins)
1699 return -EINVAL; 1702 return -EINVAL;
1700 1703
1701 if (ops->dt_node_to_map && !ops->dt_free_map) 1704 if (ops->dt_node_to_map && !ops->dt_free_map)
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index cc298fade93a..d6dd8358a6f6 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -30,4 +30,8 @@ config PINCTRL_ARMADA_XP
30 bool 30 bool
31 select PINCTRL_MVEBU 31 select PINCTRL_MVEBU
32 32
33config PINCTRL_ORION
34 bool
35 select PINCTRL_MVEBU
36
33endif 37endif
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index bc1b9f14f539..a0818e96374b 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
5obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o 5obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
6obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o 6obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
7obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o 7obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
8obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
new file mode 100644
index 000000000000..dda1e7254e15
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -0,0 +1,261 @@
1/*
2 * Marvell Orion pinctrl driver based on mvebu pinctrl core
3 *
4 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The first 16 MPP pins on Orion are easy to handle: they are
12 * configured through 2 consecutive registers, located at the base
13 * address of the MPP device.
14 *
15 * However the last 4 MPP pins are handled by a register at offset
16 * 0x50 from the base address, so it is not consecutive with the first
17 * two registers.
18 */
19
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/clk.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/pinctrl/pinctrl.h>
29
30#include "pinctrl-mvebu.h"
31
32static void __iomem *mpp_base;
33static void __iomem *high_mpp_base;
34
35static int orion_mpp_ctrl_get(unsigned pid, unsigned long *config)
36{
37 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
38
39 if (pid < 16) {
40 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
41 *config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
42 }
43 else {
44 *config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
45 }
46
47 return 0;
48}
49
50static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
51{
52 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
53
54 if (pid < 16) {
55 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
56 u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
57 writel(reg | (config << shift), mpp_base + off);
58 }
59 else {
60 u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
61 writel(reg | (config << shift), high_mpp_base);
62 }
63
64 return 0;
65}
66
67#define V(f5181l, f5182, f5281) \
68 ((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
69
70enum orion_variant {
71 V_5181L = V(1, 0, 0),
72 V_5182 = V(0, 1, 0),
73 V_5281 = V(0, 0, 1),
74 V_ALL = V(1, 1, 1),
75};
76
77static struct mvebu_mpp_mode orion_mpp_modes[] = {
78 MPP_MODE(0,
79 MPP_VAR_FUNCTION(0x0, "pcie", "rstout", V_ALL),
80 MPP_VAR_FUNCTION(0x2, "pci", "req2", V_ALL),
81 MPP_VAR_FUNCTION(0x3, "gpio", NULL, V_ALL)),
82 MPP_MODE(1,
83 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
84 MPP_VAR_FUNCTION(0x2, "pci", "gnt2", V_ALL)),
85 MPP_MODE(2,
86 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
87 MPP_VAR_FUNCTION(0x2, "pci", "req3", V_ALL),
88 MPP_VAR_FUNCTION(0x3, "pci-1", "pme", V_ALL)),
89 MPP_MODE(3,
90 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
91 MPP_VAR_FUNCTION(0x2, "pci", "gnt3", V_ALL)),
92 MPP_MODE(4,
93 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
94 MPP_VAR_FUNCTION(0x2, "pci", "req4", V_ALL),
95 MPP_VAR_FUNCTION(0x4, "bootnand", "re", V_5182 | V_5281),
96 MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V_5182)),
97 MPP_MODE(5,
98 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
99 MPP_VAR_FUNCTION(0x2, "pci", "gnt4", V_ALL),
100 MPP_VAR_FUNCTION(0x4, "bootnand", "we", V_5182 | V_5281),
101 MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V_5182)),
102 MPP_MODE(6,
103 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
104 MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL),
105 MPP_VAR_FUNCTION(0x4, "nand", "re0", V_5182 | V_5281),
106 MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181L),
107 MPP_VAR_FUNCTION(0x5, "sata0", "act", V_5182)),
108 MPP_MODE(7,
109 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
110 MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL),
111 MPP_VAR_FUNCTION(0x4, "nand", "we0", V_5182 | V_5281),
112 MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181L),
113 MPP_VAR_FUNCTION(0x5, "sata1", "act", V_5182)),
114 MPP_MODE(8,
115 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
116 MPP_VAR_FUNCTION(0x1, "ge", "col", V_ALL)),
117 MPP_MODE(9,
118 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
119 MPP_VAR_FUNCTION(0x1, "ge", "rxerr", V_ALL)),
120 MPP_MODE(10,
121 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
122 MPP_VAR_FUNCTION(0x1, "ge", "crs", V_ALL)),
123 MPP_MODE(11,
124 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
125 MPP_VAR_FUNCTION(0x1, "ge", "txerr", V_ALL)),
126 MPP_MODE(12,
127 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
128 MPP_VAR_FUNCTION(0x1, "ge", "txd4", V_ALL),
129 MPP_VAR_FUNCTION(0x4, "nand", "re1", V_5182 | V_5281),
130 MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),
131 MPP_MODE(13,
132 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
133 MPP_VAR_FUNCTION(0x1, "ge", "txd5", V_ALL),
134 MPP_VAR_FUNCTION(0x4, "nand", "we1", V_5182 | V_5281),
135 MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
136 MPP_MODE(14,
137 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
138 MPP_VAR_FUNCTION(0x1, "ge", "txd6", V_ALL),
139 MPP_VAR_FUNCTION(0x4, "nand", "re2", V_5182 | V_5281),
140 MPP_VAR_FUNCTION(0x5, "sata0", "ledact", V_5182)),
141 MPP_MODE(15,
142 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
143 MPP_VAR_FUNCTION(0x1, "ge", "txd7", V_ALL),
144 MPP_VAR_FUNCTION(0x4, "nand", "we2", V_5182 | V_5281),
145 MPP_VAR_FUNCTION(0x5, "sata1", "ledact", V_5182)),
146 MPP_MODE(16,
147 MPP_VAR_FUNCTION(0x0, "uart1", "rxd", V_5182 | V_5281),
148 MPP_VAR_FUNCTION(0x1, "ge", "rxd4", V_ALL),
149 MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
150 MPP_MODE(17,
151 MPP_VAR_FUNCTION(0x0, "uart1", "txd", V_5182 | V_5281),
152 MPP_VAR_FUNCTION(0x1, "ge", "rxd5", V_ALL),
153 MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
154 MPP_MODE(18,
155 MPP_VAR_FUNCTION(0x0, "uart1", "cts", V_5182 | V_5281),
156 MPP_VAR_FUNCTION(0x1, "ge", "rxd6", V_ALL),
157 MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
158 MPP_MODE(19,
159 MPP_VAR_FUNCTION(0x0, "uart1", "rts", V_5182 | V_5281),
160 MPP_VAR_FUNCTION(0x1, "ge", "rxd7", V_ALL),
161 MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
162};
163
164static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
165 MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
166};
167
168static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
169 MPP_GPIO_RANGE(0, 0, 0, 16),
170};
171
172static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
173 MPP_GPIO_RANGE(0, 0, 0, 19),
174};
175
176static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
177 MPP_GPIO_RANGE(0, 0, 0, 16),
178};
179
180static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
181 .variant = V_5181L,
182 .controls = orion_mpp_controls,
183 .ncontrols = ARRAY_SIZE(orion_mpp_controls),
184 .modes = orion_mpp_modes,
185 .nmodes = ARRAY_SIZE(orion_mpp_modes),
186 .gpioranges = mv88f5181l_gpio_ranges,
187 .ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
188};
189
190static struct mvebu_pinctrl_soc_info mv88f5182_info = {
191 .variant = V_5182,
192 .controls = orion_mpp_controls,
193 .ncontrols = ARRAY_SIZE(orion_mpp_controls),
194 .modes = orion_mpp_modes,
195 .nmodes = ARRAY_SIZE(orion_mpp_modes),
196 .gpioranges = mv88f5182_gpio_ranges,
197 .ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
198};
199
200static struct mvebu_pinctrl_soc_info mv88f5281_info = {
201 .variant = V_5281,
202 .controls = orion_mpp_controls,
203 .ncontrols = ARRAY_SIZE(orion_mpp_controls),
204 .modes = orion_mpp_modes,
205 .nmodes = ARRAY_SIZE(orion_mpp_modes),
206 .gpioranges = mv88f5281_gpio_ranges,
207 .ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
208};
209
210/*
211 * There are multiple variants of the Orion SoCs, but in terms of pin
212 * muxing, they are identical.
213 */
214static struct of_device_id orion_pinctrl_of_match[] = {
215 { .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
216 { .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
217 { .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
218 { }
219};
220
221static int orion_pinctrl_probe(struct platform_device *pdev)
222{
223 const struct of_device_id *match =
224 of_match_device(orion_pinctrl_of_match, &pdev->dev);
225 struct resource *res;
226
227 pdev->dev.platform_data = (void*)match->data;
228
229 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
230 mpp_base = devm_ioremap_resource(&pdev->dev, res);
231 if (IS_ERR(mpp_base))
232 return PTR_ERR(mpp_base);
233
234 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
235 high_mpp_base = devm_ioremap_resource(&pdev->dev, res);
236 if (IS_ERR(high_mpp_base))
237 return PTR_ERR(high_mpp_base);
238
239 return mvebu_pinctrl_probe(pdev);
240}
241
242static int orion_pinctrl_remove(struct platform_device *pdev)
243{
244 return mvebu_pinctrl_remove(pdev);
245}
246
247static struct platform_driver orion_pinctrl_driver = {
248 .driver = {
249 .name = "orion-pinctrl",
250 .owner = THIS_MODULE,
251 .of_match_table = of_match_ptr(orion_pinctrl_of_match),
252 },
253 .probe = orion_pinctrl_probe,
254 .remove = orion_pinctrl_remove,
255};
256
257module_platform_driver(orion_pinctrl_driver);
258
259MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
260MODULE_DESCRIPTION("Marvell Orion pinctrl driver");
261MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 3d9a999fb699..29ff77f90fcb 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -166,6 +166,7 @@ static struct pinconf_generic_dt_params dt_params[] = {
166 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 166 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
167 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 167 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
168 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, 168 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
169 { "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
169 { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, 170 { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 },
170 { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, 171 { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 },
171 { "output-low", PIN_CONFIG_OUTPUT, 0, }, 172 { "output-low", PIN_CONFIG_OUTPUT, 0, },
@@ -228,13 +229,12 @@ int pinconf_generic_parse_dt_config(struct device_node *np,
228 * Now limit the number of configs to the real number of 229 * Now limit the number of configs to the real number of
229 * found properties. 230 * found properties.
230 */ 231 */
231 *configs = kzalloc(ncfg * sizeof(unsigned long), GFP_KERNEL); 232 *configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL);
232 if (!*configs) { 233 if (!*configs) {
233 ret = -ENOMEM; 234 ret = -ENOMEM;
234 goto out; 235 goto out;
235 } 236 }
236 237
237 memcpy(*configs, cfg, ncfg * sizeof(unsigned long));
238 *nconfigs = ncfg; 238 *nconfigs = ncfg;
239 239
240out: 240out:
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c
index 0cc0eec83396..5c44feb54ebb 100644
--- a/drivers/pinctrl/pinctrl-adi2.c
+++ b/drivers/pinctrl/pinctrl-adi2.c
@@ -927,7 +927,7 @@ static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq,
927 return 0; 927 return 0;
928} 928}
929 929
930const struct irq_domain_ops adi_gpio_irq_domain_ops = { 930static const struct irq_domain_ops adi_gpio_irq_domain_ops = {
931 .map = adi_gpio_irq_map, 931 .map = adi_gpio_irq_map,
932 .xlate = irq_domain_xlate_onecell, 932 .xlate = irq_domain_xlate_onecell,
933}; 933};
diff --git a/drivers/pinctrl/pinctrl-apq8064.c b/drivers/pinctrl/pinctrl-apq8064.c
new file mode 100644
index 000000000000..519f7886b0f1
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-apq8064.c
@@ -0,0 +1,613 @@
1/*
2 * Copyright (c) 2014, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-msm.h"
20
21static const struct pinctrl_pin_desc apq8064_pins[] = {
22 PINCTRL_PIN(0, "GPIO_0"),
23 PINCTRL_PIN(1, "GPIO_1"),
24 PINCTRL_PIN(2, "GPIO_2"),
25 PINCTRL_PIN(3, "GPIO_3"),
26 PINCTRL_PIN(4, "GPIO_4"),
27 PINCTRL_PIN(5, "GPIO_5"),
28 PINCTRL_PIN(6, "GPIO_6"),
29 PINCTRL_PIN(7, "GPIO_7"),
30 PINCTRL_PIN(8, "GPIO_8"),
31 PINCTRL_PIN(9, "GPIO_9"),
32 PINCTRL_PIN(10, "GPIO_10"),
33 PINCTRL_PIN(11, "GPIO_11"),
34 PINCTRL_PIN(12, "GPIO_12"),
35 PINCTRL_PIN(13, "GPIO_13"),
36 PINCTRL_PIN(14, "GPIO_14"),
37 PINCTRL_PIN(15, "GPIO_15"),
38 PINCTRL_PIN(16, "GPIO_16"),
39 PINCTRL_PIN(17, "GPIO_17"),
40 PINCTRL_PIN(18, "GPIO_18"),
41 PINCTRL_PIN(19, "GPIO_19"),
42 PINCTRL_PIN(20, "GPIO_20"),
43 PINCTRL_PIN(21, "GPIO_21"),
44 PINCTRL_PIN(22, "GPIO_22"),
45 PINCTRL_PIN(23, "GPIO_23"),
46 PINCTRL_PIN(24, "GPIO_24"),
47 PINCTRL_PIN(25, "GPIO_25"),
48 PINCTRL_PIN(26, "GPIO_26"),
49 PINCTRL_PIN(27, "GPIO_27"),
50 PINCTRL_PIN(28, "GPIO_28"),
51 PINCTRL_PIN(29, "GPIO_29"),
52 PINCTRL_PIN(30, "GPIO_30"),
53 PINCTRL_PIN(31, "GPIO_31"),
54 PINCTRL_PIN(32, "GPIO_32"),
55 PINCTRL_PIN(33, "GPIO_33"),
56 PINCTRL_PIN(34, "GPIO_34"),
57 PINCTRL_PIN(35, "GPIO_35"),
58 PINCTRL_PIN(36, "GPIO_36"),
59 PINCTRL_PIN(37, "GPIO_37"),
60 PINCTRL_PIN(38, "GPIO_38"),
61 PINCTRL_PIN(39, "GPIO_39"),
62 PINCTRL_PIN(40, "GPIO_40"),
63 PINCTRL_PIN(41, "GPIO_41"),
64 PINCTRL_PIN(42, "GPIO_42"),
65 PINCTRL_PIN(43, "GPIO_43"),
66 PINCTRL_PIN(44, "GPIO_44"),
67 PINCTRL_PIN(45, "GPIO_45"),
68 PINCTRL_PIN(46, "GPIO_46"),
69 PINCTRL_PIN(47, "GPIO_47"),
70 PINCTRL_PIN(48, "GPIO_48"),
71 PINCTRL_PIN(49, "GPIO_49"),
72 PINCTRL_PIN(50, "GPIO_50"),
73 PINCTRL_PIN(51, "GPIO_51"),
74 PINCTRL_PIN(52, "GPIO_52"),
75 PINCTRL_PIN(53, "GPIO_53"),
76 PINCTRL_PIN(54, "GPIO_54"),
77 PINCTRL_PIN(55, "GPIO_55"),
78 PINCTRL_PIN(56, "GPIO_56"),
79 PINCTRL_PIN(57, "GPIO_57"),
80 PINCTRL_PIN(58, "GPIO_58"),
81 PINCTRL_PIN(59, "GPIO_59"),
82 PINCTRL_PIN(60, "GPIO_60"),
83 PINCTRL_PIN(61, "GPIO_61"),
84 PINCTRL_PIN(62, "GPIO_62"),
85 PINCTRL_PIN(63, "GPIO_63"),
86 PINCTRL_PIN(64, "GPIO_64"),
87 PINCTRL_PIN(65, "GPIO_65"),
88 PINCTRL_PIN(66, "GPIO_66"),
89 PINCTRL_PIN(67, "GPIO_67"),
90 PINCTRL_PIN(68, "GPIO_68"),
91 PINCTRL_PIN(69, "GPIO_69"),
92 PINCTRL_PIN(70, "GPIO_70"),
93 PINCTRL_PIN(71, "GPIO_71"),
94 PINCTRL_PIN(72, "GPIO_72"),
95 PINCTRL_PIN(73, "GPIO_73"),
96 PINCTRL_PIN(74, "GPIO_74"),
97 PINCTRL_PIN(75, "GPIO_75"),
98 PINCTRL_PIN(76, "GPIO_76"),
99 PINCTRL_PIN(77, "GPIO_77"),
100 PINCTRL_PIN(78, "GPIO_78"),
101 PINCTRL_PIN(79, "GPIO_79"),
102 PINCTRL_PIN(80, "GPIO_80"),
103 PINCTRL_PIN(81, "GPIO_81"),
104 PINCTRL_PIN(82, "GPIO_82"),
105 PINCTRL_PIN(83, "GPIO_83"),
106 PINCTRL_PIN(84, "GPIO_84"),
107 PINCTRL_PIN(85, "GPIO_85"),
108 PINCTRL_PIN(86, "GPIO_86"),
109 PINCTRL_PIN(87, "GPIO_87"),
110 PINCTRL_PIN(88, "GPIO_88"),
111 PINCTRL_PIN(89, "GPIO_89"),
112
113 PINCTRL_PIN(90, "SDC1_CLK"),
114 PINCTRL_PIN(91, "SDC1_CMD"),
115 PINCTRL_PIN(92, "SDC1_DATA"),
116 PINCTRL_PIN(93, "SDC3_CLK"),
117 PINCTRL_PIN(94, "SDC3_CMD"),
118 PINCTRL_PIN(95, "SDC3_DATA"),
119};
120
121#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
122DECLARE_APQ_GPIO_PINS(0);
123DECLARE_APQ_GPIO_PINS(1);
124DECLARE_APQ_GPIO_PINS(2);
125DECLARE_APQ_GPIO_PINS(3);
126DECLARE_APQ_GPIO_PINS(4);
127DECLARE_APQ_GPIO_PINS(5);
128DECLARE_APQ_GPIO_PINS(6);
129DECLARE_APQ_GPIO_PINS(7);
130DECLARE_APQ_GPIO_PINS(8);
131DECLARE_APQ_GPIO_PINS(9);
132DECLARE_APQ_GPIO_PINS(10);
133DECLARE_APQ_GPIO_PINS(11);
134DECLARE_APQ_GPIO_PINS(12);
135DECLARE_APQ_GPIO_PINS(13);
136DECLARE_APQ_GPIO_PINS(14);
137DECLARE_APQ_GPIO_PINS(15);
138DECLARE_APQ_GPIO_PINS(16);
139DECLARE_APQ_GPIO_PINS(17);
140DECLARE_APQ_GPIO_PINS(18);
141DECLARE_APQ_GPIO_PINS(19);
142DECLARE_APQ_GPIO_PINS(20);
143DECLARE_APQ_GPIO_PINS(21);
144DECLARE_APQ_GPIO_PINS(22);
145DECLARE_APQ_GPIO_PINS(23);
146DECLARE_APQ_GPIO_PINS(24);
147DECLARE_APQ_GPIO_PINS(25);
148DECLARE_APQ_GPIO_PINS(26);
149DECLARE_APQ_GPIO_PINS(27);
150DECLARE_APQ_GPIO_PINS(28);
151DECLARE_APQ_GPIO_PINS(29);
152DECLARE_APQ_GPIO_PINS(30);
153DECLARE_APQ_GPIO_PINS(31);
154DECLARE_APQ_GPIO_PINS(32);
155DECLARE_APQ_GPIO_PINS(33);
156DECLARE_APQ_GPIO_PINS(34);
157DECLARE_APQ_GPIO_PINS(35);
158DECLARE_APQ_GPIO_PINS(36);
159DECLARE_APQ_GPIO_PINS(37);
160DECLARE_APQ_GPIO_PINS(38);
161DECLARE_APQ_GPIO_PINS(39);
162DECLARE_APQ_GPIO_PINS(40);
163DECLARE_APQ_GPIO_PINS(41);
164DECLARE_APQ_GPIO_PINS(42);
165DECLARE_APQ_GPIO_PINS(43);
166DECLARE_APQ_GPIO_PINS(44);
167DECLARE_APQ_GPIO_PINS(45);
168DECLARE_APQ_GPIO_PINS(46);
169DECLARE_APQ_GPIO_PINS(47);
170DECLARE_APQ_GPIO_PINS(48);
171DECLARE_APQ_GPIO_PINS(49);
172DECLARE_APQ_GPIO_PINS(50);
173DECLARE_APQ_GPIO_PINS(51);
174DECLARE_APQ_GPIO_PINS(52);
175DECLARE_APQ_GPIO_PINS(53);
176DECLARE_APQ_GPIO_PINS(54);
177DECLARE_APQ_GPIO_PINS(55);
178DECLARE_APQ_GPIO_PINS(56);
179DECLARE_APQ_GPIO_PINS(57);
180DECLARE_APQ_GPIO_PINS(58);
181DECLARE_APQ_GPIO_PINS(59);
182DECLARE_APQ_GPIO_PINS(60);
183DECLARE_APQ_GPIO_PINS(61);
184DECLARE_APQ_GPIO_PINS(62);
185DECLARE_APQ_GPIO_PINS(63);
186DECLARE_APQ_GPIO_PINS(64);
187DECLARE_APQ_GPIO_PINS(65);
188DECLARE_APQ_GPIO_PINS(66);
189DECLARE_APQ_GPIO_PINS(67);
190DECLARE_APQ_GPIO_PINS(68);
191DECLARE_APQ_GPIO_PINS(69);
192DECLARE_APQ_GPIO_PINS(70);
193DECLARE_APQ_GPIO_PINS(71);
194DECLARE_APQ_GPIO_PINS(72);
195DECLARE_APQ_GPIO_PINS(73);
196DECLARE_APQ_GPIO_PINS(74);
197DECLARE_APQ_GPIO_PINS(75);
198DECLARE_APQ_GPIO_PINS(76);
199DECLARE_APQ_GPIO_PINS(77);
200DECLARE_APQ_GPIO_PINS(78);
201DECLARE_APQ_GPIO_PINS(79);
202DECLARE_APQ_GPIO_PINS(80);
203DECLARE_APQ_GPIO_PINS(81);
204DECLARE_APQ_GPIO_PINS(82);
205DECLARE_APQ_GPIO_PINS(83);
206DECLARE_APQ_GPIO_PINS(84);
207DECLARE_APQ_GPIO_PINS(85);
208DECLARE_APQ_GPIO_PINS(86);
209DECLARE_APQ_GPIO_PINS(87);
210DECLARE_APQ_GPIO_PINS(88);
211DECLARE_APQ_GPIO_PINS(89);
212
213static const unsigned int sdc1_clk_pins[] = { 90 };
214static const unsigned int sdc1_cmd_pins[] = { 91 };
215static const unsigned int sdc1_data_pins[] = { 92 };
216static const unsigned int sdc3_clk_pins[] = { 93 };
217static const unsigned int sdc3_cmd_pins[] = { 94 };
218static const unsigned int sdc3_data_pins[] = { 95 };
219
220#define FUNCTION(fname) \
221 [APQ_MUX_##fname] = { \
222 .name = #fname, \
223 .groups = fname##_groups, \
224 .ngroups = ARRAY_SIZE(fname##_groups), \
225 }
226
227#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
228 { \
229 .name = "gpio" #id, \
230 .pins = gpio##id##_pins, \
231 .npins = ARRAY_SIZE(gpio##id##_pins), \
232 .funcs = (int[]){ \
233 APQ_MUX_NA, /* gpio mode */ \
234 APQ_MUX_##f1, \
235 APQ_MUX_##f2, \
236 APQ_MUX_##f3, \
237 APQ_MUX_##f4, \
238 APQ_MUX_##f5, \
239 APQ_MUX_##f6, \
240 APQ_MUX_##f7, \
241 APQ_MUX_##f8, \
242 APQ_MUX_##f9, \
243 APQ_MUX_##f10, \
244 }, \
245 .nfuncs = 11, \
246 .ctl_reg = 0x1000 + 0x10 * id, \
247 .io_reg = 0x1004 + 0x10 * id, \
248 .intr_cfg_reg = 0x1008 + 0x10 * id, \
249 .intr_status_reg = 0x100c + 0x10 * id, \
250 .intr_target_reg = 0x400 + 0x4 * id, \
251 .mux_bit = 2, \
252 .pull_bit = 0, \
253 .drv_bit = 6, \
254 .oe_bit = 9, \
255 .in_bit = 0, \
256 .out_bit = 1, \
257 .intr_enable_bit = 0, \
258 .intr_status_bit = 0, \
259 .intr_ack_high = 1, \
260 .intr_target_bit = 0, \
261 .intr_raw_status_bit = 3, \
262 .intr_polarity_bit = 1, \
263 .intr_detection_bit = 2, \
264 .intr_detection_width = 1, \
265 }
266
267#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
268 { \
269 .name = #pg_name, \
270 .pins = pg_name##_pins, \
271 .npins = ARRAY_SIZE(pg_name##_pins), \
272 .ctl_reg = ctl, \
273 .io_reg = 0, \
274 .intr_cfg_reg = 0, \
275 .intr_status_reg = 0, \
276 .intr_target_reg = 0, \
277 .mux_bit = -1, \
278 .pull_bit = pull, \
279 .drv_bit = drv, \
280 .oe_bit = -1, \
281 .in_bit = -1, \
282 .out_bit = -1, \
283 .intr_enable_bit = -1, \
284 .intr_status_bit = -1, \
285 .intr_target_bit = -1, \
286 .intr_raw_status_bit = -1, \
287 .intr_polarity_bit = -1, \
288 .intr_detection_bit = -1, \
289 .intr_detection_width = -1, \
290 }
291
292enum apq8064_functions {
293 APQ_MUX_cam_mclk,
294 APQ_MUX_codec_mic_i2s,
295 APQ_MUX_codec_spkr_i2s,
296 APQ_MUX_gsbi1,
297 APQ_MUX_gsbi2,
298 APQ_MUX_gsbi3,
299 APQ_MUX_gsbi4,
300 APQ_MUX_gsbi4_cam_i2c,
301 APQ_MUX_gsbi5,
302 APQ_MUX_gsbi5_spi_cs1,
303 APQ_MUX_gsbi5_spi_cs2,
304 APQ_MUX_gsbi5_spi_cs3,
305 APQ_MUX_gsbi6,
306 APQ_MUX_gsbi6_spi_cs1,
307 APQ_MUX_gsbi6_spi_cs2,
308 APQ_MUX_gsbi6_spi_cs3,
309 APQ_MUX_gsbi7,
310 APQ_MUX_gsbi7_spi_cs1,
311 APQ_MUX_gsbi7_spi_cs2,
312 APQ_MUX_gsbi7_spi_cs3,
313 APQ_MUX_gsbi_cam_i2c,
314 APQ_MUX_hdmi,
315 APQ_MUX_mi2s,
316 APQ_MUX_riva_bt,
317 APQ_MUX_riva_fm,
318 APQ_MUX_riva_wlan,
319 APQ_MUX_sdc2,
320 APQ_MUX_sdc4,
321 APQ_MUX_slimbus,
322 APQ_MUX_spkr_i2s,
323 APQ_MUX_tsif1,
324 APQ_MUX_tsif2,
325 APQ_MUX_usb2_hsic,
326 APQ_MUX_NA,
327};
328
329static const char * const cam_mclk_groups[] = {
330 "gpio4" "gpio5"
331};
332static const char * const codec_mic_i2s_groups[] = {
333 "gpio34", "gpio35", "gpio36", "gpio37", "gpio38"
334};
335static const char * const codec_spkr_i2s_groups[] = {
336 "gpio39", "gpio40", "gpio41", "gpio42"
337};
338static const char * const gsbi1_groups[] = {
339 "gpio18", "gpio19", "gpio20", "gpio21"
340};
341static const char * const gsbi2_groups[] = {
342 "gpio22", "gpio23", "gpio24", "gpio25"
343};
344static const char * const gsbi3_groups[] = {
345 "gpio6", "gpio7", "gpio8", "gpio9"
346};
347static const char * const gsbi4_groups[] = {
348 "gpio10", "gpio11", "gpio12", "gpio13"
349};
350static const char * const gsbi4_cam_i2c_groups[] = {
351 "gpio10", "gpio11", "gpio12", "gpio13"
352};
353static const char * const gsbi5_groups[] = {
354 "gpio51", "gpio52", "gpio53", "gpio54"
355};
356static const char * const gsbi5_spi_cs1_groups[] = {
357 "gpio47"
358};
359static const char * const gsbi5_spi_cs2_groups[] = {
360 "gpio31"
361};
362static const char * const gsbi5_spi_cs3_groups[] = {
363 "gpio32"
364};
365static const char * const gsbi6_groups[] = {
366 "gpio14", "gpio15", "gpio16", "gpio17"
367};
368static const char * const gsbi6_spi_cs1_groups[] = {
369 "gpio47"
370};
371static const char * const gsbi6_spi_cs2_groups[] = {
372 "gpio31"
373};
374static const char * const gsbi6_spi_cs3_groups[] = {
375 "gpio32"
376};
377static const char * const gsbi7_groups[] = {
378 "gpio82", "gpio83", "gpio84", "gpio85"
379};
380static const char * const gsbi7_spi_cs1_groups[] = {
381 "gpio47"
382};
383static const char * const gsbi7_spi_cs2_groups[] = {
384 "gpio31"
385};
386static const char * const gsbi7_spi_cs3_groups[] = {
387 "gpio32"
388};
389static const char * const gsbi_cam_i2c_groups[] = {
390 "gpio10", "gpio11", "gpio12", "gpio13"
391};
392static const char * const hdmi_groups[] = {
393 "gpio69", "gpio70", "gpio71", "gpio72"
394};
395static const char * const mi2s_groups[] = {
396 "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33"
397};
398static const char * const riva_bt_groups[] = {
399 "gpio16", "gpio17"
400};
401static const char * const riva_fm_groups[] = {
402 "gpio14", "gpio15"
403};
404static const char * const riva_wlan_groups[] = {
405 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
406};
407static const char * const sdc2_groups[] = {
408 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62"
409};
410static const char * const sdc4_groups[] = {
411 "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
412};
413static const char * const slimbus_groups[] = {
414 "gpio40", "gpio41"
415};
416static const char * const spkr_i2s_groups[] = {
417 "gpio47", "gpio48", "gpio49", "gpio50"
418};
419static const char * const tsif1_groups[] = {
420 "gpio55", "gpio56", "gpio57"
421};
422static const char * const tsif2_groups[] = {
423 "gpio58", "gpio59", "gpio60"
424};
425static const char * const usb2_hsic_groups[] = {
426 "gpio88", "gpio89"
427};
428
429static const struct msm_function apq8064_functions[] = {
430 FUNCTION(cam_mclk),
431 FUNCTION(codec_mic_i2s),
432 FUNCTION(codec_spkr_i2s),
433 FUNCTION(gsbi1),
434 FUNCTION(gsbi2),
435 FUNCTION(gsbi3),
436 FUNCTION(gsbi4),
437 FUNCTION(gsbi4_cam_i2c),
438 FUNCTION(gsbi5),
439 FUNCTION(gsbi5_spi_cs1),
440 FUNCTION(gsbi5_spi_cs2),
441 FUNCTION(gsbi5_spi_cs3),
442 FUNCTION(gsbi6),
443 FUNCTION(gsbi6_spi_cs1),
444 FUNCTION(gsbi6_spi_cs2),
445 FUNCTION(gsbi6_spi_cs3),
446 FUNCTION(gsbi7),
447 FUNCTION(gsbi7_spi_cs1),
448 FUNCTION(gsbi7_spi_cs2),
449 FUNCTION(gsbi7_spi_cs3),
450 FUNCTION(gsbi_cam_i2c),
451 FUNCTION(hdmi),
452 FUNCTION(mi2s),
453 FUNCTION(riva_bt),
454 FUNCTION(riva_fm),
455 FUNCTION(riva_wlan),
456 FUNCTION(sdc2),
457 FUNCTION(sdc4),
458 FUNCTION(slimbus),
459 FUNCTION(spkr_i2s),
460 FUNCTION(tsif1),
461 FUNCTION(tsif2),
462 FUNCTION(usb2_hsic),
463};
464
465static const struct msm_pingroup apq8064_groups[] = {
466 PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
467 PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
468 PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
469 PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
470 PINGROUP(4, NA, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA),
471 PINGROUP(5, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA, NA),
472 PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
473 PINGROUP(7, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
474 PINGROUP(8, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
475 PINGROUP(9, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
476 PINGROUP(10, gsbi4, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c, NA),
477 PINGROUP(11, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c),
478 PINGROUP(12, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA),
479 PINGROUP(13, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA),
480 PINGROUP(14, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA),
481 PINGROUP(15, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA),
482 PINGROUP(16, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA),
483 PINGROUP(17, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA),
484 PINGROUP(18, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
485 PINGROUP(19, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
486 PINGROUP(20, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
487 PINGROUP(21, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
488 PINGROUP(22, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
489 PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
490 PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
491 PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
492 PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
493 PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
494 PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
495 PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
496 PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
497 PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA),
498 PINGROUP(32, mi2s, NA, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA),
499 PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
500 PINGROUP(34, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
501 PINGROUP(35, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
502 PINGROUP(36, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
503 PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
504 PINGROUP(38, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
505 PINGROUP(39, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
506 PINGROUP(40, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA),
507 PINGROUP(41, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA),
508 PINGROUP(42, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
509 PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
510 PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
511 PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
512 PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
513 PINGROUP(47, spkr_i2s, gsbi5_spi_cs1, gsbi6_spi_cs1, gsbi7_spi_cs1, NA, NA, NA, NA, NA, NA),
514 PINGROUP(48, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
515 PINGROUP(49, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
516 PINGROUP(50, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
517 PINGROUP(51, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),
518 PINGROUP(52, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),
519 PINGROUP(53, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),
520 PINGROUP(54, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),
521 PINGROUP(55, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
522 PINGROUP(56, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
523 PINGROUP(57, tsif1, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
524 PINGROUP(58, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
525 PINGROUP(59, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
526 PINGROUP(60, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
527 PINGROUP(61, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
528 PINGROUP(62, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA),
529 PINGROUP(63, NA, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
530 PINGROUP(64, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
531 PINGROUP(65, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
532 PINGROUP(66, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
533 PINGROUP(67, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
534 PINGROUP(68, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA),
535 PINGROUP(69, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA),
536 PINGROUP(70, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA),
537 PINGROUP(71, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA),
538 PINGROUP(72, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA),
539 PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
540 PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
541 PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
542 PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
543 PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
544 PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
545 PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
546 PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
547 PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
548 PINGROUP(82, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA),
549 PINGROUP(83, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
550 PINGROUP(84, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA),
551 PINGROUP(85, NA, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA),
552 PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
553 PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
554 PINGROUP(88, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
555 PINGROUP(89, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
556
557 SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6),
558 SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3),
559 SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0),
560
561 SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6),
562 SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3),
563 SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0),
564};
565
566#define NUM_GPIO_PINGROUPS 90
567
568static const struct msm_pinctrl_soc_data apq8064_pinctrl = {
569 .pins = apq8064_pins,
570 .npins = ARRAY_SIZE(apq8064_pins),
571 .functions = apq8064_functions,
572 .nfunctions = ARRAY_SIZE(apq8064_functions),
573 .groups = apq8064_groups,
574 .ngroups = ARRAY_SIZE(apq8064_groups),
575 .ngpios = NUM_GPIO_PINGROUPS,
576};
577
578static int apq8064_pinctrl_probe(struct platform_device *pdev)
579{
580 return msm_pinctrl_probe(pdev, &apq8064_pinctrl);
581}
582
583static const struct of_device_id apq8064_pinctrl_of_match[] = {
584 { .compatible = "qcom,apq8064-pinctrl", },
585 { },
586};
587
588static struct platform_driver apq8064_pinctrl_driver = {
589 .driver = {
590 .name = "apq8064-pinctrl",
591 .owner = THIS_MODULE,
592 .of_match_table = apq8064_pinctrl_of_match,
593 },
594 .probe = apq8064_pinctrl_probe,
595 .remove = msm_pinctrl_remove,
596};
597
598static int __init apq8064_pinctrl_init(void)
599{
600 return platform_driver_register(&apq8064_pinctrl_driver);
601}
602arch_initcall(apq8064_pinctrl_init);
603
604static void __exit apq8064_pinctrl_exit(void)
605{
606 platform_driver_unregister(&apq8064_pinctrl_driver);
607}
608module_exit(apq8064_pinctrl_exit);
609
610MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
611MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver");
612MODULE_LICENSE("GPL v2");
613MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 5d24aaec5dbc..421493cb490c 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -16,9 +16,6 @@
16#include <linux/of_irq.h> 16#include <linux/of_irq.h>
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
21#include <linux/irqchip/chained_irq.h>
22#include <linux/io.h> 19#include <linux/io.h>
23#include <linux/gpio.h> 20#include <linux/gpio.h>
24#include <linux/pinctrl/machine.h> 21#include <linux/pinctrl/machine.h>
@@ -47,7 +44,6 @@ struct at91_gpio_chip {
47 int pioc_idx; /* PIO bank index */ 44 int pioc_idx; /* PIO bank index */
48 void __iomem *regbase; /* PIO bank virtual address */ 45 void __iomem *regbase; /* PIO bank virtual address */
49 struct clk *clock; /* associated clock */ 46 struct clk *clock; /* associated clock */
50 struct irq_domain *domain; /* associated irq domain */
51 struct at91_pinctrl_mux_ops *ops; /* ops */ 47 struct at91_pinctrl_mux_ops *ops; /* ops */
52}; 48};
53 49
@@ -1192,21 +1188,6 @@ static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1192 return 0; 1188 return 0;
1193} 1189}
1194 1190
1195static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1196{
1197 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1198 int virq;
1199
1200 if (offset < chip->ngpio)
1201 virq = irq_create_mapping(at91_gpio->domain, offset);
1202 else
1203 virq = -ENXIO;
1204
1205 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1206 chip->label, offset + chip->base, virq);
1207 return virq;
1208}
1209
1210#ifdef CONFIG_DEBUG_FS 1191#ifdef CONFIG_DEBUG_FS
1211static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1192static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1212{ 1193{
@@ -1216,8 +1197,7 @@ static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1216 void __iomem *pio = at91_gpio->regbase; 1197 void __iomem *pio = at91_gpio->regbase;
1217 1198
1218 for (i = 0; i < chip->ngpio; i++) { 1199 for (i = 0; i < chip->ngpio; i++) {
1219 unsigned pin = chip->base + i; 1200 unsigned mask = pin_to_mask(i);
1220 unsigned mask = pin_to_mask(pin);
1221 const char *gpio_label; 1201 const char *gpio_label;
1222 u32 pdsr; 1202 u32 pdsr;
1223 1203
@@ -1336,6 +1316,11 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1336 return 0; 1316 return 0;
1337} 1317}
1338 1318
1319static void gpio_irq_ack(struct irq_data *d)
1320{
1321 /* the interrupt is already cleared before by reading ISR */
1322}
1323
1339static unsigned int gpio_irq_startup(struct irq_data *d) 1324static unsigned int gpio_irq_startup(struct irq_data *d)
1340{ 1325{
1341 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1326 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
@@ -1435,6 +1420,7 @@ void at91_pinctrl_gpio_resume(void)
1435 1420
1436static struct irq_chip gpio_irqchip = { 1421static struct irq_chip gpio_irqchip = {
1437 .name = "GPIO", 1422 .name = "GPIO",
1423 .irq_ack = gpio_irq_ack,
1438 .irq_startup = gpio_irq_startup, 1424 .irq_startup = gpio_irq_startup,
1439 .irq_shutdown = gpio_irq_shutdown, 1425 .irq_shutdown = gpio_irq_shutdown,
1440 .irq_disable = gpio_irq_mask, 1426 .irq_disable = gpio_irq_mask,
@@ -1446,9 +1432,11 @@ static struct irq_chip gpio_irqchip = {
1446 1432
1447static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 1433static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1448{ 1434{
1449 struct irq_chip *chip = irq_desc_get_chip(desc); 1435 struct irq_chip *chip = irq_get_chip(irq);
1450 struct irq_data *idata = irq_desc_get_irq_data(desc); 1436 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1451 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); 1437 struct at91_gpio_chip *at91_gpio = container_of(gpio_chip,
1438 struct at91_gpio_chip, chip);
1439
1452 void __iomem *pio = at91_gpio->regbase; 1440 void __iomem *pio = at91_gpio->regbase;
1453 unsigned long isr; 1441 unsigned long isr;
1454 int n; 1442 int n;
@@ -1465,85 +1453,25 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1465 break; 1453 break;
1466 at91_gpio = at91_gpio->next; 1454 at91_gpio = at91_gpio->next;
1467 pio = at91_gpio->regbase; 1455 pio = at91_gpio->regbase;
1456 gpio_chip = &at91_gpio->chip;
1468 continue; 1457 continue;
1469 } 1458 }
1470 1459
1471 for_each_set_bit(n, &isr, BITS_PER_LONG) { 1460 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1472 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); 1461 generic_handle_irq(irq_find_mapping(
1462 gpio_chip->irqdomain, n));
1473 } 1463 }
1474 } 1464 }
1475 chained_irq_exit(chip, desc); 1465 chained_irq_exit(chip, desc);
1476 /* now it may re-trigger */ 1466 /* now it may re-trigger */
1477} 1467}
1478 1468
1479/*
1480 * This lock class tells lockdep that GPIO irqs are in a different
1481 * category than their parents, so it won't report false recursion.
1482 */
1483static struct lock_class_key gpio_lock_class;
1484
1485static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1486 irq_hw_number_t hw)
1487{
1488 struct at91_gpio_chip *at91_gpio = h->host_data;
1489 void __iomem *pio = at91_gpio->regbase;
1490 u32 mask = 1 << hw;
1491
1492 irq_set_lockdep_class(virq, &gpio_lock_class);
1493
1494 /*
1495 * Can use the "simple" and not "edge" handler since it's
1496 * shorter, and the AIC handles interrupts sanely.
1497 */
1498 irq_set_chip(virq, &gpio_irqchip);
1499 if ((at91_gpio->ops == &at91sam9x5_ops) &&
1500 (readl_relaxed(pio + PIO_AIMMR) & mask) &&
1501 (readl_relaxed(pio + PIO_ELSR) & mask))
1502 irq_set_handler(virq, handle_level_irq);
1503 else
1504 irq_set_handler(virq, handle_simple_irq);
1505 set_irq_flags(virq, IRQF_VALID);
1506 irq_set_chip_data(virq, at91_gpio);
1507
1508 return 0;
1509}
1510
1511static int at91_gpio_irq_domain_xlate(struct irq_domain *d,
1512 struct device_node *ctrlr,
1513 const u32 *intspec, unsigned int intsize,
1514 irq_hw_number_t *out_hwirq,
1515 unsigned int *out_type)
1516{
1517 struct at91_gpio_chip *at91_gpio = d->host_data;
1518 int ret;
1519 int pin = at91_gpio->chip.base + intspec[0];
1520
1521 if (WARN_ON(intsize < 2))
1522 return -EINVAL;
1523 *out_hwirq = intspec[0];
1524 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1525
1526 ret = gpio_request(pin, ctrlr->full_name);
1527 if (ret)
1528 return ret;
1529
1530 ret = gpio_direction_input(pin);
1531 if (ret)
1532 return ret;
1533
1534 return 0;
1535}
1536
1537static struct irq_domain_ops at91_gpio_ops = {
1538 .map = at91_gpio_irq_map,
1539 .xlate = at91_gpio_irq_domain_xlate,
1540};
1541
1542static int at91_gpio_of_irq_setup(struct device_node *node, 1469static int at91_gpio_of_irq_setup(struct device_node *node,
1543 struct at91_gpio_chip *at91_gpio) 1470 struct at91_gpio_chip *at91_gpio)
1544{ 1471{
1545 struct at91_gpio_chip *prev = NULL; 1472 struct at91_gpio_chip *prev = NULL;
1546 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); 1473 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1474 int ret;
1547 1475
1548 at91_gpio->pioc_hwirq = irqd_to_hwirq(d); 1476 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1549 1477
@@ -1553,10 +1481,17 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
1553 /* Disable irqs of this PIO controller */ 1481 /* Disable irqs of this PIO controller */
1554 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); 1482 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1555 1483
1556 /* Setup irq domain */ 1484 /*
1557 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio, 1485 * Let the generic code handle this edge IRQ, the the chained
1558 &at91_gpio_ops, at91_gpio); 1486 * handler will perform the actual work of handling the parent
1559 if (!at91_gpio->domain) 1487 * interrupt.
1488 */
1489 ret = gpiochip_irqchip_add(&at91_gpio->chip,
1490 &gpio_irqchip,
1491 0,
1492 handle_edge_irq,
1493 IRQ_TYPE_EDGE_BOTH);
1494 if (ret)
1560 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", 1495 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1561 at91_gpio->pioc_idx); 1496 at91_gpio->pioc_idx);
1562 1497
@@ -1571,8 +1506,11 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
1571 if (prev && prev->next == at91_gpio) 1506 if (prev && prev->next == at91_gpio)
1572 return 0; 1507 return 0;
1573 1508
1574 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio); 1509 /* Then register the chain on the parent IRQ */
1575 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler); 1510 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1511 &gpio_irqchip,
1512 at91_gpio->pioc_virq,
1513 gpio_irq_handler);
1576 1514
1577 return 0; 1515 return 0;
1578} 1516}
@@ -1586,7 +1524,6 @@ static struct gpio_chip at91_gpio_template = {
1586 .get = at91_gpio_get, 1524 .get = at91_gpio_get,
1587 .direction_output = at91_gpio_direction_output, 1525 .direction_output = at91_gpio_direction_output,
1588 .set = at91_gpio_set, 1526 .set = at91_gpio_set,
1589 .to_irq = at91_gpio_to_irq,
1590 .dbg_show = at91_gpio_dbg_show, 1527 .dbg_show = at91_gpio_dbg_show,
1591 .can_sleep = false, 1528 .can_sleep = false,
1592 .ngpio = MAX_NB_GPIO_PER_BANK, 1529 .ngpio = MAX_NB_GPIO_PER_BANK,
diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c
index 6e8301f77187..975572e2f260 100644
--- a/drivers/pinctrl/pinctrl-baytrail.c
+++ b/drivers/pinctrl/pinctrl-baytrail.c
@@ -43,9 +43,20 @@
43#define BYT_INT_STAT_REG 0x800 43#define BYT_INT_STAT_REG 0x800
44 44
45/* BYT_CONF0_REG register bits */ 45/* BYT_CONF0_REG register bits */
46#define BYT_IODEN BIT(31)
46#define BYT_TRIG_NEG BIT(26) 47#define BYT_TRIG_NEG BIT(26)
47#define BYT_TRIG_POS BIT(25) 48#define BYT_TRIG_POS BIT(25)
48#define BYT_TRIG_LVL BIT(24) 49#define BYT_TRIG_LVL BIT(24)
50#define BYT_PULL_STR_SHIFT 9
51#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
52#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
53#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
54#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
55#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
56#define BYT_PULL_ASSIGN_SHIFT 7
57#define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
58#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
59#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
49#define BYT_PIN_MUX 0x07 60#define BYT_PIN_MUX 0x07
50 61
51/* BYT_VAL_REG register bits */ 62/* BYT_VAL_REG register bits */
@@ -321,6 +332,8 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
321 spin_lock_irqsave(&vg->lock, flags); 332 spin_lock_irqsave(&vg->lock, flags);
322 333
323 for (i = 0; i < vg->chip.ngpio; i++) { 334 for (i = 0; i < vg->chip.ngpio; i++) {
335 const char *pull_str = NULL;
336 const char *pull = NULL;
324 const char *label; 337 const char *label;
325 offs = vg->range->pins[i] * 16; 338 offs = vg->range->pins[i] * 16;
326 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); 339 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
@@ -330,8 +343,32 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
330 if (!label) 343 if (!label)
331 label = "Unrequested"; 344 label = "Unrequested";
332 345
346 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
347 case BYT_PULL_ASSIGN_UP:
348 pull = "up";
349 break;
350 case BYT_PULL_ASSIGN_DOWN:
351 pull = "down";
352 break;
353 }
354
355 switch (conf0 & BYT_PULL_STR_MASK) {
356 case BYT_PULL_STR_2K:
357 pull_str = "2k";
358 break;
359 case BYT_PULL_STR_10K:
360 pull_str = "10k";
361 break;
362 case BYT_PULL_STR_20K:
363 pull_str = "20k";
364 break;
365 case BYT_PULL_STR_40K:
366 pull_str = "40k";
367 break;
368 }
369
333 seq_printf(s, 370 seq_printf(s,
334 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n", 371 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
335 i, 372 i,
336 label, 373 label,
337 val & BYT_INPUT_EN ? " " : "in", 374 val & BYT_INPUT_EN ? " " : "in",
@@ -339,9 +376,19 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
339 val & BYT_LEVEL ? "hi" : "lo", 376 val & BYT_LEVEL ? "hi" : "lo",
340 vg->range->pins[i], offs, 377 vg->range->pins[i], offs,
341 conf0 & 0x7, 378 conf0 & 0x7,
342 conf0 & BYT_TRIG_NEG ? " fall" : "", 379 conf0 & BYT_TRIG_NEG ? " fall" : " ",
343 conf0 & BYT_TRIG_POS ? " rise" : "", 380 conf0 & BYT_TRIG_POS ? " rise" : " ",
344 conf0 & BYT_TRIG_LVL ? " level" : ""); 381 conf0 & BYT_TRIG_LVL ? " level" : " ");
382
383 if (pull && pull_str)
384 seq_printf(s, " %-4s %-3s", pull, pull_str);
385 else
386 seq_puts(s, " ");
387
388 if (conf0 & BYT_IODEN)
389 seq_puts(s, " open-drain");
390
391 seq_puts(s, "\n");
345 } 392 }
346 spin_unlock_irqrestore(&vg->lock, flags); 393 spin_unlock_irqrestore(&vg->lock, flags);
347} 394}
@@ -527,12 +574,6 @@ static int byt_gpio_probe(struct platform_device *pdev)
527 gc->can_sleep = false; 574 gc->can_sleep = false;
528 gc->dev = dev; 575 gc->dev = dev;
529 576
530 ret = gpiochip_add(gc);
531 if (ret) {
532 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
533 return ret;
534 }
535
536 /* set up interrupts */ 577 /* set up interrupts */
537 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 578 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
538 if (irq_rc && irq_rc->start) { 579 if (irq_rc && irq_rc->start) {
@@ -550,6 +591,12 @@ static int byt_gpio_probe(struct platform_device *pdev)
550 irq_set_chained_handler(hwirq, byt_gpio_irq_handler); 591 irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
551 } 592 }
552 593
594 ret = gpiochip_add(gc);
595 if (ret) {
596 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
597 return ret;
598 }
599
553 pm_runtime_enable(dev); 600 pm_runtime_enable(dev);
554 601
555 return 0; 602 return 0;
@@ -572,6 +619,7 @@ static const struct dev_pm_ops byt_gpio_pm_ops = {
572 619
573static const struct acpi_device_id byt_gpio_acpi_match[] = { 620static const struct acpi_device_id byt_gpio_acpi_match[] = {
574 { "INT33B2", 0 }, 621 { "INT33B2", 0 },
622 { "INT33FC", 0 },
575 { } 623 { }
576}; 624};
577MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); 625MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 07c81306f2f3..9609c23834ce 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -718,6 +718,73 @@ struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
718 }, 718 },
719}; 719};
720 720
721/* pin banks of exynos3250 pin-controller 0 */
722static struct samsung_pin_bank exynos3250_pin_banks0[] = {
723 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
724 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
725 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
726 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
727 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
728 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
729 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
730};
731
732/* pin banks of exynos3250 pin-controller 1 */
733static struct samsung_pin_bank exynos3250_pin_banks1[] = {
734 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
735 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
736 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
737 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
738 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
739 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
740 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
741 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
742 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
743 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
744 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
745 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
746 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
747 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
748 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
749 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
750};
751
752/*
753 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
754 * two gpio/pin-mux/pinconfig controllers.
755 */
756struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
757 {
758 /* pin-controller instance 0 data */
759 .pin_banks = exynos3250_pin_banks0,
760 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
761 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
762 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
763 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
764 .svc = EXYNOS_SVC_OFFSET,
765 .eint_gpio_init = exynos_eint_gpio_init,
766 .suspend = exynos_pinctrl_suspend,
767 .resume = exynos_pinctrl_resume,
768 .label = "exynos3250-gpio-ctrl0",
769 }, {
770 /* pin-controller instance 1 data */
771 .pin_banks = exynos3250_pin_banks1,
772 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
773 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
774 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
775 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
776 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
777 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
778 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
779 .svc = EXYNOS_SVC_OFFSET,
780 .eint_gpio_init = exynos_eint_gpio_init,
781 .eint_wkup_init = exynos_eint_wkup_init,
782 .suspend = exynos_pinctrl_suspend,
783 .resume = exynos_pinctrl_resume,
784 .label = "exynos3250-gpio-ctrl1",
785 },
786};
787
721/* pin banks of exynos4210 pin-controller 0 */ 788/* pin banks of exynos4210 pin-controller 0 */
722static struct samsung_pin_bank exynos4210_pin_banks0[] = { 789static struct samsung_pin_bank exynos4210_pin_banks0[] = {
723 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 790 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index e118fb121e02..a24448e5d399 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -491,7 +491,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
491 pin->mux_mode |= IOMUXC_CONFIG_SION; 491 pin->mux_mode |= IOMUXC_CONFIG_SION;
492 pin->config = config & ~IMX_PAD_SION; 492 pin->config = config & ~IMX_PAD_SION;
493 493
494 dev_dbg(info->dev, "%s: %d 0x%08lx", info->pins[pin_id].name, 494 dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
495 pin->mux_mode, pin->config); 495 pin->mux_mode, pin->config);
496 } 496 }
497 497
diff --git a/drivers/pinctrl/pinctrl-imx6sx.c b/drivers/pinctrl/pinctrl-imx6sx.c
new file mode 100644
index 000000000000..09758a56b9df
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx6sx.c
@@ -0,0 +1,407 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/err.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-imx.h"
18
19enum imx6sx_pads {
20 MX6Sx_PAD_RESERVE0 = 0,
21 MX6Sx_PAD_RESERVE1 = 1,
22 MX6Sx_PAD_RESERVE2 = 2,
23 MX6Sx_PAD_RESERVE3 = 3,
24 MX6Sx_PAD_RESERVE4 = 4,
25 MX6SX_PAD_GPIO1_IO00 = 5,
26 MX6SX_PAD_GPIO1_IO01 = 6,
27 MX6SX_PAD_GPIO1_IO02 = 7,
28 MX6SX_PAD_GPIO1_IO03 = 8,
29 MX6SX_PAD_GPIO1_IO04 = 9,
30 MX6SX_PAD_GPIO1_IO05 = 10,
31 MX6SX_PAD_GPIO1_IO06 = 11,
32 MX6SX_PAD_GPIO1_IO07 = 12,
33 MX6SX_PAD_GPIO1_IO08 = 13,
34 MX6SX_PAD_GPIO1_IO09 = 14,
35 MX6SX_PAD_GPIO1_IO10 = 15,
36 MX6SX_PAD_GPIO1_IO11 = 16,
37 MX6SX_PAD_GPIO1_IO12 = 17,
38 MX6SX_PAD_GPIO1_IO13 = 18,
39 MX6SX_PAD_CSI_DATA00 = 19,
40 MX6SX_PAD_CSI_DATA01 = 20,
41 MX6SX_PAD_CSI_DATA02 = 21,
42 MX6SX_PAD_CSI_DATA03 = 22,
43 MX6SX_PAD_CSI_DATA04 = 23,
44 MX6SX_PAD_CSI_DATA05 = 24,
45 MX6SX_PAD_CSI_DATA06 = 25,
46 MX6SX_PAD_CSI_DATA07 = 26,
47 MX6SX_PAD_CSI_HSYNC = 27,
48 MX6SX_PAD_CSI_MCLK = 28,
49 MX6SX_PAD_CSI_PIXCLK = 29,
50 MX6SX_PAD_CSI_VSYNC = 30,
51 MX6SX_PAD_ENET1_COL = 31,
52 MX6SX_PAD_ENET1_CRS = 32,
53 MX6SX_PAD_ENET1_MDC = 33,
54 MX6SX_PAD_ENET1_MDIO = 34,
55 MX6SX_PAD_ENET1_RX_CLK = 35,
56 MX6SX_PAD_ENET1_TX_CLK = 36,
57 MX6SX_PAD_ENET2_COL = 37,
58 MX6SX_PAD_ENET2_CRS = 38,
59 MX6SX_PAD_ENET2_RX_CLK = 39,
60 MX6SX_PAD_ENET2_TX_CLK = 40,
61 MX6SX_PAD_KEY_COL0 = 41,
62 MX6SX_PAD_KEY_COL1 = 42,
63 MX6SX_PAD_KEY_COL2 = 43,
64 MX6SX_PAD_KEY_COL3 = 44,
65 MX6SX_PAD_KEY_COL4 = 45,
66 MX6SX_PAD_KEY_ROW0 = 46,
67 MX6SX_PAD_KEY_ROW1 = 47,
68 MX6SX_PAD_KEY_ROW2 = 48,
69 MX6SX_PAD_KEY_ROW3 = 49,
70 MX6SX_PAD_KEY_ROW4 = 50,
71 MX6SX_PAD_LCD1_CLK = 51,
72 MX6SX_PAD_LCD1_DATA00 = 52,
73 MX6SX_PAD_LCD1_DATA01 = 53,
74 MX6SX_PAD_LCD1_DATA02 = 54,
75 MX6SX_PAD_LCD1_DATA03 = 55,
76 MX6SX_PAD_LCD1_DATA04 = 56,
77 MX6SX_PAD_LCD1_DATA05 = 57,
78 MX6SX_PAD_LCD1_DATA06 = 58,
79 MX6SX_PAD_LCD1_DATA07 = 59,
80 MX6SX_PAD_LCD1_DATA08 = 60,
81 MX6SX_PAD_LCD1_DATA09 = 61,
82 MX6SX_PAD_LCD1_DATA10 = 62,
83 MX6SX_PAD_LCD1_DATA11 = 63,
84 MX6SX_PAD_LCD1_DATA12 = 64,
85 MX6SX_PAD_LCD1_DATA13 = 65,
86 MX6SX_PAD_LCD1_DATA14 = 66,
87 MX6SX_PAD_LCD1_DATA15 = 67,
88 MX6SX_PAD_LCD1_DATA16 = 68,
89 MX6SX_PAD_LCD1_DATA17 = 69,
90 MX6SX_PAD_LCD1_DATA18 = 70,
91 MX6SX_PAD_LCD1_DATA19 = 71,
92 MX6SX_PAD_LCD1_DATA20 = 72,
93 MX6SX_PAD_LCD1_DATA21 = 73,
94 MX6SX_PAD_LCD1_DATA22 = 74,
95 MX6SX_PAD_LCD1_DATA23 = 75,
96 MX6SX_PAD_LCD1_ENABLE = 76,
97 MX6SX_PAD_LCD1_HSYNC = 77,
98 MX6SX_PAD_LCD1_RESET = 78,
99 MX6SX_PAD_LCD1_VSYNC = 79,
100 MX6SX_PAD_NAND_ALE = 80,
101 MX6SX_PAD_NAND_CE0_B = 81,
102 MX6SX_PAD_NAND_CE1_B = 82,
103 MX6SX_PAD_NAND_CLE = 83,
104 MX6SX_PAD_NAND_DATA00 = 84 ,
105 MX6SX_PAD_NAND_DATA01 = 85,
106 MX6SX_PAD_NAND_DATA02 = 86,
107 MX6SX_PAD_NAND_DATA03 = 87,
108 MX6SX_PAD_NAND_DATA04 = 88,
109 MX6SX_PAD_NAND_DATA05 = 89,
110 MX6SX_PAD_NAND_DATA06 = 90,
111 MX6SX_PAD_NAND_DATA07 = 91,
112 MX6SX_PAD_NAND_RE_B = 92,
113 MX6SX_PAD_NAND_READY_B = 93,
114 MX6SX_PAD_NAND_WE_B = 94,
115 MX6SX_PAD_NAND_WP_B = 95,
116 MX6SX_PAD_QSPI1A_DATA0 = 96,
117 MX6SX_PAD_QSPI1A_DATA1 = 97,
118 MX6SX_PAD_QSPI1A_DATA2 = 98,
119 MX6SX_PAD_QSPI1A_DATA3 = 99,
120 MX6SX_PAD_QSPI1A_DQS = 100,
121 MX6SX_PAD_QSPI1A_SCLK = 101,
122 MX6SX_PAD_QSPI1A_SS0_B = 102,
123 MX6SX_PAD_QSPI1A_SS1_B = 103,
124 MX6SX_PAD_QSPI1B_DATA0 = 104,
125 MX6SX_PAD_QSPI1B_DATA1 = 105,
126 MX6SX_PAD_QSPI1B_DATA2 = 106,
127 MX6SX_PAD_QSPI1B_DATA3 = 107,
128 MX6SX_PAD_QSPI1B_DQS = 108,
129 MX6SX_PAD_QSPI1B_SCLK = 109,
130 MX6SX_PAD_QSPI1B_SS0_B = 110,
131 MX6SX_PAD_QSPI1B_SS1_B = 111,
132 MX6SX_PAD_RGMII1_RD0 = 112,
133 MX6SX_PAD_RGMII1_RD1 = 113,
134 MX6SX_PAD_RGMII1_RD2 = 114,
135 MX6SX_PAD_RGMII1_RD3 = 115,
136 MX6SX_PAD_RGMII1_RX_CTL = 116,
137 MX6SX_PAD_RGMII1_RXC = 117,
138 MX6SX_PAD_RGMII1_TD0 = 118,
139 MX6SX_PAD_RGMII1_TD1 = 119,
140 MX6SX_PAD_RGMII1_TD2 = 120,
141 MX6SX_PAD_RGMII1_TD3 = 121,
142 MX6SX_PAD_RGMII1_TX_CTL = 122,
143 MX6SX_PAD_RGMII1_TXC = 123,
144 MX6SX_PAD_RGMII2_RD0 = 124,
145 MX6SX_PAD_RGMII2_RD1 = 125,
146 MX6SX_PAD_RGMII2_RD2 = 126,
147 MX6SX_PAD_RGMII2_RD3 = 127,
148 MX6SX_PAD_RGMII2_RX_CTL = 128,
149 MX6SX_PAD_RGMII2_RXC = 129,
150 MX6SX_PAD_RGMII2_TD0 = 130,
151 MX6SX_PAD_RGMII2_TD1 = 131,
152 MX6SX_PAD_RGMII2_TD2 = 132,
153 MX6SX_PAD_RGMII2_TD3 = 133,
154 MX6SX_PAD_RGMII2_TX_CTL = 134,
155 MX6SX_PAD_RGMII2_TXC = 135,
156 MX6SX_PAD_SD1_CLK = 136,
157 MX6SX_PAD_SD1_CMD = 137,
158 MX6SX_PAD_SD1_DATA0 = 138,
159 MX6SX_PAD_SD1_DATA1 = 139,
160 MX6SX_PAD_SD1_DATA2 = 140,
161 MX6SX_PAD_SD1_DATA3 = 141,
162 MX6SX_PAD_SD2_CLK = 142,
163 MX6SX_PAD_SD2_CMD = 143,
164 MX6SX_PAD_SD2_DATA0 = 144,
165 MX6SX_PAD_SD2_DATA1 = 145,
166 MX6SX_PAD_SD2_DATA2 = 146,
167 MX6SX_PAD_SD2_DATA3 = 147,
168 MX6SX_PAD_SD3_CLK = 148,
169 MX6SX_PAD_SD3_CMD = 149,
170 MX6SX_PAD_SD3_DATA0 = 150,
171 MX6SX_PAD_SD3_DATA1 = 151,
172 MX6SX_PAD_SD3_DATA2 = 152,
173 MX6SX_PAD_SD3_DATA3 = 153,
174 MX6SX_PAD_SD3_DATA4 = 154,
175 MX6SX_PAD_SD3_DATA5 = 155,
176 MX6SX_PAD_SD3_DATA6 = 156,
177 MX6SX_PAD_SD3_DATA7 = 157,
178 MX6SX_PAD_SD4_CLK = 158,
179 MX6SX_PAD_SD4_CMD = 159,
180 MX6SX_PAD_SD4_DATA0 = 160,
181 MX6SX_PAD_SD4_DATA1 = 161,
182 MX6SX_PAD_SD4_DATA2 = 162,
183 MX6SX_PAD_SD4_DATA3 = 163,
184 MX6SX_PAD_SD4_DATA4 = 164,
185 MX6SX_PAD_SD4_DATA5 = 165,
186 MX6SX_PAD_SD4_DATA6 = 166,
187 MX6SX_PAD_SD4_DATA7 = 167,
188 MX6SX_PAD_SD4_RESET_B = 168,
189 MX6SX_PAD_USB_H_DATA = 169,
190 MX6SX_PAD_USB_H_STROBE = 170,
191};
192
193/* Pad names for the pinmux subsystem */
194static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
195 IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0),
196 IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1),
197 IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2),
198 IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3),
199 IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4),
200 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00),
201 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01),
202 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02),
203 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03),
204 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04),
205 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05),
206 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06),
207 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07),
208 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08),
209 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09),
210 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10),
211 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11),
212 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12),
213 IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13),
214 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00),
215 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01),
216 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02),
217 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03),
218 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04),
219 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05),
220 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06),
221 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07),
222 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC),
223 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK),
224 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK),
225 IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC),
226 IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL),
227 IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS),
228 IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC),
229 IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO),
230 IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK),
231 IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK),
232 IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL),
233 IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS),
234 IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK),
235 IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK),
236 IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0),
237 IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1),
238 IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2),
239 IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3),
240 IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4),
241 IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0),
242 IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1),
243 IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2),
244 IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3),
245 IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4),
246 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK),
247 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00),
248 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01),
249 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02),
250 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03),
251 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04),
252 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05),
253 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06),
254 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07),
255 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08),
256 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09),
257 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10),
258 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11),
259 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12),
260 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13),
261 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14),
262 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15),
263 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16),
264 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17),
265 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18),
266 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19),
267 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20),
268 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21),
269 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22),
270 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23),
271 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE),
272 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC),
273 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET),
274 IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC),
275 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE),
276 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B),
277 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B),
278 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE),
279 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00),
280 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01),
281 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02),
282 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03),
283 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04),
284 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05),
285 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06),
286 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07),
287 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B),
288 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B),
289 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B),
290 IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B),
291 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0),
292 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1),
293 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2),
294 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3),
295 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS),
296 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK),
297 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B),
298 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B),
299 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0),
300 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1),
301 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2),
302 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3),
303 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS),
304 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK),
305 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B),
306 IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B),
307 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0),
308 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1),
309 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2),
310 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3),
311 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL),
312 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC),
313 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0),
314 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1),
315 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2),
316 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3),
317 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL),
318 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC),
319 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0),
320 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1),
321 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2),
322 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3),
323 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL),
324 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC),
325 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0),
326 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1),
327 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2),
328 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3),
329 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL),
330 IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC),
331 IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK),
332 IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD),
333 IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0),
334 IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1),
335 IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2),
336 IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3),
337 IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK),
338 IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD),
339 IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0),
340 IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1),
341 IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2),
342 IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3),
343 IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK),
344 IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD),
345 IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0),
346 IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1),
347 IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2),
348 IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3),
349 IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4),
350 IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5),
351 IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6),
352 IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7),
353 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK),
354 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD),
355 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0),
356 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1),
357 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2),
358 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3),
359 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4),
360 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5),
361 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6),
362 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7),
363 IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B),
364 IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA),
365 IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
366};
367
368static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
369 .pins = imx6sx_pinctrl_pads,
370 .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
371};
372
373static struct of_device_id imx6sx_pinctrl_of_match[] = {
374 { .compatible = "fsl,imx6sx-iomuxc", },
375 { /* sentinel */ }
376};
377
378static int imx6sx_pinctrl_probe(struct platform_device *pdev)
379{
380 return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info);
381}
382
383static struct platform_driver imx6sx_pinctrl_driver = {
384 .driver = {
385 .name = "imx6sx-pinctrl",
386 .owner = THIS_MODULE,
387 .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match),
388 },
389 .probe = imx6sx_pinctrl_probe,
390 .remove = imx_pinctrl_remove,
391};
392
393static int __init imx6sx_pinctrl_init(void)
394{
395 return platform_driver_register(&imx6sx_pinctrl_driver);
396}
397arch_initcall(imx6sx_pinctrl_init);
398
399static void __exit imx6sx_pinctrl_exit(void)
400{
401 platform_driver_unregister(&imx6sx_pinctrl_driver);
402}
403module_exit(imx6sx_pinctrl_exit);
404
405MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
406MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver");
407MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-ipq8064.c b/drivers/pinctrl/pinctrl-ipq8064.c
new file mode 100644
index 000000000000..acafea4c3a33
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-ipq8064.c
@@ -0,0 +1,653 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pinctrl/pinctrl.h>
19
20#include "pinctrl-msm.h"
21
22static const struct pinctrl_pin_desc ipq8064_pins[] = {
23 PINCTRL_PIN(0, "GPIO_0"),
24 PINCTRL_PIN(1, "GPIO_1"),
25 PINCTRL_PIN(2, "GPIO_2"),
26 PINCTRL_PIN(3, "GPIO_3"),
27 PINCTRL_PIN(4, "GPIO_4"),
28 PINCTRL_PIN(5, "GPIO_5"),
29 PINCTRL_PIN(6, "GPIO_6"),
30 PINCTRL_PIN(7, "GPIO_7"),
31 PINCTRL_PIN(8, "GPIO_8"),
32 PINCTRL_PIN(9, "GPIO_9"),
33 PINCTRL_PIN(10, "GPIO_10"),
34 PINCTRL_PIN(11, "GPIO_11"),
35 PINCTRL_PIN(12, "GPIO_12"),
36 PINCTRL_PIN(13, "GPIO_13"),
37 PINCTRL_PIN(14, "GPIO_14"),
38 PINCTRL_PIN(15, "GPIO_15"),
39 PINCTRL_PIN(16, "GPIO_16"),
40 PINCTRL_PIN(17, "GPIO_17"),
41 PINCTRL_PIN(18, "GPIO_18"),
42 PINCTRL_PIN(19, "GPIO_19"),
43 PINCTRL_PIN(20, "GPIO_20"),
44 PINCTRL_PIN(21, "GPIO_21"),
45 PINCTRL_PIN(22, "GPIO_22"),
46 PINCTRL_PIN(23, "GPIO_23"),
47 PINCTRL_PIN(24, "GPIO_24"),
48 PINCTRL_PIN(25, "GPIO_25"),
49 PINCTRL_PIN(26, "GPIO_26"),
50 PINCTRL_PIN(27, "GPIO_27"),
51 PINCTRL_PIN(28, "GPIO_28"),
52 PINCTRL_PIN(29, "GPIO_29"),
53 PINCTRL_PIN(30, "GPIO_30"),
54 PINCTRL_PIN(31, "GPIO_31"),
55 PINCTRL_PIN(32, "GPIO_32"),
56 PINCTRL_PIN(33, "GPIO_33"),
57 PINCTRL_PIN(34, "GPIO_34"),
58 PINCTRL_PIN(35, "GPIO_35"),
59 PINCTRL_PIN(36, "GPIO_36"),
60 PINCTRL_PIN(37, "GPIO_37"),
61 PINCTRL_PIN(38, "GPIO_38"),
62 PINCTRL_PIN(39, "GPIO_39"),
63 PINCTRL_PIN(40, "GPIO_40"),
64 PINCTRL_PIN(41, "GPIO_41"),
65 PINCTRL_PIN(42, "GPIO_42"),
66 PINCTRL_PIN(43, "GPIO_43"),
67 PINCTRL_PIN(44, "GPIO_44"),
68 PINCTRL_PIN(45, "GPIO_45"),
69 PINCTRL_PIN(46, "GPIO_46"),
70 PINCTRL_PIN(47, "GPIO_47"),
71 PINCTRL_PIN(48, "GPIO_48"),
72 PINCTRL_PIN(49, "GPIO_49"),
73 PINCTRL_PIN(50, "GPIO_50"),
74 PINCTRL_PIN(51, "GPIO_51"),
75 PINCTRL_PIN(52, "GPIO_52"),
76 PINCTRL_PIN(53, "GPIO_53"),
77 PINCTRL_PIN(54, "GPIO_54"),
78 PINCTRL_PIN(55, "GPIO_55"),
79 PINCTRL_PIN(56, "GPIO_56"),
80 PINCTRL_PIN(57, "GPIO_57"),
81 PINCTRL_PIN(58, "GPIO_58"),
82 PINCTRL_PIN(59, "GPIO_59"),
83 PINCTRL_PIN(60, "GPIO_60"),
84 PINCTRL_PIN(61, "GPIO_61"),
85 PINCTRL_PIN(62, "GPIO_62"),
86 PINCTRL_PIN(63, "GPIO_63"),
87 PINCTRL_PIN(64, "GPIO_64"),
88 PINCTRL_PIN(65, "GPIO_65"),
89 PINCTRL_PIN(66, "GPIO_66"),
90 PINCTRL_PIN(67, "GPIO_67"),
91 PINCTRL_PIN(68, "GPIO_68"),
92
93 PINCTRL_PIN(69, "SDC3_CLK"),
94 PINCTRL_PIN(70, "SDC3_CMD"),
95 PINCTRL_PIN(71, "SDC3_DATA"),
96};
97
98#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
99DECLARE_IPQ_GPIO_PINS(0);
100DECLARE_IPQ_GPIO_PINS(1);
101DECLARE_IPQ_GPIO_PINS(2);
102DECLARE_IPQ_GPIO_PINS(3);
103DECLARE_IPQ_GPIO_PINS(4);
104DECLARE_IPQ_GPIO_PINS(5);
105DECLARE_IPQ_GPIO_PINS(6);
106DECLARE_IPQ_GPIO_PINS(7);
107DECLARE_IPQ_GPIO_PINS(8);
108DECLARE_IPQ_GPIO_PINS(9);
109DECLARE_IPQ_GPIO_PINS(10);
110DECLARE_IPQ_GPIO_PINS(11);
111DECLARE_IPQ_GPIO_PINS(12);
112DECLARE_IPQ_GPIO_PINS(13);
113DECLARE_IPQ_GPIO_PINS(14);
114DECLARE_IPQ_GPIO_PINS(15);
115DECLARE_IPQ_GPIO_PINS(16);
116DECLARE_IPQ_GPIO_PINS(17);
117DECLARE_IPQ_GPIO_PINS(18);
118DECLARE_IPQ_GPIO_PINS(19);
119DECLARE_IPQ_GPIO_PINS(20);
120DECLARE_IPQ_GPIO_PINS(21);
121DECLARE_IPQ_GPIO_PINS(22);
122DECLARE_IPQ_GPIO_PINS(23);
123DECLARE_IPQ_GPIO_PINS(24);
124DECLARE_IPQ_GPIO_PINS(25);
125DECLARE_IPQ_GPIO_PINS(26);
126DECLARE_IPQ_GPIO_PINS(27);
127DECLARE_IPQ_GPIO_PINS(28);
128DECLARE_IPQ_GPIO_PINS(29);
129DECLARE_IPQ_GPIO_PINS(30);
130DECLARE_IPQ_GPIO_PINS(31);
131DECLARE_IPQ_GPIO_PINS(32);
132DECLARE_IPQ_GPIO_PINS(33);
133DECLARE_IPQ_GPIO_PINS(34);
134DECLARE_IPQ_GPIO_PINS(35);
135DECLARE_IPQ_GPIO_PINS(36);
136DECLARE_IPQ_GPIO_PINS(37);
137DECLARE_IPQ_GPIO_PINS(38);
138DECLARE_IPQ_GPIO_PINS(39);
139DECLARE_IPQ_GPIO_PINS(40);
140DECLARE_IPQ_GPIO_PINS(41);
141DECLARE_IPQ_GPIO_PINS(42);
142DECLARE_IPQ_GPIO_PINS(43);
143DECLARE_IPQ_GPIO_PINS(44);
144DECLARE_IPQ_GPIO_PINS(45);
145DECLARE_IPQ_GPIO_PINS(46);
146DECLARE_IPQ_GPIO_PINS(47);
147DECLARE_IPQ_GPIO_PINS(48);
148DECLARE_IPQ_GPIO_PINS(49);
149DECLARE_IPQ_GPIO_PINS(50);
150DECLARE_IPQ_GPIO_PINS(51);
151DECLARE_IPQ_GPIO_PINS(52);
152DECLARE_IPQ_GPIO_PINS(53);
153DECLARE_IPQ_GPIO_PINS(54);
154DECLARE_IPQ_GPIO_PINS(55);
155DECLARE_IPQ_GPIO_PINS(56);
156DECLARE_IPQ_GPIO_PINS(57);
157DECLARE_IPQ_GPIO_PINS(58);
158DECLARE_IPQ_GPIO_PINS(59);
159DECLARE_IPQ_GPIO_PINS(60);
160DECLARE_IPQ_GPIO_PINS(61);
161DECLARE_IPQ_GPIO_PINS(62);
162DECLARE_IPQ_GPIO_PINS(63);
163DECLARE_IPQ_GPIO_PINS(64);
164DECLARE_IPQ_GPIO_PINS(65);
165DECLARE_IPQ_GPIO_PINS(66);
166DECLARE_IPQ_GPIO_PINS(67);
167DECLARE_IPQ_GPIO_PINS(68);
168
169static const unsigned int sdc3_clk_pins[] = { 69 };
170static const unsigned int sdc3_cmd_pins[] = { 70 };
171static const unsigned int sdc3_data_pins[] = { 71 };
172
173#define FUNCTION(fname) \
174 [IPQ_MUX_##fname] = { \
175 .name = #fname, \
176 .groups = fname##_groups, \
177 .ngroups = ARRAY_SIZE(fname##_groups), \
178 }
179
180#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
181 { \
182 .name = "gpio" #id, \
183 .pins = gpio##id##_pins, \
184 .npins = ARRAY_SIZE(gpio##id##_pins), \
185 .funcs = (int[]){ \
186 IPQ_MUX_NA, /* gpio mode */ \
187 IPQ_MUX_##f1, \
188 IPQ_MUX_##f2, \
189 IPQ_MUX_##f3, \
190 IPQ_MUX_##f4, \
191 IPQ_MUX_##f5, \
192 IPQ_MUX_##f6, \
193 IPQ_MUX_##f7, \
194 IPQ_MUX_##f8, \
195 IPQ_MUX_##f9, \
196 IPQ_MUX_##f10, \
197 }, \
198 .nfuncs = 11, \
199 .ctl_reg = 0x1000 + 0x10 * id, \
200 .io_reg = 0x1004 + 0x10 * id, \
201 .intr_cfg_reg = 0x1008 + 0x10 * id, \
202 .intr_status_reg = 0x100c + 0x10 * id, \
203 .intr_target_reg = 0x400 + 0x4 * id, \
204 .mux_bit = 2, \
205 .pull_bit = 0, \
206 .drv_bit = 6, \
207 .oe_bit = 9, \
208 .in_bit = 0, \
209 .out_bit = 1, \
210 .intr_enable_bit = 0, \
211 .intr_status_bit = 0, \
212 .intr_ack_high = 1, \
213 .intr_target_bit = 0, \
214 .intr_raw_status_bit = 3, \
215 .intr_polarity_bit = 1, \
216 .intr_detection_bit = 2, \
217 .intr_detection_width = 1, \
218 }
219
220#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
221 { \
222 .name = #pg_name, \
223 .pins = pg_name##_pins, \
224 .npins = ARRAY_SIZE(pg_name##_pins), \
225 .ctl_reg = ctl, \
226 .io_reg = 0, \
227 .intr_cfg_reg = 0, \
228 .intr_status_reg = 0, \
229 .intr_target_reg = 0, \
230 .mux_bit = -1, \
231 .pull_bit = pull, \
232 .drv_bit = drv, \
233 .oe_bit = -1, \
234 .in_bit = -1, \
235 .out_bit = -1, \
236 .intr_enable_bit = -1, \
237 .intr_status_bit = -1, \
238 .intr_target_bit = -1, \
239 .intr_raw_status_bit = -1, \
240 .intr_polarity_bit = -1, \
241 .intr_detection_bit = -1, \
242 .intr_detection_width = -1, \
243 }
244
245enum ipq8064_functions {
246 IPQ_MUX_mdio,
247 IPQ_MUX_mi2s,
248 IPQ_MUX_pdm,
249 IPQ_MUX_ssbi,
250 IPQ_MUX_spmi,
251 IPQ_MUX_audio_pcm,
252 IPQ_MUX_gsbi1,
253 IPQ_MUX_gsbi2,
254 IPQ_MUX_gsbi4,
255 IPQ_MUX_gsbi5,
256 IPQ_MUX_gsbi5_spi_cs1,
257 IPQ_MUX_gsbi5_spi_cs2,
258 IPQ_MUX_gsbi5_spi_cs3,
259 IPQ_MUX_gsbi6,
260 IPQ_MUX_gsbi7,
261 IPQ_MUX_nss_spi,
262 IPQ_MUX_sdc1,
263 IPQ_MUX_spdif,
264 IPQ_MUX_nand,
265 IPQ_MUX_tsif1,
266 IPQ_MUX_tsif2,
267 IPQ_MUX_usb_fs_n,
268 IPQ_MUX_usb_fs,
269 IPQ_MUX_usb2_hsic,
270 IPQ_MUX_rgmii2,
271 IPQ_MUX_sata,
272 IPQ_MUX_pcie1_rst,
273 IPQ_MUX_pcie1_prsnt,
274 IPQ_MUX_pcie1_pwrflt,
275 IPQ_MUX_pcie1_pwren_n,
276 IPQ_MUX_pcie1_pwren,
277 IPQ_MUX_pcie1_clk_req,
278 IPQ_MUX_pcie2_rst,
279 IPQ_MUX_pcie2_prsnt,
280 IPQ_MUX_pcie2_pwrflt,
281 IPQ_MUX_pcie2_pwren_n,
282 IPQ_MUX_pcie2_pwren,
283 IPQ_MUX_pcie2_clk_req,
284 IPQ_MUX_pcie3_rst,
285 IPQ_MUX_pcie3_prsnt,
286 IPQ_MUX_pcie3_pwrflt,
287 IPQ_MUX_pcie3_pwren_n,
288 IPQ_MUX_pcie3_pwren,
289 IPQ_MUX_pcie3_clk_req,
290 IPQ_MUX_ps_hold,
291 IPQ_MUX_NA,
292};
293
294static const char * const mdio_groups[] = {
295 "gpio0", "gpio1", "gpio10", "gpio11",
296};
297
298static const char * const mi2s_groups[] = {
299 "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
300 "gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
301};
302
303static const char * const pdm_groups[] = {
304 "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
305 "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
306 "gpio59",
307};
308
309static const char * const ssbi_groups[] = {
310 "gpio10", "gpio11",
311};
312
313static const char * const spmi_groups[] = {
314 "gpio10", "gpio11",
315};
316
317static const char * const audio_pcm_groups[] = {
318 "gpio14", "gpio15", "gpio16", "gpio17",
319};
320
321static const char * const gsbi1_groups[] = {
322 "gpio51", "gpio52", "gpio53", "gpio54",
323};
324
325static const char * const gsbi2_groups[] = {
326 "gpio22", "gpio23", "gpio24", "gpio25",
327};
328
329static const char * const gsbi4_groups[] = {
330 "gpio10", "gpio11", "gpio12", "gpio13",
331};
332
333static const char * const gsbi5_groups[] = {
334 "gpio18", "gpio19", "gpio20", "gpio21",
335};
336
337static const char * const gsbi5_spi_cs1_groups[] = {
338 "gpio6", "gpio61",
339};
340
341static const char * const gsbi5_spi_cs2_groups[] = {
342 "gpio7", "gpio62",
343};
344
345static const char * const gsbi5_spi_cs3_groups[] = {
346 "gpio2",
347};
348
349static const char * const gsbi6_groups[] = {
350 "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
351 "gpio57", "gpio58",
352};
353
354static const char * const gsbi7_groups[] = {
355 "gpio6", "gpio7", "gpio8", "gpio9",
356};
357
358static const char * const nss_spi_groups[] = {
359 "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
360 "gpio57", "gpio58",
361};
362
363static const char * const sdc1_groups[] = {
364 "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
365 "gpio44", "gpio45", "gpio46", "gpio47",
366};
367
368static const char * const spdif_groups[] = {
369 "gpio10", "gpio48",
370};
371
372static const char * const nand_groups[] = {
373 "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
374 "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
375 "gpio46", "gpio47",
376};
377
378static const char * const tsif1_groups[] = {
379 "gpio55", "gpio56", "gpio57", "gpio58",
380};
381
382static const char * const tsif2_groups[] = {
383 "gpio59", "gpio60", "gpio61", "gpio62",
384};
385
386static const char * const usb_fs_n_groups[] = {
387 "gpio6",
388};
389
390static const char * const usb_fs_groups[] = {
391 "gpio6", "gpio7", "gpio8",
392};
393
394static const char * const usb2_hsic_groups[] = {
395 "gpio67", "gpio68",
396};
397
398static const char * const rgmii2_groups[] = {
399 "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
400 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
401};
402
403static const char * const sata_groups[] = {
404 "gpio10",
405};
406
407static const char * const pcie1_rst_groups[] = {
408 "gpio3",
409};
410
411static const char * const pcie1_prsnt_groups[] = {
412 "gpio3", "gpio11",
413};
414
415static const char * const pcie1_pwren_n_groups[] = {
416 "gpio4", "gpio12",
417};
418
419static const char * const pcie1_pwren_groups[] = {
420 "gpio4", "gpio12",
421};
422
423static const char * const pcie1_pwrflt_groups[] = {
424 "gpio5", "gpio13",
425};
426
427static const char * const pcie1_clk_req_groups[] = {
428 "gpio5",
429};
430
431static const char * const pcie2_rst_groups[] = {
432 "gpio48",
433};
434
435static const char * const pcie2_prsnt_groups[] = {
436 "gpio11", "gpio48",
437};
438
439static const char * const pcie2_pwren_n_groups[] = {
440 "gpio12", "gpio49",
441};
442
443static const char * const pcie2_pwren_groups[] = {
444 "gpio12", "gpio49",
445};
446
447static const char * const pcie2_pwrflt_groups[] = {
448 "gpio13", "gpio50",
449};
450
451static const char * const pcie2_clk_req_groups[] = {
452 "gpio50",
453};
454
455static const char * const pcie3_rst_groups[] = {
456 "gpio63",
457};
458
459static const char * const pcie3_prsnt_groups[] = {
460 "gpio11",
461};
462
463static const char * const pcie3_pwren_n_groups[] = {
464 "gpio12",
465};
466
467static const char * const pcie3_pwren_groups[] = {
468 "gpio12",
469};
470
471static const char * const pcie3_pwrflt_groups[] = {
472 "gpio13",
473};
474
475static const char * const pcie3_clk_req_groups[] = {
476 "gpio65",
477};
478
479static const char * const ps_hold_groups[] = {
480 "gpio26",
481};
482
483static const struct msm_function ipq8064_functions[] = {
484 FUNCTION(mdio),
485 FUNCTION(ssbi),
486 FUNCTION(spmi),
487 FUNCTION(mi2s),
488 FUNCTION(pdm),
489 FUNCTION(audio_pcm),
490 FUNCTION(gsbi1),
491 FUNCTION(gsbi2),
492 FUNCTION(gsbi4),
493 FUNCTION(gsbi5),
494 FUNCTION(gsbi5_spi_cs1),
495 FUNCTION(gsbi5_spi_cs2),
496 FUNCTION(gsbi5_spi_cs3),
497 FUNCTION(gsbi6),
498 FUNCTION(gsbi7),
499 FUNCTION(nss_spi),
500 FUNCTION(sdc1),
501 FUNCTION(spdif),
502 FUNCTION(nand),
503 FUNCTION(tsif1),
504 FUNCTION(tsif2),
505 FUNCTION(usb_fs_n),
506 FUNCTION(usb_fs),
507 FUNCTION(usb2_hsic),
508 FUNCTION(rgmii2),
509 FUNCTION(sata),
510 FUNCTION(pcie1_rst),
511 FUNCTION(pcie1_prsnt),
512 FUNCTION(pcie1_pwren_n),
513 FUNCTION(pcie1_pwren),
514 FUNCTION(pcie1_pwrflt),
515 FUNCTION(pcie1_clk_req),
516 FUNCTION(pcie2_rst),
517 FUNCTION(pcie2_prsnt),
518 FUNCTION(pcie2_pwren_n),
519 FUNCTION(pcie2_pwren),
520 FUNCTION(pcie2_pwrflt),
521 FUNCTION(pcie2_clk_req),
522 FUNCTION(pcie3_rst),
523 FUNCTION(pcie3_prsnt),
524 FUNCTION(pcie3_pwren_n),
525 FUNCTION(pcie3_pwren),
526 FUNCTION(pcie3_pwrflt),
527 FUNCTION(pcie3_clk_req),
528 FUNCTION(ps_hold),
529};
530
531static const struct msm_pingroup ipq8064_groups[] = {
532 PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
533 PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
534 PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
535 PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
536 PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
537 PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
538 PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
539 PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
540 PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
541 PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
542 PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
543 PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
544 PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
545 PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
546 PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
547 PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
548 PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
549 PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
550 PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
551 PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
552 PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
553 PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
554 PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
555 PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
556 PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
557 PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
558 PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
559 PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
560 PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
561 PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
562 PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
563 PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
564 PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
565 PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
566 PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
567 PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
568 PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
569 PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
570 PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
571 PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
572 PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
573 PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
574 PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
575 PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
576 PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
577 PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
578 PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
579 PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
580 PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
581 PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
582 PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
583 PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
584 PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
585 PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
586 PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
587 PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
588 PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
589 PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
590 PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
591 PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
592 PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
593 PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
594 PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
595 PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
596 PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
597 PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
598 PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
599 PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
600 PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
601 SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
602 SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
603 SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
604};
605
606#define NUM_GPIO_PINGROUPS 69
607
608static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
609 .pins = ipq8064_pins,
610 .npins = ARRAY_SIZE(ipq8064_pins),
611 .functions = ipq8064_functions,
612 .nfunctions = ARRAY_SIZE(ipq8064_functions),
613 .groups = ipq8064_groups,
614 .ngroups = ARRAY_SIZE(ipq8064_groups),
615 .ngpios = NUM_GPIO_PINGROUPS,
616};
617
618static int ipq8064_pinctrl_probe(struct platform_device *pdev)
619{
620 return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
621}
622
623static const struct of_device_id ipq8064_pinctrl_of_match[] = {
624 { .compatible = "qcom,ipq8064-pinctrl", },
625 { },
626};
627
628static struct platform_driver ipq8064_pinctrl_driver = {
629 .driver = {
630 .name = "ipq8064-pinctrl",
631 .owner = THIS_MODULE,
632 .of_match_table = ipq8064_pinctrl_of_match,
633 },
634 .probe = ipq8064_pinctrl_probe,
635 .remove = msm_pinctrl_remove,
636};
637
638static int __init ipq8064_pinctrl_init(void)
639{
640 return platform_driver_register(&ipq8064_pinctrl_driver);
641}
642arch_initcall(ipq8064_pinctrl_init);
643
644static void __exit ipq8064_pinctrl_exit(void)
645{
646 platform_driver_unregister(&ipq8064_pinctrl_driver);
647}
648module_exit(ipq8064_pinctrl_exit);
649
650MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
651MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
652MODULE_LICENSE("GPL v2");
653MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h
index 6d07f0238532..c7cfad5527d7 100644
--- a/drivers/pinctrl/pinctrl-lantiq.h
+++ b/drivers/pinctrl/pinctrl-lantiq.h
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#ifndef __PINCTRL_LANTIQ_H 12#ifndef __PINCTRL_LANTIQ_H
13#define __PINCTRL_LANTIQ_H
13 14
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/pinctrl/pinctrl.h> 16#include <linux/pinctrl/pinctrl.h>
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c
index e43fbce56598..df6dda4ce803 100644
--- a/drivers/pinctrl/pinctrl-msm.c
+++ b/drivers/pinctrl/pinctrl-msm.c
@@ -13,7 +13,6 @@
13 */ 13 */
14 14
15#include <linux/err.h> 15#include <linux/err.h>
16#include <linux/irqdomain.h>
17#include <linux/io.h> 16#include <linux/io.h>
18#include <linux/module.h> 17#include <linux/module.h>
19#include <linux/of.h> 18#include <linux/of.h>
@@ -26,8 +25,6 @@
26#include <linux/slab.h> 25#include <linux/slab.h>
27#include <linux/gpio.h> 26#include <linux/gpio.h>
28#include <linux/interrupt.h> 27#include <linux/interrupt.h>
29#include <linux/irq.h>
30#include <linux/irqchip/chained_irq.h>
31#include <linux/spinlock.h> 28#include <linux/spinlock.h>
32 29
33#include "core.h" 30#include "core.h"
@@ -41,7 +38,6 @@
41 * struct msm_pinctrl - state for a pinctrl-msm device 38 * struct msm_pinctrl - state for a pinctrl-msm device
42 * @dev: device handle. 39 * @dev: device handle.
43 * @pctrl: pinctrl handle. 40 * @pctrl: pinctrl handle.
44 * @domain: irqdomain handle.
45 * @chip: gpiochip handle. 41 * @chip: gpiochip handle.
46 * @irq: parent irq for the TLMM irq_chip. 42 * @irq: parent irq for the TLMM irq_chip.
47 * @lock: Spinlock to protect register resources as well 43 * @lock: Spinlock to protect register resources as well
@@ -55,7 +51,6 @@
55struct msm_pinctrl { 51struct msm_pinctrl {
56 struct device *dev; 52 struct device *dev;
57 struct pinctrl_dev *pctrl; 53 struct pinctrl_dev *pctrl;
58 struct irq_domain *domain;
59 struct gpio_chip chip; 54 struct gpio_chip chip;
60 int irq; 55 int irq;
61 56
@@ -68,6 +63,11 @@ struct msm_pinctrl {
68 void __iomem *regs; 63 void __iomem *regs;
69}; 64};
70 65
66static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc)
67{
68 return container_of(gc, struct msm_pinctrl, chip);
69}
70
71static int msm_get_groups_count(struct pinctrl_dev *pctldev) 71static int msm_get_groups_count(struct pinctrl_dev *pctldev)
72{ 72{
73 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 73 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
@@ -145,12 +145,12 @@ static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
145 if (WARN_ON(g->mux_bit < 0)) 145 if (WARN_ON(g->mux_bit < 0))
146 return -EINVAL; 146 return -EINVAL;
147 147
148 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { 148 for (i = 0; i < g->nfuncs; i++) {
149 if (g->funcs[i] == function) 149 if (g->funcs[i] == function)
150 break; 150 break;
151 } 151 }
152 152
153 if (WARN_ON(i == ARRAY_SIZE(g->funcs))) 153 if (WARN_ON(i == g->nfuncs))
154 return -EINVAL; 154 return -EINVAL;
155 155
156 spin_lock_irqsave(&pctrl->lock, flags); 156 spin_lock_irqsave(&pctrl->lock, flags);
@@ -480,13 +480,6 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
480 spin_unlock_irqrestore(&pctrl->lock, flags); 480 spin_unlock_irqrestore(&pctrl->lock, flags);
481} 481}
482 482
483static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
484{
485 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
486
487 return irq_find_mapping(pctrl->domain, offset);
488}
489
490static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) 483static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
491{ 484{
492 int gpio = chip->base + offset; 485 int gpio = chip->base + offset;
@@ -556,7 +549,6 @@ static struct gpio_chip msm_gpio_template = {
556 .direction_output = msm_gpio_direction_output, 549 .direction_output = msm_gpio_direction_output,
557 .get = msm_gpio_get, 550 .get = msm_gpio_get,
558 .set = msm_gpio_set, 551 .set = msm_gpio_set,
559 .to_irq = msm_gpio_to_irq,
560 .request = msm_gpio_request, 552 .request = msm_gpio_request,
561 .free = msm_gpio_free, 553 .free = msm_gpio_free,
562 .dbg_show = msm_gpio_dbg_show, 554 .dbg_show = msm_gpio_dbg_show,
@@ -608,12 +600,12 @@ static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
608 600
609static void msm_gpio_irq_mask(struct irq_data *d) 601static void msm_gpio_irq_mask(struct irq_data *d)
610{ 602{
603 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
604 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
611 const struct msm_pingroup *g; 605 const struct msm_pingroup *g;
612 struct msm_pinctrl *pctrl;
613 unsigned long flags; 606 unsigned long flags;
614 u32 val; 607 u32 val;
615 608
616 pctrl = irq_data_get_irq_chip_data(d);
617 g = &pctrl->soc->groups[d->hwirq]; 609 g = &pctrl->soc->groups[d->hwirq];
618 610
619 spin_lock_irqsave(&pctrl->lock, flags); 611 spin_lock_irqsave(&pctrl->lock, flags);
@@ -629,12 +621,12 @@ static void msm_gpio_irq_mask(struct irq_data *d)
629 621
630static void msm_gpio_irq_unmask(struct irq_data *d) 622static void msm_gpio_irq_unmask(struct irq_data *d)
631{ 623{
624 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
625 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
632 const struct msm_pingroup *g; 626 const struct msm_pingroup *g;
633 struct msm_pinctrl *pctrl;
634 unsigned long flags; 627 unsigned long flags;
635 u32 val; 628 u32 val;
636 629
637 pctrl = irq_data_get_irq_chip_data(d);
638 g = &pctrl->soc->groups[d->hwirq]; 630 g = &pctrl->soc->groups[d->hwirq];
639 631
640 spin_lock_irqsave(&pctrl->lock, flags); 632 spin_lock_irqsave(&pctrl->lock, flags);
@@ -654,12 +646,12 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
654 646
655static void msm_gpio_irq_ack(struct irq_data *d) 647static void msm_gpio_irq_ack(struct irq_data *d)
656{ 648{
649 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
650 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
657 const struct msm_pingroup *g; 651 const struct msm_pingroup *g;
658 struct msm_pinctrl *pctrl;
659 unsigned long flags; 652 unsigned long flags;
660 u32 val; 653 u32 val;
661 654
662 pctrl = irq_data_get_irq_chip_data(d);
663 g = &pctrl->soc->groups[d->hwirq]; 655 g = &pctrl->soc->groups[d->hwirq];
664 656
665 spin_lock_irqsave(&pctrl->lock, flags); 657 spin_lock_irqsave(&pctrl->lock, flags);
@@ -681,12 +673,12 @@ static void msm_gpio_irq_ack(struct irq_data *d)
681 673
682static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 674static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
683{ 675{
676 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
677 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
684 const struct msm_pingroup *g; 678 const struct msm_pingroup *g;
685 struct msm_pinctrl *pctrl;
686 unsigned long flags; 679 unsigned long flags;
687 u32 val; 680 u32 val;
688 681
689 pctrl = irq_data_get_irq_chip_data(d);
690 g = &pctrl->soc->groups[d->hwirq]; 682 g = &pctrl->soc->groups[d->hwirq];
691 683
692 spin_lock_irqsave(&pctrl->lock, flags); 684 spin_lock_irqsave(&pctrl->lock, flags);
@@ -775,11 +767,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
775 767
776static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 768static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
777{ 769{
778 struct msm_pinctrl *pctrl; 770 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
771 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
779 unsigned long flags; 772 unsigned long flags;
780 773
781 pctrl = irq_data_get_irq_chip_data(d);
782
783 spin_lock_irqsave(&pctrl->lock, flags); 774 spin_lock_irqsave(&pctrl->lock, flags);
784 775
785 irq_set_irq_wake(pctrl->irq, on); 776 irq_set_irq_wake(pctrl->irq, on);
@@ -789,25 +780,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
789 return 0; 780 return 0;
790} 781}
791 782
792static int msm_gpio_irq_reqres(struct irq_data *d)
793{
794 struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
795
796 if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) {
797 dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n",
798 d->hwirq);
799 return -EINVAL;
800 }
801 return 0;
802}
803
804static void msm_gpio_irq_relres(struct irq_data *d)
805{
806 struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
807
808 gpio_unlock_as_irq(&pctrl->chip, d->hwirq);
809}
810
811static struct irq_chip msm_gpio_irq_chip = { 783static struct irq_chip msm_gpio_irq_chip = {
812 .name = "msmgpio", 784 .name = "msmgpio",
813 .irq_mask = msm_gpio_irq_mask, 785 .irq_mask = msm_gpio_irq_mask,
@@ -815,14 +787,13 @@ static struct irq_chip msm_gpio_irq_chip = {
815 .irq_ack = msm_gpio_irq_ack, 787 .irq_ack = msm_gpio_irq_ack,
816 .irq_set_type = msm_gpio_irq_set_type, 788 .irq_set_type = msm_gpio_irq_set_type,
817 .irq_set_wake = msm_gpio_irq_set_wake, 789 .irq_set_wake = msm_gpio_irq_set_wake,
818 .irq_request_resources = msm_gpio_irq_reqres,
819 .irq_release_resources = msm_gpio_irq_relres,
820}; 790};
821 791
822static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 792static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
823{ 793{
794 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
824 const struct msm_pingroup *g; 795 const struct msm_pingroup *g;
825 struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc); 796 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
826 struct irq_chip *chip = irq_get_chip(irq); 797 struct irq_chip *chip = irq_get_chip(irq);
827 int irq_pin; 798 int irq_pin;
828 int handled = 0; 799 int handled = 0;
@@ -839,7 +810,7 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
839 g = &pctrl->soc->groups[i]; 810 g = &pctrl->soc->groups[i];
840 val = readl(pctrl->regs + g->intr_status_reg); 811 val = readl(pctrl->regs + g->intr_status_reg);
841 if (val & BIT(g->intr_status_bit)) { 812 if (val & BIT(g->intr_status_bit)) {
842 irq_pin = irq_find_mapping(pctrl->domain, i); 813 irq_pin = irq_find_mapping(gc->irqdomain, i);
843 generic_handle_irq(irq_pin); 814 generic_handle_irq(irq_pin);
844 handled++; 815 handled++;
845 } 816 }
@@ -852,19 +823,10 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
852 chained_irq_exit(chip, desc); 823 chained_irq_exit(chip, desc);
853} 824}
854 825
855/*
856 * This lock class tells lockdep that GPIO irqs are in a different
857 * category than their parents, so it won't report false recursion.
858 */
859static struct lock_class_key gpio_lock_class;
860
861static int msm_gpio_init(struct msm_pinctrl *pctrl) 826static int msm_gpio_init(struct msm_pinctrl *pctrl)
862{ 827{
863 struct gpio_chip *chip; 828 struct gpio_chip *chip;
864 int irq;
865 int ret; 829 int ret;
866 int i;
867 int r;
868 unsigned ngpio = pctrl->soc->ngpios; 830 unsigned ngpio = pctrl->soc->ngpios;
869 831
870 if (WARN_ON(ngpio > MAX_NR_GPIO)) 832 if (WARN_ON(ngpio > MAX_NR_GPIO))
@@ -890,23 +852,18 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
890 return ret; 852 return ret;
891 } 853 }
892 854
893 pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio, 855 ret = gpiochip_irqchip_add(chip,
894 &irq_domain_simple_ops, NULL); 856 &msm_gpio_irq_chip,
895 if (!pctrl->domain) { 857 0,
896 dev_err(pctrl->dev, "Failed to register irq domain\n"); 858 handle_edge_irq,
897 r = gpiochip_remove(&pctrl->chip); 859 IRQ_TYPE_NONE);
860 if (ret) {
861 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
898 return -ENOSYS; 862 return -ENOSYS;
899 } 863 }
900 864
901 for (i = 0; i < chip->ngpio; i++) { 865 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
902 irq = irq_create_mapping(pctrl->domain, i); 866 msm_gpio_irq_handler);
903 irq_set_lockdep_class(irq, &gpio_lock_class);
904 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
905 irq_set_chip_data(irq, pctrl);
906 }
907
908 irq_set_handler_data(pctrl->irq, pctrl);
909 irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler);
910 867
911 return 0; 868 return 0;
912} 869}
@@ -974,8 +931,6 @@ int msm_pinctrl_remove(struct platform_device *pdev)
974 return ret; 931 return ret;
975 } 932 }
976 933
977 irq_set_chained_handler(pctrl->irq, NULL);
978 irq_domain_remove(pctrl->domain);
979 pinctrl_unregister(pctrl->pctrl); 934 pinctrl_unregister(pctrl->pctrl);
980 935
981 return 0; 936 return 0;
diff --git a/drivers/pinctrl/pinctrl-msm.h b/drivers/pinctrl/pinctrl-msm.h
index 6e26f1b676d7..7b2a227a590a 100644
--- a/drivers/pinctrl/pinctrl-msm.h
+++ b/drivers/pinctrl/pinctrl-msm.h
@@ -65,7 +65,8 @@ struct msm_pingroup {
65 const unsigned *pins; 65 const unsigned *pins;
66 unsigned npins; 66 unsigned npins;
67 67
68 unsigned funcs[8]; 68 unsigned *funcs;
69 unsigned nfuncs;
69 70
70 s16 ctl_reg; 71 s16 ctl_reg;
71 s16 io_reg; 72 s16 io_reg;
diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c
index dde5529807aa..418306911a6f 100644
--- a/drivers/pinctrl/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/pinctrl-msm8x74.c
@@ -341,7 +341,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
341 .name = "gpio" #id, \ 341 .name = "gpio" #id, \
342 .pins = gpio##id##_pins, \ 342 .pins = gpio##id##_pins, \
343 .npins = ARRAY_SIZE(gpio##id##_pins), \ 343 .npins = ARRAY_SIZE(gpio##id##_pins), \
344 .funcs = { \ 344 .funcs = (int[]){ \
345 MSM_MUX_NA, /* gpio mode */ \ 345 MSM_MUX_NA, /* gpio mode */ \
346 MSM_MUX_##f1, \ 346 MSM_MUX_##f1, \
347 MSM_MUX_##f2, \ 347 MSM_MUX_##f2, \
@@ -351,6 +351,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
351 MSM_MUX_##f6, \ 351 MSM_MUX_##f6, \
352 MSM_MUX_##f7 \ 352 MSM_MUX_##f7 \
353 }, \ 353 }, \
354 .nfuncs = 8, \
354 .ctl_reg = 0x1000 + 0x10 * id, \ 355 .ctl_reg = 0x1000 + 0x10 * id, \
355 .io_reg = 0x1004 + 0x10 * id, \ 356 .io_reg = 0x1004 + 0x10 * id, \
356 .intr_cfg_reg = 0x1008 + 0x10 * id, \ 357 .intr_cfg_reg = 0x1008 + 0x10 * id, \
@@ -401,169 +402,568 @@ static const unsigned int sdc2_data_pins[] = { 151 };
401 * the pingroup table below. 402 * the pingroup table below.
402 */ 403 */
403enum msm8x74_functions { 404enum msm8x74_functions {
405 MSM_MUX_cci_i2c0,
406 MSM_MUX_cci_i2c1,
407 MSM_MUX_blsp_i2c1,
404 MSM_MUX_blsp_i2c2, 408 MSM_MUX_blsp_i2c2,
409 MSM_MUX_blsp_i2c3,
410 MSM_MUX_blsp_i2c4,
411 MSM_MUX_blsp_i2c5,
405 MSM_MUX_blsp_i2c6, 412 MSM_MUX_blsp_i2c6,
413 MSM_MUX_blsp_i2c7,
414 MSM_MUX_blsp_i2c8,
415 MSM_MUX_blsp_i2c9,
416 MSM_MUX_blsp_i2c10,
406 MSM_MUX_blsp_i2c11, 417 MSM_MUX_blsp_i2c11,
418 MSM_MUX_blsp_i2c12,
407 MSM_MUX_blsp_spi1, 419 MSM_MUX_blsp_spi1,
420 MSM_MUX_blsp_spi1_cs1,
421 MSM_MUX_blsp_spi1_cs2,
422 MSM_MUX_blsp_spi1_cs3,
423 MSM_MUX_blsp_spi2,
424 MSM_MUX_blsp_spi2_cs1,
425 MSM_MUX_blsp_spi2_cs2,
426 MSM_MUX_blsp_spi2_cs3,
427 MSM_MUX_blsp_spi3,
428 MSM_MUX_blsp_spi4,
429 MSM_MUX_blsp_spi5,
430 MSM_MUX_blsp_spi6,
431 MSM_MUX_blsp_spi7,
408 MSM_MUX_blsp_spi8, 432 MSM_MUX_blsp_spi8,
433 MSM_MUX_blsp_spi9,
434 MSM_MUX_blsp_spi10,
435 MSM_MUX_blsp_spi10_cs1,
436 MSM_MUX_blsp_spi10_cs2,
437 MSM_MUX_blsp_spi10_cs3,
438 MSM_MUX_blsp_spi11,
439 MSM_MUX_blsp_spi12,
440 MSM_MUX_blsp_uart1,
409 MSM_MUX_blsp_uart2, 441 MSM_MUX_blsp_uart2,
442 MSM_MUX_blsp_uart3,
443 MSM_MUX_blsp_uart4,
444 MSM_MUX_blsp_uart5,
445 MSM_MUX_blsp_uart6,
446 MSM_MUX_blsp_uart7,
410 MSM_MUX_blsp_uart8, 447 MSM_MUX_blsp_uart8,
448 MSM_MUX_blsp_uart9,
449 MSM_MUX_blsp_uart10,
450 MSM_MUX_blsp_uart11,
451 MSM_MUX_blsp_uart12,
452 MSM_MUX_blsp_uim1,
453 MSM_MUX_blsp_uim2,
454 MSM_MUX_blsp_uim3,
455 MSM_MUX_blsp_uim4,
456 MSM_MUX_blsp_uim5,
457 MSM_MUX_blsp_uim6,
458 MSM_MUX_blsp_uim7,
459 MSM_MUX_blsp_uim8,
460 MSM_MUX_blsp_uim9,
461 MSM_MUX_blsp_uim10,
462 MSM_MUX_blsp_uim11,
463 MSM_MUX_blsp_uim12,
464 MSM_MUX_uim1,
465 MSM_MUX_uim2,
466 MSM_MUX_uim_batt_alarm,
467 MSM_MUX_sdc3,
468 MSM_MUX_sdc4,
469 MSM_MUX_gcc_gp_clk1,
470 MSM_MUX_gcc_gp_clk2,
471 MSM_MUX_gcc_gp_clk3,
472 MSM_MUX_qua_mi2s,
473 MSM_MUX_pri_mi2s,
474 MSM_MUX_spkr_mi2s,
475 MSM_MUX_ter_mi2s,
476 MSM_MUX_sec_mi2s,
477 MSM_MUX_hdmi_cec,
478 MSM_MUX_hdmi_ddc,
479 MSM_MUX_hdmi_hpd,
480 MSM_MUX_edp_hpd,
481 MSM_MUX_mdp_vsync,
482 MSM_MUX_cam_mclk0,
483 MSM_MUX_cam_mclk1,
484 MSM_MUX_cam_mclk2,
485 MSM_MUX_cam_mclk3,
486 MSM_MUX_cci_timer0,
487 MSM_MUX_cci_timer1,
488 MSM_MUX_cci_timer2,
489 MSM_MUX_cci_timer3,
490 MSM_MUX_cci_timer4,
491 MSM_MUX_cci_async_in0,
492 MSM_MUX_cci_async_in1,
493 MSM_MUX_cci_async_in2,
494 MSM_MUX_gp_pdm0,
495 MSM_MUX_gp_pdm1,
496 MSM_MUX_gp_pdm2,
497 MSM_MUX_gp0_clk,
498 MSM_MUX_gp1_clk,
499 MSM_MUX_gp_mn,
500 MSM_MUX_tsif1,
501 MSM_MUX_tsif2,
502 MSM_MUX_hsic,
503 MSM_MUX_grfc,
504 MSM_MUX_audio_ref_clk,
505 MSM_MUX_bt,
506 MSM_MUX_fm,
507 MSM_MUX_wlan,
411 MSM_MUX_slimbus, 508 MSM_MUX_slimbus,
412 MSM_MUX_NA, 509 MSM_MUX_NA,
413}; 510};
414 511
512static const char * const blsp_uart1_groups[] = {
513 "gpio0", "gpio1", "gpio2", "gpio3"
514};
515static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" };
516static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" };
517static const char * const blsp_spi1_groups[] = {
518 "gpio0", "gpio1", "gpio2", "gpio3"
519};
520static const char * const blsp_spi1_cs1_groups[] = { "gpio8" };
521static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" };
522static const char * const blsp_spi1_cs3_groups[] = { "gpio10" };
523
524static const char * const blsp_uart2_groups[] = {
525 "gpio4", "gpio5", "gpio6", "gpio7"
526};
527static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" };
415static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; 528static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
529static const char * const blsp_spi2_groups[] = {
530 "gpio4", "gpio5", "gpio6", "gpio7"
531};
532static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" };
533static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" };
534static const char * const blsp_spi2_cs3_groups[] = { "gpio66" };
535
536static const char * const blsp_uart3_groups[] = {
537 "gpio8", "gpio9", "gpio10", "gpio11"
538};
539static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" };
540static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" };
541static const char * const blsp_spi3_groups[] = {
542 "gpio8", "gpio9", "gpio10", "gpio11"
543};
544
545static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" };
546static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" };
547
548static const char * const blsp_uart4_groups[] = {
549 "gpio19", "gpio20", "gpio21", "gpio22"
550};
551static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" };
552static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" };
553static const char * const blsp_spi4_groups[] = {
554 "gpio19", "gpio20", "gpio21", "gpio22"
555};
556
557static const char * const blsp_uart5_groups[] = {
558 "gpio23", "gpio24", "gpio25", "gpio26"
559};
560static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" };
561static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" };
562static const char * const blsp_spi5_groups[] = {
563 "gpio23", "gpio24", "gpio25", "gpio26"
564};
565
566static const char * const blsp_uart6_groups[] = {
567 "gpio27", "gpio28", "gpio29", "gpio30"
568};
569static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" };
416static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; 570static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" };
417static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; 571static const char * const blsp_spi6_groups[] = {
418static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" }; 572 "gpio27", "gpio28", "gpio29", "gpio30"
573};
574
575static const char * const blsp_uart7_groups[] = {
576 "gpio41", "gpio42", "gpio43", "gpio44"
577};
578static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" };
579static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" };
580static const char * const blsp_spi7_groups[] = {
581 "gpio41", "gpio42", "gpio43", "gpio44"
582};
583
584static const char * const blsp_uart8_groups[] = {
585 "gpio45", "gpio46", "gpio47", "gpio48"
586};
587static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" };
588static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" };
419static const char * const blsp_spi8_groups[] = { 589static const char * const blsp_spi8_groups[] = {
420 "gpio45", "gpio46", "gpio47", "gpio48" 590 "gpio45", "gpio46", "gpio47", "gpio48"
421}; 591};
422static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" }; 592
423static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" }; 593static const char * const blsp_uart9_groups[] = {
594 "gpio49", "gpio50", "gpio51", "gpio52"
595};
596static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" };
597static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" };
598static const char * const blsp_spi9_groups[] = {
599 "gpio49", "gpio50", "gpio51", "gpio52"
600};
601
602static const char * const blsp_uart10_groups[] = {
603 "gpio53", "gpio54", "gpio55", "gpio56"
604};
605static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" };
606static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" };
607static const char * const blsp_spi10_groups[] = {
608 "gpio53", "gpio54", "gpio55", "gpio56"
609};
610static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" };
611static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" };
612static const char * const blsp_spi10_cs3_groups[] = { "gpio90" };
613
614static const char * const blsp_uart11_groups[] = {
615 "gpio81", "gpio82", "gpio83", "gpio84"
616};
617static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" };
618static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" };
619static const char * const blsp_spi11_groups[] = {
620 "gpio81", "gpio82", "gpio83", "gpio84"
621};
622
623static const char * const blsp_uart12_groups[] = {
624 "gpio85", "gpio86", "gpio87", "gpio88"
625};
626static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" };
627static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" };
628static const char * const blsp_spi12_groups[] = {
629 "gpio85", "gpio86", "gpio87", "gpio88"
630};
631
632static const char * const uim1_groups[] = {
633 "gpio97", "gpio98", "gpio99", "gpio100"
634};
635
636static const char * const uim2_groups[] = {
637 "gpio49", "gpio50", "gpio51", "gpio52"
638};
639
640static const char * const uim_batt_alarm_groups[] = { "gpio101" };
641
642static const char * const sdc3_groups[] = {
643 "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"
644};
645
646static const char * const sdc4_groups[] = {
647 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96"
648};
649
650static const char * const gp0_clk_groups[] = { "gpio26" };
651static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" };
652static const char * const gp_mn_groups[] = { "gpio29" };
653static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" };
654static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" };
655static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" };
656
657static const char * const qua_mi2s_groups[] = {
658 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
659};
660
661static const char * const pri_mi2s_groups[] = {
662 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
663};
664
665static const char * const spkr_mi2s_groups[] = {
666 "gpio69", "gpio70", "gpio71", "gpio72"
667};
668
669static const char * const ter_mi2s_groups[] = {
670 "gpio73", "gpio74", "gpio75", "gpio76", "gpio77"
671};
672
673static const char * const sec_mi2s_groups[] = {
674 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82"
675};
676
677static const char * const hdmi_cec_groups[] = { "gpio31" };
678static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" };
679static const char * const hdmi_hpd_groups[] = { "gpio34" };
680static const char * const edp_hpd_groups[] = { "gpio102" };
681
682static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" };
683static const char * const cam_mclk0_groups[] = { "gpio15" };
684static const char * const cam_mclk1_groups[] = { "gpio16" };
685static const char * const cam_mclk2_groups[] = { "gpio17" };
686static const char * const cam_mclk3_groups[] = { "gpio18" };
687
688static const char * const cci_timer0_groups[] = { "gpio23" };
689static const char * const cci_timer1_groups[] = { "gpio24" };
690static const char * const cci_timer2_groups[] = { "gpio25" };
691static const char * const cci_timer3_groups[] = { "gpio26" };
692static const char * const cci_timer4_groups[] = { "gpio27" };
693static const char * const cci_async_in0_groups[] = { "gpio28" };
694static const char * const cci_async_in1_groups[] = { "gpio26" };
695static const char * const cci_async_in2_groups[] = { "gpio27" };
696
697static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" };
698static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" };
699static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" };
700
701static const char * const tsif1_groups[] = {
702 "gpio89", "gpio90", "gpio91", "gpio92"
703};
704
705static const char * const tsif2_groups[] = {
706 "gpio93", "gpio94", "gpio95", "gpio96"
707};
708
709static const char * const hsic_groups[] = { "gpio144", "gpio145" };
710static const char * const grfc_groups[] = {
711 "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
712 "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
713 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
714 "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127",
715 "gpio128", "gpio136", "gpio137", "gpio141", "gpio143"
716};
717
718static const char * const audio_ref_clk_groups[] = { "gpio69" };
719
720static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" };
721
722static const char * const fm_groups[] = { "gpio41", "gpio42" };
723
724static const char * const wlan_groups[] = {
725 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"
726};
727
424static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; 728static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
425 729
426static const struct msm_function msm8x74_functions[] = { 730static const struct msm_function msm8x74_functions[] = {
731 FUNCTION(cci_i2c0),
732 FUNCTION(cci_i2c1),
733 FUNCTION(uim1),
734 FUNCTION(uim2),
735 FUNCTION(uim_batt_alarm),
736 FUNCTION(blsp_uim1),
737 FUNCTION(blsp_uim2),
738 FUNCTION(blsp_uim3),
739 FUNCTION(blsp_uim4),
740 FUNCTION(blsp_uim5),
741 FUNCTION(blsp_uim6),
742 FUNCTION(blsp_uim7),
743 FUNCTION(blsp_uim8),
744 FUNCTION(blsp_uim9),
745 FUNCTION(blsp_uim10),
746 FUNCTION(blsp_uim11),
747 FUNCTION(blsp_uim12),
748 FUNCTION(blsp_i2c1),
427 FUNCTION(blsp_i2c2), 749 FUNCTION(blsp_i2c2),
750 FUNCTION(blsp_i2c3),
751 FUNCTION(blsp_i2c4),
752 FUNCTION(blsp_i2c5),
428 FUNCTION(blsp_i2c6), 753 FUNCTION(blsp_i2c6),
754 FUNCTION(blsp_i2c7),
755 FUNCTION(blsp_i2c8),
756 FUNCTION(blsp_i2c9),
757 FUNCTION(blsp_i2c10),
429 FUNCTION(blsp_i2c11), 758 FUNCTION(blsp_i2c11),
759 FUNCTION(blsp_i2c12),
430 FUNCTION(blsp_spi1), 760 FUNCTION(blsp_spi1),
761 FUNCTION(blsp_spi1_cs1),
762 FUNCTION(blsp_spi1_cs2),
763 FUNCTION(blsp_spi1_cs3),
764 FUNCTION(blsp_spi2),
765 FUNCTION(blsp_spi2_cs1),
766 FUNCTION(blsp_spi2_cs2),
767 FUNCTION(blsp_spi2_cs3),
768 FUNCTION(blsp_spi3),
769 FUNCTION(blsp_spi4),
770 FUNCTION(blsp_spi5),
771 FUNCTION(blsp_spi6),
772 FUNCTION(blsp_spi7),
431 FUNCTION(blsp_spi8), 773 FUNCTION(blsp_spi8),
774 FUNCTION(blsp_spi9),
775 FUNCTION(blsp_spi10),
776 FUNCTION(blsp_spi10_cs1),
777 FUNCTION(blsp_spi10_cs2),
778 FUNCTION(blsp_spi10_cs3),
779 FUNCTION(blsp_spi11),
780 FUNCTION(blsp_spi12),
781 FUNCTION(blsp_uart1),
432 FUNCTION(blsp_uart2), 782 FUNCTION(blsp_uart2),
783 FUNCTION(blsp_uart3),
784 FUNCTION(blsp_uart4),
785 FUNCTION(blsp_uart5),
786 FUNCTION(blsp_uart6),
787 FUNCTION(blsp_uart7),
433 FUNCTION(blsp_uart8), 788 FUNCTION(blsp_uart8),
789 FUNCTION(blsp_uart9),
790 FUNCTION(blsp_uart10),
791 FUNCTION(blsp_uart11),
792 FUNCTION(blsp_uart12),
793 FUNCTION(sdc3),
794 FUNCTION(sdc4),
795 FUNCTION(gcc_gp_clk1),
796 FUNCTION(gcc_gp_clk2),
797 FUNCTION(gcc_gp_clk3),
798 FUNCTION(qua_mi2s),
799 FUNCTION(pri_mi2s),
800 FUNCTION(spkr_mi2s),
801 FUNCTION(ter_mi2s),
802 FUNCTION(sec_mi2s),
803 FUNCTION(mdp_vsync),
804 FUNCTION(cam_mclk0),
805 FUNCTION(cam_mclk1),
806 FUNCTION(cam_mclk2),
807 FUNCTION(cam_mclk3),
808 FUNCTION(cci_timer0),
809 FUNCTION(cci_timer1),
810 FUNCTION(cci_timer2),
811 FUNCTION(cci_timer3),
812 FUNCTION(cci_timer4),
813 FUNCTION(cci_async_in0),
814 FUNCTION(cci_async_in1),
815 FUNCTION(cci_async_in2),
816 FUNCTION(hdmi_cec),
817 FUNCTION(hdmi_ddc),
818 FUNCTION(hdmi_hpd),
819 FUNCTION(edp_hpd),
820 FUNCTION(gp_pdm0),
821 FUNCTION(gp_pdm1),
822 FUNCTION(gp_pdm2),
823 FUNCTION(gp0_clk),
824 FUNCTION(gp1_clk),
825 FUNCTION(gp_mn),
826 FUNCTION(tsif1),
827 FUNCTION(tsif2),
828 FUNCTION(hsic),
829 FUNCTION(grfc),
830 FUNCTION(audio_ref_clk),
831 FUNCTION(bt),
832 FUNCTION(fm),
833 FUNCTION(wlan),
434 FUNCTION(slimbus), 834 FUNCTION(slimbus),
435}; 835};
436 836
437static const struct msm_pingroup msm8x74_groups[] = { 837static const struct msm_pingroup msm8x74_groups[] = {
438 PINGROUP(0, blsp_spi1, NA, NA, NA, NA, NA, NA), 838 PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
439 PINGROUP(1, blsp_spi1, NA, NA, NA, NA, NA, NA), 839 PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
440 PINGROUP(2, blsp_spi1, NA, NA, NA, NA, NA, NA), 840 PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
441 PINGROUP(3, blsp_spi1, NA, NA, NA, NA, NA, NA), 841 PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
442 PINGROUP(4, NA, blsp_uart2, NA, NA, NA, NA, NA), 842 PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
443 PINGROUP(5, NA, blsp_uart2, NA, NA, NA, NA, NA), 843 PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
444 PINGROUP(6, NA, NA, blsp_i2c2, NA, NA, NA, NA), 844 PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
445 PINGROUP(7, NA, NA, blsp_i2c2, NA, NA, NA, NA), 845 PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
446 PINGROUP(8, NA, NA, NA, NA, NA, NA, NA), 846 PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA),
447 PINGROUP(9, NA, NA, NA, NA, NA, NA, NA), 847 PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA),
448 PINGROUP(10, NA, NA, NA, NA, NA, NA, NA), 848 PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA),
449 PINGROUP(11, NA, NA, NA, NA, NA, NA, NA), 849 PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA),
450 PINGROUP(12, NA, NA, NA, NA, NA, NA, NA), 850 PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA),
451 PINGROUP(13, NA, NA, NA, NA, NA, NA, NA), 851 PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA),
452 PINGROUP(14, NA, NA, NA, NA, NA, NA, NA), 852 PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA),
453 PINGROUP(15, NA, NA, NA, NA, NA, NA, NA), 853 PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA),
454 PINGROUP(16, NA, NA, NA, NA, NA, NA, NA), 854 PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA),
455 PINGROUP(17, NA, NA, NA, NA, NA, NA, NA), 855 PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA),
456 PINGROUP(18, NA, NA, NA, NA, NA, NA, NA), 856 PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA),
457 PINGROUP(19, NA, NA, NA, NA, NA, NA, NA), 857 PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA),
458 PINGROUP(20, NA, NA, NA, NA, NA, NA, NA), 858 PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA),
459 PINGROUP(21, NA, NA, NA, NA, NA, NA, NA), 859 PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA),
460 PINGROUP(22, NA, NA, NA, NA, NA, NA, NA), 860 PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA),
461 PINGROUP(23, NA, NA, NA, NA, NA, NA, NA), 861 PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA),
462 PINGROUP(24, NA, NA, NA, NA, NA, NA, NA), 862 PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA),
463 PINGROUP(25, NA, NA, NA, NA, NA, NA, NA), 863 PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA),
464 PINGROUP(26, NA, NA, NA, NA, NA, NA, NA), 864 PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA),
465 PINGROUP(27, NA, NA, NA, NA, NA, NA, NA), 865 PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA),
466 PINGROUP(28, NA, NA, NA, NA, NA, NA, NA), 866 PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA),
467 PINGROUP(29, NA, NA, blsp_i2c6, NA, NA, NA, NA), 867 PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA),
468 PINGROUP(30, NA, NA, blsp_i2c6, NA, NA, NA, NA), 868 PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
469 PINGROUP(31, NA, NA, NA, NA, NA, NA, NA), 869 PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA),
470 PINGROUP(32, NA, NA, NA, NA, NA, NA, NA), 870 PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA),
471 PINGROUP(33, NA, NA, NA, NA, NA, NA, NA), 871 PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA),
472 PINGROUP(34, NA, NA, NA, NA, NA, NA, NA), 872 PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA),
473 PINGROUP(35, NA, NA, NA, NA, NA, NA, NA), 873 PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA),
474 PINGROUP(36, NA, NA, NA, NA, NA, NA, NA), 874 PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA),
475 PINGROUP(37, NA, NA, NA, NA, NA, NA, NA), 875 PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA),
476 PINGROUP(38, NA, NA, NA, NA, NA, NA, NA), 876 PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA),
477 PINGROUP(39, NA, NA, NA, NA, NA, NA, NA), 877 PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA),
478 PINGROUP(40, NA, NA, NA, NA, NA, NA, NA), 878 PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA),
479 PINGROUP(41, NA, NA, NA, NA, NA, NA, NA), 879 PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
480 PINGROUP(42, NA, NA, NA, NA, NA, NA, NA), 880 PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
481 PINGROUP(43, NA, NA, NA, NA, NA, NA, NA), 881 PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
482 PINGROUP(44, NA, NA, NA, NA, NA, NA, NA), 882 PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
483 PINGROUP(45, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA), 883 PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
484 PINGROUP(46, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA), 884 PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
485 PINGROUP(47, blsp_spi8, NA, NA, NA, NA, NA, NA), 885 PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA),
486 PINGROUP(48, blsp_spi8, NA, NA, NA, NA, NA, NA), 886 PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA),
487 PINGROUP(49, NA, NA, NA, NA, NA, NA, NA), 887 PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA),
488 PINGROUP(50, NA, NA, NA, NA, NA, NA, NA), 888 PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA),
489 PINGROUP(51, NA, NA, NA, NA, NA, NA, NA), 889 PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA),
490 PINGROUP(52, NA, NA, NA, NA, NA, NA, NA), 890 PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA),
491 PINGROUP(53, NA, NA, NA, NA, NA, NA, NA), 891 PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA),
492 PINGROUP(54, NA, NA, NA, NA, NA, NA, NA), 892 PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA),
493 PINGROUP(55, NA, NA, NA, NA, NA, NA, NA), 893 PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
494 PINGROUP(56, NA, NA, NA, NA, NA, NA, NA), 894 PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
495 PINGROUP(57, NA, NA, NA, NA, NA, NA, NA), 895 PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA),
496 PINGROUP(58, NA, NA, NA, NA, NA, NA, NA), 896 PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA),
497 PINGROUP(59, NA, NA, NA, NA, NA, NA, NA), 897 PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA),
498 PINGROUP(60, NA, NA, NA, NA, NA, NA, NA), 898 PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA),
499 PINGROUP(61, NA, NA, NA, NA, NA, NA, NA), 899 PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA),
500 PINGROUP(62, NA, NA, NA, NA, NA, NA, NA), 900 PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA),
501 PINGROUP(63, NA, NA, NA, NA, NA, NA, NA), 901 PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA),
502 PINGROUP(64, NA, NA, NA, NA, NA, NA, NA), 902 PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA),
503 PINGROUP(65, NA, NA, NA, NA, NA, NA, NA), 903 PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA),
504 PINGROUP(66, NA, NA, NA, NA, NA, NA, NA), 904 PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA),
505 PINGROUP(67, NA, NA, NA, NA, NA, NA, NA), 905 PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA),
506 PINGROUP(68, NA, NA, NA, NA, NA, NA, NA), 906 PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA),
507 PINGROUP(69, NA, NA, NA, NA, NA, NA, NA), 907 PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA),
508 PINGROUP(70, slimbus, NA, NA, NA, NA, NA, NA), 908 PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA),
509 PINGROUP(71, slimbus, NA, NA, NA, NA, NA, NA), 909 PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA),
510 PINGROUP(72, NA, NA, NA, NA, NA, NA, NA), 910 PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA),
511 PINGROUP(73, NA, NA, NA, NA, NA, NA, NA), 911 PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA),
512 PINGROUP(74, NA, NA, NA, NA, NA, NA, NA), 912 PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA),
513 PINGROUP(75, NA, NA, NA, NA, NA, NA, NA), 913 PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA),
514 PINGROUP(76, NA, NA, NA, NA, NA, NA, NA), 914 PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA),
515 PINGROUP(77, NA, NA, NA, NA, NA, NA, NA), 915 PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA),
516 PINGROUP(78, NA, NA, NA, NA, NA, NA, NA), 916 PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA),
517 PINGROUP(79, NA, NA, NA, NA, NA, NA, NA), 917 PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA),
518 PINGROUP(80, NA, NA, NA, NA, NA, NA, NA), 918 PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA),
519 PINGROUP(81, NA, NA, NA, NA, NA, NA, NA), 919 PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA),
520 PINGROUP(82, NA, NA, NA, NA, NA, NA, NA), 920 PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA),
521 PINGROUP(83, NA, NA, blsp_i2c11, NA, NA, NA, NA), 921 PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
522 PINGROUP(84, NA, NA, blsp_i2c11, NA, NA, NA, NA), 922 PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
523 PINGROUP(85, NA, NA, NA, NA, NA, NA, NA), 923 PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA),
524 PINGROUP(86, NA, NA, NA, NA, NA, NA, NA), 924 PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA),
525 PINGROUP(87, NA, NA, NA, NA, NA, NA, NA), 925 PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
526 PINGROUP(88, NA, NA, NA, NA, NA, NA, NA), 926 PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
527 PINGROUP(89, NA, NA, NA, NA, NA, NA, NA), 927 PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA),
528 PINGROUP(90, NA, NA, NA, NA, NA, NA, NA), 928 PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA),
529 PINGROUP(91, NA, NA, NA, NA, NA, NA, NA), 929 PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA),
530 PINGROUP(92, NA, NA, NA, NA, NA, NA, NA), 930 PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA),
531 PINGROUP(93, NA, NA, NA, NA, NA, NA, NA), 931 PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA),
532 PINGROUP(94, NA, NA, NA, NA, NA, NA, NA), 932 PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA),
533 PINGROUP(95, NA, NA, NA, NA, NA, NA, NA), 933 PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA),
534 PINGROUP(96, NA, NA, NA, NA, NA, NA, NA), 934 PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA),
535 PINGROUP(97, NA, NA, NA, NA, NA, NA, NA), 935 PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA),
536 PINGROUP(98, NA, NA, NA, NA, NA, NA, NA), 936 PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA),
537 PINGROUP(99, NA, NA, NA, NA, NA, NA, NA), 937 PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA),
538 PINGROUP(100, NA, NA, NA, NA, NA, NA, NA), 938 PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA),
539 PINGROUP(101, NA, NA, NA, NA, NA, NA, NA), 939 PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA),
540 PINGROUP(102, NA, NA, NA, NA, NA, NA, NA), 940 PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA),
541 PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), 941 PINGROUP(103, NA, NA, NA, NA, NA, NA, NA),
542 PINGROUP(104, NA, NA, NA, NA, NA, NA, NA), 942 PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA),
543 PINGROUP(105, NA, NA, NA, NA, NA, NA, NA), 943 PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA),
544 PINGROUP(106, NA, NA, NA, NA, NA, NA, NA), 944 PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA),
545 PINGROUP(107, NA, NA, NA, NA, NA, NA, NA), 945 PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA),
546 PINGROUP(108, NA, NA, NA, NA, NA, NA, NA), 946 PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA),
547 PINGROUP(109, NA, NA, NA, NA, NA, NA, NA), 947 PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA),
548 PINGROUP(110, NA, NA, NA, NA, NA, NA, NA), 948 PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA),
549 PINGROUP(111, NA, NA, NA, NA, NA, NA, NA), 949 PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA),
550 PINGROUP(112, NA, NA, NA, NA, NA, NA, NA), 950 PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA),
551 PINGROUP(113, NA, NA, NA, NA, NA, NA, NA), 951 PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA),
552 PINGROUP(114, NA, NA, NA, NA, NA, NA, NA), 952 PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA),
553 PINGROUP(115, NA, NA, NA, NA, NA, NA, NA), 953 PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA),
554 PINGROUP(116, NA, NA, NA, NA, NA, NA, NA), 954 PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA),
555 PINGROUP(117, NA, NA, NA, NA, NA, NA, NA), 955 PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA),
556 PINGROUP(118, NA, NA, NA, NA, NA, NA, NA), 956 PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA),
557 PINGROUP(119, NA, NA, NA, NA, NA, NA, NA), 957 PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA),
558 PINGROUP(120, NA, NA, NA, NA, NA, NA, NA), 958 PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA),
559 PINGROUP(121, NA, NA, NA, NA, NA, NA, NA), 959 PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA),
560 PINGROUP(122, NA, NA, NA, NA, NA, NA, NA), 960 PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA),
561 PINGROUP(123, NA, NA, NA, NA, NA, NA, NA), 961 PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA),
562 PINGROUP(124, NA, NA, NA, NA, NA, NA, NA), 962 PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA),
563 PINGROUP(125, NA, NA, NA, NA, NA, NA, NA), 963 PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA),
564 PINGROUP(126, NA, NA, NA, NA, NA, NA, NA), 964 PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA),
565 PINGROUP(127, NA, NA, NA, NA, NA, NA, NA), 965 PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA),
566 PINGROUP(128, NA, NA, NA, NA, NA, NA, NA), 966 PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA),
567 PINGROUP(129, NA, NA, NA, NA, NA, NA, NA), 967 PINGROUP(129, NA, NA, NA, NA, NA, NA, NA),
568 PINGROUP(130, NA, NA, NA, NA, NA, NA, NA), 968 PINGROUP(130, NA, NA, NA, NA, NA, NA, NA),
569 PINGROUP(131, NA, NA, NA, NA, NA, NA, NA), 969 PINGROUP(131, NA, NA, NA, NA, NA, NA, NA),
@@ -571,16 +971,16 @@ static const struct msm_pingroup msm8x74_groups[] = {
571 PINGROUP(133, NA, NA, NA, NA, NA, NA, NA), 971 PINGROUP(133, NA, NA, NA, NA, NA, NA, NA),
572 PINGROUP(134, NA, NA, NA, NA, NA, NA, NA), 972 PINGROUP(134, NA, NA, NA, NA, NA, NA, NA),
573 PINGROUP(135, NA, NA, NA, NA, NA, NA, NA), 973 PINGROUP(135, NA, NA, NA, NA, NA, NA, NA),
574 PINGROUP(136, NA, NA, NA, NA, NA, NA, NA), 974 PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA),
575 PINGROUP(137, NA, NA, NA, NA, NA, NA, NA), 975 PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA),
576 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA), 976 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
577 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA), 977 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
578 PINGROUP(140, NA, NA, NA, NA, NA, NA, NA), 978 PINGROUP(140, NA, NA, NA, NA, NA, NA, NA),
579 PINGROUP(141, NA, NA, NA, NA, NA, NA, NA), 979 PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA),
580 PINGROUP(143, NA, NA, NA, NA, NA, NA, NA), 980 PINGROUP(142, NA, NA, NA, NA, NA, NA, NA),
581 PINGROUP(143, NA, NA, NA, NA, NA, NA, NA), 981 PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA),
582 PINGROUP(144, NA, NA, NA, NA, NA, NA, NA), 982 PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA),
583 PINGROUP(145, NA, NA, NA, NA, NA, NA, NA), 983 PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA),
584 SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), 984 SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
585 SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), 985 SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
586 SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), 986 SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 96c60d230c13..bb805d5e9ff0 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -37,6 +37,8 @@
37#include <linux/pinctrl/pinconf-generic.h> 37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h> 38#include <linux/irqchip/chained_irq.h>
39#include <linux/clk.h> 39#include <linux/clk.h>
40#include <linux/regmap.h>
41#include <linux/mfd/syscon.h>
40#include <dt-bindings/pinctrl/rockchip.h> 42#include <dt-bindings/pinctrl/rockchip.h>
41 43
42#include "core.h" 44#include "core.h"
@@ -86,7 +88,7 @@ enum rockchip_pin_bank_type {
86 */ 88 */
87struct rockchip_pin_bank { 89struct rockchip_pin_bank {
88 void __iomem *reg_base; 90 void __iomem *reg_base;
89 void __iomem *reg_pull; 91 struct regmap *regmap_pull;
90 struct clk *clk; 92 struct clk *clk;
91 int irq; 93 int irq;
92 u32 pin_base; 94 u32 pin_base;
@@ -120,8 +122,9 @@ struct rockchip_pin_ctrl {
120 char *label; 122 char *label;
121 enum rockchip_pinctrl_type type; 123 enum rockchip_pinctrl_type type;
122 int mux_offset; 124 int mux_offset;
123 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, 125 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
124 void __iomem **reg, u8 *bit); 126 int pin_num, struct regmap **regmap,
127 int *reg, u8 *bit);
125}; 128};
126 129
127struct rockchip_pin_config { 130struct rockchip_pin_config {
@@ -159,8 +162,10 @@ struct rockchip_pmx_func {
159}; 162};
160 163
161struct rockchip_pinctrl { 164struct rockchip_pinctrl {
162 void __iomem *reg_base; 165 struct regmap *regmap_base;
163 void __iomem *reg_pull; 166 int reg_size;
167 struct regmap *regmap_pull;
168 struct regmap *regmap_pmu;
164 struct device *dev; 169 struct device *dev;
165 struct rockchip_pin_ctrl *ctrl; 170 struct rockchip_pin_ctrl *ctrl;
166 struct pinctrl_desc pctl; 171 struct pinctrl_desc pctl;
@@ -171,6 +176,12 @@ struct rockchip_pinctrl {
171 unsigned int nfunctions; 176 unsigned int nfunctions;
172}; 177};
173 178
179static struct regmap_config rockchip_regmap_config = {
180 .reg_bits = 32,
181 .val_bits = 32,
182 .reg_stride = 4,
183};
184
174static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) 185static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
175{ 186{
176 return container_of(gc, struct rockchip_pin_bank, gpio_chip); 187 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
@@ -329,6 +340,29 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
329 * Hardware access 340 * Hardware access
330 */ 341 */
331 342
343static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
344{
345 struct rockchip_pinctrl *info = bank->drvdata;
346 unsigned int val;
347 int reg, ret;
348 u8 bit;
349
350 if (bank->bank_type == RK3188_BANK0 && pin < 16)
351 return RK_FUNC_GPIO;
352
353 /* get basic quadrupel of mux registers and the correct reg inside */
354 reg = info->ctrl->mux_offset;
355 reg += bank->bank_num * 0x10;
356 reg += (pin / 8) * 4;
357 bit = (pin % 8) * 2;
358
359 ret = regmap_read(info->regmap_base, reg, &val);
360 if (ret)
361 return ret;
362
363 return ((val >> bit) & 3);
364}
365
332/* 366/*
333 * Set a new mux function for a pin. 367 * Set a new mux function for a pin.
334 * 368 *
@@ -345,7 +379,7 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
345static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 379static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
346{ 380{
347 struct rockchip_pinctrl *info = bank->drvdata; 381 struct rockchip_pinctrl *info = bank->drvdata;
348 void __iomem *reg = info->reg_base + info->ctrl->mux_offset; 382 int reg, ret;
349 unsigned long flags; 383 unsigned long flags;
350 u8 bit; 384 u8 bit;
351 u32 data; 385 u32 data;
@@ -368,6 +402,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
368 bank->bank_num, pin, mux); 402 bank->bank_num, pin, mux);
369 403
370 /* get basic quadrupel of mux registers and the correct reg inside */ 404 /* get basic quadrupel of mux registers and the correct reg inside */
405 reg = info->ctrl->mux_offset;
371 reg += bank->bank_num * 0x10; 406 reg += bank->bank_num * 0x10;
372 reg += (pin / 8) * 4; 407 reg += (pin / 8) * 4;
373 bit = (pin % 8) * 2; 408 bit = (pin % 8) * 2;
@@ -376,11 +411,11 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
376 411
377 data = (3 << (bit + 16)); 412 data = (3 << (bit + 16));
378 data |= (mux & 3) << bit; 413 data |= (mux & 3) << bit;
379 writel(data, reg); 414 ret = regmap_write(info->regmap_base, reg, data);
380 415
381 spin_unlock_irqrestore(&bank->slock, flags); 416 spin_unlock_irqrestore(&bank->slock, flags);
382 417
383 return 0; 418 return ret;
384} 419}
385 420
386#define RK2928_PULL_OFFSET 0x118 421#define RK2928_PULL_OFFSET 0x118
@@ -388,34 +423,46 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
388#define RK2928_PULL_BANK_STRIDE 8 423#define RK2928_PULL_BANK_STRIDE 8
389 424
390static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 425static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
391 int pin_num, void __iomem **reg, u8 *bit) 426 int pin_num, struct regmap **regmap,
427 int *reg, u8 *bit)
392{ 428{
393 struct rockchip_pinctrl *info = bank->drvdata; 429 struct rockchip_pinctrl *info = bank->drvdata;
394 430
395 *reg = info->reg_base + RK2928_PULL_OFFSET; 431 *regmap = info->regmap_base;
432 *reg = RK2928_PULL_OFFSET;
396 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 433 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
397 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 434 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
398 435
399 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 436 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
400}; 437};
401 438
439#define RK3188_PULL_OFFSET 0x164
402#define RK3188_PULL_BITS_PER_PIN 2 440#define RK3188_PULL_BITS_PER_PIN 2
403#define RK3188_PULL_PINS_PER_REG 8 441#define RK3188_PULL_PINS_PER_REG 8
404#define RK3188_PULL_BANK_STRIDE 16 442#define RK3188_PULL_BANK_STRIDE 16
443#define RK3188_PULL_PMU_OFFSET 0x64
405 444
406static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 445static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
407 int pin_num, void __iomem **reg, u8 *bit) 446 int pin_num, struct regmap **regmap,
447 int *reg, u8 *bit)
408{ 448{
409 struct rockchip_pinctrl *info = bank->drvdata; 449 struct rockchip_pinctrl *info = bank->drvdata;
410 450
411 /* The first 12 pins of the first bank are located elsewhere */ 451 /* The first 12 pins of the first bank are located elsewhere */
412 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) { 452 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
413 *reg = bank->reg_pull + 453 *regmap = info->regmap_pmu ? info->regmap_pmu
414 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 454 : bank->regmap_pull;
455 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
456 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
415 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 457 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
416 *bit *= RK3188_PULL_BITS_PER_PIN; 458 *bit *= RK3188_PULL_BITS_PER_PIN;
417 } else { 459 } else {
418 *reg = info->reg_pull - 4; 460 *regmap = info->regmap_pull ? info->regmap_pull
461 : info->regmap_base;
462 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
463
464 /* correct the offset, as it is the 2nd pull register */
465 *reg -= 4;
419 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 466 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
420 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 467 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
421 468
@@ -433,7 +480,8 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
433{ 480{
434 struct rockchip_pinctrl *info = bank->drvdata; 481 struct rockchip_pinctrl *info = bank->drvdata;
435 struct rockchip_pin_ctrl *ctrl = info->ctrl; 482 struct rockchip_pin_ctrl *ctrl = info->ctrl;
436 void __iomem *reg; 483 struct regmap *regmap;
484 int reg, ret;
437 u8 bit; 485 u8 bit;
438 u32 data; 486 u32 data;
439 487
@@ -441,15 +489,19 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
441 if (ctrl->type == RK3066B) 489 if (ctrl->type == RK3066B)
442 return PIN_CONFIG_BIAS_DISABLE; 490 return PIN_CONFIG_BIAS_DISABLE;
443 491
444 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit); 492 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
493
494 ret = regmap_read(regmap, reg, &data);
495 if (ret)
496 return ret;
445 497
446 switch (ctrl->type) { 498 switch (ctrl->type) {
447 case RK2928: 499 case RK2928:
448 return !(readl_relaxed(reg) & BIT(bit)) 500 return !(data & BIT(bit))
449 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 501 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
450 : PIN_CONFIG_BIAS_DISABLE; 502 : PIN_CONFIG_BIAS_DISABLE;
451 case RK3188: 503 case RK3188:
452 data = readl_relaxed(reg) >> bit; 504 data >>= bit;
453 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 505 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
454 506
455 switch (data) { 507 switch (data) {
@@ -476,7 +528,8 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
476{ 528{
477 struct rockchip_pinctrl *info = bank->drvdata; 529 struct rockchip_pinctrl *info = bank->drvdata;
478 struct rockchip_pin_ctrl *ctrl = info->ctrl; 530 struct rockchip_pin_ctrl *ctrl = info->ctrl;
479 void __iomem *reg; 531 struct regmap *regmap;
532 int reg, ret;
480 unsigned long flags; 533 unsigned long flags;
481 u8 bit; 534 u8 bit;
482 u32 data; 535 u32 data;
@@ -488,7 +541,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
488 if (ctrl->type == RK3066B) 541 if (ctrl->type == RK3066B)
489 return pull ? -EINVAL : 0; 542 return pull ? -EINVAL : 0;
490 543
491 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit); 544 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
492 545
493 switch (ctrl->type) { 546 switch (ctrl->type) {
494 case RK2928: 547 case RK2928:
@@ -497,7 +550,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
497 data = BIT(bit + 16); 550 data = BIT(bit + 16);
498 if (pull == PIN_CONFIG_BIAS_DISABLE) 551 if (pull == PIN_CONFIG_BIAS_DISABLE)
499 data |= BIT(bit); 552 data |= BIT(bit);
500 writel(data, reg); 553 ret = regmap_write(regmap, reg, data);
501 554
502 spin_unlock_irqrestore(&bank->slock, flags); 555 spin_unlock_irqrestore(&bank->slock, flags);
503 break; 556 break;
@@ -526,7 +579,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
526 return -EINVAL; 579 return -EINVAL;
527 } 580 }
528 581
529 writel(data, reg); 582 ret = regmap_write(regmap, reg, data);
530 583
531 spin_unlock_irqrestore(&bank->slock, flags); 584 spin_unlock_irqrestore(&bank->slock, flags);
532 break; 585 break;
@@ -535,7 +588,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
535 return -EINVAL; 588 return -EINVAL;
536 } 589 }
537 590
538 return 0; 591 return ret;
539} 592}
540 593
541/* 594/*
@@ -687,6 +740,10 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
687 return false; 740 return false;
688} 741}
689 742
743static int rockchip_gpio_direction_output(struct gpio_chip *gc,
744 unsigned offset, int value);
745static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
746
690/* set the pin config settings for a specified pin */ 747/* set the pin config settings for a specified pin */
691static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 748static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
692 unsigned long *configs, unsigned num_configs) 749 unsigned long *configs, unsigned num_configs)
@@ -724,6 +781,13 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
724 if (rc) 781 if (rc)
725 return rc; 782 return rc;
726 break; 783 break;
784 case PIN_CONFIG_OUTPUT:
785 rc = rockchip_gpio_direction_output(&bank->gpio_chip,
786 pin - bank->pin_base,
787 arg);
788 if (rc)
789 return rc;
790 break;
727 default: 791 default:
728 return -ENOTSUPP; 792 return -ENOTSUPP;
729 break; 793 break;
@@ -740,13 +804,15 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
740 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 804 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
741 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 805 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
742 enum pin_config_param param = pinconf_to_config_param(*config); 806 enum pin_config_param param = pinconf_to_config_param(*config);
807 u16 arg;
808 int rc;
743 809
744 switch (param) { 810 switch (param) {
745 case PIN_CONFIG_BIAS_DISABLE: 811 case PIN_CONFIG_BIAS_DISABLE:
746 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 812 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
747 return -EINVAL; 813 return -EINVAL;
748 814
749 *config = 0; 815 arg = 0;
750 break; 816 break;
751 case PIN_CONFIG_BIAS_PULL_UP: 817 case PIN_CONFIG_BIAS_PULL_UP:
752 case PIN_CONFIG_BIAS_PULL_DOWN: 818 case PIN_CONFIG_BIAS_PULL_DOWN:
@@ -758,13 +824,26 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
758 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 824 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
759 return -EINVAL; 825 return -EINVAL;
760 826
761 *config = 1; 827 arg = 1;
828 break;
829 case PIN_CONFIG_OUTPUT:
830 rc = rockchip_get_mux(bank, pin - bank->pin_base);
831 if (rc != RK_FUNC_GPIO)
832 return -EINVAL;
833
834 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
835 if (rc < 0)
836 return rc;
837
838 arg = rc ? 1 : 0;
762 break; 839 break;
763 default: 840 default:
764 return -ENOTSUPP; 841 return -ENOTSUPP;
765 break; 842 break;
766 } 843 }
767 844
845 *config = pinconf_to_config_packed(param, arg);
846
768 return 0; 847 return 0;
769} 848}
770 849
@@ -1365,16 +1444,17 @@ static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1365} 1444}
1366 1445
1367static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 1446static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1368 struct device *dev) 1447 struct rockchip_pinctrl *info)
1369{ 1448{
1370 struct resource res; 1449 struct resource res;
1450 void __iomem *base;
1371 1451
1372 if (of_address_to_resource(bank->of_node, 0, &res)) { 1452 if (of_address_to_resource(bank->of_node, 0, &res)) {
1373 dev_err(dev, "cannot find IO resource for bank\n"); 1453 dev_err(info->dev, "cannot find IO resource for bank\n");
1374 return -ENOENT; 1454 return -ENOENT;
1375 } 1455 }
1376 1456
1377 bank->reg_base = devm_ioremap_resource(dev, &res); 1457 bank->reg_base = devm_ioremap_resource(info->dev, &res);
1378 if (IS_ERR(bank->reg_base)) 1458 if (IS_ERR(bank->reg_base))
1379 return PTR_ERR(bank->reg_base); 1459 return PTR_ERR(bank->reg_base);
1380 1460
@@ -1384,16 +1464,30 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1384 */ 1464 */
1385 if (of_device_is_compatible(bank->of_node, 1465 if (of_device_is_compatible(bank->of_node,
1386 "rockchip,rk3188-gpio-bank0")) { 1466 "rockchip,rk3188-gpio-bank0")) {
1467 struct device_node *node;
1468
1387 bank->bank_type = RK3188_BANK0; 1469 bank->bank_type = RK3188_BANK0;
1388 1470
1389 if (of_address_to_resource(bank->of_node, 1, &res)) { 1471 node = of_parse_phandle(bank->of_node->parent,
1390 dev_err(dev, "cannot find IO resource for bank\n"); 1472 "rockchip,pmu", 0);
1391 return -ENOENT; 1473 if (!node) {
1474 if (of_address_to_resource(bank->of_node, 1, &res)) {
1475 dev_err(info->dev, "cannot find IO resource for bank\n");
1476 return -ENOENT;
1477 }
1478
1479 base = devm_ioremap_resource(info->dev, &res);
1480 if (IS_ERR(base))
1481 return PTR_ERR(base);
1482 rockchip_regmap_config.max_register =
1483 resource_size(&res) - 4;
1484 rockchip_regmap_config.name =
1485 "rockchip,rk3188-gpio-bank0-pull";
1486 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1487 base,
1488 &rockchip_regmap_config);
1392 } 1489 }
1393 1490
1394 bank->reg_pull = devm_ioremap_resource(dev, &res);
1395 if (IS_ERR(bank->reg_pull))
1396 return PTR_ERR(bank->reg_pull);
1397 } else { 1491 } else {
1398 bank->bank_type = COMMON_BANK; 1492 bank->bank_type = COMMON_BANK;
1399 } 1493 }
@@ -1433,7 +1527,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1433 if (!strcmp(bank->name, np->name)) { 1527 if (!strcmp(bank->name, np->name)) {
1434 bank->of_node = np; 1528 bank->of_node = np;
1435 1529
1436 if (!rockchip_get_bank_data(bank, &pdev->dev)) 1530 if (!rockchip_get_bank_data(bank, d))
1437 bank->valid = true; 1531 bank->valid = true;
1438 1532
1439 break; 1533 break;
@@ -1457,7 +1551,9 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
1457 struct rockchip_pinctrl *info; 1551 struct rockchip_pinctrl *info;
1458 struct device *dev = &pdev->dev; 1552 struct device *dev = &pdev->dev;
1459 struct rockchip_pin_ctrl *ctrl; 1553 struct rockchip_pin_ctrl *ctrl;
1554 struct device_node *np = pdev->dev.of_node, *node;
1460 struct resource *res; 1555 struct resource *res;
1556 void __iomem *base;
1461 int ret; 1557 int ret;
1462 1558
1463 if (!dev->of_node) { 1559 if (!dev->of_node) {
@@ -1469,25 +1565,56 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
1469 if (!info) 1565 if (!info)
1470 return -ENOMEM; 1566 return -ENOMEM;
1471 1567
1568 info->dev = dev;
1569
1472 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 1570 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1473 if (!ctrl) { 1571 if (!ctrl) {
1474 dev_err(dev, "driver data not available\n"); 1572 dev_err(dev, "driver data not available\n");
1475 return -EINVAL; 1573 return -EINVAL;
1476 } 1574 }
1477 info->ctrl = ctrl; 1575 info->ctrl = ctrl;
1478 info->dev = dev;
1479 1576
1480 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1577 node = of_parse_phandle(np, "rockchip,grf", 0);
1481 info->reg_base = devm_ioremap_resource(&pdev->dev, res); 1578 if (node) {
1482 if (IS_ERR(info->reg_base)) 1579 info->regmap_base = syscon_node_to_regmap(node);
1483 return PTR_ERR(info->reg_base); 1580 if (IS_ERR(info->regmap_base))
1484 1581 return PTR_ERR(info->regmap_base);
1485 /* The RK3188 has its pull registers in a separate place */ 1582 } else {
1486 if (ctrl->type == RK3188) { 1583 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1487 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1584 base = devm_ioremap_resource(&pdev->dev, res);
1488 info->reg_pull = devm_ioremap_resource(&pdev->dev, res); 1585 if (IS_ERR(base))
1489 if (IS_ERR(info->reg_pull)) 1586 return PTR_ERR(base);
1490 return PTR_ERR(info->reg_pull); 1587
1588 rockchip_regmap_config.max_register = resource_size(res) - 4;
1589 rockchip_regmap_config.name = "rockchip,pinctrl";
1590 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1591 &rockchip_regmap_config);
1592
1593 /* to check for the old dt-bindings */
1594 info->reg_size = resource_size(res);
1595
1596 /* Honor the old binding, with pull registers as 2nd resource */
1597 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1598 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1599 base = devm_ioremap_resource(&pdev->dev, res);
1600 if (IS_ERR(base))
1601 return PTR_ERR(base);
1602
1603 rockchip_regmap_config.max_register =
1604 resource_size(res) - 4;
1605 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1606 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
1607 base,
1608 &rockchip_regmap_config);
1609 }
1610 }
1611
1612 /* try to find the optional reference to the pmu syscon */
1613 node = of_parse_phandle(np, "rockchip,pmu", 0);
1614 if (node) {
1615 info->regmap_pmu = syscon_node_to_regmap(node);
1616 if (IS_ERR(info->regmap_pmu))
1617 return PTR_ERR(info->regmap_pmu);
1491 } 1618 }
1492 1619
1493 ret = rockchip_gpiolib_register(pdev, info); 1620 ret = rockchip_gpiolib_register(pdev, info);
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 0324d4cb19b2..3e61d0f8f146 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1114,6 +1114,8 @@ static struct syscore_ops samsung_pinctrl_syscore_ops = {
1114 1114
1115static const struct of_device_id samsung_pinctrl_dt_match[] = { 1115static const struct of_device_id samsung_pinctrl_dt_match[] = {
1116#ifdef CONFIG_PINCTRL_EXYNOS 1116#ifdef CONFIG_PINCTRL_EXYNOS
1117 { .compatible = "samsung,exynos3250-pinctrl",
1118 .data = (void *)exynos3250_pin_ctrl },
1117 { .compatible = "samsung,exynos4210-pinctrl", 1119 { .compatible = "samsung,exynos4210-pinctrl",
1118 .data = (void *)exynos4210_pin_ctrl }, 1120 .data = (void *)exynos4210_pin_ctrl },
1119 { .compatible = "samsung,exynos4x12-pinctrl", 1121 { .compatible = "samsung,exynos4x12-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index bab9c2122556..b3e41fa5798b 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -251,6 +251,7 @@ struct samsung_pmx_func {
251}; 251};
252 252
253/* list of all exported SoC specific data */ 253/* list of all exported SoC specific data */
254extern struct samsung_pin_ctrl exynos3250_pin_ctrl[];
254extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; 255extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
255extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; 256extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
256extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; 257extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index bd725b0a4341..1bd6363bc95e 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -13,10 +13,6 @@
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/irqdesc.h>
18#include <linux/irqdomain.h>
19#include <linux/irqchip/chained_irq.h>
20#include <linux/of.h> 16#include <linux/of.h>
21#include <linux/of_irq.h> 17#include <linux/of_irq.h>
22#include <linux/of_gpio.h> 18#include <linux/of_gpio.h>
@@ -242,13 +238,13 @@ struct st_pio_control {
242}; 238};
243 239
244struct st_pctl_data { 240struct st_pctl_data {
245 enum st_retime_style rt_style; 241 const enum st_retime_style rt_style;
246 unsigned int *input_delays; 242 const unsigned int *input_delays;
247 int ninput_delays; 243 const int ninput_delays;
248 unsigned int *output_delays; 244 const unsigned int *output_delays;
249 int noutput_delays; 245 const int noutput_delays;
250 /* register offset information */ 246 /* register offset information */
251 int alt, oe, pu, od, rt; 247 const int alt, oe, pu, od, rt;
252}; 248};
253 249
254struct st_pinconf { 250struct st_pinconf {
@@ -321,7 +317,6 @@ struct st_gpio_bank {
321 struct pinctrl_gpio_range range; 317 struct pinctrl_gpio_range range;
322 void __iomem *base; 318 void __iomem *base;
323 struct st_pio_control pc; 319 struct st_pio_control pc;
324 struct irq_domain *domain;
325 unsigned long irq_edge_conf; 320 unsigned long irq_edge_conf;
326 spinlock_t lock; 321 spinlock_t lock;
327}; 322};
@@ -342,15 +337,15 @@ struct st_pinctrl {
342 337
343/* SOC specific data */ 338/* SOC specific data */
344/* STiH415 data */ 339/* STiH415 data */
345static unsigned int stih415_input_delays[] = {0, 500, 1000, 1500}; 340static const unsigned int stih415_input_delays[] = {0, 500, 1000, 1500};
346static unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000}; 341static const unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000};
347 342
348#define STIH415_PCTRL_COMMON_DATA \ 343#define STIH415_PCTRL_COMMON_DATA \
349 .rt_style = st_retime_style_packed, \ 344 .rt_style = st_retime_style_packed, \
350 .input_delays = stih415_input_delays, \ 345 .input_delays = stih415_input_delays, \
351 .ninput_delays = 4, \ 346 .ninput_delays = ARRAY_SIZE(stih415_input_delays), \
352 .output_delays = stih415_output_delays, \ 347 .output_delays = stih415_output_delays, \
353 .noutput_delays = 4 348 .noutput_delays = ARRAY_SIZE(stih415_output_delays)
354 349
355static const struct st_pctl_data stih415_sbc_data = { 350static const struct st_pctl_data stih415_sbc_data = {
356 STIH415_PCTRL_COMMON_DATA, 351 STIH415_PCTRL_COMMON_DATA,
@@ -378,8 +373,8 @@ static const struct st_pctl_data stih415_right_data = {
378}; 373};
379 374
380/* STiH416 data */ 375/* STiH416 data */
381static unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250, 1500, 376static const unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250,
382 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; 377 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
383 378
384static const struct st_pctl_data stih416_data = { 379static const struct st_pctl_data stih416_data = {
385 .rt_style = st_retime_style_dedicated, 380 .rt_style = st_retime_style_dedicated,
@@ -468,7 +463,7 @@ static void st_pctl_set_function(struct st_pio_control *pc,
468static unsigned long st_pinconf_delay_to_bit(unsigned int delay, 463static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
469 const struct st_pctl_data *data, unsigned long config) 464 const struct st_pctl_data *data, unsigned long config)
470{ 465{
471 unsigned int *delay_times; 466 const unsigned int *delay_times;
472 int num_delay_times, i, closest_index = -1; 467 int num_delay_times, i, closest_index = -1;
473 unsigned int closest_divergence = UINT_MAX; 468 unsigned int closest_divergence = UINT_MAX;
474 469
@@ -501,7 +496,7 @@ static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
501static unsigned long st_pinconf_bit_to_delay(unsigned int index, 496static unsigned long st_pinconf_bit_to_delay(unsigned int index,
502 const struct st_pctl_data *data, unsigned long output) 497 const struct st_pctl_data *data, unsigned long output)
503{ 498{
504 unsigned int *delay_times; 499 const unsigned int *delay_times;
505 int num_delay_times; 500 int num_delay_times;
506 501
507 if (output) { 502 if (output) {
@@ -1285,58 +1280,26 @@ static int st_pctl_parse_functions(struct device_node *np,
1285 return 0; 1280 return 0;
1286} 1281}
1287 1282
1288static int st_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1289{
1290 struct st_gpio_bank *bank = gpio_chip_to_bank(chip);
1291 int irq = -ENXIO;
1292
1293 if (offset < chip->ngpio)
1294 irq = irq_find_mapping(bank->domain, offset);
1295
1296 dev_info(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1297 chip->label, offset + chip->base, irq);
1298 return irq;
1299}
1300
1301static void st_gpio_irq_mask(struct irq_data *d) 1283static void st_gpio_irq_mask(struct irq_data *d)
1302{ 1284{
1303 struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); 1285 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1286 struct st_gpio_bank *bank = gpio_chip_to_bank(gc);
1304 1287
1305 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); 1288 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
1306} 1289}
1307 1290
1308static void st_gpio_irq_unmask(struct irq_data *d) 1291static void st_gpio_irq_unmask(struct irq_data *d)
1309{ 1292{
1310 struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); 1293 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1294 struct st_gpio_bank *bank = gpio_chip_to_bank(gc);
1311 1295
1312 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); 1296 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
1313} 1297}
1314 1298
1315static unsigned int st_gpio_irq_startup(struct irq_data *d)
1316{
1317 struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1318
1319 if (gpio_lock_as_irq(&bank->gpio_chip, d->hwirq))
1320 dev_err(bank->gpio_chip.dev,
1321 "unable to lock HW IRQ %lu for IRQ\n",
1322 d->hwirq);
1323
1324 st_gpio_irq_unmask(d);
1325
1326 return 0;
1327}
1328
1329static void st_gpio_irq_shutdown(struct irq_data *d)
1330{
1331 struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1332
1333 st_gpio_irq_mask(d);
1334 gpio_unlock_as_irq(&bank->gpio_chip, d->hwirq);
1335}
1336
1337static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) 1299static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
1338{ 1300{
1339 struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d); 1301 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1302 struct st_gpio_bank *bank = gpio_chip_to_bank(gc);
1340 unsigned long flags; 1303 unsigned long flags;
1341 int comp, pin = d->hwirq; 1304 int comp, pin = d->hwirq;
1342 u32 val; 1305 u32 val;
@@ -1440,7 +1403,7 @@ static void __gpio_irq_handler(struct st_gpio_bank *bank)
1440 continue; 1403 continue;
1441 } 1404 }
1442 1405
1443 generic_handle_irq(irq_find_mapping(bank->domain, n)); 1406 generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n));
1444 } 1407 }
1445 } 1408 }
1446} 1409}
@@ -1449,7 +1412,8 @@ static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1449{ 1412{
1450 /* interrupt dedicated per bank */ 1413 /* interrupt dedicated per bank */
1451 struct irq_chip *chip = irq_get_chip(irq); 1414 struct irq_chip *chip = irq_get_chip(irq);
1452 struct st_gpio_bank *bank = irq_get_handler_data(irq); 1415 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1416 struct st_gpio_bank *bank = gpio_chip_to_bank(gc);
1453 1417
1454 chained_irq_enter(chip, desc); 1418 chained_irq_enter(chip, desc);
1455 __gpio_irq_handler(bank); 1419 __gpio_irq_handler(bank);
@@ -1483,7 +1447,6 @@ static struct gpio_chip st_gpio_template = {
1483 .ngpio = ST_GPIO_PINS_PER_BANK, 1447 .ngpio = ST_GPIO_PINS_PER_BANK,
1484 .of_gpio_n_cells = 1, 1448 .of_gpio_n_cells = 1,
1485 .of_xlate = st_gpio_xlate, 1449 .of_xlate = st_gpio_xlate,
1486 .to_irq = st_gpio_to_irq,
1487}; 1450};
1488 1451
1489static struct irq_chip st_gpio_irqchip = { 1452static struct irq_chip st_gpio_irqchip = {
@@ -1491,26 +1454,6 @@ static struct irq_chip st_gpio_irqchip = {
1491 .irq_mask = st_gpio_irq_mask, 1454 .irq_mask = st_gpio_irq_mask,
1492 .irq_unmask = st_gpio_irq_unmask, 1455 .irq_unmask = st_gpio_irq_unmask,
1493 .irq_set_type = st_gpio_irq_set_type, 1456 .irq_set_type = st_gpio_irq_set_type,
1494 .irq_startup = st_gpio_irq_startup,
1495 .irq_shutdown = st_gpio_irq_shutdown,
1496};
1497
1498static int st_gpio_irq_domain_map(struct irq_domain *h,
1499 unsigned int virq, irq_hw_number_t hw)
1500{
1501 struct st_gpio_bank *bank = h->host_data;
1502
1503 irq_set_chip(virq, &st_gpio_irqchip);
1504 irq_set_handler(virq, handle_simple_irq);
1505 set_irq_flags(virq, IRQF_VALID);
1506 irq_set_chip_data(virq, bank);
1507
1508 return 0;
1509}
1510
1511static struct irq_domain_ops st_gpio_irq_ops = {
1512 .map = st_gpio_irq_domain_map,
1513 .xlate = irq_domain_xlate_twocell,
1514}; 1457};
1515 1458
1516static int st_gpiolib_register_bank(struct st_pinctrl *info, 1459static int st_gpiolib_register_bank(struct st_pinctrl *info,
@@ -1521,7 +1464,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
1521 struct device *dev = info->dev; 1464 struct device *dev = info->dev;
1522 int bank_num = of_alias_get_id(np, "gpio"); 1465 int bank_num = of_alias_get_id(np, "gpio");
1523 struct resource res, irq_res; 1466 struct resource res, irq_res;
1524 int gpio_irq = 0, err, i; 1467 int gpio_irq = 0, err;
1525 1468
1526 if (of_address_to_resource(np, 0, &res)) 1469 if (of_address_to_resource(np, 0, &res))
1527 return -ENODEV; 1470 return -ENODEV;
@@ -1534,6 +1477,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
1534 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; 1477 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1535 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; 1478 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1536 bank->gpio_chip.of_node = np; 1479 bank->gpio_chip.of_node = np;
1480 bank->gpio_chip.dev = dev;
1537 spin_lock_init(&bank->lock); 1481 spin_lock_init(&bank->lock);
1538 1482
1539 of_property_read_string(np, "st,bank-name", &range->name); 1483 of_property_read_string(np, "st,bank-name", &range->name);
@@ -1571,26 +1515,18 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
1571 1515
1572 if (of_irq_to_resource(np, 0, &irq_res)) { 1516 if (of_irq_to_resource(np, 0, &irq_res)) {
1573 gpio_irq = irq_res.start; 1517 gpio_irq = irq_res.start;
1574 irq_set_chained_handler(gpio_irq, st_gpio_irq_handler); 1518 gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip,
1575 irq_set_handler_data(gpio_irq, bank); 1519 gpio_irq, st_gpio_irq_handler);
1576 } 1520 }
1577 1521
1578 if (info->irqmux_base > 0 || gpio_irq > 0) { 1522 if (info->irqmux_base > 0 || gpio_irq > 0) {
1579 /* Setup IRQ domain */ 1523 err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip,
1580 bank->domain = irq_domain_add_linear(np, 1524 0, handle_simple_irq,
1581 ST_GPIO_PINS_PER_BANK, 1525 IRQ_TYPE_LEVEL_LOW);
1582 &st_gpio_irq_ops, bank); 1526 if (err) {
1583 if (!bank->domain) { 1527 dev_info(dev, "could not add irqchip\n");
1584 dev_err(dev, "Failed to add irq domain for %s\n", 1528 return err;
1585 np->full_name);
1586 } else {
1587 for (i = 0; i < ST_GPIO_PINS_PER_BANK; i++) {
1588 if (irq_create_mapping(bank->domain, i) < 0)
1589 dev_err(dev,
1590 "Failed to map IRQ %i\n", i);
1591 }
1592 } 1529 }
1593
1594 } else { 1530 } else {
1595 dev_info(dev, "No IRQ support for %s bank\n", np->full_name); 1531 dev_info(dev, "No IRQ support for %s bank\n", np->full_name);
1596 } 1532 }
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
deleted file mode 100644
index 3d6066988a72..000000000000
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ /dev/null
@@ -1,3863 +0,0 @@
1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_SUNXI_PINS_H
14#define __PINCTRL_SUNXI_PINS_H
15
16#include "pinctrl-sunxi.h"
17
18static const struct sunxi_desc_pin sun4i_a10_pins[] = {
19 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
20 SUNXI_FUNCTION(0x0, "gpio_in"),
21 SUNXI_FUNCTION(0x1, "gpio_out"),
22 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
23 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
24 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
29 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
30 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
35 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
36 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
41 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
42 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
47 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
48 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
49 SUNXI_FUNCTION(0x0, "gpio_in"),
50 SUNXI_FUNCTION(0x1, "gpio_out"),
51 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
52 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
57 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
62 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
63 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
64 SUNXI_FUNCTION(0x0, "gpio_in"),
65 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
67 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
72 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
77 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
82 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
87 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
88 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
93 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
94 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
99 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
100 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
105 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
106 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
107 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
108 SUNXI_FUNCTION(0x0, "gpio_in"),
109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
111 SUNXI_FUNCTION(0x3, "can"), /* TX */
112 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
117 SUNXI_FUNCTION(0x3, "can"), /* RX */
118 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
119 /* Hole */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
144 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
149 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
154 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
159 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
176 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
185 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
186 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
187 SUNXI_FUNCTION(0x0, "gpio_in"),
188 SUNXI_FUNCTION(0x1, "gpio_out"),
189 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
190 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
195 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
200 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
221 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
226 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
227 /* Hole */
228 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
229 SUNXI_FUNCTION(0x0, "gpio_in"),
230 SUNXI_FUNCTION(0x1, "gpio_out"),
231 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
232 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
237 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
242 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
259 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
264 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
269 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
274 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
279 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
284 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
302 SUNXI_FUNCTION(0x0, "gpio_in"),
303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
317 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
322 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
327 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
332 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
334 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out"),
336 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
341 /* Hole */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
346 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
351 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
356 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
361 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
366 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
371 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
376 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
378 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out"),
380 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
381 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
382 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
383 SUNXI_FUNCTION(0x0, "gpio_in"),
384 SUNXI_FUNCTION(0x1, "gpio_out"),
385 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
386 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
391 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
396 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
401 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
406 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
411 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
416 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
421 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
426 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
431 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
436 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
441 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
446 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
447 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
451 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
456 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
461 SUNXI_FUNCTION(0x3, "sim")), /* DET */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
466 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
471 SUNXI_FUNCTION(0x3, "sim")), /* RST */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
476 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
481 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
482 /* Hole */
483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
484 SUNXI_FUNCTION(0x0, "gpio_in"),
485 SUNXI_FUNCTION(0x1, "gpio_out"),
486 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
487 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out"),
491 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
492 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
497 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
498 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
499 SUNXI_FUNCTION(0x0, "gpio_in"),
500 SUNXI_FUNCTION(0x1, "gpio_out"),
501 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
502 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out"),
506 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
507 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
512 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
513 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
515 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
518 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
520 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
523 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
528 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
533 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
538 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
543 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
544 /* Hole */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
549 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
554 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
559 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
560 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
561 SUNXI_FUNCTION(0x0, "gpio_in"),
562 SUNXI_FUNCTION(0x1, "gpio_out"),
563 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
564 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
566 SUNXI_FUNCTION(0x0, "gpio_in"),
567 SUNXI_FUNCTION(0x1, "gpio_out"),
568 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
569 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
571 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out"),
573 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
574 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
575 /* Hole */
576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
577 SUNXI_FUNCTION(0x0, "gpio_in"),
578 SUNXI_FUNCTION(0x1, "gpio_out"),
579 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
580 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
581 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
582 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
583 SUNXI_FUNCTION(0x0, "gpio_in"),
584 SUNXI_FUNCTION(0x1, "gpio_out"),
585 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
586 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
587 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
589 SUNXI_FUNCTION(0x0, "gpio_in"),
590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
592 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
593 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
595 SUNXI_FUNCTION(0x0, "gpio_in"),
596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
598 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
599 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
601 SUNXI_FUNCTION(0x0, "gpio_in"),
602 SUNXI_FUNCTION(0x1, "gpio_out"),
603 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
604 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
605 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
606 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
607 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
608 SUNXI_FUNCTION(0x0, "gpio_in"),
609 SUNXI_FUNCTION(0x1, "gpio_out"),
610 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
611 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
612 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
613 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
618 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
619 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
620 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
621 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
625 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
626 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
627 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
632 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
633 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
634 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
635 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
636 SUNXI_FUNCTION(0x0, "gpio_in"),
637 SUNXI_FUNCTION(0x1, "gpio_out"),
638 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
639 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
640 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
641 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
642 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
643 SUNXI_FUNCTION(0x0, "gpio_in"),
644 SUNXI_FUNCTION(0x1, "gpio_out"),
645 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
646 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
647 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
648 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
653 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
654 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
655 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
656 /* Hole */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
658 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
661 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
662 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
663 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
664 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
666 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
669 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
670 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
671 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
672 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
674 SUNXI_FUNCTION(0x0, "gpio_in"),
675 SUNXI_FUNCTION(0x1, "gpio_out"),
676 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
677 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
678 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
679 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
680 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
682 SUNXI_FUNCTION(0x0, "gpio_in"),
683 SUNXI_FUNCTION(0x1, "gpio_out"),
684 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
685 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
686 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
687 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
688 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
689 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
690 SUNXI_FUNCTION(0x0, "gpio_in"),
691 SUNXI_FUNCTION(0x1, "gpio_out"),
692 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
693 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
694 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
695 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
701 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
702 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
703 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
704 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
705 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
706 SUNXI_FUNCTION(0x0, "gpio_in"),
707 SUNXI_FUNCTION(0x1, "gpio_out"),
708 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
709 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
710 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
711 SUNXI_FUNCTION(0x5, "ms"), /* BS */
712 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
713 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
714 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
715 SUNXI_FUNCTION(0x0, "gpio_in"),
716 SUNXI_FUNCTION(0x1, "gpio_out"),
717 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
718 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
719 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
720 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
721 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
722 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
724 SUNXI_FUNCTION(0x0, "gpio_in"),
725 SUNXI_FUNCTION(0x1, "gpio_out"),
726 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
727 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
728 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
729 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
730 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
731 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
736 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
737 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
738 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
739 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
740 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out"),
744 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
745 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
746 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
747 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
748 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
749 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
751 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out"),
753 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
754 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
755 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
756 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
757 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
760 SUNXI_FUNCTION(0x0, "gpio_in"),
761 SUNXI_FUNCTION(0x1, "gpio_out"),
762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
763 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
765 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
767 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
768 SUNXI_FUNCTION(0x0, "gpio_in"),
769 SUNXI_FUNCTION(0x1, "gpio_out"),
770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
771 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
772 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
773 SUNXI_FUNCTION(0x5, "sim"), /* RST */
774 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
775 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
777 SUNXI_FUNCTION(0x0, "gpio_in"),
778 SUNXI_FUNCTION(0x1, "gpio_out"),
779 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
780 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
781 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
782 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
783 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
784 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
786 SUNXI_FUNCTION(0x0, "gpio_in"),
787 SUNXI_FUNCTION(0x1, "gpio_out"),
788 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
789 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
790 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
791 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
792 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
793 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
794 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
795 SUNXI_FUNCTION(0x0, "gpio_in"),
796 SUNXI_FUNCTION(0x1, "gpio_out"),
797 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
798 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
799 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
800 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
801 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
803 SUNXI_FUNCTION(0x0, "gpio_in"),
804 SUNXI_FUNCTION(0x1, "gpio_out"),
805 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
806 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
807 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
808 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
809 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
810 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out"),
814 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
815 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
816 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
817 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
818 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
819 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
821 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out"),
823 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
824 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
825 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
826 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
827 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
828 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
830 SUNXI_FUNCTION(0x0, "gpio_in"),
831 SUNXI_FUNCTION(0x1, "gpio_out"),
832 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
833 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
834 SUNXI_FUNCTION(0x4, "can"), /* TX */
835 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
836 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
837 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
838 SUNXI_FUNCTION(0x0, "gpio_in"),
839 SUNXI_FUNCTION(0x1, "gpio_out"),
840 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
841 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
842 SUNXI_FUNCTION(0x4, "can"), /* RX */
843 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
844 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
846 SUNXI_FUNCTION(0x0, "gpio_in"),
847 SUNXI_FUNCTION(0x1, "gpio_out"),
848 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
849 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
850 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
851 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
852 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
853 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
854 SUNXI_FUNCTION(0x0, "gpio_in"),
855 SUNXI_FUNCTION(0x1, "gpio_out"),
856 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
857 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
858 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
859 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
860 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
861 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
862 SUNXI_FUNCTION(0x0, "gpio_in"),
863 SUNXI_FUNCTION(0x1, "gpio_out"),
864 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
865 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
866 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
867 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
868 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
869 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
870 SUNXI_FUNCTION(0x0, "gpio_in"),
871 SUNXI_FUNCTION(0x1, "gpio_out"),
872 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
873 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
874 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
875 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
876 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
878 SUNXI_FUNCTION(0x0, "gpio_in"),
879 SUNXI_FUNCTION(0x1, "gpio_out"),
880 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
881 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
882 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
883 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
884 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
886 SUNXI_FUNCTION(0x0, "gpio_in"),
887 SUNXI_FUNCTION(0x1, "gpio_out"),
888 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
889 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
890 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
891 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
892 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
893 /* Hole */
894 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
895 SUNXI_FUNCTION(0x0, "gpio_in"),
896 SUNXI_FUNCTION(0x1, "gpio_out")),
897 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
898 SUNXI_FUNCTION(0x0, "gpio_in"),
899 SUNXI_FUNCTION(0x1, "gpio_out")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out")),
903 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out"),
906 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
907 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
908 SUNXI_FUNCTION(0x0, "gpio_in"),
909 SUNXI_FUNCTION(0x1, "gpio_out"),
910 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
912 SUNXI_FUNCTION(0x0, "gpio_in"),
913 SUNXI_FUNCTION(0x1, "gpio_out"),
914 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
916 SUNXI_FUNCTION(0x0, "gpio_in"),
917 SUNXI_FUNCTION(0x1, "gpio_out"),
918 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
919 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
920 SUNXI_FUNCTION(0x0, "gpio_in"),
921 SUNXI_FUNCTION(0x1, "gpio_out"),
922 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
924 SUNXI_FUNCTION(0x0, "gpio_in"),
925 SUNXI_FUNCTION(0x1, "gpio_out"),
926 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
927 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
928 SUNXI_FUNCTION(0x0, "gpio_in"),
929 SUNXI_FUNCTION(0x1, "gpio_out"),
930 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
932 SUNXI_FUNCTION(0x0, "gpio_in"),
933 SUNXI_FUNCTION(0x1, "gpio_out"),
934 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
935 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
936 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
937 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
938 SUNXI_FUNCTION(0x0, "gpio_in"),
939 SUNXI_FUNCTION(0x1, "gpio_out"),
940 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
941 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
942 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
943 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
944 SUNXI_FUNCTION(0x0, "gpio_in"),
945 SUNXI_FUNCTION(0x1, "gpio_out"),
946 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
947 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
948 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
949 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
950 SUNXI_FUNCTION(0x0, "gpio_in"),
951 SUNXI_FUNCTION(0x1, "gpio_out"),
952 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
953 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
954 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
955 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
956 SUNXI_FUNCTION(0x0, "gpio_in"),
957 SUNXI_FUNCTION(0x1, "gpio_out"),
958 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
959 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
960 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
961 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
962 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
963 SUNXI_FUNCTION(0x0, "gpio_in"),
964 SUNXI_FUNCTION(0x1, "gpio_out"),
965 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
966 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
967 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
968 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
970 SUNXI_FUNCTION(0x0, "gpio_in"),
971 SUNXI_FUNCTION(0x1, "gpio_out"),
972 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
973 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
974 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
976 SUNXI_FUNCTION(0x0, "gpio_in"),
977 SUNXI_FUNCTION(0x1, "gpio_out"),
978 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
979 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
980 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
981 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
982 SUNXI_FUNCTION(0x0, "gpio_in"),
983 SUNXI_FUNCTION(0x1, "gpio_out"),
984 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
985 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
986 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
987 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
988 SUNXI_FUNCTION(0x0, "gpio_in"),
989 SUNXI_FUNCTION(0x1, "gpio_out"),
990 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
991 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
992 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
994 SUNXI_FUNCTION(0x0, "gpio_in"),
995 SUNXI_FUNCTION(0x1, "gpio_out"),
996 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
997 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
998 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
999 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
1000 SUNXI_FUNCTION(0x0, "gpio_in"),
1001 SUNXI_FUNCTION(0x1, "gpio_out"),
1002 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1003 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1004 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1005};
1006
1007static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
1008 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
1009 SUNXI_FUNCTION(0x0, "gpio_in"),
1010 SUNXI_FUNCTION(0x1, "gpio_out"),
1011 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
1012 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
1013 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
1014 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
1015 SUNXI_FUNCTION(0x0, "gpio_in"),
1016 SUNXI_FUNCTION(0x1, "gpio_out"),
1017 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
1018 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
1019 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
1020 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
1021 SUNXI_FUNCTION(0x0, "gpio_in"),
1022 SUNXI_FUNCTION(0x1, "gpio_out"),
1023 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
1024 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
1025 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
1026 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
1027 SUNXI_FUNCTION(0x0, "gpio_in"),
1028 SUNXI_FUNCTION(0x1, "gpio_out"),
1029 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
1030 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
1031 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
1032 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
1033 SUNXI_FUNCTION(0x0, "gpio_in"),
1034 SUNXI_FUNCTION(0x1, "gpio_out"),
1035 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
1036 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
1037 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
1038 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
1039 SUNXI_FUNCTION(0x0, "gpio_in"),
1040 SUNXI_FUNCTION(0x1, "gpio_out"),
1041 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
1042 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
1043 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
1044 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
1045 SUNXI_FUNCTION(0x0, "gpio_in"),
1046 SUNXI_FUNCTION(0x1, "gpio_out"),
1047 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
1048 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
1049 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
1050 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
1051 SUNXI_FUNCTION(0x0, "gpio_in"),
1052 SUNXI_FUNCTION(0x1, "gpio_out"),
1053 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
1054 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
1055 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
1056 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
1057 SUNXI_FUNCTION(0x0, "gpio_in"),
1058 SUNXI_FUNCTION(0x1, "gpio_out"),
1059 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
1060 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
1061 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
1062 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
1063 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
1064 SUNXI_FUNCTION(0x0, "gpio_in"),
1065 SUNXI_FUNCTION(0x1, "gpio_out"),
1066 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
1067 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
1068 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
1069 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
1070 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
1071 SUNXI_FUNCTION(0x0, "gpio_in"),
1072 SUNXI_FUNCTION(0x1, "gpio_out"),
1073 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
1074 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
1075 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
1076 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
1077 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
1078 SUNXI_FUNCTION(0x0, "gpio_in"),
1079 SUNXI_FUNCTION(0x1, "gpio_out"),
1080 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
1081 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
1082 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
1083 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
1084 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
1085 SUNXI_FUNCTION(0x0, "gpio_in"),
1086 SUNXI_FUNCTION(0x1, "gpio_out"),
1087 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
1088 SUNXI_FUNCTION(0x3, "uart1"), /* TX */
1089 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
1090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
1091 SUNXI_FUNCTION(0x0, "gpio_in"),
1092 SUNXI_FUNCTION(0x1, "gpio_out"),
1093 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
1094 SUNXI_FUNCTION(0x3, "uart1"), /* RX */
1095 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
1096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
1097 SUNXI_FUNCTION(0x0, "gpio_in"),
1098 SUNXI_FUNCTION(0x1, "gpio_out"),
1099 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
1100 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
1101 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
1102 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
1103 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
1104 SUNXI_FUNCTION(0x0, "gpio_in"),
1105 SUNXI_FUNCTION(0x1, "gpio_out"),
1106 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
1107 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
1108 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
1109 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
1110 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
1111 SUNXI_FUNCTION(0x0, "gpio_in"),
1112 SUNXI_FUNCTION(0x1, "gpio_out"),
1113 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
1114 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1115 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
1116 SUNXI_FUNCTION(0x0, "gpio_in"),
1117 SUNXI_FUNCTION(0x1, "gpio_out"),
1118 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
1119 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1120 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
1121 /* Hole */
1122 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1123 SUNXI_FUNCTION(0x0, "gpio_in"),
1124 SUNXI_FUNCTION(0x1, "gpio_out"),
1125 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1126 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1127 SUNXI_FUNCTION(0x0, "gpio_in"),
1128 SUNXI_FUNCTION(0x1, "gpio_out"),
1129 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1131 SUNXI_FUNCTION(0x0, "gpio_in"),
1132 SUNXI_FUNCTION(0x1, "gpio_out"),
1133 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
1134 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1135 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1136 SUNXI_FUNCTION(0x0, "gpio_in"),
1137 SUNXI_FUNCTION(0x1, "gpio_out"),
1138 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1139 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1141 SUNXI_FUNCTION(0x0, "gpio_in"),
1142 SUNXI_FUNCTION(0x1, "gpio_out"),
1143 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1144 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
1146 SUNXI_FUNCTION(0x0, "gpio_in"),
1147 SUNXI_FUNCTION(0x1, "gpio_out"),
1148 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
1149 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
1150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
1151 SUNXI_FUNCTION(0x0, "gpio_in"),
1152 SUNXI_FUNCTION(0x1, "gpio_out"),
1153 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
1154 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
1155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
1156 SUNXI_FUNCTION(0x0, "gpio_in"),
1157 SUNXI_FUNCTION(0x1, "gpio_out"),
1158 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
1159 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
1160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
1161 SUNXI_FUNCTION(0x0, "gpio_in"),
1162 SUNXI_FUNCTION(0x1, "gpio_out"),
1163 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
1164 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
1165 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
1166 SUNXI_FUNCTION(0x0, "gpio_in"),
1167 SUNXI_FUNCTION(0x1, "gpio_out"),
1168 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
1169 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
1170 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1171 SUNXI_FUNCTION(0x0, "gpio_in"),
1172 SUNXI_FUNCTION(0x1, "gpio_out"),
1173 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1174 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
1176 SUNXI_FUNCTION(0x0, "gpio_in"),
1177 SUNXI_FUNCTION(0x1, "gpio_out"),
1178 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
1179 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
1180 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
1181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
1182 SUNXI_FUNCTION(0x0, "gpio_in"),
1183 SUNXI_FUNCTION(0x1, "gpio_out"),
1184 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
1185 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
1186 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
1187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
1188 SUNXI_FUNCTION(0x0, "gpio_in"),
1189 SUNXI_FUNCTION(0x1, "gpio_out"),
1190 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
1191 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
1192 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
1193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
1194 SUNXI_FUNCTION(0x0, "gpio_in"),
1195 SUNXI_FUNCTION(0x1, "gpio_out"),
1196 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
1197 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
1198 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
1199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1200 SUNXI_FUNCTION(0x0, "gpio_in"),
1201 SUNXI_FUNCTION(0x1, "gpio_out"),
1202 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1204 SUNXI_FUNCTION(0x0, "gpio_in"),
1205 SUNXI_FUNCTION(0x1, "gpio_out"),
1206 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1208 SUNXI_FUNCTION(0x0, "gpio_in"),
1209 SUNXI_FUNCTION(0x1, "gpio_out"),
1210 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1212 SUNXI_FUNCTION(0x0, "gpio_in"),
1213 SUNXI_FUNCTION(0x1, "gpio_out"),
1214 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1215 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
1216 SUNXI_FUNCTION(0x0, "gpio_in"),
1217 SUNXI_FUNCTION(0x1, "gpio_out"),
1218 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
1219 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
1220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
1221 SUNXI_FUNCTION(0x0, "gpio_in"),
1222 SUNXI_FUNCTION(0x1, "gpio_out"),
1223 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
1224 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
1225 /* Hole */
1226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1227 SUNXI_FUNCTION(0x0, "gpio_in"),
1228 SUNXI_FUNCTION(0x1, "gpio_out"),
1229 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1230 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1231 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1232 SUNXI_FUNCTION(0x0, "gpio_in"),
1233 SUNXI_FUNCTION(0x1, "gpio_out"),
1234 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1235 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1237 SUNXI_FUNCTION(0x0, "gpio_in"),
1238 SUNXI_FUNCTION(0x1, "gpio_out"),
1239 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1240 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
1241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1242 SUNXI_FUNCTION(0x0, "gpio_in"),
1243 SUNXI_FUNCTION(0x1, "gpio_out"),
1244 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1245 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1247 SUNXI_FUNCTION(0x0, "gpio_in"),
1248 SUNXI_FUNCTION(0x1, "gpio_out"),
1249 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1251 SUNXI_FUNCTION(0x0, "gpio_in"),
1252 SUNXI_FUNCTION(0x1, "gpio_out"),
1253 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1254 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1255 SUNXI_FUNCTION(0x0, "gpio_in"),
1256 SUNXI_FUNCTION(0x1, "gpio_out"),
1257 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1258 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1259 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1260 SUNXI_FUNCTION(0x0, "gpio_in"),
1261 SUNXI_FUNCTION(0x1, "gpio_out"),
1262 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1263 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1264 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1265 SUNXI_FUNCTION(0x0, "gpio_in"),
1266 SUNXI_FUNCTION(0x1, "gpio_out"),
1267 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1268 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1269 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1270 SUNXI_FUNCTION(0x0, "gpio_in"),
1271 SUNXI_FUNCTION(0x1, "gpio_out"),
1272 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1273 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1275 SUNXI_FUNCTION(0x0, "gpio_in"),
1276 SUNXI_FUNCTION(0x1, "gpio_out"),
1277 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1278 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1279 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1280 SUNXI_FUNCTION(0x0, "gpio_in"),
1281 SUNXI_FUNCTION(0x1, "gpio_out"),
1282 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1283 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1284 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1285 SUNXI_FUNCTION(0x0, "gpio_in"),
1286 SUNXI_FUNCTION(0x1, "gpio_out"),
1287 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1288 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1290 SUNXI_FUNCTION(0x0, "gpio_in"),
1291 SUNXI_FUNCTION(0x1, "gpio_out"),
1292 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1293 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1294 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1295 SUNXI_FUNCTION(0x0, "gpio_in"),
1296 SUNXI_FUNCTION(0x1, "gpio_out"),
1297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1298 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1299 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1300 SUNXI_FUNCTION(0x0, "gpio_in"),
1301 SUNXI_FUNCTION(0x1, "gpio_out"),
1302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1303 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
1305 SUNXI_FUNCTION(0x0, "gpio_in"),
1306 SUNXI_FUNCTION(0x1, "gpio_out"),
1307 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
1308 SUNXI_FUNCTION(0x4, "uart3")), /* TX */
1309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
1310 SUNXI_FUNCTION(0x0, "gpio_in"),
1311 SUNXI_FUNCTION(0x1, "gpio_out"),
1312 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
1313 SUNXI_FUNCTION(0x4, "uart3")), /* RX */
1314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
1315 SUNXI_FUNCTION(0x0, "gpio_in"),
1316 SUNXI_FUNCTION(0x1, "gpio_out"),
1317 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
1318 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
1319 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
1320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1321 SUNXI_FUNCTION(0x0, "gpio_in"),
1322 SUNXI_FUNCTION(0x1, "gpio_out"),
1323 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
1324 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1325 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1326 /* Hole */
1327 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
1328 SUNXI_FUNCTION(0x0, "gpio_in"),
1329 SUNXI_FUNCTION(0x1, "gpio_out"),
1330 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
1331 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
1332 SUNXI_FUNCTION(0x0, "gpio_in"),
1333 SUNXI_FUNCTION(0x1, "gpio_out"),
1334 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
1335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1336 SUNXI_FUNCTION(0x0, "gpio_in"),
1337 SUNXI_FUNCTION(0x1, "gpio_out"),
1338 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
1339 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1340 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1341 SUNXI_FUNCTION(0x0, "gpio_in"),
1342 SUNXI_FUNCTION(0x1, "gpio_out"),
1343 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
1344 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
1345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1346 SUNXI_FUNCTION(0x0, "gpio_in"),
1347 SUNXI_FUNCTION(0x1, "gpio_out"),
1348 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
1349 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
1350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1351 SUNXI_FUNCTION(0x0, "gpio_in"),
1352 SUNXI_FUNCTION(0x1, "gpio_out"),
1353 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
1354 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
1355 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1356 SUNXI_FUNCTION(0x0, "gpio_in"),
1357 SUNXI_FUNCTION(0x1, "gpio_out"),
1358 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
1359 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
1360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1361 SUNXI_FUNCTION(0x0, "gpio_in"),
1362 SUNXI_FUNCTION(0x1, "gpio_out"),
1363 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
1364 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
1365 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
1366 SUNXI_FUNCTION(0x0, "gpio_in"),
1367 SUNXI_FUNCTION(0x1, "gpio_out"),
1368 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
1369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
1370 SUNXI_FUNCTION(0x0, "gpio_in"),
1371 SUNXI_FUNCTION(0x1, "gpio_out"),
1372 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
1373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1374 SUNXI_FUNCTION(0x0, "gpio_in"),
1375 SUNXI_FUNCTION(0x1, "gpio_out"),
1376 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
1377 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
1378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1379 SUNXI_FUNCTION(0x0, "gpio_in"),
1380 SUNXI_FUNCTION(0x1, "gpio_out"),
1381 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
1382 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
1383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1384 SUNXI_FUNCTION(0x0, "gpio_in"),
1385 SUNXI_FUNCTION(0x1, "gpio_out"),
1386 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
1387 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
1388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1389 SUNXI_FUNCTION(0x0, "gpio_in"),
1390 SUNXI_FUNCTION(0x1, "gpio_out"),
1391 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
1392 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
1393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1394 SUNXI_FUNCTION(0x0, "gpio_in"),
1395 SUNXI_FUNCTION(0x1, "gpio_out"),
1396 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
1397 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
1398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1399 SUNXI_FUNCTION(0x0, "gpio_in"),
1400 SUNXI_FUNCTION(0x1, "gpio_out"),
1401 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
1402 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
1403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
1404 SUNXI_FUNCTION(0x0, "gpio_in"),
1405 SUNXI_FUNCTION(0x1, "gpio_out"),
1406 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
1407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
1408 SUNXI_FUNCTION(0x0, "gpio_in"),
1409 SUNXI_FUNCTION(0x1, "gpio_out"),
1410 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
1411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1412 SUNXI_FUNCTION(0x0, "gpio_in"),
1413 SUNXI_FUNCTION(0x1, "gpio_out"),
1414 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
1415 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
1416 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1417 SUNXI_FUNCTION(0x0, "gpio_in"),
1418 SUNXI_FUNCTION(0x1, "gpio_out"),
1419 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
1420 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
1421 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1422 SUNXI_FUNCTION(0x0, "gpio_in"),
1423 SUNXI_FUNCTION(0x1, "gpio_out"),
1424 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
1425 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
1426 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1427 SUNXI_FUNCTION(0x0, "gpio_in"),
1428 SUNXI_FUNCTION(0x1, "gpio_out"),
1429 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
1430 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
1431 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1432 SUNXI_FUNCTION(0x0, "gpio_in"),
1433 SUNXI_FUNCTION(0x1, "gpio_out"),
1434 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
1435 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
1436 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1437 SUNXI_FUNCTION(0x0, "gpio_in"),
1438 SUNXI_FUNCTION(0x1, "gpio_out"),
1439 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
1440 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
1441 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1442 SUNXI_FUNCTION(0x0, "gpio_in"),
1443 SUNXI_FUNCTION(0x1, "gpio_out"),
1444 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
1445 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
1446 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1447 SUNXI_FUNCTION(0x0, "gpio_in"),
1448 SUNXI_FUNCTION(0x1, "gpio_out"),
1449 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
1450 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
1451 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1452 SUNXI_FUNCTION(0x0, "gpio_in"),
1453 SUNXI_FUNCTION(0x1, "gpio_out"),
1454 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
1455 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
1456 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1457 SUNXI_FUNCTION(0x0, "gpio_in"),
1458 SUNXI_FUNCTION(0x1, "gpio_out"),
1459 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
1460 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
1461 /* Hole */
1462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1463 SUNXI_FUNCTION(0x0, "gpio_in"),
1464 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
1465 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
1466 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1467 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1468 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1469 SUNXI_FUNCTION(0x0, "gpio_in"),
1470 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
1471 SUNXI_FUNCTION(0x3, "csi0"), /* CK */
1472 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1473 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1474 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1475 SUNXI_FUNCTION(0x0, "gpio_in"),
1476 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
1477 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1478 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1480 SUNXI_FUNCTION(0x0, "gpio_in"),
1481 SUNXI_FUNCTION(0x1, "gpio_out"),
1482 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
1483 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1484 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1486 SUNXI_FUNCTION(0x0, "gpio_in"),
1487 SUNXI_FUNCTION(0x1, "gpio_out"),
1488 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
1489 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1490 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1492 SUNXI_FUNCTION(0x0, "gpio_in"),
1493 SUNXI_FUNCTION(0x1, "gpio_out"),
1494 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
1495 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1496 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1498 SUNXI_FUNCTION(0x0, "gpio_in"),
1499 SUNXI_FUNCTION(0x1, "gpio_out"),
1500 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
1501 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1502 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1504 SUNXI_FUNCTION(0x0, "gpio_in"),
1505 SUNXI_FUNCTION(0x1, "gpio_out"),
1506 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
1507 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1508 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1509 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1510 SUNXI_FUNCTION(0x0, "gpio_in"),
1511 SUNXI_FUNCTION(0x1, "gpio_out"),
1512 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
1513 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1514 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1515 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1516 SUNXI_FUNCTION(0x0, "gpio_in"),
1517 SUNXI_FUNCTION(0x1, "gpio_out"),
1518 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
1519 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1520 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1522 SUNXI_FUNCTION(0x0, "gpio_in"),
1523 SUNXI_FUNCTION(0x1, "gpio_out"),
1524 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
1525 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1526 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1528 SUNXI_FUNCTION(0x0, "gpio_in"),
1529 SUNXI_FUNCTION(0x1, "gpio_out"),
1530 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
1531 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1532 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1533 /* Hole */
1534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1535 SUNXI_FUNCTION(0x0, "gpio_in"),
1536 SUNXI_FUNCTION(0x1, "gpio_out"),
1537 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
1538 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
1539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1540 SUNXI_FUNCTION(0x0, "gpio_in"),
1541 SUNXI_FUNCTION(0x1, "gpio_out"),
1542 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
1543 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
1544 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1545 SUNXI_FUNCTION(0x0, "gpio_in"),
1546 SUNXI_FUNCTION(0x1, "gpio_out"),
1547 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
1548 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
1549 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1550 SUNXI_FUNCTION(0x0, "gpio_in"),
1551 SUNXI_FUNCTION(0x1, "gpio_out"),
1552 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
1553 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
1554 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1555 SUNXI_FUNCTION(0x0, "gpio_in"),
1556 SUNXI_FUNCTION(0x1, "gpio_out"),
1557 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
1558 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
1559 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1560 SUNXI_FUNCTION(0x0, "gpio_in"),
1561 SUNXI_FUNCTION(0x1, "gpio_out"),
1562 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
1563 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
1564 /* Hole */
1565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1566 SUNXI_FUNCTION(0x0, "gpio_in"),
1567 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
1568 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1569 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1570 SUNXI_FUNCTION(0x0, "gpio_in"),
1571 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
1572 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1574 SUNXI_FUNCTION(0x0, "gpio_in"),
1575 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
1576 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1578 SUNXI_FUNCTION(0x0, "gpio_in"),
1579 SUNXI_FUNCTION(0x1, "gpio_out"),
1580 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1581 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1582 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1584 SUNXI_FUNCTION(0x0, "gpio_in"),
1585 SUNXI_FUNCTION(0x1, "gpio_out"),
1586 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1587 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1588 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
1590 SUNXI_FUNCTION(0x0, "gpio_in"),
1591 SUNXI_FUNCTION(0x1, "gpio_out"),
1592 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
1593 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
1594 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
1595 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
1596 SUNXI_FUNCTION(0x0, "gpio_in"),
1597 SUNXI_FUNCTION(0x1, "gpio_out"),
1598 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
1599 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
1600 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
1601 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
1602 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
1603 SUNXI_FUNCTION(0x0, "gpio_in"),
1604 SUNXI_FUNCTION(0x1, "gpio_out"),
1605 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
1606 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
1607 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
1608 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
1609 SUNXI_FUNCTION(0x0, "gpio_in"),
1610 SUNXI_FUNCTION(0x1, "gpio_out"),
1611 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
1612 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
1613 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
1614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1615 SUNXI_FUNCTION(0x0, "gpio_in"),
1616 SUNXI_FUNCTION(0x1, "gpio_out"),
1617 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1618 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1619 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1621 SUNXI_FUNCTION(0x0, "gpio_in"),
1622 SUNXI_FUNCTION(0x1, "gpio_out"),
1623 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1624 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1625 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1626 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1627 SUNXI_FUNCTION(0x0, "gpio_in"),
1628 SUNXI_FUNCTION(0x1, "gpio_out"),
1629 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1630 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1631 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
1632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
1633 SUNXI_FUNCTION(0x0, "gpio_in"),
1634 SUNXI_FUNCTION(0x1, "gpio_out"),
1635 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1636 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
1637 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
1638 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
1639 SUNXI_FUNCTION(0x0, "gpio_in"),
1640 SUNXI_FUNCTION(0x1, "gpio_out"),
1641 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
1642 SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */
1643 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
1644 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
1645};
1646
1647static const struct sunxi_desc_pin sun5i_a13_pins[] = {
1648 /* Hole */
1649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1650 SUNXI_FUNCTION(0x0, "gpio_in"),
1651 SUNXI_FUNCTION(0x1, "gpio_out"),
1652 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1653 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1654 SUNXI_FUNCTION(0x0, "gpio_in"),
1655 SUNXI_FUNCTION(0x1, "gpio_out"),
1656 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1658 SUNXI_FUNCTION(0x0, "gpio_in"),
1659 SUNXI_FUNCTION(0x1, "gpio_out"),
1660 SUNXI_FUNCTION(0x2, "pwm"),
1661 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1663 SUNXI_FUNCTION(0x0, "gpio_in"),
1664 SUNXI_FUNCTION(0x1, "gpio_out"),
1665 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1666 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1668 SUNXI_FUNCTION(0x0, "gpio_in"),
1669 SUNXI_FUNCTION(0x1, "gpio_out"),
1670 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1671 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1672 /* Hole */
1673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1674 SUNXI_FUNCTION(0x0, "gpio_in"),
1675 SUNXI_FUNCTION(0x1, "gpio_out"),
1676 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1677 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1678 /* Hole */
1679 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1680 SUNXI_FUNCTION(0x0, "gpio_in"),
1681 SUNXI_FUNCTION(0x1, "gpio_out"),
1682 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1683 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1684 SUNXI_FUNCTION(0x0, "gpio_in"),
1685 SUNXI_FUNCTION(0x1, "gpio_out"),
1686 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1688 SUNXI_FUNCTION(0x0, "gpio_in"),
1689 SUNXI_FUNCTION(0x1, "gpio_out"),
1690 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1692 SUNXI_FUNCTION(0x0, "gpio_in"),
1693 SUNXI_FUNCTION(0x1, "gpio_out"),
1694 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1695 /* Hole */
1696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1697 SUNXI_FUNCTION(0x0, "gpio_in"),
1698 SUNXI_FUNCTION(0x1, "gpio_out"),
1699 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1700 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1701 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1702 SUNXI_FUNCTION(0x0, "gpio_in"),
1703 SUNXI_FUNCTION(0x1, "gpio_out"),
1704 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1705 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1706 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1707 SUNXI_FUNCTION(0x0, "gpio_in"),
1708 SUNXI_FUNCTION(0x1, "gpio_out"),
1709 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1710 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
1711 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1712 SUNXI_FUNCTION(0x0, "gpio_in"),
1713 SUNXI_FUNCTION(0x1, "gpio_out"),
1714 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1715 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1717 SUNXI_FUNCTION(0x0, "gpio_in"),
1718 SUNXI_FUNCTION(0x1, "gpio_out"),
1719 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1721 SUNXI_FUNCTION(0x0, "gpio_in"),
1722 SUNXI_FUNCTION(0x1, "gpio_out"),
1723 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1725 SUNXI_FUNCTION(0x0, "gpio_in"),
1726 SUNXI_FUNCTION(0x1, "gpio_out"),
1727 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1728 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1729 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1730 SUNXI_FUNCTION(0x0, "gpio_in"),
1731 SUNXI_FUNCTION(0x1, "gpio_out"),
1732 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1733 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1734 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1735 SUNXI_FUNCTION(0x0, "gpio_in"),
1736 SUNXI_FUNCTION(0x1, "gpio_out"),
1737 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1738 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1739 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1740 SUNXI_FUNCTION(0x0, "gpio_in"),
1741 SUNXI_FUNCTION(0x1, "gpio_out"),
1742 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1743 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1745 SUNXI_FUNCTION(0x0, "gpio_in"),
1746 SUNXI_FUNCTION(0x1, "gpio_out"),
1747 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1748 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1749 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1750 SUNXI_FUNCTION(0x0, "gpio_in"),
1751 SUNXI_FUNCTION(0x1, "gpio_out"),
1752 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1753 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1754 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1755 SUNXI_FUNCTION(0x0, "gpio_in"),
1756 SUNXI_FUNCTION(0x1, "gpio_out"),
1757 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1758 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1760 SUNXI_FUNCTION(0x0, "gpio_in"),
1761 SUNXI_FUNCTION(0x1, "gpio_out"),
1762 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1763 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1765 SUNXI_FUNCTION(0x0, "gpio_in"),
1766 SUNXI_FUNCTION(0x1, "gpio_out"),
1767 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1768 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1769 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1770 SUNXI_FUNCTION(0x0, "gpio_in"),
1771 SUNXI_FUNCTION(0x1, "gpio_out"),
1772 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1773 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1774 /* Hole */
1775 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1776 SUNXI_FUNCTION(0x0, "gpio_in"),
1777 SUNXI_FUNCTION(0x1, "gpio_out"),
1778 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
1779 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1780 /* Hole */
1781 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1782 SUNXI_FUNCTION(0x0, "gpio_in"),
1783 SUNXI_FUNCTION(0x1, "gpio_out"),
1784 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
1785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1786 SUNXI_FUNCTION(0x0, "gpio_in"),
1787 SUNXI_FUNCTION(0x1, "gpio_out"),
1788 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
1789 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1790 SUNXI_FUNCTION(0x0, "gpio_in"),
1791 SUNXI_FUNCTION(0x1, "gpio_out"),
1792 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
1793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1794 SUNXI_FUNCTION(0x0, "gpio_in"),
1795 SUNXI_FUNCTION(0x1, "gpio_out"),
1796 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
1797 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1798 SUNXI_FUNCTION(0x0, "gpio_in"),
1799 SUNXI_FUNCTION(0x1, "gpio_out"),
1800 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
1801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1802 SUNXI_FUNCTION(0x0, "gpio_in"),
1803 SUNXI_FUNCTION(0x1, "gpio_out"),
1804 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
1805 /* Hole */
1806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1807 SUNXI_FUNCTION(0x0, "gpio_in"),
1808 SUNXI_FUNCTION(0x1, "gpio_out"),
1809 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
1810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1811 SUNXI_FUNCTION(0x0, "gpio_in"),
1812 SUNXI_FUNCTION(0x1, "gpio_out"),
1813 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
1814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1815 SUNXI_FUNCTION(0x0, "gpio_in"),
1816 SUNXI_FUNCTION(0x1, "gpio_out"),
1817 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
1818 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1819 SUNXI_FUNCTION(0x0, "gpio_in"),
1820 SUNXI_FUNCTION(0x1, "gpio_out"),
1821 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
1822 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1823 SUNXI_FUNCTION(0x0, "gpio_in"),
1824 SUNXI_FUNCTION(0x1, "gpio_out"),
1825 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
1826 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1827 SUNXI_FUNCTION(0x0, "gpio_in"),
1828 SUNXI_FUNCTION(0x1, "gpio_out"),
1829 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
1830 /* Hole */
1831 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1832 SUNXI_FUNCTION(0x0, "gpio_in"),
1833 SUNXI_FUNCTION(0x1, "gpio_out"),
1834 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
1835 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1836 SUNXI_FUNCTION(0x0, "gpio_in"),
1837 SUNXI_FUNCTION(0x1, "gpio_out"),
1838 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
1839 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1840 SUNXI_FUNCTION(0x0, "gpio_in"),
1841 SUNXI_FUNCTION(0x1, "gpio_out"),
1842 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
1843 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1844 SUNXI_FUNCTION(0x0, "gpio_in"),
1845 SUNXI_FUNCTION(0x1, "gpio_out"),
1846 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
1847 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1848 SUNXI_FUNCTION(0x0, "gpio_in"),
1849 SUNXI_FUNCTION(0x1, "gpio_out"),
1850 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
1851 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1852 SUNXI_FUNCTION(0x0, "gpio_in"),
1853 SUNXI_FUNCTION(0x1, "gpio_out"),
1854 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
1855 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1856 SUNXI_FUNCTION(0x0, "gpio_in"),
1857 SUNXI_FUNCTION(0x1, "gpio_out"),
1858 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
1859 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1860 SUNXI_FUNCTION(0x0, "gpio_in"),
1861 SUNXI_FUNCTION(0x1, "gpio_out"),
1862 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
1863 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1864 SUNXI_FUNCTION(0x0, "gpio_in"),
1865 SUNXI_FUNCTION(0x1, "gpio_out"),
1866 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
1867 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1868 SUNXI_FUNCTION(0x0, "gpio_in"),
1869 SUNXI_FUNCTION(0x1, "gpio_out"),
1870 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
1871 /* Hole */
1872 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1873 SUNXI_FUNCTION(0x0, "gpio_in"),
1874 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
1875 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1876 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1878 SUNXI_FUNCTION(0x0, "gpio_in"),
1879 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
1880 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1881 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1883 SUNXI_FUNCTION(0x0, "gpio_in"),
1884 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1885 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1886 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1887 SUNXI_FUNCTION(0x0, "gpio_in"),
1888 SUNXI_FUNCTION(0x1, "gpio_out"),
1889 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1890 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1891 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1892 SUNXI_FUNCTION(0x0, "gpio_in"),
1893 SUNXI_FUNCTION(0x1, "gpio_out"),
1894 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1895 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1896 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1897 SUNXI_FUNCTION(0x0, "gpio_in"),
1898 SUNXI_FUNCTION(0x1, "gpio_out"),
1899 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1900 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1902 SUNXI_FUNCTION(0x0, "gpio_in"),
1903 SUNXI_FUNCTION(0x1, "gpio_out"),
1904 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1905 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1906 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1907 SUNXI_FUNCTION(0x0, "gpio_in"),
1908 SUNXI_FUNCTION(0x1, "gpio_out"),
1909 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1910 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1912 SUNXI_FUNCTION(0x0, "gpio_in"),
1913 SUNXI_FUNCTION(0x1, "gpio_out"),
1914 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1915 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1916 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1917 SUNXI_FUNCTION(0x0, "gpio_in"),
1918 SUNXI_FUNCTION(0x1, "gpio_out"),
1919 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1920 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1921 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1922 SUNXI_FUNCTION(0x0, "gpio_in"),
1923 SUNXI_FUNCTION(0x1, "gpio_out"),
1924 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1925 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1926 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1927 SUNXI_FUNCTION(0x0, "gpio_in"),
1928 SUNXI_FUNCTION(0x1, "gpio_out"),
1929 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1930 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1931 /* Hole */
1932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1933 SUNXI_FUNCTION(0x0, "gpio_in"),
1934 SUNXI_FUNCTION(0x1, "gpio_out"),
1935 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
1936 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1937 SUNXI_FUNCTION(0x0, "gpio_in"),
1938 SUNXI_FUNCTION(0x1, "gpio_out"),
1939 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
1940 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1941 SUNXI_FUNCTION(0x0, "gpio_in"),
1942 SUNXI_FUNCTION(0x1, "gpio_out"),
1943 SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
1944 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1945 SUNXI_FUNCTION(0x0, "gpio_in"),
1946 SUNXI_FUNCTION(0x1, "gpio_out"),
1947 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
1948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1949 SUNXI_FUNCTION(0x0, "gpio_in"),
1950 SUNXI_FUNCTION(0x1, "gpio_out"),
1951 SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
1952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1953 SUNXI_FUNCTION(0x0, "gpio_in"),
1954 SUNXI_FUNCTION(0x1, "gpio_out"),
1955 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
1956 /* Hole */
1957 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1958 SUNXI_FUNCTION(0x0, "gpio_in"),
1959 SUNXI_FUNCTION(0x1, "gpio_out"),
1960 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1961 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1962 SUNXI_FUNCTION(0x0, "gpio_in"),
1963 SUNXI_FUNCTION(0x1, "gpio_out"),
1964 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1965 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1966 SUNXI_FUNCTION(0x0, "gpio_in"),
1967 SUNXI_FUNCTION(0x1, "gpio_out"),
1968 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1970 SUNXI_FUNCTION(0x0, "gpio_in"),
1971 SUNXI_FUNCTION(0x1, "gpio_out"),
1972 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1973 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1974 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1976 SUNXI_FUNCTION(0x0, "gpio_in"),
1977 SUNXI_FUNCTION(0x1, "gpio_out"),
1978 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1979 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1980 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1981 /* Hole */
1982 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1983 SUNXI_FUNCTION(0x0, "gpio_in"),
1984 SUNXI_FUNCTION(0x1, "gpio_out"),
1985 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1986 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1987 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1988 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1989 SUNXI_FUNCTION(0x0, "gpio_in"),
1990 SUNXI_FUNCTION(0x1, "gpio_out"),
1991 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1992 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1993 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1994 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1995 SUNXI_FUNCTION(0x0, "gpio_in"),
1996 SUNXI_FUNCTION(0x1, "gpio_out"),
1997 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1998 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1999 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
2000 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
2001 SUNXI_FUNCTION(0x0, "gpio_in"),
2002 SUNXI_FUNCTION(0x1, "gpio_out"),
2003 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
2004 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
2005 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
2006};
2007
2008static const struct sunxi_desc_pin sun6i_a31_pins[] = {
2009 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
2010 SUNXI_FUNCTION(0x0, "gpio_in"),
2011 SUNXI_FUNCTION(0x1, "gpio_out"),
2012 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
2013 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
2014 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
2015 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
2016 SUNXI_FUNCTION(0x0, "gpio_in"),
2017 SUNXI_FUNCTION(0x1, "gpio_out"),
2018 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
2019 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
2020 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
2021 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
2022 SUNXI_FUNCTION(0x0, "gpio_in"),
2023 SUNXI_FUNCTION(0x1, "gpio_out"),
2024 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
2025 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
2026 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
2027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
2028 SUNXI_FUNCTION(0x0, "gpio_in"),
2029 SUNXI_FUNCTION(0x1, "gpio_out"),
2030 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
2031 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
2032 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
2033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
2034 SUNXI_FUNCTION(0x0, "gpio_in"),
2035 SUNXI_FUNCTION(0x1, "gpio_out"),
2036 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
2037 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
2038 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
2039 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
2040 SUNXI_FUNCTION(0x0, "gpio_in"),
2041 SUNXI_FUNCTION(0x1, "gpio_out"),
2042 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
2043 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
2044 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
2045 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
2046 SUNXI_FUNCTION(0x0, "gpio_in"),
2047 SUNXI_FUNCTION(0x1, "gpio_out"),
2048 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
2049 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
2050 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
2051 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
2052 SUNXI_FUNCTION(0x0, "gpio_in"),
2053 SUNXI_FUNCTION(0x1, "gpio_out"),
2054 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
2055 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
2056 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
2057 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
2058 SUNXI_FUNCTION(0x0, "gpio_in"),
2059 SUNXI_FUNCTION(0x1, "gpio_out"),
2060 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
2061 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */
2062 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
2063 SUNXI_FUNCTION(0x0, "gpio_in"),
2064 SUNXI_FUNCTION(0x1, "gpio_out"),
2065 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
2066 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
2067 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
2068 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */
2069 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
2070 SUNXI_FUNCTION(0x0, "gpio_in"),
2071 SUNXI_FUNCTION(0x1, "gpio_out"),
2072 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
2073 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
2074 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
2075 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */
2076 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
2077 SUNXI_FUNCTION(0x0, "gpio_in"),
2078 SUNXI_FUNCTION(0x1, "gpio_out"),
2079 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
2080 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
2081 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
2082 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */
2083 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
2084 SUNXI_FUNCTION(0x0, "gpio_in"),
2085 SUNXI_FUNCTION(0x1, "gpio_out"),
2086 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
2087 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
2088 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
2089 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */
2090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
2091 SUNXI_FUNCTION(0x0, "gpio_in"),
2092 SUNXI_FUNCTION(0x1, "gpio_out"),
2093 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
2094 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
2095 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
2096 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */
2097 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
2098 SUNXI_FUNCTION(0x0, "gpio_in"),
2099 SUNXI_FUNCTION(0x1, "gpio_out"),
2100 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
2101 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
2102 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
2103 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */
2104 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
2105 SUNXI_FUNCTION(0x0, "gpio_in"),
2106 SUNXI_FUNCTION(0x1, "gpio_out"),
2107 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
2108 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */
2109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
2110 SUNXI_FUNCTION(0x0, "gpio_in"),
2111 SUNXI_FUNCTION(0x1, "gpio_out"),
2112 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
2113 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */
2114 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
2115 SUNXI_FUNCTION(0x0, "gpio_in"),
2116 SUNXI_FUNCTION(0x1, "gpio_out"),
2117 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
2118 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */
2119 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA18,
2120 SUNXI_FUNCTION(0x0, "gpio_in"),
2121 SUNXI_FUNCTION(0x1, "gpio_out"),
2122 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
2123 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */
2124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA19,
2125 SUNXI_FUNCTION(0x0, "gpio_in"),
2126 SUNXI_FUNCTION(0x1, "gpio_out"),
2127 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
2128 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
2129 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */
2130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA20,
2131 SUNXI_FUNCTION(0x0, "gpio_in"),
2132 SUNXI_FUNCTION(0x1, "gpio_out"),
2133 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
2134 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
2135 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */
2136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA21,
2137 SUNXI_FUNCTION(0x0, "gpio_in"),
2138 SUNXI_FUNCTION(0x1, "gpio_out"),
2139 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
2140 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
2141 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */
2142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA22,
2143 SUNXI_FUNCTION(0x0, "gpio_in"),
2144 SUNXI_FUNCTION(0x1, "gpio_out"),
2145 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
2146 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
2147 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */
2148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA23,
2149 SUNXI_FUNCTION(0x0, "gpio_in"),
2150 SUNXI_FUNCTION(0x1, "gpio_out"),
2151 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
2152 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
2153 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */
2154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA24,
2155 SUNXI_FUNCTION(0x0, "gpio_in"),
2156 SUNXI_FUNCTION(0x1, "gpio_out"),
2157 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
2158 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
2159 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */
2160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA25,
2161 SUNXI_FUNCTION(0x0, "gpio_in"),
2162 SUNXI_FUNCTION(0x1, "gpio_out"),
2163 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
2164 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
2165 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */
2166 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA26,
2167 SUNXI_FUNCTION(0x0, "gpio_in"),
2168 SUNXI_FUNCTION(0x1, "gpio_out"),
2169 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
2170 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */
2171 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA27,
2172 SUNXI_FUNCTION(0x0, "gpio_in"),
2173 SUNXI_FUNCTION(0x1, "gpio_out"),
2174 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
2175 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */
2176 /* Hole */
2177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
2178 SUNXI_FUNCTION(0x0, "gpio_in"),
2179 SUNXI_FUNCTION(0x1, "gpio_out"),
2180 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
2181 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
2182 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */
2183 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
2184 SUNXI_FUNCTION(0x0, "gpio_in"),
2185 SUNXI_FUNCTION(0x1, "gpio_out"),
2186 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */
2187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
2188 SUNXI_FUNCTION(0x0, "gpio_in"),
2189 SUNXI_FUNCTION(0x1, "gpio_out"),
2190 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */
2191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
2192 SUNXI_FUNCTION(0x0, "gpio_in"),
2193 SUNXI_FUNCTION(0x1, "gpio_out"),
2194 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */
2195 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
2196 SUNXI_FUNCTION(0x0, "gpio_in"),
2197 SUNXI_FUNCTION(0x1, "gpio_out"),
2198 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
2199 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
2200 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
2201 SUNXI_FUNCTION(0x0, "gpio_in"),
2202 SUNXI_FUNCTION(0x1, "gpio_out"),
2203 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
2204 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
2205 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */
2206 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
2207 SUNXI_FUNCTION(0x0, "gpio_in"),
2208 SUNXI_FUNCTION(0x1, "gpio_out"),
2209 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
2210 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
2211 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */
2212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
2213 SUNXI_FUNCTION(0x0, "gpio_in"),
2214 SUNXI_FUNCTION(0x1, "gpio_out"),
2215 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */
2216 /* Hole */
2217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
2218 SUNXI_FUNCTION(0x0, "gpio_in"),
2219 SUNXI_FUNCTION(0x1, "gpio_out"),
2220 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
2221 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
2222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
2223 SUNXI_FUNCTION(0x0, "gpio_in"),
2224 SUNXI_FUNCTION(0x1, "gpio_out"),
2225 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
2226 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
2227 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
2228 SUNXI_FUNCTION(0x0, "gpio_in"),
2229 SUNXI_FUNCTION(0x1, "gpio_out"),
2230 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
2231 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
2232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
2233 SUNXI_FUNCTION(0x0, "gpio_in"),
2234 SUNXI_FUNCTION(0x1, "gpio_out"),
2235 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
2236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
2237 SUNXI_FUNCTION(0x0, "gpio_in"),
2238 SUNXI_FUNCTION(0x1, "gpio_out"),
2239 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
2240 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
2241 SUNXI_FUNCTION(0x0, "gpio_in"),
2242 SUNXI_FUNCTION(0x1, "gpio_out"),
2243 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
2244 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
2245 SUNXI_FUNCTION(0x0, "gpio_in"),
2246 SUNXI_FUNCTION(0x1, "gpio_out"),
2247 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
2248 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
2249 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
2250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
2251 SUNXI_FUNCTION(0x0, "gpio_in"),
2252 SUNXI_FUNCTION(0x1, "gpio_out"),
2253 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
2254 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
2255 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
2256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
2257 SUNXI_FUNCTION(0x0, "gpio_in"),
2258 SUNXI_FUNCTION(0x1, "gpio_out"),
2259 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
2260 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
2261 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
2262 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
2263 SUNXI_FUNCTION(0x0, "gpio_in"),
2264 SUNXI_FUNCTION(0x1, "gpio_out"),
2265 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
2266 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
2267 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
2268 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
2269 SUNXI_FUNCTION(0x0, "gpio_in"),
2270 SUNXI_FUNCTION(0x1, "gpio_out"),
2271 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
2272 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
2273 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
2274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
2275 SUNXI_FUNCTION(0x0, "gpio_in"),
2276 SUNXI_FUNCTION(0x1, "gpio_out"),
2277 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
2278 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
2279 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
2280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
2281 SUNXI_FUNCTION(0x0, "gpio_in"),
2282 SUNXI_FUNCTION(0x1, "gpio_out"),
2283 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
2284 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
2285 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
2286 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
2287 SUNXI_FUNCTION(0x0, "gpio_in"),
2288 SUNXI_FUNCTION(0x1, "gpio_out"),
2289 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
2290 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
2291 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
2292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
2293 SUNXI_FUNCTION(0x0, "gpio_in"),
2294 SUNXI_FUNCTION(0x1, "gpio_out"),
2295 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
2296 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
2297 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
2298 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
2299 SUNXI_FUNCTION(0x0, "gpio_in"),
2300 SUNXI_FUNCTION(0x1, "gpio_out"),
2301 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
2302 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
2303 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
2304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
2305 SUNXI_FUNCTION(0x0, "gpio_in"),
2306 SUNXI_FUNCTION(0x1, "gpio_out"),
2307 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
2308 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
2309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
2310 SUNXI_FUNCTION(0x0, "gpio_in"),
2311 SUNXI_FUNCTION(0x1, "gpio_out"),
2312 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
2313 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
2314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
2315 SUNXI_FUNCTION(0x0, "gpio_in"),
2316 SUNXI_FUNCTION(0x1, "gpio_out"),
2317 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
2318 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
2319 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
2320 SUNXI_FUNCTION(0x0, "gpio_in"),
2321 SUNXI_FUNCTION(0x1, "gpio_out"),
2322 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
2323 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
2324 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
2325 SUNXI_FUNCTION(0x0, "gpio_in"),
2326 SUNXI_FUNCTION(0x1, "gpio_out"),
2327 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
2328 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
2329 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
2330 SUNXI_FUNCTION(0x0, "gpio_in"),
2331 SUNXI_FUNCTION(0x1, "gpio_out"),
2332 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
2333 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
2334 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
2335 SUNXI_FUNCTION(0x0, "gpio_in"),
2336 SUNXI_FUNCTION(0x1, "gpio_out"),
2337 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
2338 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
2339 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
2340 SUNXI_FUNCTION(0x0, "gpio_in"),
2341 SUNXI_FUNCTION(0x1, "gpio_out"),
2342 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
2343 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
2344 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
2345 SUNXI_FUNCTION(0x0, "gpio_in"),
2346 SUNXI_FUNCTION(0x1, "gpio_out"),
2347 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
2348 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
2349 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
2350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC25,
2351 SUNXI_FUNCTION(0x0, "gpio_in"),
2352 SUNXI_FUNCTION(0x1, "gpio_out"),
2353 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
2354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC26,
2355 SUNXI_FUNCTION(0x0, "gpio_in"),
2356 SUNXI_FUNCTION(0x1, "gpio_out"),
2357 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
2358 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC27,
2359 SUNXI_FUNCTION(0x0, "gpio_in"),
2360 SUNXI_FUNCTION(0x1, "gpio_out"),
2361 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
2362 /* Hole */
2363 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
2364 SUNXI_FUNCTION(0x0, "gpio_in"),
2365 SUNXI_FUNCTION(0x1, "gpio_out"),
2366 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
2367 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
2368 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
2369 SUNXI_FUNCTION(0x0, "gpio_in"),
2370 SUNXI_FUNCTION(0x1, "gpio_out"),
2371 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
2372 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
2373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
2374 SUNXI_FUNCTION(0x0, "gpio_in"),
2375 SUNXI_FUNCTION(0x1, "gpio_out"),
2376 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
2377 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
2378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
2379 SUNXI_FUNCTION(0x0, "gpio_in"),
2380 SUNXI_FUNCTION(0x1, "gpio_out"),
2381 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
2382 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
2383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
2384 SUNXI_FUNCTION(0x0, "gpio_in"),
2385 SUNXI_FUNCTION(0x1, "gpio_out"),
2386 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
2387 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
2388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
2389 SUNXI_FUNCTION(0x0, "gpio_in"),
2390 SUNXI_FUNCTION(0x1, "gpio_out"),
2391 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
2392 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
2393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
2394 SUNXI_FUNCTION(0x0, "gpio_in"),
2395 SUNXI_FUNCTION(0x1, "gpio_out"),
2396 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
2397 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
2398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
2399 SUNXI_FUNCTION(0x0, "gpio_in"),
2400 SUNXI_FUNCTION(0x1, "gpio_out"),
2401 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
2402 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
2403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
2404 SUNXI_FUNCTION(0x0, "gpio_in"),
2405 SUNXI_FUNCTION(0x1, "gpio_out"),
2406 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
2407 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
2408 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
2409 SUNXI_FUNCTION(0x0, "gpio_in"),
2410 SUNXI_FUNCTION(0x1, "gpio_out"),
2411 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
2412 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
2413 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
2414 SUNXI_FUNCTION(0x0, "gpio_in"),
2415 SUNXI_FUNCTION(0x1, "gpio_out"),
2416 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
2417 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
2418 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
2419 SUNXI_FUNCTION(0x0, "gpio_in"),
2420 SUNXI_FUNCTION(0x1, "gpio_out"),
2421 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
2422 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
2423 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
2424 SUNXI_FUNCTION(0x0, "gpio_in"),
2425 SUNXI_FUNCTION(0x1, "gpio_out"),
2426 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
2427 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
2428 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
2429 SUNXI_FUNCTION(0x0, "gpio_in"),
2430 SUNXI_FUNCTION(0x1, "gpio_out"),
2431 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
2432 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
2433 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
2434 SUNXI_FUNCTION(0x0, "gpio_in"),
2435 SUNXI_FUNCTION(0x1, "gpio_out"),
2436 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
2437 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
2438 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
2439 SUNXI_FUNCTION(0x0, "gpio_in"),
2440 SUNXI_FUNCTION(0x1, "gpio_out"),
2441 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
2442 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
2443 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
2444 SUNXI_FUNCTION(0x0, "gpio_in"),
2445 SUNXI_FUNCTION(0x1, "gpio_out"),
2446 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
2447 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
2448 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
2449 SUNXI_FUNCTION(0x0, "gpio_in"),
2450 SUNXI_FUNCTION(0x1, "gpio_out"),
2451 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
2452 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
2453 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
2454 SUNXI_FUNCTION(0x0, "gpio_in"),
2455 SUNXI_FUNCTION(0x1, "gpio_out"),
2456 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
2457 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
2458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
2459 SUNXI_FUNCTION(0x0, "gpio_in"),
2460 SUNXI_FUNCTION(0x1, "gpio_out"),
2461 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
2462 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
2463 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
2464 SUNXI_FUNCTION(0x0, "gpio_in"),
2465 SUNXI_FUNCTION(0x1, "gpio_out"),
2466 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
2467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
2468 SUNXI_FUNCTION(0x0, "gpio_in"),
2469 SUNXI_FUNCTION(0x1, "gpio_out"),
2470 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
2471 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
2472 SUNXI_FUNCTION(0x0, "gpio_in"),
2473 SUNXI_FUNCTION(0x1, "gpio_out"),
2474 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
2475 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
2476 SUNXI_FUNCTION(0x0, "gpio_in"),
2477 SUNXI_FUNCTION(0x1, "gpio_out"),
2478 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
2479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
2480 SUNXI_FUNCTION(0x0, "gpio_in"),
2481 SUNXI_FUNCTION(0x1, "gpio_out"),
2482 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
2483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
2484 SUNXI_FUNCTION(0x0, "gpio_in"),
2485 SUNXI_FUNCTION(0x1, "gpio_out"),
2486 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
2487 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
2488 SUNXI_FUNCTION(0x0, "gpio_in"),
2489 SUNXI_FUNCTION(0x1, "gpio_out"),
2490 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
2491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
2492 SUNXI_FUNCTION(0x0, "gpio_in"),
2493 SUNXI_FUNCTION(0x1, "gpio_out"),
2494 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
2495 /* Hole */
2496 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
2497 SUNXI_FUNCTION(0x0, "gpio_in"),
2498 SUNXI_FUNCTION(0x1, "gpio_out"),
2499 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
2500 SUNXI_FUNCTION(0x3, "ts")), /* CLK */
2501 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
2502 SUNXI_FUNCTION(0x0, "gpio_in"),
2503 SUNXI_FUNCTION(0x1, "gpio_out"),
2504 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
2505 SUNXI_FUNCTION(0x3, "ts")), /* ERR */
2506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
2507 SUNXI_FUNCTION(0x0, "gpio_in"),
2508 SUNXI_FUNCTION(0x1, "gpio_out"),
2509 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
2510 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */
2511 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
2512 SUNXI_FUNCTION(0x0, "gpio_in"),
2513 SUNXI_FUNCTION(0x1, "gpio_out"),
2514 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
2515 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */
2516 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
2517 SUNXI_FUNCTION(0x0, "gpio_in"),
2518 SUNXI_FUNCTION(0x1, "gpio_out"),
2519 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
2520 SUNXI_FUNCTION(0x3, "uart5")), /* TX */
2521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
2522 SUNXI_FUNCTION(0x0, "gpio_in"),
2523 SUNXI_FUNCTION(0x1, "gpio_out"),
2524 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
2525 SUNXI_FUNCTION(0x3, "uart5")), /* RX */
2526 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
2527 SUNXI_FUNCTION(0x0, "gpio_in"),
2528 SUNXI_FUNCTION(0x1, "gpio_out"),
2529 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
2530 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */
2531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
2532 SUNXI_FUNCTION(0x0, "gpio_in"),
2533 SUNXI_FUNCTION(0x1, "gpio_out"),
2534 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
2535 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */
2536 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
2537 SUNXI_FUNCTION(0x0, "gpio_in"),
2538 SUNXI_FUNCTION(0x1, "gpio_out"),
2539 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
2540 SUNXI_FUNCTION(0x3, "ts")), /* D0 */
2541 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
2542 SUNXI_FUNCTION(0x0, "gpio_in"),
2543 SUNXI_FUNCTION(0x1, "gpio_out"),
2544 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
2545 SUNXI_FUNCTION(0x3, "ts")), /* D1 */
2546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
2547 SUNXI_FUNCTION(0x0, "gpio_in"),
2548 SUNXI_FUNCTION(0x1, "gpio_out"),
2549 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
2550 SUNXI_FUNCTION(0x3, "ts")), /* D2 */
2551 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
2552 SUNXI_FUNCTION(0x0, "gpio_in"),
2553 SUNXI_FUNCTION(0x1, "gpio_out"),
2554 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
2555 SUNXI_FUNCTION(0x3, "ts")), /* D3 */
2556 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE12,
2557 SUNXI_FUNCTION(0x0, "gpio_in"),
2558 SUNXI_FUNCTION(0x1, "gpio_out"),
2559 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
2560 SUNXI_FUNCTION(0x3, "ts")), /* D4 */
2561 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE13,
2562 SUNXI_FUNCTION(0x0, "gpio_in"),
2563 SUNXI_FUNCTION(0x1, "gpio_out"),
2564 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
2565 SUNXI_FUNCTION(0x3, "ts")), /* D5 */
2566 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE14,
2567 SUNXI_FUNCTION(0x0, "gpio_in"),
2568 SUNXI_FUNCTION(0x1, "gpio_out"),
2569 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
2570 SUNXI_FUNCTION(0x3, "ts")), /* D6 */
2571 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE15,
2572 SUNXI_FUNCTION(0x0, "gpio_in"),
2573 SUNXI_FUNCTION(0x1, "gpio_out"),
2574 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
2575 SUNXI_FUNCTION(0x3, "ts")), /* D7 */
2576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE16,
2577 SUNXI_FUNCTION(0x0, "gpio_in"),
2578 SUNXI_FUNCTION(0x1, "gpio_out"),
2579 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */
2580 /* Hole */
2581 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
2582 SUNXI_FUNCTION(0x0, "gpio_in"),
2583 SUNXI_FUNCTION(0x1, "gpio_out"),
2584 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
2585 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
2586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
2587 SUNXI_FUNCTION(0x0, "gpio_in"),
2588 SUNXI_FUNCTION(0x1, "gpio_out"),
2589 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
2590 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
2591 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
2592 SUNXI_FUNCTION(0x0, "gpio_in"),
2593 SUNXI_FUNCTION(0x1, "gpio_out"),
2594 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
2595 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
2596 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
2597 SUNXI_FUNCTION(0x0, "gpio_in"),
2598 SUNXI_FUNCTION(0x1, "gpio_out"),
2599 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
2600 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
2601 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
2602 SUNXI_FUNCTION(0x0, "gpio_in"),
2603 SUNXI_FUNCTION(0x1, "gpio_out"),
2604 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
2605 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
2606 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
2607 SUNXI_FUNCTION(0x0, "gpio_in"),
2608 SUNXI_FUNCTION(0x1, "gpio_out"),
2609 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
2610 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
2611 /* Hole */
2612 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
2613 SUNXI_FUNCTION(0x0, "gpio_in"),
2614 SUNXI_FUNCTION(0x1, "gpio_out"),
2615 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */
2616 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
2617 SUNXI_FUNCTION(0x0, "gpio_in"),
2618 SUNXI_FUNCTION(0x1, "gpio_out"),
2619 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */
2620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
2621 SUNXI_FUNCTION(0x0, "gpio_in"),
2622 SUNXI_FUNCTION(0x1, "gpio_out"),
2623 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */
2624 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
2625 SUNXI_FUNCTION(0x0, "gpio_in"),
2626 SUNXI_FUNCTION(0x1, "gpio_out"),
2627 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */
2628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
2629 SUNXI_FUNCTION(0x0, "gpio_in"),
2630 SUNXI_FUNCTION(0x1, "gpio_out"),
2631 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */
2632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
2633 SUNXI_FUNCTION(0x0, "gpio_in"),
2634 SUNXI_FUNCTION(0x1, "gpio_out"),
2635 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */
2636 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
2637 SUNXI_FUNCTION(0x0, "gpio_in"),
2638 SUNXI_FUNCTION(0x1, "gpio_out"),
2639 SUNXI_FUNCTION(0x2, "uart2")), /* TX */
2640 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
2641 SUNXI_FUNCTION(0x0, "gpio_in"),
2642 SUNXI_FUNCTION(0x1, "gpio_out"),
2643 SUNXI_FUNCTION(0x2, "uart2")), /* RX */
2644 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
2645 SUNXI_FUNCTION(0x0, "gpio_in"),
2646 SUNXI_FUNCTION(0x1, "gpio_out"),
2647 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */
2648 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
2649 SUNXI_FUNCTION(0x0, "gpio_in"),
2650 SUNXI_FUNCTION(0x1, "gpio_out"),
2651 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */
2652 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
2653 SUNXI_FUNCTION(0x0, "gpio_in"),
2654 SUNXI_FUNCTION(0x1, "gpio_out"),
2655 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
2656 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */
2657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
2658 SUNXI_FUNCTION(0x0, "gpio_in"),
2659 SUNXI_FUNCTION(0x1, "gpio_out"),
2660 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
2661 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */
2662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
2663 SUNXI_FUNCTION(0x0, "gpio_in"),
2664 SUNXI_FUNCTION(0x1, "gpio_out"),
2665 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
2666 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */
2667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
2668 SUNXI_FUNCTION(0x0, "gpio_in"),
2669 SUNXI_FUNCTION(0x1, "gpio_out"),
2670 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
2671 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */
2672 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG14,
2673 SUNXI_FUNCTION(0x0, "gpio_in"),
2674 SUNXI_FUNCTION(0x1, "gpio_out"),
2675 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
2676 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */
2677 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG15,
2678 SUNXI_FUNCTION(0x0, "gpio_in"),
2679 SUNXI_FUNCTION(0x1, "gpio_out"),
2680 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
2681 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
2682 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG16,
2683 SUNXI_FUNCTION(0x0, "gpio_in"),
2684 SUNXI_FUNCTION(0x1, "gpio_out"),
2685 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
2686 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
2687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG17,
2688 SUNXI_FUNCTION(0x0, "gpio_in"),
2689 SUNXI_FUNCTION(0x1, "gpio_out"),
2690 SUNXI_FUNCTION(0x2, "uart4")), /* TX */
2691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG18,
2692 SUNXI_FUNCTION(0x0, "gpio_in"),
2693 SUNXI_FUNCTION(0x1, "gpio_out"),
2694 SUNXI_FUNCTION(0x2, "uart4")), /* RX */
2695 /* Hole */
2696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
2697 SUNXI_FUNCTION(0x0, "gpio_in"),
2698 SUNXI_FUNCTION(0x1, "gpio_out"),
2699 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
2700 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
2701 SUNXI_FUNCTION(0x0, "gpio_in"),
2702 SUNXI_FUNCTION(0x1, "gpio_out"),
2703 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
2704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
2705 SUNXI_FUNCTION(0x0, "gpio_in"),
2706 SUNXI_FUNCTION(0x1, "gpio_out"),
2707 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
2708 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
2709 SUNXI_FUNCTION(0x0, "gpio_in"),
2710 SUNXI_FUNCTION(0x1, "gpio_out"),
2711 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
2712 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
2713 SUNXI_FUNCTION(0x0, "gpio_in"),
2714 SUNXI_FUNCTION(0x1, "gpio_out"),
2715 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
2716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
2717 SUNXI_FUNCTION(0x0, "gpio_in"),
2718 SUNXI_FUNCTION(0x1, "gpio_out"),
2719 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
2720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
2721 SUNXI_FUNCTION(0x0, "gpio_in"),
2722 SUNXI_FUNCTION(0x1, "gpio_out"),
2723 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
2724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
2725 SUNXI_FUNCTION(0x0, "gpio_in"),
2726 SUNXI_FUNCTION(0x1, "gpio_out"),
2727 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
2728 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
2729 SUNXI_FUNCTION(0x0, "gpio_in"),
2730 SUNXI_FUNCTION(0x1, "gpio_out"),
2731 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
2732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
2733 SUNXI_FUNCTION(0x0, "gpio_in"),
2734 SUNXI_FUNCTION(0x1, "gpio_out"),
2735 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
2736 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
2737 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
2738 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
2739 SUNXI_FUNCTION(0x0, "gpio_in"),
2740 SUNXI_FUNCTION(0x1, "gpio_out"),
2741 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
2742 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
2743 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
2744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
2745 SUNXI_FUNCTION(0x0, "gpio_in"),
2746 SUNXI_FUNCTION(0x1, "gpio_out"),
2747 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
2748 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
2749 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
2750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
2751 SUNXI_FUNCTION(0x0, "gpio_in"),
2752 SUNXI_FUNCTION(0x1, "gpio_out"),
2753 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
2754 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
2755 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
2756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
2757 SUNXI_FUNCTION(0x0, "gpio_in"),
2758 SUNXI_FUNCTION(0x1, "gpio_out"),
2759 SUNXI_FUNCTION(0x2, "pwm0")),
2760 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
2761 SUNXI_FUNCTION(0x0, "gpio_in"),
2762 SUNXI_FUNCTION(0x1, "gpio_out"),
2763 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
2764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
2765 SUNXI_FUNCTION(0x0, "gpio_in"),
2766 SUNXI_FUNCTION(0x1, "gpio_out"),
2767 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
2768 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
2769 SUNXI_FUNCTION(0x0, "gpio_in"),
2770 SUNXI_FUNCTION(0x1, "gpio_out"),
2771 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
2772 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
2773 SUNXI_FUNCTION(0x0, "gpio_in"),
2774 SUNXI_FUNCTION(0x1, "gpio_out"),
2775 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
2776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
2777 SUNXI_FUNCTION(0x0, "gpio_in"),
2778 SUNXI_FUNCTION(0x1, "gpio_out"),
2779 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
2780 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
2781 SUNXI_FUNCTION(0x0, "gpio_in"),
2782 SUNXI_FUNCTION(0x1, "gpio_out"),
2783 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
2784 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
2785 SUNXI_FUNCTION(0x0, "gpio_in"),
2786 SUNXI_FUNCTION(0x1, "gpio_out"),
2787 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
2788 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
2789 SUNXI_FUNCTION(0x0, "gpio_in"),
2790 SUNXI_FUNCTION(0x1, "gpio_out"),
2791 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
2792 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
2793 SUNXI_FUNCTION(0x0, "gpio_in"),
2794 SUNXI_FUNCTION(0x1, "gpio_out")),
2795 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
2796 SUNXI_FUNCTION(0x0, "gpio_in"),
2797 SUNXI_FUNCTION(0x1, "gpio_out")),
2798 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
2799 SUNXI_FUNCTION(0x0, "gpio_in"),
2800 SUNXI_FUNCTION(0x1, "gpio_out")),
2801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
2802 SUNXI_FUNCTION(0x0, "gpio_in"),
2803 SUNXI_FUNCTION(0x1, "gpio_out")),
2804 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
2805 SUNXI_FUNCTION(0x0, "gpio_in"),
2806 SUNXI_FUNCTION(0x1, "gpio_out")),
2807 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
2808 SUNXI_FUNCTION(0x0, "gpio_in"),
2809 SUNXI_FUNCTION(0x1, "gpio_out")),
2810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH28,
2811 SUNXI_FUNCTION(0x0, "gpio_in"),
2812 SUNXI_FUNCTION(0x1, "gpio_out")),
2813 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH29,
2814 SUNXI_FUNCTION(0x0, "gpio_in"),
2815 SUNXI_FUNCTION(0x1, "gpio_out"),
2816 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
2817 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH30,
2818 SUNXI_FUNCTION(0x0, "gpio_in"),
2819 SUNXI_FUNCTION(0x1, "gpio_out"),
2820 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
2821};
2822
2823static const struct sunxi_desc_pin sun7i_a20_pins[] = {
2824 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
2825 SUNXI_FUNCTION(0x0, "gpio_in"),
2826 SUNXI_FUNCTION(0x1, "gpio_out"),
2827 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
2828 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
2829 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
2830 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
2831 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
2832 SUNXI_FUNCTION(0x0, "gpio_in"),
2833 SUNXI_FUNCTION(0x1, "gpio_out"),
2834 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
2835 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
2836 SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
2837 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
2838 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
2839 SUNXI_FUNCTION(0x0, "gpio_in"),
2840 SUNXI_FUNCTION(0x1, "gpio_out"),
2841 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
2842 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
2843 SUNXI_FUNCTION(0x4, "uart2"), /* TX */
2844 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
2845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
2846 SUNXI_FUNCTION(0x0, "gpio_in"),
2847 SUNXI_FUNCTION(0x1, "gpio_out"),
2848 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
2849 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
2850 SUNXI_FUNCTION(0x4, "uart2"), /* RX */
2851 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
2852 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
2853 SUNXI_FUNCTION(0x0, "gpio_in"),
2854 SUNXI_FUNCTION(0x1, "gpio_out"),
2855 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
2856 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
2857 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
2858 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
2859 SUNXI_FUNCTION(0x0, "gpio_in"),
2860 SUNXI_FUNCTION(0x1, "gpio_out"),
2861 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
2862 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
2863 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */
2864 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
2865 SUNXI_FUNCTION(0x0, "gpio_in"),
2866 SUNXI_FUNCTION(0x1, "gpio_out"),
2867 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
2868 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
2869 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */
2870 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
2871 SUNXI_FUNCTION(0x0, "gpio_in"),
2872 SUNXI_FUNCTION(0x1, "gpio_out"),
2873 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
2874 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
2875 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */
2876 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
2877 SUNXI_FUNCTION(0x0, "gpio_in"),
2878 SUNXI_FUNCTION(0x1, "gpio_out"),
2879 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
2880 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
2881 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */
2882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
2883 SUNXI_FUNCTION(0x0, "gpio_in"),
2884 SUNXI_FUNCTION(0x1, "gpio_out"),
2885 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
2886 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
2887 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */
2888 SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */
2889 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
2890 SUNXI_FUNCTION(0x0, "gpio_in"),
2891 SUNXI_FUNCTION(0x1, "gpio_out"),
2892 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
2893 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
2894 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */
2895 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
2896 SUNXI_FUNCTION(0x0, "gpio_in"),
2897 SUNXI_FUNCTION(0x1, "gpio_out"),
2898 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
2899 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
2900 SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */
2901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
2902 SUNXI_FUNCTION(0x0, "gpio_in"),
2903 SUNXI_FUNCTION(0x1, "gpio_out"),
2904 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
2905 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
2906 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
2907 SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */
2908 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
2909 SUNXI_FUNCTION(0x0, "gpio_in"),
2910 SUNXI_FUNCTION(0x1, "gpio_out"),
2911 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
2912 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
2913 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
2914 SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */
2915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
2916 SUNXI_FUNCTION(0x0, "gpio_in"),
2917 SUNXI_FUNCTION(0x1, "gpio_out"),
2918 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
2919 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
2920 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
2921 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */
2922 SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */
2923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
2924 SUNXI_FUNCTION(0x0, "gpio_in"),
2925 SUNXI_FUNCTION(0x1, "gpio_out"),
2926 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
2927 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
2928 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
2929 SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */
2930 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
2931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
2932 SUNXI_FUNCTION(0x0, "gpio_in"),
2933 SUNXI_FUNCTION(0x1, "gpio_out"),
2934 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
2935 SUNXI_FUNCTION(0x3, "can"), /* TX */
2936 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
2937 SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */
2938 SUNXI_FUNCTION(0x6, "i2s1")), /* DO */
2939 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
2940 SUNXI_FUNCTION(0x0, "gpio_in"),
2941 SUNXI_FUNCTION(0x1, "gpio_out"),
2942 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
2943 SUNXI_FUNCTION(0x3, "can"), /* RX */
2944 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
2945 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */
2946 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
2947 /* Hole */
2948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
2949 SUNXI_FUNCTION(0x0, "gpio_in"),
2950 SUNXI_FUNCTION(0x1, "gpio_out"),
2951 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
2952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
2953 SUNXI_FUNCTION(0x0, "gpio_in"),
2954 SUNXI_FUNCTION(0x1, "gpio_out"),
2955 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
2956 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
2957 SUNXI_FUNCTION(0x0, "gpio_in"),
2958 SUNXI_FUNCTION(0x1, "gpio_out"),
2959 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
2960 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
2961 SUNXI_FUNCTION(0x0, "gpio_in"),
2962 SUNXI_FUNCTION(0x1, "gpio_out"),
2963 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
2964 SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */
2965 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
2966 SUNXI_FUNCTION(0x0, "gpio_in"),
2967 SUNXI_FUNCTION(0x1, "gpio_out"),
2968 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
2969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
2970 SUNXI_FUNCTION(0x0, "gpio_in"),
2971 SUNXI_FUNCTION(0x1, "gpio_out"),
2972 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
2973 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
2974 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
2975 SUNXI_FUNCTION(0x0, "gpio_in"),
2976 SUNXI_FUNCTION(0x1, "gpio_out"),
2977 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
2978 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
2979 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
2980 SUNXI_FUNCTION(0x0, "gpio_in"),
2981 SUNXI_FUNCTION(0x1, "gpio_out"),
2982 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
2983 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
2984 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
2985 SUNXI_FUNCTION(0x0, "gpio_in"),
2986 SUNXI_FUNCTION(0x1, "gpio_out"),
2987 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
2988 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
2989 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
2990 SUNXI_FUNCTION(0x0, "gpio_in"),
2991 SUNXI_FUNCTION(0x1, "gpio_out"),
2992 SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */
2993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
2994 SUNXI_FUNCTION(0x0, "gpio_in"),
2995 SUNXI_FUNCTION(0x1, "gpio_out"),
2996 SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */
2997 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
2998 SUNXI_FUNCTION(0x0, "gpio_in"),
2999 SUNXI_FUNCTION(0x1, "gpio_out"),
3000 SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */
3001 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
3002 SUNXI_FUNCTION(0x0, "gpio_in"),
3003 SUNXI_FUNCTION(0x1, "gpio_out"),
3004 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
3005 SUNXI_FUNCTION(0x3, "ac97"), /* DI */
3006 SUNXI_FUNCTION(0x4, "spdif")), /* DI */
3007 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
3008 SUNXI_FUNCTION(0x0, "gpio_in"),
3009 SUNXI_FUNCTION(0x1, "gpio_out"),
3010 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
3011 SUNXI_FUNCTION(0x4, "spdif")), /* DO */
3012 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
3013 SUNXI_FUNCTION(0x0, "gpio_in"),
3014 SUNXI_FUNCTION(0x1, "gpio_out"),
3015 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
3016 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
3017 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
3018 SUNXI_FUNCTION(0x0, "gpio_in"),
3019 SUNXI_FUNCTION(0x1, "gpio_out"),
3020 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
3021 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
3022 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
3023 SUNXI_FUNCTION(0x0, "gpio_in"),
3024 SUNXI_FUNCTION(0x1, "gpio_out"),
3025 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
3026 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
3027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
3028 SUNXI_FUNCTION(0x0, "gpio_in"),
3029 SUNXI_FUNCTION(0x1, "gpio_out"),
3030 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
3031 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
3032 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
3033 SUNXI_FUNCTION(0x0, "gpio_in"),
3034 SUNXI_FUNCTION(0x1, "gpio_out"),
3035 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
3036 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
3037 SUNXI_FUNCTION(0x0, "gpio_in"),
3038 SUNXI_FUNCTION(0x1, "gpio_out"),
3039 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
3040 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
3041 SUNXI_FUNCTION(0x0, "gpio_in"),
3042 SUNXI_FUNCTION(0x1, "gpio_out"),
3043 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
3044 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
3045 SUNXI_FUNCTION(0x0, "gpio_in"),
3046 SUNXI_FUNCTION(0x1, "gpio_out"),
3047 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
3048 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
3049 SUNXI_FUNCTION(0x0, "gpio_in"),
3050 SUNXI_FUNCTION(0x1, "gpio_out"),
3051 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
3052 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
3053 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
3054 SUNXI_FUNCTION(0x0, "gpio_in"),
3055 SUNXI_FUNCTION(0x1, "gpio_out"),
3056 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
3057 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
3058 /* Hole */
3059 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
3060 SUNXI_FUNCTION(0x0, "gpio_in"),
3061 SUNXI_FUNCTION(0x1, "gpio_out"),
3062 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
3063 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
3064 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
3065 SUNXI_FUNCTION(0x0, "gpio_in"),
3066 SUNXI_FUNCTION(0x1, "gpio_out"),
3067 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
3068 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
3069 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
3070 SUNXI_FUNCTION(0x0, "gpio_in"),
3071 SUNXI_FUNCTION(0x1, "gpio_out"),
3072 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
3073 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
3074 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
3075 SUNXI_FUNCTION(0x0, "gpio_in"),
3076 SUNXI_FUNCTION(0x1, "gpio_out"),
3077 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
3078 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
3079 SUNXI_FUNCTION(0x0, "gpio_in"),
3080 SUNXI_FUNCTION(0x1, "gpio_out"),
3081 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
3082 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
3083 SUNXI_FUNCTION(0x0, "gpio_in"),
3084 SUNXI_FUNCTION(0x1, "gpio_out"),
3085 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
3086 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
3087 SUNXI_FUNCTION(0x0, "gpio_in"),
3088 SUNXI_FUNCTION(0x1, "gpio_out"),
3089 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
3090 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
3091 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
3092 SUNXI_FUNCTION(0x0, "gpio_in"),
3093 SUNXI_FUNCTION(0x1, "gpio_out"),
3094 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
3095 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
3096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
3097 SUNXI_FUNCTION(0x0, "gpio_in"),
3098 SUNXI_FUNCTION(0x1, "gpio_out"),
3099 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
3100 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
3101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
3102 SUNXI_FUNCTION(0x0, "gpio_in"),
3103 SUNXI_FUNCTION(0x1, "gpio_out"),
3104 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
3105 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
3106 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
3107 SUNXI_FUNCTION(0x0, "gpio_in"),
3108 SUNXI_FUNCTION(0x1, "gpio_out"),
3109 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
3110 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
3111 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
3112 SUNXI_FUNCTION(0x0, "gpio_in"),
3113 SUNXI_FUNCTION(0x1, "gpio_out"),
3114 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
3115 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
3116 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
3117 SUNXI_FUNCTION(0x0, "gpio_in"),
3118 SUNXI_FUNCTION(0x1, "gpio_out"),
3119 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
3120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
3121 SUNXI_FUNCTION(0x0, "gpio_in"),
3122 SUNXI_FUNCTION(0x1, "gpio_out"),
3123 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
3124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
3125 SUNXI_FUNCTION(0x0, "gpio_in"),
3126 SUNXI_FUNCTION(0x1, "gpio_out"),
3127 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
3128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
3129 SUNXI_FUNCTION(0x0, "gpio_in"),
3130 SUNXI_FUNCTION(0x1, "gpio_out"),
3131 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
3132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
3133 SUNXI_FUNCTION(0x0, "gpio_in"),
3134 SUNXI_FUNCTION(0x1, "gpio_out"),
3135 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
3136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
3137 SUNXI_FUNCTION(0x0, "gpio_in"),
3138 SUNXI_FUNCTION(0x1, "gpio_out"),
3139 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
3140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
3141 SUNXI_FUNCTION(0x0, "gpio_in"),
3142 SUNXI_FUNCTION(0x1, "gpio_out"),
3143 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
3144 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
3145 SUNXI_FUNCTION(0x0, "gpio_in"),
3146 SUNXI_FUNCTION(0x1, "gpio_out"),
3147 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
3148 SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
3149 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
3150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
3151 SUNXI_FUNCTION(0x0, "gpio_in"),
3152 SUNXI_FUNCTION(0x1, "gpio_out"),
3153 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
3154 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
3155 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
3156 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
3157 SUNXI_FUNCTION(0x0, "gpio_in"),
3158 SUNXI_FUNCTION(0x1, "gpio_out"),
3159 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
3160 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
3161 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
3162 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
3163 SUNXI_FUNCTION(0x0, "gpio_in"),
3164 SUNXI_FUNCTION(0x1, "gpio_out"),
3165 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
3166 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
3167 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
3168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
3169 SUNXI_FUNCTION(0x0, "gpio_in"),
3170 SUNXI_FUNCTION(0x1, "gpio_out"),
3171 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
3172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
3173 SUNXI_FUNCTION(0x0, "gpio_in"),
3174 SUNXI_FUNCTION(0x1, "gpio_out"),
3175 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
3176 /* Hole */
3177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
3178 SUNXI_FUNCTION(0x0, "gpio_in"),
3179 SUNXI_FUNCTION(0x1, "gpio_out"),
3180 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
3181 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
3182 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
3183 SUNXI_FUNCTION(0x0, "gpio_in"),
3184 SUNXI_FUNCTION(0x1, "gpio_out"),
3185 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
3186 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
3187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
3188 SUNXI_FUNCTION(0x0, "gpio_in"),
3189 SUNXI_FUNCTION(0x1, "gpio_out"),
3190 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
3191 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
3192 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
3193 SUNXI_FUNCTION(0x0, "gpio_in"),
3194 SUNXI_FUNCTION(0x1, "gpio_out"),
3195 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
3196 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
3197 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
3198 SUNXI_FUNCTION(0x0, "gpio_in"),
3199 SUNXI_FUNCTION(0x1, "gpio_out"),
3200 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
3201 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
3202 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
3203 SUNXI_FUNCTION(0x0, "gpio_in"),
3204 SUNXI_FUNCTION(0x1, "gpio_out"),
3205 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
3206 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
3207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
3208 SUNXI_FUNCTION(0x0, "gpio_in"),
3209 SUNXI_FUNCTION(0x1, "gpio_out"),
3210 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
3211 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
3212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
3213 SUNXI_FUNCTION(0x0, "gpio_in"),
3214 SUNXI_FUNCTION(0x1, "gpio_out"),
3215 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
3216 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
3217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
3218 SUNXI_FUNCTION(0x0, "gpio_in"),
3219 SUNXI_FUNCTION(0x1, "gpio_out"),
3220 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
3221 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
3222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
3223 SUNXI_FUNCTION(0x0, "gpio_in"),
3224 SUNXI_FUNCTION(0x1, "gpio_out"),
3225 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
3226 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
3227 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
3228 SUNXI_FUNCTION(0x0, "gpio_in"),
3229 SUNXI_FUNCTION(0x1, "gpio_out"),
3230 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
3231 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
3232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
3233 SUNXI_FUNCTION(0x0, "gpio_in"),
3234 SUNXI_FUNCTION(0x1, "gpio_out"),
3235 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
3236 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
3237 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
3238 SUNXI_FUNCTION(0x0, "gpio_in"),
3239 SUNXI_FUNCTION(0x1, "gpio_out"),
3240 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
3241 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
3242 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
3243 SUNXI_FUNCTION(0x0, "gpio_in"),
3244 SUNXI_FUNCTION(0x1, "gpio_out"),
3245 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
3246 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
3247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
3248 SUNXI_FUNCTION(0x0, "gpio_in"),
3249 SUNXI_FUNCTION(0x1, "gpio_out"),
3250 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
3251 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
3252 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
3253 SUNXI_FUNCTION(0x0, "gpio_in"),
3254 SUNXI_FUNCTION(0x1, "gpio_out"),
3255 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
3256 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
3257 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
3258 SUNXI_FUNCTION(0x0, "gpio_in"),
3259 SUNXI_FUNCTION(0x1, "gpio_out"),
3260 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
3261 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
3262 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
3263 SUNXI_FUNCTION(0x0, "gpio_in"),
3264 SUNXI_FUNCTION(0x1, "gpio_out"),
3265 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
3266 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
3267 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
3268 SUNXI_FUNCTION(0x0, "gpio_in"),
3269 SUNXI_FUNCTION(0x1, "gpio_out"),
3270 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
3271 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
3272 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
3273 SUNXI_FUNCTION(0x0, "gpio_in"),
3274 SUNXI_FUNCTION(0x1, "gpio_out"),
3275 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
3276 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
3277 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
3278 SUNXI_FUNCTION(0x0, "gpio_in"),
3279 SUNXI_FUNCTION(0x1, "gpio_out"),
3280 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
3281 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
3282 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
3283 SUNXI_FUNCTION(0x0, "gpio_in"),
3284 SUNXI_FUNCTION(0x1, "gpio_out"),
3285 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
3286 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
3287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
3288 SUNXI_FUNCTION(0x0, "gpio_in"),
3289 SUNXI_FUNCTION(0x1, "gpio_out"),
3290 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
3291 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
3292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
3293 SUNXI_FUNCTION(0x0, "gpio_in"),
3294 SUNXI_FUNCTION(0x1, "gpio_out"),
3295 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
3296 SUNXI_FUNCTION(0x3, "sim")), /* DET */
3297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
3298 SUNXI_FUNCTION(0x0, "gpio_in"),
3299 SUNXI_FUNCTION(0x1, "gpio_out"),
3300 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
3301 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
3302 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
3303 SUNXI_FUNCTION(0x0, "gpio_in"),
3304 SUNXI_FUNCTION(0x1, "gpio_out"),
3305 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
3306 SUNXI_FUNCTION(0x3, "sim")), /* RST */
3307 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
3308 SUNXI_FUNCTION(0x0, "gpio_in"),
3309 SUNXI_FUNCTION(0x1, "gpio_out"),
3310 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
3311 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
3312 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
3313 SUNXI_FUNCTION(0x0, "gpio_in"),
3314 SUNXI_FUNCTION(0x1, "gpio_out"),
3315 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
3316 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
3317 /* Hole */
3318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
3319 SUNXI_FUNCTION(0x0, "gpio_in"),
3320 SUNXI_FUNCTION(0x1, "gpio_out"),
3321 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
3322 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
3323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
3324 SUNXI_FUNCTION(0x0, "gpio_in"),
3325 SUNXI_FUNCTION(0x1, "gpio_out"),
3326 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
3327 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
3328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
3329 SUNXI_FUNCTION(0x0, "gpio_in"),
3330 SUNXI_FUNCTION(0x1, "gpio_out"),
3331 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
3332 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
3333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
3334 SUNXI_FUNCTION(0x0, "gpio_in"),
3335 SUNXI_FUNCTION(0x1, "gpio_out"),
3336 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
3337 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
3338 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
3339 SUNXI_FUNCTION(0x0, "gpio_in"),
3340 SUNXI_FUNCTION(0x1, "gpio_out"),
3341 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
3342 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
3343 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
3344 SUNXI_FUNCTION(0x0, "gpio_in"),
3345 SUNXI_FUNCTION(0x1, "gpio_out"),
3346 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
3347 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
3348 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
3349 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
3350 SUNXI_FUNCTION(0x0, "gpio_in"),
3351 SUNXI_FUNCTION(0x1, "gpio_out"),
3352 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
3353 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
3354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
3355 SUNXI_FUNCTION(0x0, "gpio_in"),
3356 SUNXI_FUNCTION(0x1, "gpio_out"),
3357 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
3358 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
3359 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
3360 SUNXI_FUNCTION(0x0, "gpio_in"),
3361 SUNXI_FUNCTION(0x1, "gpio_out"),
3362 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
3363 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
3364 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
3365 SUNXI_FUNCTION(0x0, "gpio_in"),
3366 SUNXI_FUNCTION(0x1, "gpio_out"),
3367 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
3368 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
3369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
3370 SUNXI_FUNCTION(0x0, "gpio_in"),
3371 SUNXI_FUNCTION(0x1, "gpio_out"),
3372 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
3373 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
3374 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
3375 SUNXI_FUNCTION(0x0, "gpio_in"),
3376 SUNXI_FUNCTION(0x1, "gpio_out"),
3377 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
3378 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
3379 /* Hole */
3380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
3381 SUNXI_FUNCTION(0x0, "gpio_in"),
3382 SUNXI_FUNCTION(0x1, "gpio_out"),
3383 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
3384 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
3385 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
3386 SUNXI_FUNCTION(0x0, "gpio_in"),
3387 SUNXI_FUNCTION(0x1, "gpio_out"),
3388 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
3389 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
3390 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
3391 SUNXI_FUNCTION(0x0, "gpio_in"),
3392 SUNXI_FUNCTION(0x1, "gpio_out"),
3393 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
3394 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
3395 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
3396 SUNXI_FUNCTION(0x0, "gpio_in"),
3397 SUNXI_FUNCTION(0x1, "gpio_out"),
3398 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
3399 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
3400 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
3401 SUNXI_FUNCTION(0x0, "gpio_in"),
3402 SUNXI_FUNCTION(0x1, "gpio_out"),
3403 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
3404 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
3405 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
3406 SUNXI_FUNCTION(0x0, "gpio_in"),
3407 SUNXI_FUNCTION(0x1, "gpio_out"),
3408 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
3409 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
3410 /* Hole */
3411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
3412 SUNXI_FUNCTION(0x0, "gpio_in"),
3413 SUNXI_FUNCTION(0x1, "gpio_out"),
3414 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
3415 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
3416 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
3417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
3418 SUNXI_FUNCTION(0x0, "gpio_in"),
3419 SUNXI_FUNCTION(0x1, "gpio_out"),
3420 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
3421 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
3422 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
3423 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
3424 SUNXI_FUNCTION(0x0, "gpio_in"),
3425 SUNXI_FUNCTION(0x1, "gpio_out"),
3426 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
3427 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
3428 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
3429 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
3430 SUNXI_FUNCTION(0x0, "gpio_in"),
3431 SUNXI_FUNCTION(0x1, "gpio_out"),
3432 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
3433 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
3434 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
3435 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
3436 SUNXI_FUNCTION(0x0, "gpio_in"),
3437 SUNXI_FUNCTION(0x1, "gpio_out"),
3438 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
3439 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
3440 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
3441 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
3442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
3443 SUNXI_FUNCTION(0x0, "gpio_in"),
3444 SUNXI_FUNCTION(0x1, "gpio_out"),
3445 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
3446 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
3447 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
3448 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
3449 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
3450 SUNXI_FUNCTION(0x0, "gpio_in"),
3451 SUNXI_FUNCTION(0x1, "gpio_out"),
3452 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
3453 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
3454 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
3455 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
3456 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
3457 SUNXI_FUNCTION(0x0, "gpio_in"),
3458 SUNXI_FUNCTION(0x1, "gpio_out"),
3459 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
3460 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
3461 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
3462 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
3463 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
3464 SUNXI_FUNCTION(0x0, "gpio_in"),
3465 SUNXI_FUNCTION(0x1, "gpio_out"),
3466 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
3467 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
3468 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
3469 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
3470 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
3471 SUNXI_FUNCTION(0x0, "gpio_in"),
3472 SUNXI_FUNCTION(0x1, "gpio_out"),
3473 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
3474 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
3475 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
3476 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
3477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
3478 SUNXI_FUNCTION(0x0, "gpio_in"),
3479 SUNXI_FUNCTION(0x1, "gpio_out"),
3480 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
3481 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
3482 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
3483 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
3484 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
3485 SUNXI_FUNCTION(0x0, "gpio_in"),
3486 SUNXI_FUNCTION(0x1, "gpio_out"),
3487 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
3488 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
3489 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
3490 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
3491 /* Hole */
3492 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
3493 SUNXI_FUNCTION(0x0, "gpio_in"),
3494 SUNXI_FUNCTION(0x1, "gpio_out"),
3495 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
3496 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
3497 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
3498 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
3499 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
3500 SUNXI_FUNCTION(0x0, "gpio_in"),
3501 SUNXI_FUNCTION(0x1, "gpio_out"),
3502 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
3503 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
3504 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
3505 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
3506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
3507 SUNXI_FUNCTION(0x0, "gpio_in"),
3508 SUNXI_FUNCTION(0x1, "gpio_out"),
3509 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
3510 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
3511 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
3512 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
3513 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
3514 SUNXI_FUNCTION(0x0, "gpio_in"),
3515 SUNXI_FUNCTION(0x1, "gpio_out"),
3516 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
3517 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
3518 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
3519 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
3520 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
3521 SUNXI_FUNCTION(0x0, "gpio_in"),
3522 SUNXI_FUNCTION(0x1, "gpio_out"),
3523 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
3524 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
3525 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
3526 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
3527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
3528 SUNXI_FUNCTION(0x0, "gpio_in"),
3529 SUNXI_FUNCTION(0x1, "gpio_out"),
3530 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
3531 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
3532 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
3533 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
3534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
3535 SUNXI_FUNCTION(0x0, "gpio_in"),
3536 SUNXI_FUNCTION(0x1, "gpio_out"),
3537 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
3538 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
3539 SUNXI_FUNCTION(0x5, "ms"), /* BS */
3540 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
3541 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
3542 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
3543 SUNXI_FUNCTION(0x0, "gpio_in"),
3544 SUNXI_FUNCTION(0x1, "gpio_out"),
3545 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
3546 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
3547 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
3548 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
3549 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
3550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
3551 SUNXI_FUNCTION(0x0, "gpio_in"),
3552 SUNXI_FUNCTION(0x1, "gpio_out"),
3553 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
3554 SUNXI_FUNCTION(0x3, "emac"), /* ERXD3 */
3555 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
3556 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
3557 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
3558 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
3559 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
3560 SUNXI_FUNCTION(0x0, "gpio_in"),
3561 SUNXI_FUNCTION(0x1, "gpio_out"),
3562 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
3563 SUNXI_FUNCTION(0x3, "emac"), /* ERXD2 */
3564 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
3565 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
3566 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
3567 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
3568 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
3569 SUNXI_FUNCTION(0x0, "gpio_in"),
3570 SUNXI_FUNCTION(0x1, "gpio_out"),
3571 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
3572 SUNXI_FUNCTION(0x3, "emac"), /* ERXD1 */
3573 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
3574 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
3575 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
3576 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
3577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
3578 SUNXI_FUNCTION(0x0, "gpio_in"),
3579 SUNXI_FUNCTION(0x1, "gpio_out"),
3580 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
3581 SUNXI_FUNCTION(0x3, "emac"), /* ERXD0 */
3582 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
3583 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
3584 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
3585 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
3586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
3587 SUNXI_FUNCTION(0x0, "gpio_in"),
3588 SUNXI_FUNCTION(0x1, "gpio_out"),
3589 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
3590 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
3591 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
3592 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
3593 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
3594 SUNXI_FUNCTION(0x0, "gpio_in"),
3595 SUNXI_FUNCTION(0x1, "gpio_out"),
3596 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
3597 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
3598 SUNXI_FUNCTION(0x5, "sim"), /* RST */
3599 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
3600 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
3601 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
3602 SUNXI_FUNCTION(0x0, "gpio_in"),
3603 SUNXI_FUNCTION(0x1, "gpio_out"),
3604 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
3605 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
3606 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
3607 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
3608 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
3609 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
3610 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
3611 SUNXI_FUNCTION(0x0, "gpio_in"),
3612 SUNXI_FUNCTION(0x1, "gpio_out"),
3613 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
3614 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
3615 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
3616 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
3617 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
3618 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
3619 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
3620 SUNXI_FUNCTION(0x0, "gpio_in"),
3621 SUNXI_FUNCTION(0x1, "gpio_out"),
3622 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
3623 SUNXI_FUNCTION(0x3, "emac"), /* ETXD2 */
3624 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
3625 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
3626 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
3627 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
3628 SUNXI_FUNCTION(0x0, "gpio_in"),
3629 SUNXI_FUNCTION(0x1, "gpio_out"),
3630 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
3631 SUNXI_FUNCTION(0x3, "emac"), /* ETXD1 */
3632 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
3633 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
3634 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
3635 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
3636 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
3637 SUNXI_FUNCTION(0x0, "gpio_in"),
3638 SUNXI_FUNCTION(0x1, "gpio_out"),
3639 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
3640 SUNXI_FUNCTION(0x3, "emac"), /* ETXD0 */
3641 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
3642 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
3643 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
3644 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
3645 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
3646 SUNXI_FUNCTION(0x0, "gpio_in"),
3647 SUNXI_FUNCTION(0x1, "gpio_out"),
3648 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
3649 SUNXI_FUNCTION(0x3, "emac"), /* ERXERR */
3650 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
3651 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
3652 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
3653 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
3654 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
3655 SUNXI_FUNCTION(0x0, "gpio_in"),
3656 SUNXI_FUNCTION(0x1, "gpio_out"),
3657 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
3658 SUNXI_FUNCTION(0x3, "emac"), /* ERXDV */
3659 SUNXI_FUNCTION(0x4, "can"), /* TX */
3660 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
3661 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
3662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
3663 SUNXI_FUNCTION(0x0, "gpio_in"),
3664 SUNXI_FUNCTION(0x1, "gpio_out"),
3665 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
3666 SUNXI_FUNCTION(0x3, "emac"), /* EMDC */
3667 SUNXI_FUNCTION(0x4, "can"), /* RX */
3668 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
3669 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
3670 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
3671 SUNXI_FUNCTION(0x0, "gpio_in"),
3672 SUNXI_FUNCTION(0x1, "gpio_out"),
3673 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
3674 SUNXI_FUNCTION(0x3, "emac"), /* EMDIO */
3675 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
3676 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
3677 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
3678 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
3679 SUNXI_FUNCTION(0x0, "gpio_in"),
3680 SUNXI_FUNCTION(0x1, "gpio_out"),
3681 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
3682 SUNXI_FUNCTION(0x3, "emac"), /* ETXEN */
3683 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
3684 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
3685 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
3686 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
3687 SUNXI_FUNCTION(0x0, "gpio_in"),
3688 SUNXI_FUNCTION(0x1, "gpio_out"),
3689 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
3690 SUNXI_FUNCTION(0x3, "emac"), /* ETXCK */
3691 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
3692 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
3693 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
3694 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
3695 SUNXI_FUNCTION(0x0, "gpio_in"),
3696 SUNXI_FUNCTION(0x1, "gpio_out"),
3697 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
3698 SUNXI_FUNCTION(0x3, "emac"), /* ECRS */
3699 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
3700 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
3701 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
3702 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
3703 SUNXI_FUNCTION(0x0, "gpio_in"),
3704 SUNXI_FUNCTION(0x1, "gpio_out"),
3705 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
3706 SUNXI_FUNCTION(0x3, "emac"), /* ECOL */
3707 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
3708 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
3709 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
3710 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
3711 SUNXI_FUNCTION(0x0, "gpio_in"),
3712 SUNXI_FUNCTION(0x1, "gpio_out"),
3713 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
3714 SUNXI_FUNCTION(0x3, "emac"), /* ETXERR */
3715 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
3716 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
3717 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
3718 /* Hole */
3719 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
3720 SUNXI_FUNCTION(0x0, "gpio_in"),
3721 SUNXI_FUNCTION(0x1, "gpio_out"),
3722 SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */
3723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
3724 SUNXI_FUNCTION(0x0, "gpio_in"),
3725 SUNXI_FUNCTION(0x1, "gpio_out"),
3726 SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */
3727 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
3728 SUNXI_FUNCTION(0x0, "gpio_in"),
3729 SUNXI_FUNCTION(0x1, "gpio_out"),
3730 SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */
3731 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
3732 SUNXI_FUNCTION(0x0, "gpio_in"),
3733 SUNXI_FUNCTION(0x1, "gpio_out"),
3734 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
3735 SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */
3736 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
3737 SUNXI_FUNCTION(0x0, "gpio_in"),
3738 SUNXI_FUNCTION(0x1, "gpio_out"),
3739 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
3740 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
3741 SUNXI_FUNCTION(0x0, "gpio_in"),
3742 SUNXI_FUNCTION(0x1, "gpio_out"),
3743 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
3744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
3745 SUNXI_FUNCTION(0x0, "gpio_in"),
3746 SUNXI_FUNCTION(0x1, "gpio_out"),
3747 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
3748 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
3749 SUNXI_FUNCTION(0x0, "gpio_in"),
3750 SUNXI_FUNCTION(0x1, "gpio_out"),
3751 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
3752 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
3753 SUNXI_FUNCTION(0x0, "gpio_in"),
3754 SUNXI_FUNCTION(0x1, "gpio_out"),
3755 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
3756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
3757 SUNXI_FUNCTION(0x0, "gpio_in"),
3758 SUNXI_FUNCTION(0x1, "gpio_out"),
3759 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
3760 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
3761 SUNXI_FUNCTION(0x0, "gpio_in"),
3762 SUNXI_FUNCTION(0x1, "gpio_out"),
3763 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
3764 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
3765 SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
3766 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
3767 SUNXI_FUNCTION(0x0, "gpio_in"),
3768 SUNXI_FUNCTION(0x1, "gpio_out"),
3769 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
3770 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
3771 SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
3772 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
3773 SUNXI_FUNCTION(0x0, "gpio_in"),
3774 SUNXI_FUNCTION(0x1, "gpio_out"),
3775 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
3776 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
3777 SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
3778 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
3779 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
3780 SUNXI_FUNCTION(0x0, "gpio_in"),
3781 SUNXI_FUNCTION(0x1, "gpio_out"),
3782 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
3783 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
3784 SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
3785 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
3786 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
3787 SUNXI_FUNCTION(0x0, "gpio_in"),
3788 SUNXI_FUNCTION(0x1, "gpio_out"),
3789 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
3790 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
3791 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
3792 SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
3793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
3794 SUNXI_FUNCTION(0x0, "gpio_in"),
3795 SUNXI_FUNCTION(0x1, "gpio_out"),
3796 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
3797 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
3798 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
3799 SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
3800 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
3801 SUNXI_FUNCTION(0x0, "gpio_in"),
3802 SUNXI_FUNCTION(0x1, "gpio_out"),
3803 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
3804 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
3805 SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
3806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
3807 SUNXI_FUNCTION(0x0, "gpio_in"),
3808 SUNXI_FUNCTION(0x1, "gpio_out"),
3809 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
3810 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
3811 SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
3812 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
3813 SUNXI_FUNCTION(0x0, "gpio_in"),
3814 SUNXI_FUNCTION(0x1, "gpio_out"),
3815 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
3816 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
3817 SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
3818 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
3819 SUNXI_FUNCTION(0x0, "gpio_in"),
3820 SUNXI_FUNCTION(0x1, "gpio_out"),
3821 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
3822 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
3823 SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
3824 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
3825 SUNXI_FUNCTION(0x0, "gpio_in"),
3826 SUNXI_FUNCTION(0x1, "gpio_out"),
3827 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
3828 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
3829 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
3830 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
3831 SUNXI_FUNCTION(0x0, "gpio_in"),
3832 SUNXI_FUNCTION(0x1, "gpio_out"),
3833 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
3834 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
3835 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
3836};
3837
3838static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
3839 .pins = sun4i_a10_pins,
3840 .npins = ARRAY_SIZE(sun4i_a10_pins),
3841};
3842
3843static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
3844 .pins = sun5i_a10s_pins,
3845 .npins = ARRAY_SIZE(sun5i_a10s_pins),
3846};
3847
3848static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
3849 .pins = sun5i_a13_pins,
3850 .npins = ARRAY_SIZE(sun5i_a13_pins),
3851};
3852
3853static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
3854 .pins = sun6i_a31_pins,
3855 .npins = ARRAY_SIZE(sun6i_a31_pins),
3856};
3857
3858static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
3859 .pins = sun7i_a20_pins,
3860 .npins = ARRAY_SIZE(sun7i_a20_pins),
3861};
3862
3863#endif /* __PINCTRL_SUNXI_PINS_H */
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
deleted file mode 100644
index 552b0e97077a..000000000000
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ /dev/null
@@ -1,548 +0,0 @@
1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_SUNXI_H
14#define __PINCTRL_SUNXI_H
15
16#include <linux/kernel.h>
17#include <linux/spinlock.h>
18
19#define PA_BASE 0
20#define PB_BASE 32
21#define PC_BASE 64
22#define PD_BASE 96
23#define PE_BASE 128
24#define PF_BASE 160
25#define PG_BASE 192
26#define PH_BASE 224
27#define PI_BASE 256
28
29#define SUNXI_PINCTRL_PIN_PA0 PINCTRL_PIN(PA_BASE + 0, "PA0")
30#define SUNXI_PINCTRL_PIN_PA1 PINCTRL_PIN(PA_BASE + 1, "PA1")
31#define SUNXI_PINCTRL_PIN_PA2 PINCTRL_PIN(PA_BASE + 2, "PA2")
32#define SUNXI_PINCTRL_PIN_PA3 PINCTRL_PIN(PA_BASE + 3, "PA3")
33#define SUNXI_PINCTRL_PIN_PA4 PINCTRL_PIN(PA_BASE + 4, "PA4")
34#define SUNXI_PINCTRL_PIN_PA5 PINCTRL_PIN(PA_BASE + 5, "PA5")
35#define SUNXI_PINCTRL_PIN_PA6 PINCTRL_PIN(PA_BASE + 6, "PA6")
36#define SUNXI_PINCTRL_PIN_PA7 PINCTRL_PIN(PA_BASE + 7, "PA7")
37#define SUNXI_PINCTRL_PIN_PA8 PINCTRL_PIN(PA_BASE + 8, "PA8")
38#define SUNXI_PINCTRL_PIN_PA9 PINCTRL_PIN(PA_BASE + 9, "PA9")
39#define SUNXI_PINCTRL_PIN_PA10 PINCTRL_PIN(PA_BASE + 10, "PA10")
40#define SUNXI_PINCTRL_PIN_PA11 PINCTRL_PIN(PA_BASE + 11, "PA11")
41#define SUNXI_PINCTRL_PIN_PA12 PINCTRL_PIN(PA_BASE + 12, "PA12")
42#define SUNXI_PINCTRL_PIN_PA13 PINCTRL_PIN(PA_BASE + 13, "PA13")
43#define SUNXI_PINCTRL_PIN_PA14 PINCTRL_PIN(PA_BASE + 14, "PA14")
44#define SUNXI_PINCTRL_PIN_PA15 PINCTRL_PIN(PA_BASE + 15, "PA15")
45#define SUNXI_PINCTRL_PIN_PA16 PINCTRL_PIN(PA_BASE + 16, "PA16")
46#define SUNXI_PINCTRL_PIN_PA17 PINCTRL_PIN(PA_BASE + 17, "PA17")
47#define SUNXI_PINCTRL_PIN_PA18 PINCTRL_PIN(PA_BASE + 18, "PA18")
48#define SUNXI_PINCTRL_PIN_PA19 PINCTRL_PIN(PA_BASE + 19, "PA19")
49#define SUNXI_PINCTRL_PIN_PA20 PINCTRL_PIN(PA_BASE + 20, "PA20")
50#define SUNXI_PINCTRL_PIN_PA21 PINCTRL_PIN(PA_BASE + 21, "PA21")
51#define SUNXI_PINCTRL_PIN_PA22 PINCTRL_PIN(PA_BASE + 22, "PA22")
52#define SUNXI_PINCTRL_PIN_PA23 PINCTRL_PIN(PA_BASE + 23, "PA23")
53#define SUNXI_PINCTRL_PIN_PA24 PINCTRL_PIN(PA_BASE + 24, "PA24")
54#define SUNXI_PINCTRL_PIN_PA25 PINCTRL_PIN(PA_BASE + 25, "PA25")
55#define SUNXI_PINCTRL_PIN_PA26 PINCTRL_PIN(PA_BASE + 26, "PA26")
56#define SUNXI_PINCTRL_PIN_PA27 PINCTRL_PIN(PA_BASE + 27, "PA27")
57#define SUNXI_PINCTRL_PIN_PA28 PINCTRL_PIN(PA_BASE + 28, "PA28")
58#define SUNXI_PINCTRL_PIN_PA29 PINCTRL_PIN(PA_BASE + 29, "PA29")
59#define SUNXI_PINCTRL_PIN_PA30 PINCTRL_PIN(PA_BASE + 30, "PA30")
60#define SUNXI_PINCTRL_PIN_PA31 PINCTRL_PIN(PA_BASE + 31, "PA31")
61
62#define SUNXI_PINCTRL_PIN_PB0 PINCTRL_PIN(PB_BASE + 0, "PB0")
63#define SUNXI_PINCTRL_PIN_PB1 PINCTRL_PIN(PB_BASE + 1, "PB1")
64#define SUNXI_PINCTRL_PIN_PB2 PINCTRL_PIN(PB_BASE + 2, "PB2")
65#define SUNXI_PINCTRL_PIN_PB3 PINCTRL_PIN(PB_BASE + 3, "PB3")
66#define SUNXI_PINCTRL_PIN_PB4 PINCTRL_PIN(PB_BASE + 4, "PB4")
67#define SUNXI_PINCTRL_PIN_PB5 PINCTRL_PIN(PB_BASE + 5, "PB5")
68#define SUNXI_PINCTRL_PIN_PB6 PINCTRL_PIN(PB_BASE + 6, "PB6")
69#define SUNXI_PINCTRL_PIN_PB7 PINCTRL_PIN(PB_BASE + 7, "PB7")
70#define SUNXI_PINCTRL_PIN_PB8 PINCTRL_PIN(PB_BASE + 8, "PB8")
71#define SUNXI_PINCTRL_PIN_PB9 PINCTRL_PIN(PB_BASE + 9, "PB9")
72#define SUNXI_PINCTRL_PIN_PB10 PINCTRL_PIN(PB_BASE + 10, "PB10")
73#define SUNXI_PINCTRL_PIN_PB11 PINCTRL_PIN(PB_BASE + 11, "PB11")
74#define SUNXI_PINCTRL_PIN_PB12 PINCTRL_PIN(PB_BASE + 12, "PB12")
75#define SUNXI_PINCTRL_PIN_PB13 PINCTRL_PIN(PB_BASE + 13, "PB13")
76#define SUNXI_PINCTRL_PIN_PB14 PINCTRL_PIN(PB_BASE + 14, "PB14")
77#define SUNXI_PINCTRL_PIN_PB15 PINCTRL_PIN(PB_BASE + 15, "PB15")
78#define SUNXI_PINCTRL_PIN_PB16 PINCTRL_PIN(PB_BASE + 16, "PB16")
79#define SUNXI_PINCTRL_PIN_PB17 PINCTRL_PIN(PB_BASE + 17, "PB17")
80#define SUNXI_PINCTRL_PIN_PB18 PINCTRL_PIN(PB_BASE + 18, "PB18")
81#define SUNXI_PINCTRL_PIN_PB19 PINCTRL_PIN(PB_BASE + 19, "PB19")
82#define SUNXI_PINCTRL_PIN_PB20 PINCTRL_PIN(PB_BASE + 20, "PB20")
83#define SUNXI_PINCTRL_PIN_PB21 PINCTRL_PIN(PB_BASE + 21, "PB21")
84#define SUNXI_PINCTRL_PIN_PB22 PINCTRL_PIN(PB_BASE + 22, "PB22")
85#define SUNXI_PINCTRL_PIN_PB23 PINCTRL_PIN(PB_BASE + 23, "PB23")
86#define SUNXI_PINCTRL_PIN_PB24 PINCTRL_PIN(PB_BASE + 24, "PB24")
87#define SUNXI_PINCTRL_PIN_PB25 PINCTRL_PIN(PB_BASE + 25, "PB25")
88#define SUNXI_PINCTRL_PIN_PB26 PINCTRL_PIN(PB_BASE + 26, "PB26")
89#define SUNXI_PINCTRL_PIN_PB27 PINCTRL_PIN(PB_BASE + 27, "PB27")
90#define SUNXI_PINCTRL_PIN_PB28 PINCTRL_PIN(PB_BASE + 28, "PB28")
91#define SUNXI_PINCTRL_PIN_PB29 PINCTRL_PIN(PB_BASE + 29, "PB29")
92#define SUNXI_PINCTRL_PIN_PB30 PINCTRL_PIN(PB_BASE + 30, "PB30")
93#define SUNXI_PINCTRL_PIN_PB31 PINCTRL_PIN(PB_BASE + 31, "PB31")
94
95#define SUNXI_PINCTRL_PIN_PC0 PINCTRL_PIN(PC_BASE + 0, "PC0")
96#define SUNXI_PINCTRL_PIN_PC1 PINCTRL_PIN(PC_BASE + 1, "PC1")
97#define SUNXI_PINCTRL_PIN_PC2 PINCTRL_PIN(PC_BASE + 2, "PC2")
98#define SUNXI_PINCTRL_PIN_PC3 PINCTRL_PIN(PC_BASE + 3, "PC3")
99#define SUNXI_PINCTRL_PIN_PC4 PINCTRL_PIN(PC_BASE + 4, "PC4")
100#define SUNXI_PINCTRL_PIN_PC5 PINCTRL_PIN(PC_BASE + 5, "PC5")
101#define SUNXI_PINCTRL_PIN_PC6 PINCTRL_PIN(PC_BASE + 6, "PC6")
102#define SUNXI_PINCTRL_PIN_PC7 PINCTRL_PIN(PC_BASE + 7, "PC7")
103#define SUNXI_PINCTRL_PIN_PC8 PINCTRL_PIN(PC_BASE + 8, "PC8")
104#define SUNXI_PINCTRL_PIN_PC9 PINCTRL_PIN(PC_BASE + 9, "PC9")
105#define SUNXI_PINCTRL_PIN_PC10 PINCTRL_PIN(PC_BASE + 10, "PC10")
106#define SUNXI_PINCTRL_PIN_PC11 PINCTRL_PIN(PC_BASE + 11, "PC11")
107#define SUNXI_PINCTRL_PIN_PC12 PINCTRL_PIN(PC_BASE + 12, "PC12")
108#define SUNXI_PINCTRL_PIN_PC13 PINCTRL_PIN(PC_BASE + 13, "PC13")
109#define SUNXI_PINCTRL_PIN_PC14 PINCTRL_PIN(PC_BASE + 14, "PC14")
110#define SUNXI_PINCTRL_PIN_PC15 PINCTRL_PIN(PC_BASE + 15, "PC15")
111#define SUNXI_PINCTRL_PIN_PC16 PINCTRL_PIN(PC_BASE + 16, "PC16")
112#define SUNXI_PINCTRL_PIN_PC17 PINCTRL_PIN(PC_BASE + 17, "PC17")
113#define SUNXI_PINCTRL_PIN_PC18 PINCTRL_PIN(PC_BASE + 18, "PC18")
114#define SUNXI_PINCTRL_PIN_PC19 PINCTRL_PIN(PC_BASE + 19, "PC19")
115#define SUNXI_PINCTRL_PIN_PC20 PINCTRL_PIN(PC_BASE + 20, "PC20")
116#define SUNXI_PINCTRL_PIN_PC21 PINCTRL_PIN(PC_BASE + 21, "PC21")
117#define SUNXI_PINCTRL_PIN_PC22 PINCTRL_PIN(PC_BASE + 22, "PC22")
118#define SUNXI_PINCTRL_PIN_PC23 PINCTRL_PIN(PC_BASE + 23, "PC23")
119#define SUNXI_PINCTRL_PIN_PC24 PINCTRL_PIN(PC_BASE + 24, "PC24")
120#define SUNXI_PINCTRL_PIN_PC25 PINCTRL_PIN(PC_BASE + 25, "PC25")
121#define SUNXI_PINCTRL_PIN_PC26 PINCTRL_PIN(PC_BASE + 26, "PC26")
122#define SUNXI_PINCTRL_PIN_PC27 PINCTRL_PIN(PC_BASE + 27, "PC27")
123#define SUNXI_PINCTRL_PIN_PC28 PINCTRL_PIN(PC_BASE + 28, "PC28")
124#define SUNXI_PINCTRL_PIN_PC29 PINCTRL_PIN(PC_BASE + 29, "PC29")
125#define SUNXI_PINCTRL_PIN_PC30 PINCTRL_PIN(PC_BASE + 30, "PC30")
126#define SUNXI_PINCTRL_PIN_PC31 PINCTRL_PIN(PC_BASE + 31, "PC31")
127
128#define SUNXI_PINCTRL_PIN_PD0 PINCTRL_PIN(PD_BASE + 0, "PD0")
129#define SUNXI_PINCTRL_PIN_PD1 PINCTRL_PIN(PD_BASE + 1, "PD1")
130#define SUNXI_PINCTRL_PIN_PD2 PINCTRL_PIN(PD_BASE + 2, "PD2")
131#define SUNXI_PINCTRL_PIN_PD3 PINCTRL_PIN(PD_BASE + 3, "PD3")
132#define SUNXI_PINCTRL_PIN_PD4 PINCTRL_PIN(PD_BASE + 4, "PD4")
133#define SUNXI_PINCTRL_PIN_PD5 PINCTRL_PIN(PD_BASE + 5, "PD5")
134#define SUNXI_PINCTRL_PIN_PD6 PINCTRL_PIN(PD_BASE + 6, "PD6")
135#define SUNXI_PINCTRL_PIN_PD7 PINCTRL_PIN(PD_BASE + 7, "PD7")
136#define SUNXI_PINCTRL_PIN_PD8 PINCTRL_PIN(PD_BASE + 8, "PD8")
137#define SUNXI_PINCTRL_PIN_PD9 PINCTRL_PIN(PD_BASE + 9, "PD9")
138#define SUNXI_PINCTRL_PIN_PD10 PINCTRL_PIN(PD_BASE + 10, "PD10")
139#define SUNXI_PINCTRL_PIN_PD11 PINCTRL_PIN(PD_BASE + 11, "PD11")
140#define SUNXI_PINCTRL_PIN_PD12 PINCTRL_PIN(PD_BASE + 12, "PD12")
141#define SUNXI_PINCTRL_PIN_PD13 PINCTRL_PIN(PD_BASE + 13, "PD13")
142#define SUNXI_PINCTRL_PIN_PD14 PINCTRL_PIN(PD_BASE + 14, "PD14")
143#define SUNXI_PINCTRL_PIN_PD15 PINCTRL_PIN(PD_BASE + 15, "PD15")
144#define SUNXI_PINCTRL_PIN_PD16 PINCTRL_PIN(PD_BASE + 16, "PD16")
145#define SUNXI_PINCTRL_PIN_PD17 PINCTRL_PIN(PD_BASE + 17, "PD17")
146#define SUNXI_PINCTRL_PIN_PD18 PINCTRL_PIN(PD_BASE + 18, "PD18")
147#define SUNXI_PINCTRL_PIN_PD19 PINCTRL_PIN(PD_BASE + 19, "PD19")
148#define SUNXI_PINCTRL_PIN_PD20 PINCTRL_PIN(PD_BASE + 20, "PD20")
149#define SUNXI_PINCTRL_PIN_PD21 PINCTRL_PIN(PD_BASE + 21, "PD21")
150#define SUNXI_PINCTRL_PIN_PD22 PINCTRL_PIN(PD_BASE + 22, "PD22")
151#define SUNXI_PINCTRL_PIN_PD23 PINCTRL_PIN(PD_BASE + 23, "PD23")
152#define SUNXI_PINCTRL_PIN_PD24 PINCTRL_PIN(PD_BASE + 24, "PD24")
153#define SUNXI_PINCTRL_PIN_PD25 PINCTRL_PIN(PD_BASE + 25, "PD25")
154#define SUNXI_PINCTRL_PIN_PD26 PINCTRL_PIN(PD_BASE + 26, "PD26")
155#define SUNXI_PINCTRL_PIN_PD27 PINCTRL_PIN(PD_BASE + 27, "PD27")
156#define SUNXI_PINCTRL_PIN_PD28 PINCTRL_PIN(PD_BASE + 28, "PD28")
157#define SUNXI_PINCTRL_PIN_PD29 PINCTRL_PIN(PD_BASE + 29, "PD29")
158#define SUNXI_PINCTRL_PIN_PD30 PINCTRL_PIN(PD_BASE + 30, "PD30")
159#define SUNXI_PINCTRL_PIN_PD31 PINCTRL_PIN(PD_BASE + 31, "PD31")
160
161#define SUNXI_PINCTRL_PIN_PE0 PINCTRL_PIN(PE_BASE + 0, "PE0")
162#define SUNXI_PINCTRL_PIN_PE1 PINCTRL_PIN(PE_BASE + 1, "PE1")
163#define SUNXI_PINCTRL_PIN_PE2 PINCTRL_PIN(PE_BASE + 2, "PE2")
164#define SUNXI_PINCTRL_PIN_PE3 PINCTRL_PIN(PE_BASE + 3, "PE3")
165#define SUNXI_PINCTRL_PIN_PE4 PINCTRL_PIN(PE_BASE + 4, "PE4")
166#define SUNXI_PINCTRL_PIN_PE5 PINCTRL_PIN(PE_BASE + 5, "PE5")
167#define SUNXI_PINCTRL_PIN_PE6 PINCTRL_PIN(PE_BASE + 6, "PE6")
168#define SUNXI_PINCTRL_PIN_PE7 PINCTRL_PIN(PE_BASE + 7, "PE7")
169#define SUNXI_PINCTRL_PIN_PE8 PINCTRL_PIN(PE_BASE + 8, "PE8")
170#define SUNXI_PINCTRL_PIN_PE9 PINCTRL_PIN(PE_BASE + 9, "PE9")
171#define SUNXI_PINCTRL_PIN_PE10 PINCTRL_PIN(PE_BASE + 10, "PE10")
172#define SUNXI_PINCTRL_PIN_PE11 PINCTRL_PIN(PE_BASE + 11, "PE11")
173#define SUNXI_PINCTRL_PIN_PE12 PINCTRL_PIN(PE_BASE + 12, "PE12")
174#define SUNXI_PINCTRL_PIN_PE13 PINCTRL_PIN(PE_BASE + 13, "PE13")
175#define SUNXI_PINCTRL_PIN_PE14 PINCTRL_PIN(PE_BASE + 14, "PE14")
176#define SUNXI_PINCTRL_PIN_PE15 PINCTRL_PIN(PE_BASE + 15, "PE15")
177#define SUNXI_PINCTRL_PIN_PE16 PINCTRL_PIN(PE_BASE + 16, "PE16")
178#define SUNXI_PINCTRL_PIN_PE17 PINCTRL_PIN(PE_BASE + 17, "PE17")
179#define SUNXI_PINCTRL_PIN_PE18 PINCTRL_PIN(PE_BASE + 18, "PE18")
180#define SUNXI_PINCTRL_PIN_PE19 PINCTRL_PIN(PE_BASE + 19, "PE19")
181#define SUNXI_PINCTRL_PIN_PE20 PINCTRL_PIN(PE_BASE + 20, "PE20")
182#define SUNXI_PINCTRL_PIN_PE21 PINCTRL_PIN(PE_BASE + 21, "PE21")
183#define SUNXI_PINCTRL_PIN_PE22 PINCTRL_PIN(PE_BASE + 22, "PE22")
184#define SUNXI_PINCTRL_PIN_PE23 PINCTRL_PIN(PE_BASE + 23, "PE23")
185#define SUNXI_PINCTRL_PIN_PE24 PINCTRL_PIN(PE_BASE + 24, "PE24")
186#define SUNXI_PINCTRL_PIN_PE25 PINCTRL_PIN(PE_BASE + 25, "PE25")
187#define SUNXI_PINCTRL_PIN_PE26 PINCTRL_PIN(PE_BASE + 26, "PE26")
188#define SUNXI_PINCTRL_PIN_PE27 PINCTRL_PIN(PE_BASE + 27, "PE27")
189#define SUNXI_PINCTRL_PIN_PE28 PINCTRL_PIN(PE_BASE + 28, "PE28")
190#define SUNXI_PINCTRL_PIN_PE29 PINCTRL_PIN(PE_BASE + 29, "PE29")
191#define SUNXI_PINCTRL_PIN_PE30 PINCTRL_PIN(PE_BASE + 30, "PE30")
192#define SUNXI_PINCTRL_PIN_PE31 PINCTRL_PIN(PE_BASE + 31, "PE31")
193
194#define SUNXI_PINCTRL_PIN_PF0 PINCTRL_PIN(PF_BASE + 0, "PF0")
195#define SUNXI_PINCTRL_PIN_PF1 PINCTRL_PIN(PF_BASE + 1, "PF1")
196#define SUNXI_PINCTRL_PIN_PF2 PINCTRL_PIN(PF_BASE + 2, "PF2")
197#define SUNXI_PINCTRL_PIN_PF3 PINCTRL_PIN(PF_BASE + 3, "PF3")
198#define SUNXI_PINCTRL_PIN_PF4 PINCTRL_PIN(PF_BASE + 4, "PF4")
199#define SUNXI_PINCTRL_PIN_PF5 PINCTRL_PIN(PF_BASE + 5, "PF5")
200#define SUNXI_PINCTRL_PIN_PF6 PINCTRL_PIN(PF_BASE + 6, "PF6")
201#define SUNXI_PINCTRL_PIN_PF7 PINCTRL_PIN(PF_BASE + 7, "PF7")
202#define SUNXI_PINCTRL_PIN_PF8 PINCTRL_PIN(PF_BASE + 8, "PF8")
203#define SUNXI_PINCTRL_PIN_PF9 PINCTRL_PIN(PF_BASE + 9, "PF9")
204#define SUNXI_PINCTRL_PIN_PF10 PINCTRL_PIN(PF_BASE + 10, "PF10")
205#define SUNXI_PINCTRL_PIN_PF11 PINCTRL_PIN(PF_BASE + 11, "PF11")
206#define SUNXI_PINCTRL_PIN_PF12 PINCTRL_PIN(PF_BASE + 12, "PF12")
207#define SUNXI_PINCTRL_PIN_PF13 PINCTRL_PIN(PF_BASE + 13, "PF13")
208#define SUNXI_PINCTRL_PIN_PF14 PINCTRL_PIN(PF_BASE + 14, "PF14")
209#define SUNXI_PINCTRL_PIN_PF15 PINCTRL_PIN(PF_BASE + 15, "PF15")
210#define SUNXI_PINCTRL_PIN_PF16 PINCTRL_PIN(PF_BASE + 16, "PF16")
211#define SUNXI_PINCTRL_PIN_PF17 PINCTRL_PIN(PF_BASE + 17, "PF17")
212#define SUNXI_PINCTRL_PIN_PF18 PINCTRL_PIN(PF_BASE + 18, "PF18")
213#define SUNXI_PINCTRL_PIN_PF19 PINCTRL_PIN(PF_BASE + 19, "PF19")
214#define SUNXI_PINCTRL_PIN_PF20 PINCTRL_PIN(PF_BASE + 20, "PF20")
215#define SUNXI_PINCTRL_PIN_PF21 PINCTRL_PIN(PF_BASE + 21, "PF21")
216#define SUNXI_PINCTRL_PIN_PF22 PINCTRL_PIN(PF_BASE + 22, "PF22")
217#define SUNXI_PINCTRL_PIN_PF23 PINCTRL_PIN(PF_BASE + 23, "PF23")
218#define SUNXI_PINCTRL_PIN_PF24 PINCTRL_PIN(PF_BASE + 24, "PF24")
219#define SUNXI_PINCTRL_PIN_PF25 PINCTRL_PIN(PF_BASE + 25, "PF25")
220#define SUNXI_PINCTRL_PIN_PF26 PINCTRL_PIN(PF_BASE + 26, "PF26")
221#define SUNXI_PINCTRL_PIN_PF27 PINCTRL_PIN(PF_BASE + 27, "PF27")
222#define SUNXI_PINCTRL_PIN_PF28 PINCTRL_PIN(PF_BASE + 28, "PF28")
223#define SUNXI_PINCTRL_PIN_PF29 PINCTRL_PIN(PF_BASE + 29, "PF29")
224#define SUNXI_PINCTRL_PIN_PF30 PINCTRL_PIN(PF_BASE + 30, "PF30")
225#define SUNXI_PINCTRL_PIN_PF31 PINCTRL_PIN(PF_BASE + 31, "PF31")
226
227#define SUNXI_PINCTRL_PIN_PG0 PINCTRL_PIN(PG_BASE + 0, "PG0")
228#define SUNXI_PINCTRL_PIN_PG1 PINCTRL_PIN(PG_BASE + 1, "PG1")
229#define SUNXI_PINCTRL_PIN_PG2 PINCTRL_PIN(PG_BASE + 2, "PG2")
230#define SUNXI_PINCTRL_PIN_PG3 PINCTRL_PIN(PG_BASE + 3, "PG3")
231#define SUNXI_PINCTRL_PIN_PG4 PINCTRL_PIN(PG_BASE + 4, "PG4")
232#define SUNXI_PINCTRL_PIN_PG5 PINCTRL_PIN(PG_BASE + 5, "PG5")
233#define SUNXI_PINCTRL_PIN_PG6 PINCTRL_PIN(PG_BASE + 6, "PG6")
234#define SUNXI_PINCTRL_PIN_PG7 PINCTRL_PIN(PG_BASE + 7, "PG7")
235#define SUNXI_PINCTRL_PIN_PG8 PINCTRL_PIN(PG_BASE + 8, "PG8")
236#define SUNXI_PINCTRL_PIN_PG9 PINCTRL_PIN(PG_BASE + 9, "PG9")
237#define SUNXI_PINCTRL_PIN_PG10 PINCTRL_PIN(PG_BASE + 10, "PG10")
238#define SUNXI_PINCTRL_PIN_PG11 PINCTRL_PIN(PG_BASE + 11, "PG11")
239#define SUNXI_PINCTRL_PIN_PG12 PINCTRL_PIN(PG_BASE + 12, "PG12")
240#define SUNXI_PINCTRL_PIN_PG13 PINCTRL_PIN(PG_BASE + 13, "PG13")
241#define SUNXI_PINCTRL_PIN_PG14 PINCTRL_PIN(PG_BASE + 14, "PG14")
242#define SUNXI_PINCTRL_PIN_PG15 PINCTRL_PIN(PG_BASE + 15, "PG15")
243#define SUNXI_PINCTRL_PIN_PG16 PINCTRL_PIN(PG_BASE + 16, "PG16")
244#define SUNXI_PINCTRL_PIN_PG17 PINCTRL_PIN(PG_BASE + 17, "PG17")
245#define SUNXI_PINCTRL_PIN_PG18 PINCTRL_PIN(PG_BASE + 18, "PG18")
246#define SUNXI_PINCTRL_PIN_PG19 PINCTRL_PIN(PG_BASE + 19, "PG19")
247#define SUNXI_PINCTRL_PIN_PG20 PINCTRL_PIN(PG_BASE + 20, "PG20")
248#define SUNXI_PINCTRL_PIN_PG21 PINCTRL_PIN(PG_BASE + 21, "PG21")
249#define SUNXI_PINCTRL_PIN_PG22 PINCTRL_PIN(PG_BASE + 22, "PG22")
250#define SUNXI_PINCTRL_PIN_PG23 PINCTRL_PIN(PG_BASE + 23, "PG23")
251#define SUNXI_PINCTRL_PIN_PG24 PINCTRL_PIN(PG_BASE + 24, "PG24")
252#define SUNXI_PINCTRL_PIN_PG25 PINCTRL_PIN(PG_BASE + 25, "PG25")
253#define SUNXI_PINCTRL_PIN_PG26 PINCTRL_PIN(PG_BASE + 26, "PG26")
254#define SUNXI_PINCTRL_PIN_PG27 PINCTRL_PIN(PG_BASE + 27, "PG27")
255#define SUNXI_PINCTRL_PIN_PG28 PINCTRL_PIN(PG_BASE + 28, "PG28")
256#define SUNXI_PINCTRL_PIN_PG29 PINCTRL_PIN(PG_BASE + 29, "PG29")
257#define SUNXI_PINCTRL_PIN_PG30 PINCTRL_PIN(PG_BASE + 30, "PG30")
258#define SUNXI_PINCTRL_PIN_PG31 PINCTRL_PIN(PG_BASE + 31, "PG31")
259
260#define SUNXI_PINCTRL_PIN_PH0 PINCTRL_PIN(PH_BASE + 0, "PH0")
261#define SUNXI_PINCTRL_PIN_PH1 PINCTRL_PIN(PH_BASE + 1, "PH1")
262#define SUNXI_PINCTRL_PIN_PH2 PINCTRL_PIN(PH_BASE + 2, "PH2")
263#define SUNXI_PINCTRL_PIN_PH3 PINCTRL_PIN(PH_BASE + 3, "PH3")
264#define SUNXI_PINCTRL_PIN_PH4 PINCTRL_PIN(PH_BASE + 4, "PH4")
265#define SUNXI_PINCTRL_PIN_PH5 PINCTRL_PIN(PH_BASE + 5, "PH5")
266#define SUNXI_PINCTRL_PIN_PH6 PINCTRL_PIN(PH_BASE + 6, "PH6")
267#define SUNXI_PINCTRL_PIN_PH7 PINCTRL_PIN(PH_BASE + 7, "PH7")
268#define SUNXI_PINCTRL_PIN_PH8 PINCTRL_PIN(PH_BASE + 8, "PH8")
269#define SUNXI_PINCTRL_PIN_PH9 PINCTRL_PIN(PH_BASE + 9, "PH9")
270#define SUNXI_PINCTRL_PIN_PH10 PINCTRL_PIN(PH_BASE + 10, "PH10")
271#define SUNXI_PINCTRL_PIN_PH11 PINCTRL_PIN(PH_BASE + 11, "PH11")
272#define SUNXI_PINCTRL_PIN_PH12 PINCTRL_PIN(PH_BASE + 12, "PH12")
273#define SUNXI_PINCTRL_PIN_PH13 PINCTRL_PIN(PH_BASE + 13, "PH13")
274#define SUNXI_PINCTRL_PIN_PH14 PINCTRL_PIN(PH_BASE + 14, "PH14")
275#define SUNXI_PINCTRL_PIN_PH15 PINCTRL_PIN(PH_BASE + 15, "PH15")
276#define SUNXI_PINCTRL_PIN_PH16 PINCTRL_PIN(PH_BASE + 16, "PH16")
277#define SUNXI_PINCTRL_PIN_PH17 PINCTRL_PIN(PH_BASE + 17, "PH17")
278#define SUNXI_PINCTRL_PIN_PH18 PINCTRL_PIN(PH_BASE + 18, "PH18")
279#define SUNXI_PINCTRL_PIN_PH19 PINCTRL_PIN(PH_BASE + 19, "PH19")
280#define SUNXI_PINCTRL_PIN_PH20 PINCTRL_PIN(PH_BASE + 20, "PH20")
281#define SUNXI_PINCTRL_PIN_PH21 PINCTRL_PIN(PH_BASE + 21, "PH21")
282#define SUNXI_PINCTRL_PIN_PH22 PINCTRL_PIN(PH_BASE + 22, "PH22")
283#define SUNXI_PINCTRL_PIN_PH23 PINCTRL_PIN(PH_BASE + 23, "PH23")
284#define SUNXI_PINCTRL_PIN_PH24 PINCTRL_PIN(PH_BASE + 24, "PH24")
285#define SUNXI_PINCTRL_PIN_PH25 PINCTRL_PIN(PH_BASE + 25, "PH25")
286#define SUNXI_PINCTRL_PIN_PH26 PINCTRL_PIN(PH_BASE + 26, "PH26")
287#define SUNXI_PINCTRL_PIN_PH27 PINCTRL_PIN(PH_BASE + 27, "PH27")
288#define SUNXI_PINCTRL_PIN_PH28 PINCTRL_PIN(PH_BASE + 28, "PH28")
289#define SUNXI_PINCTRL_PIN_PH29 PINCTRL_PIN(PH_BASE + 29, "PH29")
290#define SUNXI_PINCTRL_PIN_PH30 PINCTRL_PIN(PH_BASE + 30, "PH30")
291#define SUNXI_PINCTRL_PIN_PH31 PINCTRL_PIN(PH_BASE + 31, "PH31")
292
293#define SUNXI_PINCTRL_PIN_PI0 PINCTRL_PIN(PI_BASE + 0, "PI0")
294#define SUNXI_PINCTRL_PIN_PI1 PINCTRL_PIN(PI_BASE + 1, "PI1")
295#define SUNXI_PINCTRL_PIN_PI2 PINCTRL_PIN(PI_BASE + 2, "PI2")
296#define SUNXI_PINCTRL_PIN_PI3 PINCTRL_PIN(PI_BASE + 3, "PI3")
297#define SUNXI_PINCTRL_PIN_PI4 PINCTRL_PIN(PI_BASE + 4, "PI4")
298#define SUNXI_PINCTRL_PIN_PI5 PINCTRL_PIN(PI_BASE + 5, "PI5")
299#define SUNXI_PINCTRL_PIN_PI6 PINCTRL_PIN(PI_BASE + 6, "PI6")
300#define SUNXI_PINCTRL_PIN_PI7 PINCTRL_PIN(PI_BASE + 7, "PI7")
301#define SUNXI_PINCTRL_PIN_PI8 PINCTRL_PIN(PI_BASE + 8, "PI8")
302#define SUNXI_PINCTRL_PIN_PI9 PINCTRL_PIN(PI_BASE + 9, "PI9")
303#define SUNXI_PINCTRL_PIN_PI10 PINCTRL_PIN(PI_BASE + 10, "PI10")
304#define SUNXI_PINCTRL_PIN_PI11 PINCTRL_PIN(PI_BASE + 11, "PI11")
305#define SUNXI_PINCTRL_PIN_PI12 PINCTRL_PIN(PI_BASE + 12, "PI12")
306#define SUNXI_PINCTRL_PIN_PI13 PINCTRL_PIN(PI_BASE + 13, "PI13")
307#define SUNXI_PINCTRL_PIN_PI14 PINCTRL_PIN(PI_BASE + 14, "PI14")
308#define SUNXI_PINCTRL_PIN_PI15 PINCTRL_PIN(PI_BASE + 15, "PI15")
309#define SUNXI_PINCTRL_PIN_PI16 PINCTRL_PIN(PI_BASE + 16, "PI16")
310#define SUNXI_PINCTRL_PIN_PI17 PINCTRL_PIN(PI_BASE + 17, "PI17")
311#define SUNXI_PINCTRL_PIN_PI18 PINCTRL_PIN(PI_BASE + 18, "PI18")
312#define SUNXI_PINCTRL_PIN_PI19 PINCTRL_PIN(PI_BASE + 19, "PI19")
313#define SUNXI_PINCTRL_PIN_PI20 PINCTRL_PIN(PI_BASE + 20, "PI20")
314#define SUNXI_PINCTRL_PIN_PI21 PINCTRL_PIN(PI_BASE + 21, "PI21")
315#define SUNXI_PINCTRL_PIN_PI22 PINCTRL_PIN(PI_BASE + 22, "PI22")
316#define SUNXI_PINCTRL_PIN_PI23 PINCTRL_PIN(PI_BASE + 23, "PI23")
317#define SUNXI_PINCTRL_PIN_PI24 PINCTRL_PIN(PI_BASE + 24, "PI24")
318#define SUNXI_PINCTRL_PIN_PI25 PINCTRL_PIN(PI_BASE + 25, "PI25")
319#define SUNXI_PINCTRL_PIN_PI26 PINCTRL_PIN(PI_BASE + 26, "PI26")
320#define SUNXI_PINCTRL_PIN_PI27 PINCTRL_PIN(PI_BASE + 27, "PI27")
321#define SUNXI_PINCTRL_PIN_PI28 PINCTRL_PIN(PI_BASE + 28, "PI28")
322#define SUNXI_PINCTRL_PIN_PI29 PINCTRL_PIN(PI_BASE + 29, "PI29")
323#define SUNXI_PINCTRL_PIN_PI30 PINCTRL_PIN(PI_BASE + 30, "PI30")
324#define SUNXI_PINCTRL_PIN_PI31 PINCTRL_PIN(PI_BASE + 31, "PI31")
325
326#define SUNXI_PIN_NAME_MAX_LEN 5
327
328#define BANK_MEM_SIZE 0x24
329#define MUX_REGS_OFFSET 0x0
330#define DATA_REGS_OFFSET 0x10
331#define DLEVEL_REGS_OFFSET 0x14
332#define PULL_REGS_OFFSET 0x1c
333
334#define PINS_PER_BANK 32
335#define MUX_PINS_PER_REG 8
336#define MUX_PINS_BITS 4
337#define MUX_PINS_MASK 0x0f
338#define DATA_PINS_PER_REG 32
339#define DATA_PINS_BITS 1
340#define DATA_PINS_MASK 0x01
341#define DLEVEL_PINS_PER_REG 16
342#define DLEVEL_PINS_BITS 2
343#define DLEVEL_PINS_MASK 0x03
344#define PULL_PINS_PER_REG 16
345#define PULL_PINS_BITS 2
346#define PULL_PINS_MASK 0x03
347
348#define SUNXI_IRQ_NUMBER 32
349
350#define IRQ_CFG_REG 0x200
351#define IRQ_CFG_IRQ_PER_REG 8
352#define IRQ_CFG_IRQ_BITS 4
353#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
354#define IRQ_CTRL_REG 0x210
355#define IRQ_CTRL_IRQ_PER_REG 32
356#define IRQ_CTRL_IRQ_BITS 1
357#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
358#define IRQ_STATUS_REG 0x214
359#define IRQ_STATUS_IRQ_PER_REG 32
360#define IRQ_STATUS_IRQ_BITS 1
361#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
362
363#define IRQ_EDGE_RISING 0x00
364#define IRQ_EDGE_FALLING 0x01
365#define IRQ_LEVEL_HIGH 0x02
366#define IRQ_LEVEL_LOW 0x03
367#define IRQ_EDGE_BOTH 0x04
368
369struct sunxi_desc_function {
370 const char *name;
371 u8 muxval;
372 u8 irqnum;
373};
374
375struct sunxi_desc_pin {
376 struct pinctrl_pin_desc pin;
377 struct sunxi_desc_function *functions;
378};
379
380struct sunxi_pinctrl_desc {
381 const struct sunxi_desc_pin *pins;
382 int npins;
383 struct pinctrl_gpio_range *ranges;
384 int nranges;
385};
386
387struct sunxi_pinctrl_function {
388 const char *name;
389 const char **groups;
390 unsigned ngroups;
391};
392
393struct sunxi_pinctrl_group {
394 const char *name;
395 unsigned long config;
396 unsigned pin;
397};
398
399struct sunxi_pinctrl {
400 void __iomem *membase;
401 struct gpio_chip *chip;
402 struct sunxi_pinctrl_desc *desc;
403 struct device *dev;
404 struct irq_domain *domain;
405 struct sunxi_pinctrl_function *functions;
406 unsigned nfunctions;
407 struct sunxi_pinctrl_group *groups;
408 unsigned ngroups;
409 int irq;
410 int irq_array[SUNXI_IRQ_NUMBER];
411 spinlock_t lock;
412 struct pinctrl_dev *pctl_dev;
413};
414
415#define SUNXI_PIN(_pin, ...) \
416 { \
417 .pin = _pin, \
418 .functions = (struct sunxi_desc_function[]){ \
419 __VA_ARGS__, { } }, \
420 }
421
422#define SUNXI_FUNCTION(_val, _name) \
423 { \
424 .name = _name, \
425 .muxval = _val, \
426 }
427
428#define SUNXI_FUNCTION_IRQ(_val, _irq) \
429 { \
430 .name = "irq", \
431 .muxval = _val, \
432 .irqnum = _irq, \
433 }
434
435/*
436 * The sunXi PIO registers are organized as is:
437 * 0x00 - 0x0c Muxing values.
438 * 8 pins per register, each pin having a 4bits value
439 * 0x10 Pin values
440 * 32 bits per register, each pin corresponding to one bit
441 * 0x14 - 0x18 Drive level
442 * 16 pins per register, each pin having a 2bits value
443 * 0x1c - 0x20 Pull-Up values
444 * 16 pins per register, each pin having a 2bits value
445 *
446 * This is for the first bank. Each bank will have the same layout,
447 * with an offset being a multiple of 0x24.
448 *
449 * The following functions calculate from the pin number the register
450 * and the bit offset that we should access.
451 */
452static inline u32 sunxi_mux_reg(u16 pin)
453{
454 u8 bank = pin / PINS_PER_BANK;
455 u32 offset = bank * BANK_MEM_SIZE;
456 offset += MUX_REGS_OFFSET;
457 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
458 return round_down(offset, 4);
459}
460
461static inline u32 sunxi_mux_offset(u16 pin)
462{
463 u32 pin_num = pin % MUX_PINS_PER_REG;
464 return pin_num * MUX_PINS_BITS;
465}
466
467static inline u32 sunxi_data_reg(u16 pin)
468{
469 u8 bank = pin / PINS_PER_BANK;
470 u32 offset = bank * BANK_MEM_SIZE;
471 offset += DATA_REGS_OFFSET;
472 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
473 return round_down(offset, 4);
474}
475
476static inline u32 sunxi_data_offset(u16 pin)
477{
478 u32 pin_num = pin % DATA_PINS_PER_REG;
479 return pin_num * DATA_PINS_BITS;
480}
481
482static inline u32 sunxi_dlevel_reg(u16 pin)
483{
484 u8 bank = pin / PINS_PER_BANK;
485 u32 offset = bank * BANK_MEM_SIZE;
486 offset += DLEVEL_REGS_OFFSET;
487 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
488 return round_down(offset, 4);
489}
490
491static inline u32 sunxi_dlevel_offset(u16 pin)
492{
493 u32 pin_num = pin % DLEVEL_PINS_PER_REG;
494 return pin_num * DLEVEL_PINS_BITS;
495}
496
497static inline u32 sunxi_pull_reg(u16 pin)
498{
499 u8 bank = pin / PINS_PER_BANK;
500 u32 offset = bank * BANK_MEM_SIZE;
501 offset += PULL_REGS_OFFSET;
502 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
503 return round_down(offset, 4);
504}
505
506static inline u32 sunxi_pull_offset(u16 pin)
507{
508 u32 pin_num = pin % PULL_PINS_PER_REG;
509 return pin_num * PULL_PINS_BITS;
510}
511
512static inline u32 sunxi_irq_cfg_reg(u16 irq)
513{
514 u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
515 return reg + IRQ_CFG_REG;
516}
517
518static inline u32 sunxi_irq_cfg_offset(u16 irq)
519{
520 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
521 return irq_num * IRQ_CFG_IRQ_BITS;
522}
523
524static inline u32 sunxi_irq_ctrl_reg(u16 irq)
525{
526 u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
527 return reg + IRQ_CTRL_REG;
528}
529
530static inline u32 sunxi_irq_ctrl_offset(u16 irq)
531{
532 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
533 return irq_num * IRQ_CTRL_IRQ_BITS;
534}
535
536static inline u32 sunxi_irq_status_reg(u16 irq)
537{
538 u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
539 return reg + IRQ_STATUS_REG;
540}
541
542static inline u32 sunxi_irq_status_offset(u16 irq)
543{
544 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
545 return irq_num * IRQ_STATUS_IRQ_BITS;
546}
547
548#endif /* __PINCTRL_SUNXI_H */
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 65458096f41e..2d43bff74f59 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -295,17 +295,11 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
295{ 295{
296 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 296 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
297 const struct tegra_pingroup *g; 297 const struct tegra_pingroup *g;
298 u32 val;
299 298
300 g = &pmx->soc->groups[group]; 299 g = &pmx->soc->groups[group];
301 300
302 if (WARN_ON(g->mux_reg < 0)) 301 if (WARN_ON(g->mux_reg < 0))
303 return; 302 return;
304
305 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
306 val &= ~(0x3 << g->mux_bit);
307 val |= g->func_safe << g->mux_bit;
308 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
309} 303}
310 304
311static const struct pinmux_ops tegra_pinmux_ops = { 305static const struct pinmux_ops tegra_pinmux_ops = {
@@ -336,32 +330,32 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
336 *width = 1; 330 *width = 1;
337 break; 331 break;
338 case TEGRA_PINCONF_PARAM_ENABLE_INPUT: 332 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
339 *bank = g->einput_bank; 333 *bank = g->mux_bank;
340 *reg = g->einput_reg; 334 *reg = g->mux_reg;
341 *bit = g->einput_bit; 335 *bit = g->einput_bit;
342 *width = 1; 336 *width = 1;
343 break; 337 break;
344 case TEGRA_PINCONF_PARAM_OPEN_DRAIN: 338 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
345 *bank = g->odrain_bank; 339 *bank = g->mux_bank;
346 *reg = g->odrain_reg; 340 *reg = g->mux_reg;
347 *bit = g->odrain_bit; 341 *bit = g->odrain_bit;
348 *width = 1; 342 *width = 1;
349 break; 343 break;
350 case TEGRA_PINCONF_PARAM_LOCK: 344 case TEGRA_PINCONF_PARAM_LOCK:
351 *bank = g->lock_bank; 345 *bank = g->mux_bank;
352 *reg = g->lock_reg; 346 *reg = g->mux_reg;
353 *bit = g->lock_bit; 347 *bit = g->lock_bit;
354 *width = 1; 348 *width = 1;
355 break; 349 break;
356 case TEGRA_PINCONF_PARAM_IORESET: 350 case TEGRA_PINCONF_PARAM_IORESET:
357 *bank = g->ioreset_bank; 351 *bank = g->mux_bank;
358 *reg = g->ioreset_reg; 352 *reg = g->mux_reg;
359 *bit = g->ioreset_bit; 353 *bit = g->ioreset_bit;
360 *width = 1; 354 *width = 1;
361 break; 355 break;
362 case TEGRA_PINCONF_PARAM_RCV_SEL: 356 case TEGRA_PINCONF_PARAM_RCV_SEL:
363 *bank = g->rcv_sel_bank; 357 *bank = g->mux_bank;
364 *reg = g->rcv_sel_reg; 358 *reg = g->mux_reg;
365 *bit = g->rcv_sel_bit; 359 *bit = g->rcv_sel_bit;
366 *width = 1; 360 *width = 1;
367 break; 361 break;
@@ -408,8 +402,8 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
408 *width = g->slwr_width; 402 *width = g->slwr_width;
409 break; 403 break;
410 case TEGRA_PINCONF_PARAM_DRIVE_TYPE: 404 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
411 *bank = g->drvtype_bank; 405 *bank = g->drv_bank;
412 *reg = g->drvtype_reg; 406 *reg = g->drv_reg;
413 *bit = g->drvtype_bit; 407 *bit = g->drvtype_bit;
414 *width = 2; 408 *width = 2;
415 break; 409 break;
@@ -418,11 +412,22 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
418 return -ENOTSUPP; 412 return -ENOTSUPP;
419 } 413 }
420 414
421 if (*reg < 0) { 415 if (*reg < 0 || *bit > 31) {
422 if (report_err) 416 if (report_err) {
417 const char *prop = "unknown";
418 int i;
419
420 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
421 if (cfg_params[i].param == param) {
422 prop = cfg_params[i].property;
423 break;
424 }
425 }
426
423 dev_err(pmx->dev, 427 dev_err(pmx->dev,
424 "Config param %04x not supported on group %s\n", 428 "Config param %04x (%s) not supported on group %s\n",
425 param, g->name); 429 param, prop, g->name);
430 }
426 return -ENOTSUPP; 431 return -ENOTSUPP;
427 } 432 }
428 433
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 6053832d433e..8d94d1332e7b 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -78,98 +78,83 @@ struct tegra_function {
78 78
79/** 79/**
80 * struct tegra_pingroup - Tegra pin group 80 * struct tegra_pingroup - Tegra pin group
81 * @mux_reg: Mux register offset. -1 if unsupported. 81 * @name The name of the pin group.
82 * @mux_bank: Mux register bank. 0 if unsupported. 82 * @pins An array of pin IDs included in this pin group.
83 * @mux_bit: Mux register bit. 0 if unsupported. 83 * @npins The number of entries in @pins.
84 * @pupd_reg: Pull-up/down register offset. -1 if unsupported. 84 * @funcs The mux functions which can be muxed onto this group.
85 * @pupd_bank: Pull-up/down register bank. 0 if unsupported. 85 * @mux_reg: Mux register offset.
86 * @pupd_bit: Pull-up/down register bit. 0 if unsupported. 86 * This register contains the mux, einput, odrain, lock,
87 * @tri_reg: Tri-state register offset. -1 if unsupported. 87 * ioreset, rcv_sel parameters.
88 * @tri_bank: Tri-state register bank. 0 if unsupported. 88 * @mux_bank: Mux register bank.
89 * @tri_bit: Tri-state register bit. 0 if unsupported. 89 * @mux_bit: Mux register bit.
90 * @einput_reg: Enable-input register offset. -1 if unsupported. 90 * @pupd_reg: Pull-up/down register offset.
91 * @einput_bank: Enable-input register bank. 0 if unsupported. 91 * @pupd_bank: Pull-up/down register bank.
92 * @einput_bit: Enable-input register bit. 0 if unsupported. 92 * @pupd_bit: Pull-up/down register bit.
93 * @odrain_reg: Open-drain register offset. -1 if unsupported. 93 * @tri_reg: Tri-state register offset.
94 * @odrain_bank: Open-drain register bank. 0 if unsupported. 94 * @tri_bank: Tri-state register bank.
95 * @odrain_bit: Open-drain register bit. 0 if unsupported. 95 * @tri_bit: Tri-state register bit.
96 * @lock_reg: Lock register offset. -1 if unsupported. 96 * @einput_bit: Enable-input register bit.
97 * @lock_bank: Lock register bank. 0 if unsupported. 97 * @odrain_bit: Open-drain register bit.
98 * @lock_bit: Lock register bit. 0 if unsupported. 98 * @lock_bit: Lock register bit.
99 * @ioreset_reg: IO reset register offset. -1 if unsupported. 99 * @ioreset_bit: IO reset register bit.
100 * @ioreset_bank: IO reset register bank. 0 if unsupported. 100 * @rcv_sel_bit: Receiver select bit.
101 * @ioreset_bit: IO reset register bit. 0 if unsupported. 101 * @drv_reg: Drive fields register offset.
102 * @rcv_sel_reg: Receiver select offset. -1 if unsupported. 102 * This register contains hsm, schmitt, lpmd, drvdn,
103 * @rcv_sel_bank: Receiver select bank. 0 if unsupported. 103 * drvup, slwr, slwf, and drvtype parameters.
104 * @rcv_sel_bit: Receiver select bit. 0 if unsupported. 104 * @drv_bank: Drive fields register bank.
105 * @drv_reg: Drive fields register offset. -1 if unsupported. 105 * @hsm_bit: High Speed Mode register bit.
106 * This register contains the hsm, schmitt, lpmd, drvdn, 106 * @schmitt_bit: Scmitt register bit.
107 * drvup, slwr, and slwf parameters. 107 * @lpmd_bit: Low Power Mode register bit.
108 * @drv_bank: Drive fields register bank. 0 if unsupported. 108 * @drvdn_bit: Drive Down register bit.
109 * @hsm_bit: High Speed Mode register bit. 0 if unsupported. 109 * @drvdn_width: Drive Down field width.
110 * @schmitt_bit: Scmitt register bit. 0 if unsupported. 110 * @drvup_bit: Drive Up register bit.
111 * @lpmd_bit: Low Power Mode register bit. 0 if unsupported. 111 * @drvup_width: Drive Up field width.
112 * @drvdn_bit: Drive Down register bit. 0 if unsupported. 112 * @slwr_bit: Slew Rising register bit.
113 * @drvdn_width: Drive Down field width. 0 if unsupported. 113 * @slwr_width: Slew Rising field width.
114 * @drvup_bit: Drive Up register bit. 0 if unsupported. 114 * @slwf_bit: Slew Falling register bit.
115 * @drvup_width: Drive Up field width. 0 if unsupported. 115 * @slwf_width: Slew Falling field width.
116 * @slwr_bit: Slew Rising register bit. 0 if unsupported. 116 * @drvtype_bit: Drive type register bit.
117 * @slwr_width: Slew Rising field width. 0 if unsupported. 117 *
118 * @slwf_bit: Slew Falling register bit. 0 if unsupported. 118 * -1 in a *_reg field means that feature is unsupported for this group.
119 * @slwf_width: Slew Falling field width. 0 if unsupported. 119 * *_bank and *_reg values are irrelevant when *_reg is -1.
120 * @drvtype_reg: Drive type fields register offset. -1 if unsupported. 120 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
121 * @drvtype_bank: Drive type fields register bank. 0 if unsupported.
122 * @drvtype_bit: Drive type register bit. 0 if unsupported.
123 * 121 *
124 * A representation of a group of pins (possibly just one pin) in the Tegra 122 * A representation of a group of pins (possibly just one pin) in the Tegra
125 * pin controller. Each group allows some parameter or parameters to be 123 * pin controller. Each group allows some parameter or parameters to be
126 * configured. The most common is mux function selection. Many others exist 124 * configured. The most common is mux function selection. Many others exist
127 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex; 125 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
128 * certain groups may only support configuring certain parameters, hence 126 * certain groups may only support configuring certain parameters, hence
129 * each parameter is optional, represented by a -1 "reg" value. 127 * each parameter is optional.
130 */ 128 */
131struct tegra_pingroup { 129struct tegra_pingroup {
132 const char *name; 130 const char *name;
133 const unsigned *pins; 131 const unsigned *pins;
134 unsigned npins; 132 u8 npins;
135 unsigned funcs[4]; 133 u8 funcs[4];
136 unsigned func_safe;
137 s16 mux_reg; 134 s16 mux_reg;
138 s16 pupd_reg; 135 s16 pupd_reg;
139 s16 tri_reg; 136 s16 tri_reg;
140 s16 einput_reg;
141 s16 odrain_reg;
142 s16 lock_reg;
143 s16 ioreset_reg;
144 s16 rcv_sel_reg;
145 s16 drv_reg; 137 s16 drv_reg;
146 s16 drvtype_reg;
147 u32 mux_bank:2; 138 u32 mux_bank:2;
148 u32 pupd_bank:2; 139 u32 pupd_bank:2;
149 u32 tri_bank:2; 140 u32 tri_bank:2;
150 u32 einput_bank:2;
151 u32 odrain_bank:2;
152 u32 ioreset_bank:2;
153 u32 rcv_sel_bank:2;
154 u32 lock_bank:2;
155 u32 drv_bank:2; 141 u32 drv_bank:2;
156 u32 drvtype_bank:2; 142 u32 mux_bit:6;
157 u32 mux_bit:5; 143 u32 pupd_bit:6;
158 u32 pupd_bit:5; 144 u32 tri_bit:6;
159 u32 tri_bit:5; 145 u32 einput_bit:6;
160 u32 einput_bit:5; 146 u32 odrain_bit:6;
161 u32 odrain_bit:5; 147 u32 lock_bit:6;
162 u32 lock_bit:5; 148 u32 ioreset_bit:6;
163 u32 ioreset_bit:5; 149 u32 rcv_sel_bit:6;
164 u32 rcv_sel_bit:5; 150 u32 hsm_bit:6;
165 u32 hsm_bit:5; 151 u32 schmitt_bit:6;
166 u32 schmitt_bit:5; 152 u32 lpmd_bit:6;
167 u32 lpmd_bit:5; 153 u32 drvdn_bit:6;
168 u32 drvdn_bit:5; 154 u32 drvup_bit:6;
169 u32 drvup_bit:5; 155 u32 slwr_bit:6;
170 u32 slwr_bit:5; 156 u32 slwf_bit:6;
171 u32 slwf_bit:5; 157 u32 drvtype_bit:6;
172 u32 drvtype_bit:5;
173 u32 drvdn_width:6; 158 u32 drvdn_width:6;
174 u32 drvup_width:6; 159 u32 drvup_width:6;
175 u32 slwr_width:6; 160 u32 slwr_width:6;
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c
index 63fe7619d3ff..33614baab4c0 100644
--- a/drivers/pinctrl/pinctrl-tegra114.c
+++ b/drivers/pinctrl/pinctrl-tegra114.c
@@ -1547,10 +1547,12 @@ static struct tegra_function tegra114_functions[] = {
1547#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1547#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1548#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1548#define PINGROUP_REG_A 0x3000 /* bank 1 */
1549 1549
1550#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) 1550#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1551#define PINGROUP_REG_N(r) -1
1552 1551
1553#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \ 1552#define PINGROUP_BIT_Y(b) (b)
1553#define PINGROUP_BIT_N(b) (-1)
1554
1555#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \
1554 { \ 1556 { \
1555 .name = #pg_name, \ 1557 .name = #pg_name, \
1556 .pins = pg_name##_pins, \ 1558 .pins = pg_name##_pins, \
@@ -1561,38 +1563,24 @@ static struct tegra_function tegra114_functions[] = {
1561 TEGRA_MUX_##f2, \ 1563 TEGRA_MUX_##f2, \
1562 TEGRA_MUX_##f3, \ 1564 TEGRA_MUX_##f3, \
1563 }, \ 1565 }, \
1564 .func_safe = TEGRA_MUX_##f_safe, \ 1566 .mux_reg = PINGROUP_REG(r), \
1565 .mux_reg = PINGROUP_REG_Y(r), \
1566 .mux_bank = 1, \ 1567 .mux_bank = 1, \
1567 .mux_bit = 0, \ 1568 .mux_bit = 0, \
1568 .pupd_reg = PINGROUP_REG_Y(r), \ 1569 .pupd_reg = PINGROUP_REG(r), \
1569 .pupd_bank = 1, \ 1570 .pupd_bank = 1, \
1570 .pupd_bit = 2, \ 1571 .pupd_bit = 2, \
1571 .tri_reg = PINGROUP_REG_Y(r), \ 1572 .tri_reg = PINGROUP_REG(r), \
1572 .tri_bank = 1, \ 1573 .tri_bank = 1, \
1573 .tri_bit = 4, \ 1574 .tri_bit = 4, \
1574 .einput_reg = PINGROUP_REG_Y(r), \ 1575 .einput_bit = PINGROUP_BIT_Y(5), \
1575 .einput_bank = 1, \ 1576 .odrain_bit = PINGROUP_BIT_##od(6), \
1576 .einput_bit = 5, \ 1577 .lock_bit = PINGROUP_BIT_Y(7), \
1577 .odrain_reg = PINGROUP_REG_##od(r), \ 1578 .ioreset_bit = PINGROUP_BIT_##ior(8), \
1578 .odrain_bank = 1, \ 1579 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
1579 .odrain_bit = 6, \
1580 .lock_reg = PINGROUP_REG_Y(r), \
1581 .lock_bank = 1, \
1582 .lock_bit = 7, \
1583 .ioreset_reg = PINGROUP_REG_##ior(r), \
1584 .ioreset_bank = 1, \
1585 .ioreset_bit = 8, \
1586 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r), \
1587 .rcv_sel_bank = 1, \
1588 .rcv_sel_bit = 9, \
1589 .drv_reg = -1, \ 1580 .drv_reg = -1, \
1590 .drvtype_reg = -1, \
1591 } 1581 }
1592 1582
1593#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A) 1583#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1594#define DRV_PINGROUP_REG_N(r) -1
1595
1596 1584
1597#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1585#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
1598 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 1586 drvdn_b, drvdn_w, drvup_b, drvup_w, \
@@ -1605,12 +1593,12 @@ static struct tegra_function tegra114_functions[] = {
1605 .mux_reg = -1, \ 1593 .mux_reg = -1, \
1606 .pupd_reg = -1, \ 1594 .pupd_reg = -1, \
1607 .tri_reg = -1, \ 1595 .tri_reg = -1, \
1608 .einput_reg = -1, \ 1596 .einput_bit = -1, \
1609 .odrain_reg = -1, \ 1597 .odrain_bit = -1, \
1610 .lock_reg = -1, \ 1598 .lock_bit = -1, \
1611 .ioreset_reg = -1, \ 1599 .ioreset_bit = -1, \
1612 .rcv_sel_reg = -1, \ 1600 .rcv_sel_bit = -1, \
1613 .drv_reg = DRV_PINGROUP_REG_Y(r), \ 1601 .drv_reg = DRV_PINGROUP_REG(r), \
1614 .drv_bank = 0, \ 1602 .drv_bank = 0, \
1615 .hsm_bit = hsm_b, \ 1603 .hsm_bit = hsm_b, \
1616 .schmitt_bit = schmitt_b, \ 1604 .schmitt_bit = schmitt_b, \
@@ -1623,190 +1611,188 @@ static struct tegra_function tegra114_functions[] = {
1623 .slwr_width = slwr_w, \ 1611 .slwr_width = slwr_w, \
1624 .slwf_bit = slwf_b, \ 1612 .slwf_bit = slwf_b, \
1625 .slwf_width = slwf_w, \ 1613 .slwf_width = slwf_w, \
1626 .drvtype_reg = DRV_PINGROUP_REG_##drvtype(r), \ 1614 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
1627 .drvtype_bank = 0, \
1628 .drvtype_bit = 6, \
1629 } 1615 }
1630 1616
1631static const struct tegra_pingroup tegra114_groups[] = { 1617static const struct tegra_pingroup tegra114_groups[] = {
1632 /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */ 1618 /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
1633 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N, N), 1619 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
1634 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N, N), 1620 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N),
1635 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N, N), 1621 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N),
1636 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, ULPI, 0x300c, N, N, N), 1622 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N),
1637 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, ULPI, 0x3010, N, N, N), 1623 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N),
1638 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, ULPI, 0x3014, N, N, N), 1624 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N),
1639 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, ULPI, 0x3018, N, N, N), 1625 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N),
1640 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, ULPI, 0x301c, N, N, N), 1626 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N),
1641 PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3020, N, N, N), 1627 PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N),
1642 PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3024, N, N, N), 1628 PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N),
1643 PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3028, N, N, N), 1629 PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N),
1644 PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, ULPI, 0x302c, N, N, N), 1630 PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N),
1645 PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3030, N, N, N), 1631 PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N),
1646 PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3034, N, N, N), 1632 PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N),
1647 PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3038, N, N, N), 1633 PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3038, N, N, N),
1648 PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x303c, N, N, N), 1634 PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x303c, N, N, N),
1649 PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x3040, N, N, N), 1635 PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N),
1650 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3044, N, N, N), 1636 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N),
1651 PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, RSVD4, 0x3048, N, N, N), 1637 PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N),
1652 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x304c, N, N, N), 1638 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N),
1653 PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x3050, N, N, N), 1639 PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N),
1654 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, SDMMC1, 0x3054, N, N, N), 1640 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
1655 PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, SDMMC1, 0x3058, N, N, N), 1641 PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N),
1656 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, RSVD2, 0x305c, N, N, N), 1642 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N),
1657 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, RSVD4, 0x3068, N, N, N), 1643 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N),
1658 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, RSVD4, 0x306c, N, N, N), 1644 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N),
1659 PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3110, N, N, Y), 1645 PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y),
1660 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3114, N, N, Y), 1646 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y),
1661 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3118, N, N, Y), 1647 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y),
1662 PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3164, N, N, N), 1648 PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N),
1663 PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3168, N, N, N), 1649 PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N),
1664 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, RSVD3, 0x316c, N, N, N), 1650 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, 0x316c, N, N, N),
1665 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, RSVD3, 0x3170, N, N, N), 1651 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, 0x3170, N, N, N),
1666 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, RSVD3, 0x3174, N, N, N), 1652 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, 0x3174, N, N, N),
1667 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, RSVD3, 0x3178, N, N, N), 1653 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, 0x3178, N, N, N),
1668 PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, UARTC, 0x317c, N, N, N), 1654 PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, 0x317c, N, N, N),
1669 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, UARTC, 0x3180, N, N, N), 1655 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, 0x3180, N, N, N),
1670 PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, RSVD4, 0x3184, N, N, N), 1656 PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, 0x3184, N, N, N),
1671 PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, RSVD4, 0x3188, N, N, N), 1657 PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, 0x3188, N, N, N),
1672 PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, RSVD4, 0x318c, N, N, N), 1658 PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, 0x318c, N, N, N),
1673 PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, PWM0, 0x3190, N, N, N), 1659 PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, 0x3190, N, N, N),
1674 PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, PWM1, 0x3194, N, N, N), 1660 PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, 0x3194, N, N, N),
1675 PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, PWM2, 0x3198, N, N, N), 1661 PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, 0x3198, N, N, N),
1676 PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, PWM3, 0x319c, N, N, N), 1662 PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, 0x319c, N, N, N),
1677 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a0, Y, N, N), 1663 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N),
1678 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a4, Y, N, N), 1664 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N),
1679 PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, RSVD4, 0x31a8, N, N, N), 1665 PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, 0x31a8, N, N, N),
1680 PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31ac, N, N, N), 1666 PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, 0x31ac, N, N, N),
1681 PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, RSVD4, 0x31b0, N, N, N), 1667 PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, 0x31b0, N, N, N),
1682 PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31b4, N, N, N), 1668 PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, 0x31b4, N, N, N),
1683 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31b8, N, N, N), 1669 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N),
1684 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31bc, N, N, N), 1670 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N),
1685 PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, RSVD1, 0x31c0, N, N, N), 1671 PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N, N),
1686 PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, RSVD2, 0x31c4, N, N, N), 1672 PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, 0x31c4, N, N, N),
1687 PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, NAND, 0x31c8, N, N, N), 1673 PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, 0x31c8, N, N, N),
1688 PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, RSVD1, 0x31cc, N, N, N), 1674 PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, 0x31cc, N, N, N),
1689 PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, GMI, 0x31d0, N, N, N), 1675 PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, 0x31d0, N, N, N),
1690 PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, RSVD1, 0x31d4, N, N, N), 1676 PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, 0x31d4, N, N, N),
1691 PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, RSVD1, 0x31d8, N, N, N), 1677 PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, 0x31d8, N, N, N),
1692 PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, GMI, 0x31dc, N, N, N), 1678 PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, 0x31dc, N, N, N),
1693 PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, GMI, 0x31e0, N, N, N), 1679 PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, 0x31e0, N, N, N),
1694 PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, GMI, 0x31e4, N, N, N), 1680 PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, 0x31e4, N, N, N),
1695 PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, NAND, 0x31e8, N, N, N), 1681 PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, 0x31e8, N, N, N),
1696 PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, NAND, 0x31ec, N, N, N), 1682 PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, 0x31ec, N, N, N),
1697 PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f0, N, N, N), 1683 PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N, N),
1698 PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f4, N, N, N), 1684 PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N, N),
1699 PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f8, N, N, N), 1685 PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N, N),
1700 PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31fc, N, N, N), 1686 PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N, N),
1701 PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3200, N, N, N), 1687 PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N, N),
1702 PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3204, N, N, N), 1688 PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, 0x3204, N, N, N),
1703 PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3208, N, N, N), 1689 PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, 0x3208, N, N, N),
1704 PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, RSVD1, 0x320c, N, N, N), 1690 PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, 0x320c, N, N, N),
1705 PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, GMI, 0x3210, N, N, N), 1691 PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, 0x3210, N, N, N),
1706 PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, GMI, 0x3214, N, N, N), 1692 PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, 0x3214, N, N, N),
1707 PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, GMI, 0x3218, N, N, N), 1693 PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, 0x3218, N, N, N),
1708 PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, GMI, 0x321c, N, N, N), 1694 PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, 0x321c, N, N, N),
1709 PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, RSVD4, 0x3220, N, N, N), 1695 PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, 0x3220, N, N, N),
1710 PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, RSVD4, 0x3224, N, N, N), 1696 PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, 0x3224, N, N, N),
1711 PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, GMI, 0x3228, N, N, N), 1697 PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, 0x3228, N, N, N),
1712 PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, GMI, 0x322c, N, N, N), 1698 PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, 0x322c, N, N, N),
1713 PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, GMI, 0x3230, N, N, N), 1699 PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, 0x3230, N, N, N),
1714 PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, RSVD2, 0x3234, N, N, N), 1700 PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, 0x3234, N, N, N),
1715 PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, RSVD2, 0x3238, N, N, N), 1701 PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, 0x3238, N, N, N),
1716 PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, GMI, 0x323c, N, N, N), 1702 PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, 0x323c, N, N, N),
1717 PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3240, N, N, N), 1703 PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, 0x3240, N, N, N),
1718 PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, RSVD1, 0x3244, N, N, N), 1704 PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, 0x3244, N, N, N),
1719 PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, NAND, 0x3248, N, N, N), 1705 PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, 0x3248, N, N, N),
1720 PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, RSVD4, 0x324c, N, N, N), 1706 PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N, N),
1721 PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, RSVD4, 0x3250, Y, N, N), 1707 PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N),
1722 PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, RSVD4, 0x3254, Y, N, N), 1708 PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N),
1723 PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x3258, N, Y, N), 1709 PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N),
1724 PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x325c, N, Y, N), 1710 PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N),
1725 PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3260, N, Y, N), 1711 PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N),
1726 PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3264, N, Y, N), 1712 PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N),
1727 PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3268, N, Y, N), 1713 PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N),
1728 PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x326c, N, Y, N), 1714 PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N),
1729 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3270, N, Y, N), 1715 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N),
1730 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3274, N, Y, N), 1716 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, 0x3274, N, Y, N),
1731 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3278, N, Y, N), 1717 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N),
1732 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x327c, N, Y, N), 1718 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N),
1733 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, RSVD4, 0x3284, N, N, N), 1719 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, 0x3284, N, N, N),
1734 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3288, N, N, N), 1720 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, 0x3288, N, N, N),
1735 PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, I2S4, 0x328c, N, N, N), 1721 PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, 0x328c, N, N, N),
1736 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, RSVD4, 0x3290, Y, N, N), 1722 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, 0x3290, Y, N, N),
1737 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, RSVD4, 0x3294, Y, N, N), 1723 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, 0x3294, Y, N, N),
1738 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x3298, N, N, N), 1724 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, 0x3298, N, N, N),
1739 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x329c, N, N, N), 1725 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, 0x329c, N, N, N),
1740 PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x32a0, N, N, N), 1726 PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, 0x32a0, N, N, N),
1741 PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x32a4, N, N, N), 1727 PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, 0x32a4, N, N, N),
1742 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32a8, N, N, N), 1728 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, 0x32a8, N, N, N),
1743 PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32ac, N, N, N), 1729 PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N, N),
1744 PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, RTCK, 0x32b0, N, N, N), 1730 PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N),
1745 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b4, Y, N, N), 1731 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N),
1746 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b8, Y, N, N), 1732 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N),
1747 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32bc, N, N, N), 1733 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N),
1748 PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c0, N, N, N), 1734 PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N),
1749 PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c4, N, N, N), 1735 PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N),
1750 PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, RSVD3, 0x32c8, N, N, N), 1736 PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32c8, N, N, N),
1751 PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, KBC, 0x32cc, N, N, N), 1737 PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32cc, N, N, N),
1752 PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, KBC, 0x32d0, N, N, N), 1738 PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32d0, N, N, N),
1753 PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, KBC, 0x32d4, N, N, N), 1739 PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N),
1754 PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32d8, N, N, N), 1740 PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N),
1755 PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32dc, N, N, N), 1741 PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N),
1756 PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, RSVD3, 0x32e0, N, N, N), 1742 PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N),
1757 PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, RSVD3, 0x32e4, N, N, N), 1743 PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N),
1758 PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, KBC, 0x32fc, N, N, N), 1744 PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, 0x32fc, N, N, N),
1759 PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, RSVD2, 0x3300, N, N, N), 1745 PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, 0x3300, N, N, N),
1760 PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, RSVD2, 0x3304, N, N, N), 1746 PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N),
1761 PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, KBC, 0x3308, N, N, N), 1747 PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N),
1762 PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, KBC, 0x330c, N, N, N), 1748 PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N),
1763 PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, RSVD4, 0x3310, N, N, N), 1749 PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, 0x3310, N, N, N),
1764 PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3314, N, N, N), 1750 PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, 0x3314, N, N, N),
1765 PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3318, N, N, N), 1751 PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, 0x3318, N, N, N),
1766 PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, RSVD4, 0x331c, N, N, N), 1752 PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N),
1767 PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, RSVD4, 0x3320, N, N, N), 1753 PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N, N),
1768 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, RSVD4, 0x3324, N, N, N), 1754 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N),
1769 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, RSVD4, 0x3328, N, N, N), 1755 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N),
1770 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, RSVD4, 0x332c, N, N, N), 1756 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N),
1771 PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, CLK, 0x3330, N, N, N), 1757 PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
1772 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x3334, N, N, Y), 1758 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y),
1773 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3338, N, N, N), 1759 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N),
1774 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, RSVD4, 0x333c, N, N, N), 1760 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N),
1775 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3340, N, N, N), 1761 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, 0x3340, N, N, N),
1776 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3344, N, N, N), 1762 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N),
1777 PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, RSVD4, 0x3348, N, N, N), 1763 PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, 0x3348, N, N, N),
1778 PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, RSVD4, 0x334c, N, N, N), 1764 PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N),
1779 PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, RSVD4, 0x3350, N, N, N), 1765 PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, 0x3350, N, N, N),
1780 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, RSVD4, 0x3354, N, N, N), 1766 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, 0x3354, N, N, N),
1781 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3358, N, N, N), 1767 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, 0x3358, N, N, N),
1782 PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x335c, N, N, N), 1768 PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, 0x335c, N, N, N),
1783 PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3360, N, N, N), 1769 PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, 0x3360, N, N, N),
1784 PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3364, N, N, N), 1770 PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, 0x3364, N, N, N),
1785 PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, RSVD4, 0x3368, N, N, N), 1771 PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, 0x3368, N, N, N),
1786 PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, RSVD4, 0x336c, N, N, N), 1772 PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, 0x336c, N, N, N),
1787 PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, RSVD4, 0x3370, N, N, N), 1773 PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, 0x3370, N, N, N),
1788 PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, RSVD4, 0x3374, N, N, N), 1774 PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, 0x3374, N, N, N),
1789 PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, RSVD1, 0x3378, N, N, N), 1775 PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, 0x3378, N, N, N),
1790 PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, RSVD1, 0x337c, N, N, N), 1776 PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, 0x337c, N, N, N),
1791 PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, RSVD4, 0x3380, N, N, N), 1777 PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, 0x3380, N, N, N),
1792 PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, RSVD4, 0x3384, N, N, N), 1778 PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N),
1793 PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, RSVD3, 0x3390, N, N, N), 1779 PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N),
1794 PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, SDMMC3, 0x3394, N, N, N), 1780 PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N),
1795 PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, RSVD3, 0x3398, N, N, N), 1781 PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N),
1796 PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, SDMMC3, 0x339c, N, N, N), 1782 PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N),
1797 PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, SDMMC3, 0x33a0, N, N, N), 1783 PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N),
1798 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, SDMMC3, 0x33a4, N, N, N), 1784 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
1799 PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, RSVD3, 0x33e0, Y, N, N), 1785 PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, 0x33e0, Y, N, N),
1800 PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, SDMMC1, 0x33e4, N, N, N), 1786 PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N),
1801 PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, RSVD4, 0x33e8, N, N, N), 1787 PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N),
1802 PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, RSVD2, 0x33ec, N, N, N), 1788 PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N),
1803 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, SPI6, 0x33f0, N, N, N), 1789 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N),
1804 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x33f4, Y, N, N), 1790 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N),
1805 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x33f8, Y, N, N), 1791 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N),
1806 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x33fc, N, N, N), 1792 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N),
1807 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x3400, N, N, N), 1793 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N),
1808 PINGROUP(gmi_clk_lb, SDMMC2, NAND, GMI, RSVD4, GMI, 0x3404, N, N, N), 1794 PINGROUP(gmi_clk_lb, SDMMC2, NAND, GMI, RSVD4, 0x3404, N, N, N),
1809 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD3, 0x3408, N, N, N), 1795 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N),
1810 1796
1811 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */ 1797 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
1812 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1798 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index 73773706755b..e80797e20017 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -1677,10 +1677,12 @@ static struct tegra_function tegra124_functions[] = {
1677#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1677#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1678#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1678#define PINGROUP_REG_A 0x3000 /* bank 1 */
1679 1679
1680#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) 1680#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1681#define PINGROUP_REG_N(r) -1
1682 1681
1683#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \ 1682#define PINGROUP_BIT_Y(b) (b)
1683#define PINGROUP_BIT_N(b) (-1)
1684
1685#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \
1684 { \ 1686 { \
1685 .name = #pg_name, \ 1687 .name = #pg_name, \
1686 .pins = pg_name##_pins, \ 1688 .pins = pg_name##_pins, \
@@ -1691,38 +1693,24 @@ static struct tegra_function tegra124_functions[] = {
1691 TEGRA_MUX_##f2, \ 1693 TEGRA_MUX_##f2, \
1692 TEGRA_MUX_##f3, \ 1694 TEGRA_MUX_##f3, \
1693 }, \ 1695 }, \
1694 .func_safe = TEGRA_MUX_##f_safe, \ 1696 .mux_reg = PINGROUP_REG(r), \
1695 .mux_reg = PINGROUP_REG_Y(r), \
1696 .mux_bank = 1, \ 1697 .mux_bank = 1, \
1697 .mux_bit = 0, \ 1698 .mux_bit = 0, \
1698 .pupd_reg = PINGROUP_REG_Y(r), \ 1699 .pupd_reg = PINGROUP_REG(r), \
1699 .pupd_bank = 1, \ 1700 .pupd_bank = 1, \
1700 .pupd_bit = 2, \ 1701 .pupd_bit = 2, \
1701 .tri_reg = PINGROUP_REG_Y(r), \ 1702 .tri_reg = PINGROUP_REG(r), \
1702 .tri_bank = 1, \ 1703 .tri_bank = 1, \
1703 .tri_bit = 4, \ 1704 .tri_bit = 4, \
1704 .einput_reg = PINGROUP_REG_Y(r), \ 1705 .einput_bit = PINGROUP_BIT_Y(5), \
1705 .einput_bank = 1, \ 1706 .odrain_bit = PINGROUP_BIT_##od(6), \
1706 .einput_bit = 5, \ 1707 .lock_bit = PINGROUP_BIT_Y(7), \
1707 .odrain_reg = PINGROUP_REG_##od(r), \ 1708 .ioreset_bit = PINGROUP_BIT_##ior(8), \
1708 .odrain_bank = 1, \ 1709 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
1709 .odrain_bit = 6, \
1710 .lock_reg = PINGROUP_REG_Y(r), \
1711 .lock_bank = 1, \
1712 .lock_bit = 7, \
1713 .ioreset_reg = PINGROUP_REG_##ior(r), \
1714 .ioreset_bank = 1, \
1715 .ioreset_bit = 8, \
1716 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r), \
1717 .rcv_sel_bank = 1, \
1718 .rcv_sel_bit = 9, \
1719 .drv_reg = -1, \ 1710 .drv_reg = -1, \
1720 .drvtype_reg = -1, \
1721 } 1711 }
1722 1712
1723#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A) 1713#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1724#define DRV_PINGROUP_REG_N(r) -1
1725
1726 1714
1727#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1715#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
1728 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 1716 drvdn_b, drvdn_w, drvup_b, drvup_w, \
@@ -1735,12 +1723,12 @@ static struct tegra_function tegra124_functions[] = {
1735 .mux_reg = -1, \ 1723 .mux_reg = -1, \
1736 .pupd_reg = -1, \ 1724 .pupd_reg = -1, \
1737 .tri_reg = -1, \ 1725 .tri_reg = -1, \
1738 .einput_reg = -1, \ 1726 .einput_bit = -1, \
1739 .odrain_reg = -1, \ 1727 .odrain_bit = -1, \
1740 .lock_reg = -1, \ 1728 .lock_bit = -1, \
1741 .ioreset_reg = -1, \ 1729 .ioreset_bit = -1, \
1742 .rcv_sel_reg = -1, \ 1730 .rcv_sel_bit = -1, \
1743 .drv_reg = DRV_PINGROUP_REG_Y(r), \ 1731 .drv_reg = DRV_PINGROUP_REG(r), \
1744 .drv_bank = 0, \ 1732 .drv_bank = 0, \
1745 .hsm_bit = hsm_b, \ 1733 .hsm_bit = hsm_b, \
1746 .schmitt_bit = schmitt_b, \ 1734 .schmitt_bit = schmitt_b, \
@@ -1753,246 +1741,244 @@ static struct tegra_function tegra124_functions[] = {
1753 .slwr_width = slwr_w, \ 1741 .slwr_width = slwr_w, \
1754 .slwf_bit = slwf_b, \ 1742 .slwf_bit = slwf_b, \
1755 .slwf_width = slwf_w, \ 1743 .slwf_width = slwf_w, \
1756 .drvtype_reg = DRV_PINGROUP_REG_##drvtype(r), \ 1744 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
1757 .drvtype_bank = 0, \
1758 .drvtype_bit = 6, \
1759 } 1745 }
1760 1746
1761static const struct tegra_pingroup tegra124_groups[] = { 1747static const struct tegra_pingroup tegra124_groups[] = {
1762 /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */ 1748 /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
1763 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, SPI3, 0x3000, N, N, N), 1749 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
1764 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, SPI3, 0x3004, N, N, N), 1750 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N),
1765 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, SPI3, 0x3008, N, N, N), 1751 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N),
1766 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, SPI3, 0x300c, N, N, N), 1752 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N),
1767 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, SPI2, 0x3010, N, N, N), 1753 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N),
1768 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, SPI2, 0x3014, N, N, N), 1754 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N),
1769 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, SPI2, 0x3018, N, N, N), 1755 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N),
1770 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, SPI2, 0x301c, N, N, N), 1756 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N),
1771 PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, SPI1, 0x3020, N, N, N), 1757 PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N),
1772 PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, SPI1, 0x3024, N, N, N), 1758 PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N),
1773 PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, SPI1, 0x3028, N, N, N), 1759 PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N),
1774 PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, SPI1, 0x302c, N, N, N), 1760 PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N),
1775 PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3030, N, N, N), 1761 PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N),
1776 PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3034, N, N, N), 1762 PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N),
1777 PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, RSVD4, I2S2, 0x3038, N, N, N), 1763 PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, RSVD4, 0x3038, N, N, N),
1778 PINGROUP(dap3_sclk_pp3, I2S2, SPI5, RSVD3, DISPLAYB, I2S2, 0x303c, N, N, N), 1764 PINGROUP(dap3_sclk_pp3, I2S2, SPI5, RSVD3, DISPLAYB, 0x303c, N, N, N),
1779 PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, RSVD1, 0x3040, N, N, N), 1765 PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N),
1780 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, RSVD1, 0x3044, N, N, N), 1766 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N),
1781 PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, RSVD3, 0x3048, N, N, N), 1767 PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N),
1782 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x304c, N, N, N), 1768 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N),
1783 PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x3050, N, N, N), 1769 PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N),
1784 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, SDMMC1, 0x3054, N, N, N), 1770 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
1785 PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, SDMMC1, 0x3058, N, N, N), 1771 PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N),
1786 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, SDMMC1, 0x305c, N, N, N), 1772 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N),
1787 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, EXTPERIPH2, 0x3068, N, N, N), 1773 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N),
1788 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, DAP, 0x306c, N, N, N), 1774 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N),
1789 PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, RSVD1, 0x3110, N, N, Y), 1775 PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y),
1790 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, I2C4, 0x3114, N, N, Y), 1776 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y),
1791 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, I2C4, 0x3118, N, N, Y), 1777 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y),
1792 PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3164, N, N, N), 1778 PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N),
1793 PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3168, N, N, N), 1779 PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N),
1794 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, UARTA, 0x316c, N, N, N), 1780 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N, N),
1795 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, UARTA, 0x3170, N, N, N), 1781 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N, N),
1796 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, SPI4, UARTC, 0x3174, N, N, N), 1782 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, SPI4, 0x3174, N, N, N),
1797 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, SPI4, UARTC, 0x3178, N, N, N), 1783 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, SPI4, 0x3178, N, N, N),
1798 PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, GMI, UARTC, 0x317c, N, N, N), 1784 PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, GMI, 0x317c, N, N, N),
1799 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, UARTC, 0x3180, N, N, N), 1785 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, 0x3180, N, N, N),
1800 PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, RSVD4, 0x3184, N, N, N), 1786 PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N, N),
1801 PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, RSVD4, 0x3188, N, N, N), 1787 PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N, N),
1802 PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, RSVD4, 0x318c, N, N, N), 1788 PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N, N),
1803 PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, PWM0, 0x3190, N, N, N), 1789 PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, 0x3190, N, N, N),
1804 PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, PWM1, 0x3194, N, N, N), 1790 PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, 0x3194, N, N, N),
1805 PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, PWM2, 0x3198, N, N, N), 1791 PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, 0x3198, N, N, N),
1806 PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, RSVD3, 0x319c, N, N, N), 1792 PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, 0x319c, N, N, N),
1807 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, I2C1, 0x31a0, Y, N, N), 1793 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N),
1808 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, I2C1, 0x31a4, Y, N, N), 1794 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N),
1809 PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, I2S3, 0x31a8, N, N, N), 1795 PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, 0x31a8, N, N, N),
1810 PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, I2S3, 0x31ac, N, N, N), 1796 PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, 0x31ac, N, N, N),
1811 PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, I2S3, 0x31b0, N, N, N), 1797 PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, 0x31b0, N, N, N),
1812 PINGROUP(dap4_sclk_pp7, I2S3, GMI, RSVD3, RSVD4, I2S3, 0x31b4, N, N, N), 1798 PINGROUP(dap4_sclk_pp7, I2S3, GMI, RSVD3, RSVD4, 0x31b4, N, N, N),
1813 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, RSVD3, 0x31b8, N, N, N), 1799 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N),
1814 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31bc, N, N, N), 1800 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N),
1815 PINGROUP(pc7, RSVD1, RSVD2, GMI, GMI_ALT, RSVD1, 0x31c0, N, N, N), 1801 PINGROUP(pc7, RSVD1, RSVD2, GMI, GMI_ALT, 0x31c0, N, N, N),
1816 PINGROUP(pi5, SDMMC2, RSVD2, GMI, RSVD4, GMI, 0x31c4, N, N, N), 1802 PINGROUP(pi5, SDMMC2, RSVD2, GMI, RSVD4, 0x31c4, N, N, N),
1817 PINGROUP(pi7, RSVD1, TRACE, GMI, DTV, RSVD1, 0x31c8, N, N, N), 1803 PINGROUP(pi7, RSVD1, TRACE, GMI, DTV, 0x31c8, N, N, N),
1818 PINGROUP(pk0, RSVD1, SDMMC3, GMI, SOC, RSVD1, 0x31cc, N, N, N), 1804 PINGROUP(pk0, RSVD1, SDMMC3, GMI, SOC, 0x31cc, N, N, N),
1819 PINGROUP(pk1, SDMMC2, TRACE, GMI, RSVD4, GMI, 0x31d0, N, N, N), 1805 PINGROUP(pk1, SDMMC2, TRACE, GMI, RSVD4, 0x31d0, N, N, N),
1820 PINGROUP(pj0, RSVD1, RSVD2, GMI, USB, RSVD1, 0x31d4, N, N, N), 1806 PINGROUP(pj0, RSVD1, RSVD2, GMI, USB, 0x31d4, N, N, N),
1821 PINGROUP(pj2, RSVD1, RSVD2, GMI, SOC, RSVD1, 0x31d8, N, N, N), 1807 PINGROUP(pj2, RSVD1, RSVD2, GMI, SOC, 0x31d8, N, N, N),
1822 PINGROUP(pk3, SDMMC2, TRACE, GMI, CCLA, GMI, 0x31dc, N, N, N), 1808 PINGROUP(pk3, SDMMC2, TRACE, GMI, CCLA, 0x31dc, N, N, N),
1823 PINGROUP(pk4, SDMMC2, RSVD2, GMI, GMI_ALT, GMI, 0x31e0, N, N, N), 1809 PINGROUP(pk4, SDMMC2, RSVD2, GMI, GMI_ALT, 0x31e0, N, N, N),
1824 PINGROUP(pk2, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x31e4, N, N, N), 1810 PINGROUP(pk2, RSVD1, RSVD2, GMI, RSVD4, 0x31e4, N, N, N),
1825 PINGROUP(pi3, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x31e8, N, N, N), 1811 PINGROUP(pi3, RSVD1, RSVD2, GMI, SPI4, 0x31e8, N, N, N),
1826 PINGROUP(pi6, RSVD1, RSVD2, GMI, SDMMC2, RSVD1, 0x31ec, N, N, N), 1812 PINGROUP(pi6, RSVD1, RSVD2, GMI, SDMMC2, 0x31ec, N, N, N),
1827 PINGROUP(pg0, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x31f0, N, N, N), 1813 PINGROUP(pg0, RSVD1, RSVD2, GMI, RSVD4, 0x31f0, N, N, N),
1828 PINGROUP(pg1, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x31f4, N, N, N), 1814 PINGROUP(pg1, RSVD1, RSVD2, GMI, RSVD4, 0x31f4, N, N, N),
1829 PINGROUP(pg2, RSVD1, TRACE, GMI, RSVD4, RSVD4, 0x31f8, N, N, N), 1815 PINGROUP(pg2, RSVD1, TRACE, GMI, RSVD4, 0x31f8, N, N, N),
1830 PINGROUP(pg3, RSVD1, TRACE, GMI, RSVD4, RSVD4, 0x31fc, N, N, N), 1816 PINGROUP(pg3, RSVD1, TRACE, GMI, RSVD4, 0x31fc, N, N, N),
1831 PINGROUP(pg4, RSVD1, TMDS, GMI, SPI4, RSVD1, 0x3200, N, N, N), 1817 PINGROUP(pg4, RSVD1, TMDS, GMI, SPI4, 0x3200, N, N, N),
1832 PINGROUP(pg5, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x3204, N, N, N), 1818 PINGROUP(pg5, RSVD1, RSVD2, GMI, SPI4, 0x3204, N, N, N),
1833 PINGROUP(pg6, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x3208, N, N, N), 1819 PINGROUP(pg6, RSVD1, RSVD2, GMI, SPI4, 0x3208, N, N, N),
1834 PINGROUP(pg7, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x320c, N, N, N), 1820 PINGROUP(pg7, RSVD1, RSVD2, GMI, SPI4, 0x320c, N, N, N),
1835 PINGROUP(ph0, PWM0, TRACE, GMI, DTV, GMI, 0x3210, N, N, N), 1821 PINGROUP(ph0, PWM0, TRACE, GMI, DTV, 0x3210, N, N, N),
1836 PINGROUP(ph1, PWM1, TMDS, GMI, DISPLAYA, GMI, 0x3214, N, N, N), 1822 PINGROUP(ph1, PWM1, TMDS, GMI, DISPLAYA, 0x3214, N, N, N),
1837 PINGROUP(ph2, PWM2, TMDS, GMI, CLDVFS, GMI, 0x3218, N, N, N), 1823 PINGROUP(ph2, PWM2, TMDS, GMI, CLDVFS, 0x3218, N, N, N),
1838 PINGROUP(ph3, PWM3, SPI4, GMI, CLDVFS, GMI, 0x321c, N, N, N), 1824 PINGROUP(ph3, PWM3, SPI4, GMI, CLDVFS, 0x321c, N, N, N),
1839 PINGROUP(ph4, SDMMC2, RSVD2, GMI, RSVD4, GMI, 0x3220, N, N, N), 1825 PINGROUP(ph4, SDMMC2, RSVD2, GMI, RSVD4, 0x3220, N, N, N),
1840 PINGROUP(ph5, SDMMC2, RSVD2, GMI, RSVD4, GMI, 0x3224, N, N, N), 1826 PINGROUP(ph5, SDMMC2, RSVD2, GMI, RSVD4, 0x3224, N, N, N),
1841 PINGROUP(ph6, SDMMC2, TRACE, GMI, DTV, GMI, 0x3228, N, N, N), 1827 PINGROUP(ph6, SDMMC2, TRACE, GMI, DTV, 0x3228, N, N, N),
1842 PINGROUP(ph7, SDMMC2, TRACE, GMI, DTV, GMI, 0x322c, N, N, N), 1828 PINGROUP(ph7, SDMMC2, TRACE, GMI, DTV, 0x322c, N, N, N),
1843 PINGROUP(pj7, UARTD, RSVD2, GMI, GMI_ALT, RSVD2, 0x3230, N, N, N), 1829 PINGROUP(pj7, UARTD, RSVD2, GMI, GMI_ALT, 0x3230, N, N, N),
1844 PINGROUP(pb0, UARTD, RSVD2, GMI, RSVD4, RSVD2, 0x3234, N, N, N), 1830 PINGROUP(pb0, UARTD, RSVD2, GMI, RSVD4, 0x3234, N, N, N),
1845 PINGROUP(pb1, UARTD, RSVD2, GMI, RSVD4, RSVD2, 0x3238, N, N, N), 1831 PINGROUP(pb1, UARTD, RSVD2, GMI, RSVD4, 0x3238, N, N, N),
1846 PINGROUP(pk7, UARTD, RSVD2, GMI, RSVD4, RSVD2, 0x323c, N, N, N), 1832 PINGROUP(pk7, UARTD, RSVD2, GMI, RSVD4, 0x323c, N, N, N),
1847 PINGROUP(pi0, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x3240, N, N, N), 1833 PINGROUP(pi0, RSVD1, RSVD2, GMI, RSVD4, 0x3240, N, N, N),
1848 PINGROUP(pi1, RSVD1, RSVD2, GMI, RSVD4, RSVD1, 0x3244, N, N, N), 1834 PINGROUP(pi1, RSVD1, RSVD2, GMI, RSVD4, 0x3244, N, N, N),
1849 PINGROUP(pi2, SDMMC2, TRACE, GMI, RSVD4, GMI, 0x3248, N, N, N), 1835 PINGROUP(pi2, SDMMC2, TRACE, GMI, RSVD4, 0x3248, N, N, N),
1850 PINGROUP(pi4, SPI4, TRACE, GMI, DISPLAYA, GMI, 0x324c, N, N, N), 1836 PINGROUP(pi4, SPI4, TRACE, GMI, DISPLAYA, 0x324c, N, N, N),
1851 PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, RSVD2, 0x3250, Y, N, N), 1837 PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N),
1852 PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, RSVD2, 0x3254, Y, N, N), 1838 PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N),
1853 PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, RSVD2, 0x3258, N, Y, N), 1839 PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N),
1854 PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, RSVD2, 0x325c, N, Y, N), 1840 PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N),
1855 PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3260, N, Y, N), 1841 PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N),
1856 PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3264, N, Y, N), 1842 PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N),
1857 PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3268, N, Y, N), 1843 PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N),
1858 PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x326c, N, Y, N), 1844 PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N),
1859 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3270, N, Y, N), 1845 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N),
1860 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, SDMMC4, 0x3274, N, Y, N), 1846 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, 0x3274, N, Y, N),
1861 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3278, N, Y, N), 1847 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N),
1862 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, SDMMC4, 0x327c, N, Y, N), 1848 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N),
1863 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, VI, 0x3284, N, N, N), 1849 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, 0x3284, N, N, N),
1864 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, I2S4, 0x3288, N, N, N), 1850 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, 0x3288, N, N, N),
1865 PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, VGP6, 0x328c, N, N, N), 1851 PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, 0x328c, N, N, N),
1866 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, VGP1, 0x3290, Y, N, N), 1852 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, 0x3290, Y, N, N),
1867 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, VGP2, 0x3294, Y, N, N), 1853 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, 0x3294, Y, N, N),
1868 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC2, VGP3, 0x3298, N, N, N), 1854 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC2, 0x3298, N, N, N),
1869 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC2, VGP4, 0x329c, N, N, N), 1855 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC2, 0x329c, N, N, N),
1870 PINGROUP(pbb5, VGP5, DISPLAYA, RSVD3, SDMMC2, VGP5, 0x32a0, N, N, N), 1856 PINGROUP(pbb5, VGP5, DISPLAYA, RSVD3, SDMMC2, 0x32a0, N, N, N),
1871 PINGROUP(pbb6, I2S4, RSVD2, DISPLAYB, SDMMC2, I2S4, 0x32a4, N, N, N), 1857 PINGROUP(pbb6, I2S4, RSVD2, DISPLAYB, SDMMC2, 0x32a4, N, N, N),
1872 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC2, I2S4, 0x32a8, N, N, N), 1858 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC2, 0x32a8, N, N, N),
1873 PINGROUP(pcc2, I2S4, RSVD2, SDMMC3, SDMMC2, I2S4, 0x32ac, N, N, N), 1859 PINGROUP(pcc2, I2S4, RSVD2, SDMMC3, SDMMC2, 0x32ac, N, N, N),
1874 PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, RTCK, 0x32b0, N, N, N), 1860 PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N),
1875 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD2, 0x32b4, Y, N, N), 1861 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N),
1876 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD2, 0x32b8, Y, N, N), 1862 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N),
1877 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32bc, N, N, N), 1863 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N),
1878 PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c0, N, N, N), 1864 PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N),
1879 PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c4, N, N, N), 1865 PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N),
1880 PINGROUP(kb_row3_pr3, KBC, DISPLAYA, SYS, DISPLAYB, KBC, 0x32c8, N, N, N), 1866 PINGROUP(kb_row3_pr3, KBC, DISPLAYA, SYS, DISPLAYB, 0x32c8, N, N, N),
1881 PINGROUP(kb_row4_pr4, KBC, DISPLAYA, RSVD3, DISPLAYB, RSVD3, 0x32cc, N, N, N), 1867 PINGROUP(kb_row4_pr4, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32cc, N, N, N),
1882 PINGROUP(kb_row5_pr5, KBC, DISPLAYA, RSVD3, DISPLAYB, RSVD3, 0x32d0, N, N, N), 1868 PINGROUP(kb_row5_pr5, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32d0, N, N, N),
1883 PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, KBC, 0x32d4, N, N, N), 1869 PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N),
1884 PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32d8, N, N, N), 1870 PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N),
1885 PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32dc, N, N, N), 1871 PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N),
1886 PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, KBC, 0x32e0, N, N, N), 1872 PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N),
1887 PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, KBC, 0x32e4, N, N, N), 1873 PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N),
1888 PINGROUP(kb_row11_ps3, KBC, RSVD2, RSVD3, IRDA, RSVD3, 0x32e8, N, N, N), 1874 PINGROUP(kb_row11_ps3, KBC, RSVD2, RSVD3, IRDA, 0x32e8, N, N, N),
1889 PINGROUP(kb_row12_ps4, KBC, RSVD2, RSVD3, IRDA, RSVD3, 0x32ec, N, N, N), 1875 PINGROUP(kb_row12_ps4, KBC, RSVD2, RSVD3, IRDA, 0x32ec, N, N, N),
1890 PINGROUP(kb_row13_ps5, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x32f0, N, N, N), 1876 PINGROUP(kb_row13_ps5, KBC, RSVD2, SPI2, RSVD4, 0x32f0, N, N, N),
1891 PINGROUP(kb_row14_ps6, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x32f4, N, N, N), 1877 PINGROUP(kb_row14_ps6, KBC, RSVD2, SPI2, RSVD4, 0x32f4, N, N, N),
1892 PINGROUP(kb_row15_ps7, KBC, SOC, RSVD3, RSVD4, KBC, 0x32f8, N, N, N), 1878 PINGROUP(kb_row15_ps7, KBC, SOC, RSVD3, RSVD4, 0x32f8, N, N, N),
1893 PINGROUP(kb_col0_pq0, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x32fc, N, N, N), 1879 PINGROUP(kb_col0_pq0, KBC, RSVD2, SPI2, RSVD4, 0x32fc, N, N, N),
1894 PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3300, N, N, N), 1880 PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, RSVD4, 0x3300, N, N, N),
1895 PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3304, N, N, N), 1881 PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N),
1896 PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, KBC, 0x3308, N, N, N), 1882 PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N),
1897 PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, KBC, 0x330c, N, N, N), 1883 PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N),
1898 PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC3, RSVD4, RSVD4, 0x3310, N, N, N), 1884 PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC3, RSVD4, 0x3310, N, N, N),
1899 PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, UARTD, RSVD2, 0x3314, N, N, N), 1885 PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, UARTD, 0x3314, N, N, N),
1900 PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, UARTD, RSVD2, 0x3318, N, N, N), 1886 PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, UARTD, 0x3318, N, N, N),
1901 PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, RSVD3, 0x331c, N, N, N), 1887 PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N),
1902 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, RSVD2, 0x3324, N, N, N), 1888 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N),
1903 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, RSVD2, 0x3328, N, N, N), 1889 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N),
1904 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, RSVD2, 0x332c, N, N, N), 1890 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N),
1905 PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, RSVD2, 0x3330, N, N, N), 1891 PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
1906 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, RSVD2, 0x3334, N, N, Y), 1892 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y),
1907 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3338, N, N, N), 1893 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N),
1908 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, RSVD4, 0x333c, N, N, N), 1894 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N),
1909 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SATA, I2S0, 0x3340, N, N, N), 1895 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SATA, 0x3340, N, N, N),
1910 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, I2S0, 0x3344, N, N, N), 1896 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N),
1911 PINGROUP(dap_mclk1_req_pee2, DAP, DAP1, SATA, RSVD4, DAP, 0x3348, N, N, N), 1897 PINGROUP(dap_mclk1_req_pee2, DAP, DAP1, SATA, RSVD4, 0x3348, N, N, N),
1912 PINGROUP(dap_mclk1_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, RSVD3, 0x334c, N, N, N), 1898 PINGROUP(dap_mclk1_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N),
1913 PINGROUP(spdif_in_pk6, SPDIF, RSVD2, RSVD3, I2C3, RSVD3, 0x3350, N, N, N), 1899 PINGROUP(spdif_in_pk6, SPDIF, RSVD2, RSVD3, I2C3, 0x3350, N, N, N),
1914 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, I2C3, RSVD3, 0x3354, N, N, N), 1900 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, I2C3, 0x3354, N, N, N),
1915 PINGROUP(dap2_fs_pa2, I2S1, HDA, GMI, RSVD4, I2S1, 0x3358, N, N, N), 1901 PINGROUP(dap2_fs_pa2, I2S1, HDA, GMI, RSVD4, 0x3358, N, N, N),
1916 PINGROUP(dap2_din_pa4, I2S1, HDA, GMI, RSVD4, I2S1, 0x335c, N, N, N), 1902 PINGROUP(dap2_din_pa4, I2S1, HDA, GMI, RSVD4, 0x335c, N, N, N),
1917 PINGROUP(dap2_dout_pa5, I2S1, HDA, GMI, RSVD4, I2S1, 0x3360, N, N, N), 1903 PINGROUP(dap2_dout_pa5, I2S1, HDA, GMI, RSVD4, 0x3360, N, N, N),
1918 PINGROUP(dap2_sclk_pa3, I2S1, HDA, GMI, RSVD4, I2S1, 0x3364, N, N, N), 1904 PINGROUP(dap2_sclk_pa3, I2S1, HDA, GMI, RSVD4, 0x3364, N, N, N),
1919 PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, GMI, RSVD4, SPI6, 0x3368, N, N, N), 1905 PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, GMI, RSVD4, 0x3368, N, N, N),
1920 PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, GMI, RSVD4, SPI6, 0x336c, N, N, N), 1906 PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, GMI, RSVD4, 0x336c, N, N, N),
1921 PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, GMI, RSVD4, SPI6, 0x3370, N, N, N), 1907 PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, GMI, RSVD4, 0x3370, N, N, N),
1922 PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, GMI, RSVD4, SPI6, 0x3374, N, N, N), 1908 PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, GMI, RSVD4, 0x3374, N, N, N),
1923 PINGROUP(gpio_x4_aud_px4, GMI, SPI1, SPI2, DAP2, SPI1, 0x3378, N, N, N), 1909 PINGROUP(gpio_x4_aud_px4, GMI, SPI1, SPI2, DAP2, 0x3378, N, N, N),
1924 PINGROUP(gpio_x5_aud_px5, GMI, SPI1, SPI2, RSVD4, SPI1, 0x337c, N, N, N), 1910 PINGROUP(gpio_x5_aud_px5, GMI, SPI1, SPI2, RSVD4, 0x337c, N, N, N),
1925 PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, GMI, SPI1, 0x3380, N, N, N), 1911 PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, GMI, 0x3380, N, N, N),
1926 PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, SPI1, 0x3384, N, N, N), 1912 PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N),
1927 PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, SDMMC3, 0x3390, N, N, N), 1913 PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N),
1928 PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, SDMMC3, 0x3394, N, N, N), 1914 PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N),
1929 PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, SDMMC3, 0x3398, N, N, N), 1915 PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N),
1930 PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, SDMMC3, 0x339c, N, N, N), 1916 PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N),
1931 PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, SDMMC3, 0x33a0, N, N, N), 1917 PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N),
1932 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, SDMMC3, 0x33a4, N, N, N), 1918 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
1933 PINGROUP(pex_l0_rst_n_pdd1, PE0, RSVD2, RSVD3, RSVD4, PE0, 0x33bc, N, N, N), 1919 PINGROUP(pex_l0_rst_n_pdd1, PE0, RSVD2, RSVD3, RSVD4, 0x33bc, N, N, N),
1934 PINGROUP(pex_l0_clkreq_n_pdd2, PE0, RSVD2, RSVD3, RSVD4, PE0, 0x33c0, N, N, N), 1920 PINGROUP(pex_l0_clkreq_n_pdd2, PE0, RSVD2, RSVD3, RSVD4, 0x33c0, N, N, N),
1935 PINGROUP(pex_wake_n_pdd3, PE, RSVD2, RSVD3, RSVD4, PE, 0x33c4, N, N, N), 1921 PINGROUP(pex_wake_n_pdd3, PE, RSVD2, RSVD3, RSVD4, 0x33c4, N, N, N),
1936 PINGROUP(pex_l1_rst_n_pdd5, PE1, RSVD2, RSVD3, RSVD4, PE1, 0x33cc, N, N, N), 1922 PINGROUP(pex_l1_rst_n_pdd5, PE1, RSVD2, RSVD3, RSVD4, 0x33cc, N, N, N),
1937 PINGROUP(pex_l1_clkreq_n_pdd6, PE1, RSVD2, RSVD3, RSVD4, PE1, 0x33d0, N, N, N), 1923 PINGROUP(pex_l1_clkreq_n_pdd6, PE1, RSVD2, RSVD3, RSVD4, 0x33d0, N, N, N),
1938 PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, CEC, 0x33e0, Y, N, N), 1924 PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N, N),
1939 PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, SDMMC1, 0x33e4, N, N, N), 1925 PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N),
1940 PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, SDMMC3, 0x33e8, N, N, N), 1926 PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N),
1941 PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, RSVD2, 0x33ec, N, N, N), 1927 PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N),
1942 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, SPI1, 0x33f0, N, N, N), 1928 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N),
1943 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, USB, 0x33f4, Y, N, N), 1929 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N),
1944 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, USB, 0x33f8, Y, N, N), 1930 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N),
1945 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, SDMMC3, 0x33fc, N, N, N), 1931 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N),
1946 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, SDMMC3, 0x3400, N, N, N), 1932 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N),
1947 PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, SDMMC2, 0x3404, N, N, N), 1933 PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, 0x3404, N, N, N),
1948 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD1, 0x3408, N, N, N), 1934 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N),
1949 PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, KBC, 0x340c, N, N, N), 1935 PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, 0x340c, N, N, N),
1950 PINGROUP(kb_row17_pt1, KBC, RSVD2, RSVD3, UARTC, KBC, 0x3410, N, N, N), 1936 PINGROUP(kb_row17_pt1, KBC, RSVD2, RSVD3, UARTC, 0x3410, N, N, N),
1951 PINGROUP(usb_vbus_en2_pff1, USB, RSVD2, RSVD3, RSVD4, USB, 0x3414, Y, N, N), 1937 PINGROUP(usb_vbus_en2_pff1, USB, RSVD2, RSVD3, RSVD4, 0x3414, Y, N, N),
1952 PINGROUP(pff2, SATA, RSVD2, RSVD3, RSVD4, RSVD2, 0x3418, Y, N, N), 1938 PINGROUP(pff2, SATA, RSVD2, RSVD3, RSVD4, 0x3418, Y, N, N),
1953 PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, DP, 0x3430, N, N, N), 1939 PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, 0x3430, N, N, N),
1954 1940
1955 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */ 1941 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
1956 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1942 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1957 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1943 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1958 DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1944 DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
1959 DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1945 DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
1960 DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1946 DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
1961 DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1947 DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
1962 DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1948 DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
1963 DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1949 DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1964 DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1950 DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1965 DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1951 DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1966 DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1952 DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1967 DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1953 DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1968 DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1954 DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1969 DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1955 DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1970 DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), 1956 DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
1971 DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1957 DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1972 DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1958 DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1973 DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1959 DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1974 DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1960 DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1975 DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1961 DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1976 DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), 1962 DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
1977 DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1963 DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1978 DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y), 1964 DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y),
1979 DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1965 DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
1980 DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1966 DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
1981 DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1967 DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
1982 DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1968 DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
1983 DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1969 DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1984 DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1970 DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1985 DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1971 DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1986 DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1972 DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1987 DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1973 DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1988 DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1974 DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
1989 DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1975 DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1990 DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1976 DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1991 DRV_PINGROUP(ao3, 0x9a8, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), 1977 DRV_PINGROUP(ao3, 0x9a8, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
1992 DRV_PINGROUP(ao0, 0x9b0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1978 DRV_PINGROUP(ao0, 0x9b0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1993 DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), 1979 DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
1994 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1980 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1995 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1981 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
1996}; 1982};
1997 1983
1998static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { 1984static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index e0b504088387..7563ebc9c791 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -1973,7 +1973,7 @@ static struct tegra_function tegra20_functions[] = {
1973#define PINGROUP_REG_A 0x868 1973#define PINGROUP_REG_A 0x868
1974 1974
1975/* Pin group with mux control, and typically tri-state and pull-up/down too */ 1975/* Pin group with mux control, and typically tri-state and pull-up/down too */
1976#define MUX_PG(pg_name, f0, f1, f2, f3, f_safe, \ 1976#define MUX_PG(pg_name, f0, f1, f2, f3, \
1977 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \ 1977 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
1978 { \ 1978 { \
1979 .name = #pg_name, \ 1979 .name = #pg_name, \
@@ -1985,7 +1985,6 @@ static struct tegra_function tegra20_functions[] = {
1985 TEGRA_MUX_ ## f2, \ 1985 TEGRA_MUX_ ## f2, \
1986 TEGRA_MUX_ ## f3, \ 1986 TEGRA_MUX_ ## f3, \
1987 }, \ 1987 }, \
1988 .func_safe = TEGRA_MUX_ ## f_safe, \
1989 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \ 1988 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
1990 .mux_bank = 1, \ 1989 .mux_bank = 1, \
1991 .mux_bit = mux_b, \ 1990 .mux_bit = mux_b, \
@@ -1995,13 +1994,12 @@ static struct tegra_function tegra20_functions[] = {
1995 .tri_reg = ((tri_r) - TRISTATE_REG_A), \ 1994 .tri_reg = ((tri_r) - TRISTATE_REG_A), \
1996 .tri_bank = 0, \ 1995 .tri_bank = 0, \
1997 .tri_bit = tri_b, \ 1996 .tri_bit = tri_b, \
1998 .einput_reg = -1, \ 1997 .einput_bit = -1, \
1999 .odrain_reg = -1, \ 1998 .odrain_bit = -1, \
2000 .lock_reg = -1, \ 1999 .lock_bit = -1, \
2001 .ioreset_reg = -1, \ 2000 .ioreset_bit = -1, \
2002 .rcv_sel_reg = -1, \ 2001 .rcv_sel_bit = -1, \
2003 .drv_reg = -1, \ 2002 .drv_reg = -1, \
2004 .drvtype_reg = -1, \
2005 } 2003 }
2006 2004
2007/* Pin groups with only pull up and pull down control */ 2005/* Pin groups with only pull up and pull down control */
@@ -2014,14 +2012,7 @@ static struct tegra_function tegra20_functions[] = {
2014 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ 2012 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
2015 .pupd_bank = 2, \ 2013 .pupd_bank = 2, \
2016 .pupd_bit = pupd_b, \ 2014 .pupd_bit = pupd_b, \
2017 .tri_reg = -1, \
2018 .einput_reg = -1, \
2019 .odrain_reg = -1, \
2020 .lock_reg = -1, \
2021 .ioreset_reg = -1, \
2022 .rcv_sel_reg = -1, \
2023 .drv_reg = -1, \ 2015 .drv_reg = -1, \
2024 .drvtype_reg = -1, \
2025 } 2016 }
2026 2017
2027/* Pin groups for drive strength registers (configurable version) */ 2018/* Pin groups for drive strength registers (configurable version) */
@@ -2035,11 +2026,6 @@ static struct tegra_function tegra20_functions[] = {
2035 .mux_reg = -1, \ 2026 .mux_reg = -1, \
2036 .pupd_reg = -1, \ 2027 .pupd_reg = -1, \
2037 .tri_reg = -1, \ 2028 .tri_reg = -1, \
2038 .einput_reg = -1, \
2039 .odrain_reg = -1, \
2040 .lock_reg = -1, \
2041 .ioreset_reg = -1, \
2042 .rcv_sel_reg = -1, \
2043 .drv_reg = ((r) - PINGROUP_REG_A), \ 2029 .drv_reg = ((r) - PINGROUP_REG_A), \
2044 .drv_bank = 3, \ 2030 .drv_bank = 3, \
2045 .hsm_bit = hsm_b, \ 2031 .hsm_bit = hsm_b, \
@@ -2053,7 +2039,7 @@ static struct tegra_function tegra20_functions[] = {
2053 .slwr_width = slwr_w, \ 2039 .slwr_width = slwr_w, \
2054 .slwf_bit = slwf_b, \ 2040 .slwf_bit = slwf_b, \
2055 .slwf_width = slwf_w, \ 2041 .slwf_width = slwf_w, \
2056 .drvtype_reg = -1, \ 2042 .drvtype_bit = -1, \
2057 } 2043 }
2058 2044
2059/* Pin groups for drive strength registers (simple version) */ 2045/* Pin groups for drive strength registers (simple version) */
@@ -2061,114 +2047,114 @@ static struct tegra_function tegra20_functions[] = {
2061 DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2) 2047 DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2)
2062 2048
2063static const struct tegra_pingroup tegra20_groups[] = { 2049static const struct tegra_pingroup tegra20_groups[] = {
2064 /* name, f0, f1, f2, f3, f_safe, tri r/b, mux r/b, pupd r/b */ 2050 /* name, f0, f1, f2, f3, tri r/b, mux r/b, pupd r/b */
2065 MUX_PG(ata, IDE, NAND, GMI, RSVD4, IDE, 0x14, 0, 0x80, 24, 0xa0, 0), 2051 MUX_PG(ata, IDE, NAND, GMI, RSVD4, 0x14, 0, 0x80, 24, 0xa0, 0),
2066 MUX_PG(atb, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xa0, 2), 2052 MUX_PG(atb, IDE, NAND, GMI, SDIO4, 0x14, 1, 0x80, 16, 0xa0, 2),
2067 MUX_PG(atc, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xa0, 4), 2053 MUX_PG(atc, IDE, NAND, GMI, SDIO4, 0x14, 2, 0x80, 22, 0xa0, 4),
2068 MUX_PG(atd, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xa0, 6), 2054 MUX_PG(atd, IDE, NAND, GMI, SDIO4, 0x14, 3, 0x80, 20, 0xa0, 6),
2069 MUX_PG(ate, IDE, NAND, GMI, RSVD4, IDE, 0x18, 25, 0x80, 12, 0xa0, 8), 2055 MUX_PG(ate, IDE, NAND, GMI, RSVD4, 0x18, 25, 0x80, 12, 0xa0, 8),
2070 MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xa8, 0), 2056 MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0),
2071 MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xa8, 2), 2057 MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2),
2072 MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, RSVD2, 0x20, 14, 0x98, 20, 0xa4, 24), 2058 MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, 0x20, 14, 0x98, 20, 0xa4, 24),
2073 MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xac, 24), 2059 MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, 0x14, 6, 0x88, 6, 0xac, 24),
2074 MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xa0, 10), 2060 MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, 0x14, 7, 0x88, 20, 0xa0, 10),
2075 MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, DAP2, 0x14, 8, 0x88, 22, 0xa0, 12), 2061 MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, 0x14, 8, 0x88, 22, 0xa0, 12),
2076 MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, DAP3, 0x14, 9, 0x88, 24, 0xa0, 14), 2062 MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, 0x14, 9, 0x88, 24, 0xa0, 14),
2077 MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, DAP4, 0x14, 10, 0x88, 26, 0xa0, 16), 2063 MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, 0x14, 10, 0x88, 26, 0xa0, 16),
2078 MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28), 2064 MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28),
2079 MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18), 2065 MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18),
2080 MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xa0, 20), 2066 MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, 0x14, 12, 0x84, 22, 0xa0, 20),
2081 MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, RSVD1, 0x14, 13, 0x84, 26, 0xa0, 22), 2067 MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, 0x14, 13, 0x84, 26, 0xa0, 22),
2082 MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, RSVD1, 0x14, 14, 0x84, 28, 0xa0, 24), 2068 MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, 0x14, 14, 0x84, 28, 0xa0, 24),
2083 MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xa0, 26), 2069 MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, 0x14, 15, 0x84, 30, 0xa0, 26),
2084 MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28), 2070 MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28),
2085 MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xb0, 20), 2071 MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, 0x14, 28, 0x84, 0, 0xb0, 20),
2086 MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xb0, 22), 2072 MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, 0x18, 29, 0x88, 28, 0xb0, 22),
2087 MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xb0, 24), 2073 MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, 0x14, 29, 0x84, 2, 0xb0, 24),
2088 MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xb0, 26), 2074 MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, 0x18, 30, 0x88, 30, 0xb0, 26),
2089 MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8c, 0, 0xa8, 24), 2075 MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, 0x18, 0, 0x8c, 0, 0xa8, 24),
2090 MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20), 2076 MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
2091 MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, RTCK, 0x20, 11, 0x98, 28, 0xa4, 6), 2077 MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, 0x20, 11, 0x98, 28, 0xa4, 6),
2092 MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, PCIE, 0x14, 17, 0x8c, 2, 0xa0, 30), 2078 MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, 0x14, 17, 0x8c, 2, 0xa0, 30),
2093 MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, HDMI, 0x1c, 23, 0x84, 4, -1, -1), 2079 MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, 0x1c, 23, 0x84, 4, -1, -1),
2094 MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2), 2080 MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2),
2095 MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xa8, 22), 2081 MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, 0x14, 20, 0x88, 18, 0xa8, 22),
2096 MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xa8, 20), 2082 MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, 0x14, 19, 0x88, 16, 0xa8, 20),
2097 MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xa4, 8), 2083 MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, 0x14, 22, 0x88, 10, 0xa4, 8),
2098 MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xa4, 10), 2084 MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, 0x14, 21, 0x88, 12, 0xa4, 10),
2099 MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xa4, 12), 2085 MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, 0x18, 26, 0x88, 14, 0xa4, 12),
2100 MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xa4, 14), 2086 MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, 0x20, 10, 0x98, 26, 0xa4, 14),
2101 MUX_PG(kbce, KBC, NAND, OWR, RSVD4, KBC, 0x14, 26, 0x80, 28, 0xb0, 2), 2087 MUX_PG(kbce, KBC, NAND, OWR, RSVD4, 0x14, 26, 0x80, 28, 0xb0, 2),
2102 MUX_PG(kbcf, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xb0, 0), 2088 MUX_PG(kbcf, KBC, NAND, TRACE, MIO, 0x14, 27, 0x80, 26, 0xb0, 0),
2103 MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, RSVD4, 0x1c, 31, 0x90, 12, -1, -1), 2089 MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 31, 0x90, 12, -1, -1),
2104 MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 0, 0x94, 0, -1, -1), 2090 MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 0, 0x94, 0, -1, -1),
2105 MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 1, 0x94, 2, -1, -1), 2091 MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 1, 0x94, 2, -1, -1),
2106 MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 2, 0x94, 4, -1, -1), 2092 MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 2, 0x94, 4, -1, -1),
2107 MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 3, 0x94, 6, -1, -1), 2093 MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 3, 0x94, 6, -1, -1),
2108 MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 4, 0x94, 8, -1, -1), 2094 MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 4, 0x94, 8, -1, -1),
2109 MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 5, 0x94, 10, -1, -1), 2095 MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 5, 0x94, 10, -1, -1),
2110 MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 6, 0x94, 12, -1, -1), 2096 MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 6, 0x94, 12, -1, -1),
2111 MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 7, 0x94, 14, -1, -1), 2097 MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 7, 0x94, 14, -1, -1),
2112 MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 8, 0x94, 16, -1, -1), 2098 MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 8, 0x94, 16, -1, -1),
2113 MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 9, 0x94, 18, -1, -1), 2099 MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 9, 0x94, 18, -1, -1),
2114 MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 10, 0x94, 20, -1, -1), 2100 MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 10, 0x94, 20, -1, -1),
2115 MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 11, 0x94, 22, -1, -1), 2101 MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 11, 0x94, 22, -1, -1),
2116 MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 12, 0x94, 24, -1, -1), 2102 MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 12, 0x94, 24, -1, -1),
2117 MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 13, 0x94, 26, -1, -1), 2103 MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 13, 0x94, 26, -1, -1),
2118 MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 14, 0x94, 28, -1, -1), 2104 MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 14, 0x94, 28, -1, -1),
2119 MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 15, 0x94, 30, -1, -1), 2105 MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 15, 0x94, 30, -1, -1),
2120 MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 16, 0x98, 0, -1, -1), 2106 MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 16, 0x98, 0, -1, -1),
2121 MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 17, 0x98, 2, -1, -1), 2107 MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 17, 0x98, 2, -1, -1),
2122 MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 30, 0x90, 14, -1, -1), 2108 MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 30, 0x90, 14, -1, -1),
2123 MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 6, 0x98, 16, -1, -1), 2109 MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 6, 0x98, 16, -1, -1),
2124 MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 18, 0x98, 10, -1, -1), 2110 MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 18, 0x98, 10, -1, -1),
2125 MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 19, 0x98, 4, -1, -1), 2111 MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 19, 0x98, 4, -1, -1),
2126 MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 20, 0x98, 6, -1, -1), 2112 MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 20, 0x98, 6, -1, -1),
2127 MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x20, 7, 0x90, 22, -1, -1), 2113 MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x20, 7, 0x90, 22, -1, -1),
2128 MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, RSVD4, 0x1c, 24, 0x90, 26, -1, -1), 2114 MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 24, 0x90, 26, -1, -1),
2129 MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, RSVD3, 0x1c, 25, 0x90, 28, -1, -1), 2115 MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, 0x1c, 25, 0x90, 28, -1, -1),
2130 MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 8, 0x98, 14, -1, -1), 2116 MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 8, 0x98, 14, -1, -1),
2131 MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, -1, -1), 2117 MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 3, 0x90, 0, -1, -1),
2132 MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x20, 4, 0x90, 2, -1, -1), 2118 MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 4, 0x90, 2, -1, -1),
2133 MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, -1, -1), 2119 MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 5, 0x90, 4, -1, -1),
2134 MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 27, 0x90, 18, -1, -1), 2120 MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 27, 0x90, 18, -1, -1),
2135 MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1c, 28, 0x90, 20, -1, -1), 2121 MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 28, 0x90, 20, -1, -1),
2136 MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1c, 29, 0x90, 16, -1, -1), 2122 MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 29, 0x90, 16, -1, -1),
2137 MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, -1, -1), 2123 MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 1, 0x90, 8, -1, -1),
2138 MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, DISPLAYA, 0x20, 2, 0x90, 6, -1, -1), 2124 MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x20, 2, 0x90, 6, -1, -1),
2139 MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, -1, -1), 2125 MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, 0x20, 0, 0x90, 10, -1, -1),
2140 MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 21, 0x90, 30, -1, -1), 2126 MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 21, 0x90, 30, -1, -1),
2141 MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x1c, 22, 0x98, 8, -1, -1), 2127 MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 22, 0x98, 8, -1, -1),
2142 MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, RSVD4, 0x1c, 26, 0x90, 24, -1, -1), 2128 MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 26, 0x90, 24, -1, -1),
2143 MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, OWR, 0x14, 31, 0x84, 8, 0xb0, 30), 2129 MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, 0x14, 31, 0x84, 8, 0xb0, 30),
2144 MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, PWR_ON, 0x14, 23, 0x98, 18, -1, -1), 2130 MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, 0x14, 23, 0x98, 18, -1, -1),
2145 MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4), 2131 MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4),
2146 MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0), 2132 MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0),
2147 MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8c, 10, -1, -1), 2133 MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
2148 MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8c, 12, 0xac, 28), 2134 MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
2149 MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8c, 14, 0xac, 30), 2135 MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
2150 MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xb0, 18), 2136 MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, 0x14, 30, 0x80, 30, 0xb0, 18),
2151 MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xa4, 22), 2137 MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, 0x18, 3, 0x84, 6, 0xa4, 22),
2152 MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xa4, 26), 2138 MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, 0x18, 5, 0x84, 10, 0xa4, 26),
2153 MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xa4, 28), 2139 MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, 0x18, 6, 0x84, 12, 0xa4, 28),
2154 MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xa4, 30), 2140 MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, 0x18, 7, 0x84, 14, 0xa4, 30),
2155 MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, RSVD2, 0x18, 8, 0x8c, 8, 0xa4, 16), 2141 MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 8, 0x8c, 8, 0xa4, 16),
2156 MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, RSVD2, 0x18, 9, 0x8c, 6, 0xa4, 18), 2142 MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 9, 0x8c, 6, 0xa4, 18),
2157 MUX_PG(spia, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4), 2143 MUX_PG(spia, SPI1, SPI2, SPI3, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4),
2158 MUX_PG(spib, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6), 2144 MUX_PG(spib, SPI1, SPI2, SPI3, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6),
2159 MUX_PG(spic, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8), 2145 MUX_PG(spic, SPI1, SPI2, SPI3, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8),
2160 MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10), 2146 MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10),
2161 MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12), 2147 MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12),
2162 MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14), 2148 MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14),
2163 MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, SPI2_ALT, 0x18, 16, 0x8c, 18, 0xa8, 16), 2149 MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 16, 0x8c, 18, 0xa8, 16),
2164 MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, SPI2_ALT, 0x18, 17, 0x8c, 16, 0xa8, 18), 2150 MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 17, 0x8c, 16, 0xa8, 18),
2165 MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xac, 0), 2151 MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, 0x18, 18, 0x80, 0, 0xac, 0),
2166 MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xac, 2), 2152 MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, 0x18, 19, 0x80, 2, 0xac, 2),
2167 MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4), 2153 MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4),
2168 MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xac, 6), 2154 MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, 0x18, 21, 0x80, 6, 0xac, 6),
2169 MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8), 2155 MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8),
2170 MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10), 2156 MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
2171 MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xb0, 16), 2157 MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, 0x20, 13, 0x80, 8, 0xb0, 16),
2172 /* pg_name, pupd_r/b */ 2158 /* pg_name, pupd_r/b */
2173 PULL_PG(ck32, 0xb0, 14), 2159 PULL_PG(ck32, 0xb0, 14),
2174 PULL_PG(ddrc, 0xac, 26), 2160 PULL_PG(ddrc, 0xac, 26),
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 41d24f5c2854..fe2d2cf78ad9 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -2108,10 +2108,12 @@ static struct tegra_function tegra30_functions[] = {
2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2109#define PINGROUP_REG_A 0x3000 /* bank 1 */ 2109#define PINGROUP_REG_A 0x3000 /* bank 1 */
2110 2110
2111#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) 2111#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
2112#define PINGROUP_REG_N(r) -1
2113 2112
2114#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \ 2113#define PINGROUP_BIT_Y(b) (b)
2114#define PINGROUP_BIT_N(b) (-1)
2115
2116#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \
2115 { \ 2117 { \
2116 .name = #pg_name, \ 2118 .name = #pg_name, \
2117 .pins = pg_name##_pins, \ 2119 .pins = pg_name##_pins, \
@@ -2122,35 +2124,24 @@ static struct tegra_function tegra30_functions[] = {
2122 TEGRA_MUX_##f2, \ 2124 TEGRA_MUX_##f2, \
2123 TEGRA_MUX_##f3, \ 2125 TEGRA_MUX_##f3, \
2124 }, \ 2126 }, \
2125 .func_safe = TEGRA_MUX_##f_safe, \ 2127 .mux_reg = PINGROUP_REG(r), \
2126 .mux_reg = PINGROUP_REG_Y(r), \
2127 .mux_bank = 1, \ 2128 .mux_bank = 1, \
2128 .mux_bit = 0, \ 2129 .mux_bit = 0, \
2129 .pupd_reg = PINGROUP_REG_Y(r), \ 2130 .pupd_reg = PINGROUP_REG(r), \
2130 .pupd_bank = 1, \ 2131 .pupd_bank = 1, \
2131 .pupd_bit = 2, \ 2132 .pupd_bit = 2, \
2132 .tri_reg = PINGROUP_REG_Y(r), \ 2133 .tri_reg = PINGROUP_REG(r), \
2133 .tri_bank = 1, \ 2134 .tri_bank = 1, \
2134 .tri_bit = 4, \ 2135 .tri_bit = 4, \
2135 .einput_reg = PINGROUP_REG_Y(r), \ 2136 .einput_bit = PINGROUP_BIT_Y(5), \
2136 .einput_bank = 1, \ 2137 .odrain_bit = PINGROUP_BIT_##od(6), \
2137 .einput_bit = 5, \ 2138 .lock_bit = PINGROUP_BIT_Y(7), \
2138 .odrain_reg = PINGROUP_REG_##od(r), \ 2139 .ioreset_bit = PINGROUP_BIT_##ior(8), \
2139 .odrain_bank = 1, \ 2140 .rcv_sel_bit = -1, \
2140 .odrain_bit = 6, \
2141 .lock_reg = PINGROUP_REG_Y(r), \
2142 .lock_bank = 1, \
2143 .lock_bit = 7, \
2144 .ioreset_reg = PINGROUP_REG_##ior(r), \
2145 .ioreset_bank = 1, \
2146 .ioreset_bit = 8, \
2147 .rcv_sel_reg = -1, \
2148 .drv_reg = -1, \ 2141 .drv_reg = -1, \
2149 .drvtype_reg = -1, \
2150 } 2142 }
2151 2143
2152#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A) 2144#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
2153#define DRV_PINGROUP_REG_N(r) -1
2154 2145
2155#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 2146#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2156 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 2147 drvdn_b, drvdn_w, drvup_b, drvup_w, \
@@ -2162,12 +2153,12 @@ static struct tegra_function tegra30_functions[] = {
2162 .mux_reg = -1, \ 2153 .mux_reg = -1, \
2163 .pupd_reg = -1, \ 2154 .pupd_reg = -1, \
2164 .tri_reg = -1, \ 2155 .tri_reg = -1, \
2165 .einput_reg = -1, \ 2156 .einput_bit = -1, \
2166 .odrain_reg = -1, \ 2157 .odrain_bit = -1, \
2167 .lock_reg = -1, \ 2158 .lock_bit = -1, \
2168 .ioreset_reg = -1, \ 2159 .ioreset_bit = -1, \
2169 .rcv_sel_reg = -1, \ 2160 .rcv_sel_bit = -1, \
2170 .drv_reg = DRV_PINGROUP_REG_Y(r), \ 2161 .drv_reg = DRV_PINGROUP_REG(r), \
2171 .drv_bank = 0, \ 2162 .drv_bank = 0, \
2172 .hsm_bit = hsm_b, \ 2163 .hsm_bit = hsm_b, \
2173 .schmitt_bit = schmitt_b, \ 2164 .schmitt_bit = schmitt_b, \
@@ -2180,260 +2171,260 @@ static struct tegra_function tegra30_functions[] = {
2180 .slwr_width = slwr_w, \ 2171 .slwr_width = slwr_w, \
2181 .slwf_bit = slwf_b, \ 2172 .slwf_bit = slwf_b, \
2182 .slwf_width = slwf_w, \ 2173 .slwf_width = slwf_w, \
2183 .drvtype_reg = -1, \ 2174 .drvtype_bit = -1, \
2184 } 2175 }
2185 2176
2186static const struct tegra_pingroup tegra30_groups[] = { 2177static const struct tegra_pingroup tegra30_groups[] = {
2187 /* pg_name, f0, f1, f2, f3, safe, r, od, ior */ 2178 /* pg_name, f0, f1, f2, f3, r, od, ior */
2188 PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, RSVD4, 0x331c, N, N), 2179 PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, 0x331c, N, N),
2189 PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x317c, N, N), 2180 PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, 0x317c, N, N),
2190 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3358, N, N), 2181 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, 0x3358, N, N),
2191 PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3364, N, N), 2182 PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, GMI, 0x3364, N, N),
2192 PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, GMI, RSVD3, 0x335c, N, N), 2183 PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, GMI, 0x335c, N, N),
2193 PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, GMI, RSVD3, 0x3360, N, N), 2184 PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, GMI, 0x3360, N, N),
2194 PINGROUP(sdmmc3_clk_pa6, UARTA, PWM2, SDMMC3, SPI3, SPI3, 0x3390, N, N), 2185 PINGROUP(sdmmc3_clk_pa6, UARTA, PWM2, SDMMC3, SPI3, 0x3390, N, N),
2195 PINGROUP(sdmmc3_cmd_pa7, UARTA, PWM3, SDMMC3, SPI2, SPI2, 0x3394, N, N), 2186 PINGROUP(sdmmc3_cmd_pa7, UARTA, PWM3, SDMMC3, SPI2, 0x3394, N, N),
2196 PINGROUP(gmi_a17_pb0, UARTD, SPI4, GMI, DTV, DTV, 0x3234, N, N), 2187 PINGROUP(gmi_a17_pb0, UARTD, SPI4, GMI, DTV, 0x3234, N, N),
2197 PINGROUP(gmi_a18_pb1, UARTD, SPI4, GMI, DTV, DTV, 0x3238, N, N), 2188 PINGROUP(gmi_a18_pb1, UARTD, SPI4, GMI, DTV, 0x3238, N, N),
2198 PINGROUP(lcd_pwr0_pb2, DISPLAYA, DISPLAYB, SPI5, HDCP, HDCP, 0x3090, N, N), 2189 PINGROUP(lcd_pwr0_pb2, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3090, N, N),
2199 PINGROUP(lcd_pclk_pb3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3094, N, N), 2190 PINGROUP(lcd_pclk_pb3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3094, N, N),
2200 PINGROUP(sdmmc3_dat3_pb4, RSVD1, PWM0, SDMMC3, SPI3, RSVD1, 0x33a4, N, N), 2191 PINGROUP(sdmmc3_dat3_pb4, RSVD1, PWM0, SDMMC3, SPI3, 0x33a4, N, N),
2201 PINGROUP(sdmmc3_dat2_pb5, RSVD1, PWM1, SDMMC3, SPI3, RSVD1, 0x33a0, N, N), 2192 PINGROUP(sdmmc3_dat2_pb5, RSVD1, PWM1, SDMMC3, SPI3, 0x33a0, N, N),
2202 PINGROUP(sdmmc3_dat1_pb6, RSVD1, RSVD2, SDMMC3, SPI3, RSVD2, 0x339c, N, N), 2193 PINGROUP(sdmmc3_dat1_pb6, RSVD1, RSVD2, SDMMC3, SPI3, 0x339c, N, N),
2203 PINGROUP(sdmmc3_dat0_pb7, RSVD1, RSVD2, SDMMC3, SPI3, RSVD2, 0x3398, N, N), 2194 PINGROUP(sdmmc3_dat0_pb7, RSVD1, RSVD2, SDMMC3, SPI3, 0x3398, N, N),
2204 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, GMI, RSVD4, RSVD4, 0x3180, N, N), 2195 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, GMI, RSVD4, 0x3180, N, N),
2205 PINGROUP(lcd_pwr1_pc1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3070, N, N), 2196 PINGROUP(lcd_pwr1_pc1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3070, N, N),
2206 PINGROUP(uart2_txd_pc2, UARTB, SPDIF, UARTA, SPI4, SPI4, 0x3168, N, N), 2197 PINGROUP(uart2_txd_pc2, UARTB, SPDIF, UARTA, SPI4, 0x3168, N, N),
2207 PINGROUP(uart2_rxd_pc3, UARTB, SPDIF, UARTA, SPI4, SPI4, 0x3164, N, N), 2198 PINGROUP(uart2_rxd_pc3, UARTB, SPDIF, UARTA, SPI4, 0x3164, N, N),
2208 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a4, Y, N), 2199 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N),
2209 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a0, Y, N), 2200 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N),
2210 PINGROUP(lcd_pwr2_pc6, DISPLAYA, DISPLAYB, SPI5, HDCP, HDCP, 0x3074, N, N), 2201 PINGROUP(lcd_pwr2_pc6, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3074, N, N),
2211 PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, RSVD1, 0x31c0, N, N), 2202 PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N),
2212 PINGROUP(sdmmc3_dat5_pd0, PWM0, SPI4, SDMMC3, SPI2, SPI2, 0x33ac, N, N), 2203 PINGROUP(sdmmc3_dat5_pd0, PWM0, SPI4, SDMMC3, SPI2, 0x33ac, N, N),
2213 PINGROUP(sdmmc3_dat4_pd1, PWM1, SPI4, SDMMC3, SPI2, SPI2, 0x33a8, N, N), 2204 PINGROUP(sdmmc3_dat4_pd1, PWM1, SPI4, SDMMC3, SPI2, 0x33a8, N, N),
2214 PINGROUP(lcd_dc1_pd2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x310c, N, N), 2205 PINGROUP(lcd_dc1_pd2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x310c, N, N),
2215 PINGROUP(sdmmc3_dat6_pd3, SPDIF, SPI4, SDMMC3, SPI2, SPI2, 0x33b0, N, N), 2206 PINGROUP(sdmmc3_dat6_pd3, SPDIF, SPI4, SDMMC3, SPI2, 0x33b0, N, N),
2216 PINGROUP(sdmmc3_dat7_pd4, SPDIF, SPI4, SDMMC3, SPI2, SPI2, 0x33b4, N, N), 2207 PINGROUP(sdmmc3_dat7_pd4, SPDIF, SPI4, SDMMC3, SPI2, 0x33b4, N, N),
2217 PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3128, N, Y), 2208 PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, Y),
2218 PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, RSVD4, 0x315c, N, Y), 2209 PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, Y),
2219 PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, RSVD4, 0x3160, N, Y), 2210 PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, Y),
2220 PINGROUP(lcd_d0_pe0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30a4, N, N), 2211 PINGROUP(lcd_d0_pe0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a4, N, N),
2221 PINGROUP(lcd_d1_pe1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30a8, N, N), 2212 PINGROUP(lcd_d1_pe1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a8, N, N),
2222 PINGROUP(lcd_d2_pe2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30ac, N, N), 2213 PINGROUP(lcd_d2_pe2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ac, N, N),
2223 PINGROUP(lcd_d3_pe3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30b0, N, N), 2214 PINGROUP(lcd_d3_pe3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b0, N, N),
2224 PINGROUP(lcd_d4_pe4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30b4, N, N), 2215 PINGROUP(lcd_d4_pe4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b4, N, N),
2225 PINGROUP(lcd_d5_pe5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30b8, N, N), 2216 PINGROUP(lcd_d5_pe5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b8, N, N),
2226 PINGROUP(lcd_d6_pe6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30bc, N, N), 2217 PINGROUP(lcd_d6_pe6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30bc, N, N),
2227 PINGROUP(lcd_d7_pe7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30c0, N, N), 2218 PINGROUP(lcd_d7_pe7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c0, N, N),
2228 PINGROUP(lcd_d8_pf0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30c4, N, N), 2219 PINGROUP(lcd_d8_pf0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c4, N, N),
2229 PINGROUP(lcd_d9_pf1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30c8, N, N), 2220 PINGROUP(lcd_d9_pf1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c8, N, N),
2230 PINGROUP(lcd_d10_pf2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30cc, N, N), 2221 PINGROUP(lcd_d10_pf2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30cc, N, N),
2231 PINGROUP(lcd_d11_pf3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30d0, N, N), 2222 PINGROUP(lcd_d11_pf3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d0, N, N),
2232 PINGROUP(lcd_d12_pf4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30d4, N, N), 2223 PINGROUP(lcd_d12_pf4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d4, N, N),
2233 PINGROUP(lcd_d13_pf5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30d8, N, N), 2224 PINGROUP(lcd_d13_pf5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d8, N, N),
2234 PINGROUP(lcd_d14_pf6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30dc, N, N), 2225 PINGROUP(lcd_d14_pf6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30dc, N, N),
2235 PINGROUP(lcd_d15_pf7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30e0, N, N), 2226 PINGROUP(lcd_d15_pf7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e0, N, N),
2236 PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f0, N, N), 2227 PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N),
2237 PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f4, N, N), 2228 PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N),
2238 PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f8, N, N), 2229 PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N),
2239 PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31fc, N, N), 2230 PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N),
2240 PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3200, N, N), 2231 PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N),
2241 PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3204, N, N), 2232 PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, N),
2242 PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3208, N, N), 2233 PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, N),
2243 PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x320c, N, N), 2234 PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, N),
2244 PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, RSVD4, 0x3210, N, N), 2235 PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, N),
2245 PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, RSVD4, RSVD4, 0x3214, N, N), 2236 PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, RSVD4, 0x3214, N, N),
2246 PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, RSVD4, RSVD4, 0x3218, N, N), 2237 PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, RSVD4, 0x3218, N, N),
2247 PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, RSVD4, RSVD4, 0x321c, N, N), 2238 PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, RSVD4, 0x321c, N, N),
2248 PINGROUP(gmi_ad12_ph4, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3220, N, N), 2239 PINGROUP(gmi_ad12_ph4, RSVD1, NAND, GMI, RSVD4, 0x3220, N, N),
2249 PINGROUP(gmi_ad13_ph5, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3224, N, N), 2240 PINGROUP(gmi_ad13_ph5, RSVD1, NAND, GMI, RSVD4, 0x3224, N, N),
2250 PINGROUP(gmi_ad14_ph6, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3228, N, N), 2241 PINGROUP(gmi_ad14_ph6, RSVD1, NAND, GMI, RSVD4, 0x3228, N, N),
2251 PINGROUP(gmi_ad15_ph7, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x322c, N, N), 2242 PINGROUP(gmi_ad15_ph7, RSVD1, NAND, GMI, RSVD4, 0x322c, N, N),
2252 PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3240, N, N), 2243 PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, RSVD4, 0x3240, N, N),
2253 PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3244, N, N), 2244 PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, RSVD4, 0x3244, N, N),
2254 PINGROUP(gmi_dqs_pi2, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3248, N, N), 2245 PINGROUP(gmi_dqs_pi2, RSVD1, NAND, GMI, RSVD4, 0x3248, N, N),
2255 PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SATA, SATA, 0x31e8, N, N), 2246 PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SATA, 0x31e8, N, N),
2256 PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, RSVD4, 0x324c, N, N), 2247 PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N),
2257 PINGROUP(gmi_iordy_pi5, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31c4, N, N), 2248 PINGROUP(gmi_iordy_pi5, RSVD1, NAND, GMI, RSVD4, 0x31c4, N, N),
2258 PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, GMI_ALT, GMI_ALT, 0x31ec, N, N), 2249 PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, GMI_ALT, 0x31ec, N, N),
2259 PINGROUP(gmi_wait_pi7, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31c8, N, N), 2250 PINGROUP(gmi_wait_pi7, RSVD1, NAND, GMI, RSVD4, 0x31c8, N, N),
2260 PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, DTV, RSVD1, 0x31d4, N, N), 2251 PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, DTV, 0x31d4, N, N),
2261 PINGROUP(lcd_de_pj1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3098, N, N), 2252 PINGROUP(lcd_de_pj1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3098, N, N),
2262 PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, DTV, RSVD1, 0x31d8, N, N), 2253 PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, DTV, 0x31d8, N, N),
2263 PINGROUP(lcd_hsync_pj3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x309c, N, N), 2254 PINGROUP(lcd_hsync_pj3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x309c, N, N),
2264 PINGROUP(lcd_vsync_pj4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30a0, N, N), 2255 PINGROUP(lcd_vsync_pj4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a0, N, N),
2265 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, SPI4, 0x3170, N, N), 2256 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N),
2266 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, SPI4, 0x316c, N, N), 2257 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N),
2267 PINGROUP(gmi_a16_pj7, UARTD, SPI4, GMI, GMI_ALT, GMI_ALT, 0x3230, N, N), 2258 PINGROUP(gmi_a16_pj7, UARTD, SPI4, GMI, GMI_ALT, 0x3230, N, N),
2268 PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31cc, N, N), 2259 PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, RSVD4, 0x31cc, N, N),
2269 PINGROUP(gmi_clk_pk1, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31d0, N, N), 2260 PINGROUP(gmi_clk_pk1, RSVD1, NAND, GMI, RSVD4, 0x31d0, N, N),
2270 PINGROUP(gmi_cs4_n_pk2, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31e4, N, N), 2261 PINGROUP(gmi_cs4_n_pk2, RSVD1, NAND, GMI, RSVD4, 0x31e4, N, N),
2271 PINGROUP(gmi_cs2_n_pk3, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31dc, N, N), 2262 PINGROUP(gmi_cs2_n_pk3, RSVD1, NAND, GMI, RSVD4, 0x31dc, N, N),
2272 PINGROUP(gmi_cs3_n_pk4, RSVD1, NAND, GMI, GMI_ALT, RSVD1, 0x31e0, N, N), 2263 PINGROUP(gmi_cs3_n_pk4, RSVD1, NAND, GMI, GMI_ALT, 0x31e0, N, N),
2273 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, I2C1, SDMMC2, RSVD2, 0x3354, N, N), 2264 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, I2C1, SDMMC2, 0x3354, N, N),
2274 PINGROUP(spdif_in_pk6, SPDIF, HDA, I2C1, SDMMC2, SDMMC2, 0x3350, N, N), 2265 PINGROUP(spdif_in_pk6, SPDIF, HDA, I2C1, SDMMC2, 0x3350, N, N),
2275 PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, RSVD4, RSVD4, 0x323c, N, N), 2266 PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, RSVD4, 0x323c, N, N),
2276 PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x312c, N, Y), 2267 PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, Y),
2277 PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3130, N, Y), 2268 PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, Y),
2278 PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3134, N, Y), 2269 PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, Y),
2279 PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3138, N, Y), 2270 PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, Y),
2280 PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x313c, N, Y), 2271 PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, Y),
2281 PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3140, N, Y), 2272 PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, Y),
2282 PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3144, N, Y), 2273 PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, Y),
2283 PINGROUP(vi_d9_pl7, DDR, SDMMC2, VI, RSVD4, RSVD4, 0x3148, N, Y), 2274 PINGROUP(vi_d9_pl7, DDR, SDMMC2, VI, RSVD4, 0x3148, N, Y),
2284 PINGROUP(lcd_d16_pm0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30e4, N, N), 2275 PINGROUP(lcd_d16_pm0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e4, N, N),
2285 PINGROUP(lcd_d17_pm1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30e8, N, N), 2276 PINGROUP(lcd_d17_pm1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e8, N, N),
2286 PINGROUP(lcd_d18_pm2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30ec, N, N), 2277 PINGROUP(lcd_d18_pm2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ec, N, N),
2287 PINGROUP(lcd_d19_pm3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30f0, N, N), 2278 PINGROUP(lcd_d19_pm3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f0, N, N),
2288 PINGROUP(lcd_d20_pm4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30f4, N, N), 2279 PINGROUP(lcd_d20_pm4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f4, N, N),
2289 PINGROUP(lcd_d21_pm5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30f8, N, N), 2280 PINGROUP(lcd_d21_pm5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f8, N, N),
2290 PINGROUP(lcd_d22_pm6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x30fc, N, N), 2281 PINGROUP(lcd_d22_pm6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30fc, N, N),
2291 PINGROUP(lcd_d23_pm7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3100, N, N), 2282 PINGROUP(lcd_d23_pm7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3100, N, N),
2292 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, SDMMC2, SDMMC2, 0x3338, N, N), 2283 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, SDMMC2, 0x3338, N, N),
2293 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, SDMMC2, SDMMC2, 0x333c, N, N), 2284 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, SDMMC2, 0x333c, N, N),
2294 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SDMMC2, SDMMC2, 0x3340, N, N), 2285 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SDMMC2, 0x3340, N, N),
2295 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, SDMMC2, SDMMC2, 0x3344, N, N), 2286 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, SDMMC2, 0x3344, N, N),
2296 PINGROUP(lcd_cs0_n_pn4, DISPLAYA, DISPLAYB, SPI5, RSVD4, RSVD4, 0x3084, N, N), 2287 PINGROUP(lcd_cs0_n_pn4, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3084, N, N),
2297 PINGROUP(lcd_sdout_pn5, DISPLAYA, DISPLAYB, SPI5, HDCP, HDCP, 0x307c, N, N), 2288 PINGROUP(lcd_sdout_pn5, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x307c, N, N),
2298 PINGROUP(lcd_dc0_pn6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3088, N, N), 2289 PINGROUP(lcd_dc0_pn6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3088, N, N),
2299 PINGROUP(hdmi_int_pn7, HDMI, RSVD2, RSVD3, RSVD4, RSVD4, 0x3110, N, N), 2290 PINGROUP(hdmi_int_pn7, HDMI, RSVD2, RSVD3, RSVD4, 0x3110, N, N),
2300 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, ULPI, 0x301c, N, N), 2291 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N),
2301 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N), 2292 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N),
2302 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N), 2293 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N),
2303 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N), 2294 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N),
2304 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, ULPI, 0x300c, N, N), 2295 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N),
2305 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, ULPI, 0x3010, N, N), 2296 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N),
2306 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, ULPI, 0x3014, N, N), 2297 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N),
2307 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, ULPI, 0x3018, N, N), 2298 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N),
2308 PINGROUP(dap3_fs_pp0, I2S2, RSVD2, DISPLAYA, DISPLAYB, RSVD2, 0x3030, N, N), 2299 PINGROUP(dap3_fs_pp0, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3030, N, N),
2309 PINGROUP(dap3_din_pp1, I2S2, RSVD2, DISPLAYA, DISPLAYB, RSVD2, 0x3034, N, N), 2300 PINGROUP(dap3_din_pp1, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3034, N, N),
2310 PINGROUP(dap3_dout_pp2, I2S2, RSVD2, DISPLAYA, DISPLAYB, RSVD2, 0x3038, N, N), 2301 PINGROUP(dap3_dout_pp2, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3038, N, N),
2311 PINGROUP(dap3_sclk_pp3, I2S2, RSVD2, DISPLAYA, DISPLAYB, RSVD2, 0x303c, N, N), 2302 PINGROUP(dap3_sclk_pp3, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x303c, N, N),
2312 PINGROUP(dap4_fs_pp4, I2S3, RSVD2, GMI, RSVD4, RSVD4, 0x31a8, N, N), 2303 PINGROUP(dap4_fs_pp4, I2S3, RSVD2, GMI, RSVD4, 0x31a8, N, N),
2313 PINGROUP(dap4_din_pp5, I2S3, RSVD2, GMI, RSVD4, RSVD4, 0x31ac, N, N), 2304 PINGROUP(dap4_din_pp5, I2S3, RSVD2, GMI, RSVD4, 0x31ac, N, N),
2314 PINGROUP(dap4_dout_pp6, I2S3, RSVD2, GMI, RSVD4, RSVD4, 0x31b0, N, N), 2305 PINGROUP(dap4_dout_pp6, I2S3, RSVD2, GMI, RSVD4, 0x31b0, N, N),
2315 PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, GMI, RSVD4, RSVD4, 0x31b4, N, N), 2306 PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, GMI, RSVD4, 0x31b4, N, N),
2316 PINGROUP(kb_col0_pq0, KBC, NAND, TRACE, TEST, TEST, 0x32fc, N, N), 2307 PINGROUP(kb_col0_pq0, KBC, NAND, TRACE, TEST, 0x32fc, N, N),
2317 PINGROUP(kb_col1_pq1, KBC, NAND, TRACE, TEST, TEST, 0x3300, N, N), 2308 PINGROUP(kb_col1_pq1, KBC, NAND, TRACE, TEST, 0x3300, N, N),
2318 PINGROUP(kb_col2_pq2, KBC, NAND, TRACE, RSVD4, RSVD4, 0x3304, N, N), 2309 PINGROUP(kb_col2_pq2, KBC, NAND, TRACE, RSVD4, 0x3304, N, N),
2319 PINGROUP(kb_col3_pq3, KBC, NAND, TRACE, RSVD4, RSVD4, 0x3308, N, N), 2310 PINGROUP(kb_col3_pq3, KBC, NAND, TRACE, RSVD4, 0x3308, N, N),
2320 PINGROUP(kb_col4_pq4, KBC, NAND, TRACE, RSVD4, RSVD4, 0x330c, N, N), 2311 PINGROUP(kb_col4_pq4, KBC, NAND, TRACE, RSVD4, 0x330c, N, N),
2321 PINGROUP(kb_col5_pq5, KBC, NAND, TRACE, RSVD4, RSVD4, 0x3310, N, N), 2312 PINGROUP(kb_col5_pq5, KBC, NAND, TRACE, RSVD4, 0x3310, N, N),
2322 PINGROUP(kb_col6_pq6, KBC, NAND, TRACE, MIO, MIO, 0x3314, N, N), 2313 PINGROUP(kb_col6_pq6, KBC, NAND, TRACE, MIO, 0x3314, N, N),
2323 PINGROUP(kb_col7_pq7, KBC, NAND, TRACE, MIO, MIO, 0x3318, N, N), 2314 PINGROUP(kb_col7_pq7, KBC, NAND, TRACE, MIO, 0x3318, N, N),
2324 PINGROUP(kb_row0_pr0, KBC, NAND, RSVD3, RSVD4, RSVD4, 0x32bc, N, N), 2315 PINGROUP(kb_row0_pr0, KBC, NAND, RSVD3, RSVD4, 0x32bc, N, N),
2325 PINGROUP(kb_row1_pr1, KBC, NAND, RSVD3, RSVD4, RSVD4, 0x32c0, N, N), 2316 PINGROUP(kb_row1_pr1, KBC, NAND, RSVD3, RSVD4, 0x32c0, N, N),
2326 PINGROUP(kb_row2_pr2, KBC, NAND, RSVD3, RSVD4, RSVD4, 0x32c4, N, N), 2317 PINGROUP(kb_row2_pr2, KBC, NAND, RSVD3, RSVD4, 0x32c4, N, N),
2327 PINGROUP(kb_row3_pr3, KBC, NAND, RSVD3, INVALID, RSVD3, 0x32c8, N, N), 2318 PINGROUP(kb_row3_pr3, KBC, NAND, RSVD3, INVALID, 0x32c8, N, N),
2328 PINGROUP(kb_row4_pr4, KBC, NAND, TRACE, RSVD4, RSVD4, 0x32cc, N, N), 2319 PINGROUP(kb_row4_pr4, KBC, NAND, TRACE, RSVD4, 0x32cc, N, N),
2329 PINGROUP(kb_row5_pr5, KBC, NAND, TRACE, OWR, OWR, 0x32d0, N, N), 2320 PINGROUP(kb_row5_pr5, KBC, NAND, TRACE, OWR, 0x32d0, N, N),
2330 PINGROUP(kb_row6_pr6, KBC, NAND, SDMMC2, MIO, MIO, 0x32d4, N, N), 2321 PINGROUP(kb_row6_pr6, KBC, NAND, SDMMC2, MIO, 0x32d4, N, N),
2331 PINGROUP(kb_row7_pr7, KBC, NAND, SDMMC2, MIO, MIO, 0x32d8, N, N), 2322 PINGROUP(kb_row7_pr7, KBC, NAND, SDMMC2, MIO, 0x32d8, N, N),
2332 PINGROUP(kb_row8_ps0, KBC, NAND, SDMMC2, MIO, MIO, 0x32dc, N, N), 2323 PINGROUP(kb_row8_ps0, KBC, NAND, SDMMC2, MIO, 0x32dc, N, N),
2333 PINGROUP(kb_row9_ps1, KBC, NAND, SDMMC2, MIO, MIO, 0x32e0, N, N), 2324 PINGROUP(kb_row9_ps1, KBC, NAND, SDMMC2, MIO, 0x32e0, N, N),
2334 PINGROUP(kb_row10_ps2, KBC, NAND, SDMMC2, MIO, MIO, 0x32e4, N, N), 2325 PINGROUP(kb_row10_ps2, KBC, NAND, SDMMC2, MIO, 0x32e4, N, N),
2335 PINGROUP(kb_row11_ps3, KBC, NAND, SDMMC2, MIO, MIO, 0x32e8, N, N), 2326 PINGROUP(kb_row11_ps3, KBC, NAND, SDMMC2, MIO, 0x32e8, N, N),
2336 PINGROUP(kb_row12_ps4, KBC, NAND, SDMMC2, MIO, MIO, 0x32ec, N, N), 2327 PINGROUP(kb_row12_ps4, KBC, NAND, SDMMC2, MIO, 0x32ec, N, N),
2337 PINGROUP(kb_row13_ps5, KBC, NAND, SDMMC2, MIO, MIO, 0x32f0, N, N), 2328 PINGROUP(kb_row13_ps5, KBC, NAND, SDMMC2, MIO, 0x32f0, N, N),
2338 PINGROUP(kb_row14_ps6, KBC, NAND, SDMMC2, MIO, MIO, 0x32f4, N, N), 2329 PINGROUP(kb_row14_ps6, KBC, NAND, SDMMC2, MIO, 0x32f4, N, N),
2339 PINGROUP(kb_row15_ps7, KBC, NAND, SDMMC2, MIO, MIO, 0x32f8, N, N), 2330 PINGROUP(kb_row15_ps7, KBC, NAND, SDMMC2, MIO, 0x32f8, N, N),
2340 PINGROUP(vi_pclk_pt0, RSVD1, SDMMC2, VI, RSVD4, RSVD4, 0x3154, N, Y), 2331 PINGROUP(vi_pclk_pt0, RSVD1, SDMMC2, VI, RSVD4, 0x3154, N, Y),
2341 PINGROUP(vi_mclk_pt1, VI, VI_ALT1, VI_ALT2, VI_ALT3, VI_ALT3, 0x3158, N, Y), 2332 PINGROUP(vi_mclk_pt1, VI, VI_ALT1, VI_ALT2, VI_ALT3, 0x3158, N, Y),
2342 PINGROUP(vi_d10_pt2, DDR, RSVD2, VI, RSVD4, RSVD4, 0x314c, N, Y), 2333 PINGROUP(vi_d10_pt2, DDR, RSVD2, VI, RSVD4, 0x314c, N, Y),
2343 PINGROUP(vi_d11_pt3, DDR, RSVD2, VI, RSVD4, RSVD4, 0x3150, N, Y), 2334 PINGROUP(vi_d11_pt3, DDR, RSVD2, VI, RSVD4, 0x3150, N, Y),
2344 PINGROUP(vi_d0_pt4, DDR, RSVD2, VI, RSVD4, RSVD4, 0x3124, N, Y), 2335 PINGROUP(vi_d0_pt4, DDR, RSVD2, VI, RSVD4, 0x3124, N, Y),
2345 PINGROUP(gen2_i2c_scl_pt5, I2C2, HDCP, GMI, RSVD4, RSVD4, 0x3250, Y, N), 2336 PINGROUP(gen2_i2c_scl_pt5, I2C2, HDCP, GMI, RSVD4, 0x3250, Y, N),
2346 PINGROUP(gen2_i2c_sda_pt6, I2C2, HDCP, GMI, RSVD4, RSVD4, 0x3254, Y, N), 2337 PINGROUP(gen2_i2c_sda_pt6, I2C2, HDCP, GMI, RSVD4, 0x3254, Y, N),
2347 PINGROUP(sdmmc4_cmd_pt7, I2C3, NAND, GMI, SDMMC4, SDMMC4, 0x325c, N, Y), 2338 PINGROUP(sdmmc4_cmd_pt7, I2C3, NAND, GMI, SDMMC4, 0x325c, N, Y),
2348 PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, RSVD4, 0x3184, N, N), 2339 PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N),
2349 PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, RSVD4, 0x3188, N, N), 2340 PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N),
2350 PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, RSVD4, 0x318c, N, N), 2341 PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N),
2351 PINGROUP(pu3, PWM0, UARTA, GMI, RSVD4, RSVD4, 0x3190, N, N), 2342 PINGROUP(pu3, PWM0, UARTA, GMI, RSVD4, 0x3190, N, N),
2352 PINGROUP(pu4, PWM1, UARTA, GMI, RSVD4, RSVD4, 0x3194, N, N), 2343 PINGROUP(pu4, PWM1, UARTA, GMI, RSVD4, 0x3194, N, N),
2353 PINGROUP(pu5, PWM2, UARTA, GMI, RSVD4, RSVD4, 0x3198, N, N), 2344 PINGROUP(pu5, PWM2, UARTA, GMI, RSVD4, 0x3198, N, N),
2354 PINGROUP(pu6, PWM3, UARTA, GMI, RSVD4, RSVD4, 0x319c, N, N), 2345 PINGROUP(pu6, PWM3, UARTA, GMI, RSVD4, 0x319c, N, N),
2355 PINGROUP(jtag_rtck_pu7, RTCK, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b0, N, N), 2346 PINGROUP(jtag_rtck_pu7, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N),
2356 PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3040, N, N), 2347 PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N),
2357 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3044, N, N), 2348 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N),
2358 PINGROUP(pv2, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x3060, N, N), 2349 PINGROUP(pv2, OWR, RSVD2, RSVD3, RSVD4, 0x3060, N, N),
2359 PINGROUP(pv3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4, RSVD4, 0x3064, N, N), 2350 PINGROUP(pv3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4, 0x3064, N, N),
2360 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3114, N, N), 2351 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N),
2361 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3118, N, N), 2352 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N),
2362 PINGROUP(crt_hsync_pv6, CRT, RSVD2, RSVD3, RSVD4, RSVD4, 0x311c, N, N), 2353 PINGROUP(crt_hsync_pv6, CRT, RSVD2, RSVD3, RSVD4, 0x311c, N, N),
2363 PINGROUP(crt_vsync_pv7, CRT, RSVD2, RSVD3, RSVD4, RSVD4, 0x3120, N, N), 2354 PINGROUP(crt_vsync_pv7, CRT, RSVD2, RSVD3, RSVD4, 0x3120, N, N),
2364 PINGROUP(lcd_cs1_n_pw0, DISPLAYA, DISPLAYB, SPI5, RSVD4, RSVD4, 0x3104, N, N), 2355 PINGROUP(lcd_cs1_n_pw0, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3104, N, N),
2365 PINGROUP(lcd_m1_pw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, RSVD4, 0x3108, N, N), 2356 PINGROUP(lcd_m1_pw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3108, N, N),
2366 PINGROUP(spi2_cs1_n_pw2, SPI3, SPI2, SPI2_ALT, I2C1, I2C1, 0x3388, N, N), 2357 PINGROUP(spi2_cs1_n_pw2, SPI3, SPI2, SPI2_ALT, I2C1, 0x3388, N, N),
2367 PINGROUP(spi2_cs2_n_pw3, SPI3, SPI2, SPI2_ALT, I2C1, I2C1, 0x338c, N, N), 2358 PINGROUP(spi2_cs2_n_pw3, SPI3, SPI2, SPI2_ALT, I2C1, 0x338c, N, N),
2368 PINGROUP(clk1_out_pw4, EXTPERIPH1, RSVD2, RSVD3, RSVD4, RSVD4, 0x334c, N, N), 2359 PINGROUP(clk1_out_pw4, EXTPERIPH1, RSVD2, RSVD3, RSVD4, 0x334c, N, N),
2369 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, RSVD4, 0x3068, N, N), 2360 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N),
2370 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x3174, N, N), 2361 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, RSVD4, 0x3174, N, N),
2371 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, RSVD4, RSVD4, 0x3178, N, N), 2362 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, RSVD4, 0x3178, N, N),
2372 PINGROUP(spi2_mosi_px0, SPI6, SPI2, SPI3, GMI, GMI, 0x3368, N, N), 2363 PINGROUP(spi2_mosi_px0, SPI6, SPI2, SPI3, GMI, 0x3368, N, N),
2373 PINGROUP(spi2_miso_px1, SPI6, SPI2, SPI3, GMI, GMI, 0x336c, N, N), 2364 PINGROUP(spi2_miso_px1, SPI6, SPI2, SPI3, GMI, 0x336c, N, N),
2374 PINGROUP(spi2_sck_px2, SPI6, SPI2, SPI3, GMI, GMI, 0x3374, N, N), 2365 PINGROUP(spi2_sck_px2, SPI6, SPI2, SPI3, GMI, 0x3374, N, N),
2375 PINGROUP(spi2_cs0_n_px3, SPI6, SPI2, SPI3, GMI, GMI, 0x3370, N, N), 2366 PINGROUP(spi2_cs0_n_px3, SPI6, SPI2, SPI3, GMI, 0x3370, N, N),
2376 PINGROUP(spi1_mosi_px4, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x3378, N, N), 2367 PINGROUP(spi1_mosi_px4, SPI2, SPI1, SPI2_ALT, GMI, 0x3378, N, N),
2377 PINGROUP(spi1_sck_px5, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x337c, N, N), 2368 PINGROUP(spi1_sck_px5, SPI2, SPI1, SPI2_ALT, GMI, 0x337c, N, N),
2378 PINGROUP(spi1_cs0_n_px6, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x3380, N, N), 2369 PINGROUP(spi1_cs0_n_px6, SPI2, SPI1, SPI2_ALT, GMI, 0x3380, N, N),
2379 PINGROUP(spi1_miso_px7, SPI3, SPI1, SPI2_ALT, RSVD4, RSVD4, 0x3384, N, N), 2370 PINGROUP(spi1_miso_px7, SPI3, SPI1, SPI2_ALT, RSVD4, 0x3384, N, N),
2380 PINGROUP(ulpi_clk_py0, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x3020, N, N), 2371 PINGROUP(ulpi_clk_py0, SPI1, RSVD2, UARTD, ULPI, 0x3020, N, N),
2381 PINGROUP(ulpi_dir_py1, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x3024, N, N), 2372 PINGROUP(ulpi_dir_py1, SPI1, RSVD2, UARTD, ULPI, 0x3024, N, N),
2382 PINGROUP(ulpi_nxt_py2, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x3028, N, N), 2373 PINGROUP(ulpi_nxt_py2, SPI1, RSVD2, UARTD, ULPI, 0x3028, N, N),
2383 PINGROUP(ulpi_stp_py3, SPI1, RSVD2, UARTD, ULPI, RSVD2, 0x302c, N, N), 2374 PINGROUP(ulpi_stp_py3, SPI1, RSVD2, UARTD, ULPI, 0x302c, N, N),
2384 PINGROUP(sdmmc1_dat3_py4, SDMMC1, RSVD2, UARTE, UARTA, RSVD2, 0x3050, N, N), 2375 PINGROUP(sdmmc1_dat3_py4, SDMMC1, RSVD2, UARTE, UARTA, 0x3050, N, N),
2385 PINGROUP(sdmmc1_dat2_py5, SDMMC1, RSVD2, UARTE, UARTA, RSVD2, 0x3054, N, N), 2376 PINGROUP(sdmmc1_dat2_py5, SDMMC1, RSVD2, UARTE, UARTA, 0x3054, N, N),
2386 PINGROUP(sdmmc1_dat1_py6, SDMMC1, RSVD2, UARTE, UARTA, RSVD2, 0x3058, N, N), 2377 PINGROUP(sdmmc1_dat1_py6, SDMMC1, RSVD2, UARTE, UARTA, 0x3058, N, N),
2387 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, UARTE, UARTA, RSVD2, 0x305c, N, N), 2378 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, UARTE, UARTA, 0x305c, N, N),
2388 PINGROUP(sdmmc1_clk_pz0, SDMMC1, RSVD2, RSVD3, UARTA, RSVD3, 0x3048, N, N), 2379 PINGROUP(sdmmc1_clk_pz0, SDMMC1, RSVD2, RSVD3, UARTA, 0x3048, N, N),
2389 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, RSVD2, RSVD3, UARTA, RSVD3, 0x304c, N, N), 2380 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, RSVD2, RSVD3, UARTA, 0x304c, N, N),
2390 PINGROUP(lcd_sdin_pz2, DISPLAYA, DISPLAYB, SPI5, RSVD4, RSVD4, 0x3078, N, N), 2381 PINGROUP(lcd_sdin_pz2, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3078, N, N),
2391 PINGROUP(lcd_wr_n_pz3, DISPLAYA, DISPLAYB, SPI5, HDCP, HDCP, 0x3080, N, N), 2382 PINGROUP(lcd_wr_n_pz3, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3080, N, N),
2392 PINGROUP(lcd_sck_pz4, DISPLAYA, DISPLAYB, SPI5, HDCP, HDCP, 0x308c, N, N), 2383 PINGROUP(lcd_sck_pz4, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x308c, N, N),
2393 PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, RSVD4, 0x3320, N, N), 2384 PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N),
2394 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b4, Y, N), 2385 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N),
2395 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b8, Y, N), 2386 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N),
2396 PINGROUP(sdmmc4_dat0_paa0, UARTE, SPI3, GMI, SDMMC4, SDMMC4, 0x3260, N, Y), 2387 PINGROUP(sdmmc4_dat0_paa0, UARTE, SPI3, GMI, SDMMC4, 0x3260, N, Y),
2397 PINGROUP(sdmmc4_dat1_paa1, UARTE, SPI3, GMI, SDMMC4, SDMMC4, 0x3264, N, Y), 2388 PINGROUP(sdmmc4_dat1_paa1, UARTE, SPI3, GMI, SDMMC4, 0x3264, N, Y),
2398 PINGROUP(sdmmc4_dat2_paa2, UARTE, SPI3, GMI, SDMMC4, SDMMC4, 0x3268, N, Y), 2389 PINGROUP(sdmmc4_dat2_paa2, UARTE, SPI3, GMI, SDMMC4, 0x3268, N, Y),
2399 PINGROUP(sdmmc4_dat3_paa3, UARTE, SPI3, GMI, SDMMC4, SDMMC4, 0x326c, N, Y), 2390 PINGROUP(sdmmc4_dat3_paa3, UARTE, SPI3, GMI, SDMMC4, 0x326c, N, Y),
2400 PINGROUP(sdmmc4_dat4_paa4, I2C3, I2S4, GMI, SDMMC4, SDMMC4, 0x3270, N, Y), 2391 PINGROUP(sdmmc4_dat4_paa4, I2C3, I2S4, GMI, SDMMC4, 0x3270, N, Y),
2401 PINGROUP(sdmmc4_dat5_paa5, VGP3, I2S4, GMI, SDMMC4, SDMMC4, 0x3274, N, Y), 2392 PINGROUP(sdmmc4_dat5_paa5, VGP3, I2S4, GMI, SDMMC4, 0x3274, N, Y),
2402 PINGROUP(sdmmc4_dat6_paa6, VGP4, I2S4, GMI, SDMMC4, SDMMC4, 0x3278, N, Y), 2393 PINGROUP(sdmmc4_dat6_paa6, VGP4, I2S4, GMI, SDMMC4, 0x3278, N, Y),
2403 PINGROUP(sdmmc4_dat7_paa7, VGP5, I2S4, GMI, SDMMC4, SDMMC4, 0x327c, N, Y), 2394 PINGROUP(sdmmc4_dat7_paa7, VGP5, I2S4, GMI, SDMMC4, 0x327c, N, Y),
2404 PINGROUP(pbb0, I2S4, RSVD2, RSVD3, SDMMC4, RSVD3, 0x328c, N, N), 2395 PINGROUP(pbb0, I2S4, RSVD2, RSVD3, SDMMC4, 0x328c, N, N),
2405 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC4, RSVD3, 0x3290, Y, N), 2396 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC4, 0x3290, Y, N),
2406 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC4, RSVD3, 0x3294, Y, N), 2397 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC4, 0x3294, Y, N),
2407 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC4, SDMMC4, 0x3298, N, N), 2398 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC4, 0x3298, N, N),
2408 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC4, SDMMC4, 0x329c, N, N), 2399 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC4, 0x329c, N, N),
2409 PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, SDMMC4, SDMMC4, 0x32a0, N, N), 2400 PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, SDMMC4, 0x32a0, N, N),
2410 PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, SDMMC4, SDMMC4, 0x32a4, N, N), 2401 PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, SDMMC4, 0x32a4, N, N),
2411 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC4, RSVD3, 0x32a8, N, N), 2402 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC4, 0x32a8, N, N),
2412 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC4, SDMMC4, 0x3284, N, N), 2403 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC4, 0x3284, N, N),
2413 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC4, RSVD3, 0x3288, N, N), 2404 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC4, 0x3288, N, N),
2414 PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32ac, N, N), 2405 PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N),
2415 PINGROUP(sdmmc4_rst_n_pcc3, VGP6, RSVD2, RSVD3, SDMMC4, RSVD3, 0x3280, N, Y), 2406 PINGROUP(sdmmc4_rst_n_pcc3, VGP6, RSVD2, RSVD3, SDMMC4, 0x3280, N, Y),
2416 PINGROUP(sdmmc4_clk_pcc4, INVALID, NAND, GMI, SDMMC4, SDMMC4, 0x3258, N, Y), 2407 PINGROUP(sdmmc4_clk_pcc4, INVALID, NAND, GMI, SDMMC4, 0x3258, N, Y),
2417 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, RSVD4, 0x306c, N, N), 2408 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N),
2418 PINGROUP(pex_l2_rst_n_pcc6, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33d8, N, N), 2409 PINGROUP(pex_l2_rst_n_pcc6, PCIE, HDA, RSVD3, RSVD4, 0x33d8, N, N),
2419 PINGROUP(pex_l2_clkreq_n_pcc7, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33dc, N, N), 2410 PINGROUP(pex_l2_clkreq_n_pcc7, PCIE, HDA, RSVD3, RSVD4, 0x33dc, N, N),
2420 PINGROUP(pex_l0_prsnt_n_pdd0, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33b8, N, N), 2411 PINGROUP(pex_l0_prsnt_n_pdd0, PCIE, HDA, RSVD3, RSVD4, 0x33b8, N, N),
2421 PINGROUP(pex_l0_rst_n_pdd1, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33bc, N, N), 2412 PINGROUP(pex_l0_rst_n_pdd1, PCIE, HDA, RSVD3, RSVD4, 0x33bc, N, N),
2422 PINGROUP(pex_l0_clkreq_n_pdd2, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33c0, N, N), 2413 PINGROUP(pex_l0_clkreq_n_pdd2, PCIE, HDA, RSVD3, RSVD4, 0x33c0, N, N),
2423 PINGROUP(pex_wake_n_pdd3, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33c4, N, N), 2414 PINGROUP(pex_wake_n_pdd3, PCIE, HDA, RSVD3, RSVD4, 0x33c4, N, N),
2424 PINGROUP(pex_l1_prsnt_n_pdd4, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33c8, N, N), 2415 PINGROUP(pex_l1_prsnt_n_pdd4, PCIE, HDA, RSVD3, RSVD4, 0x33c8, N, N),
2425 PINGROUP(pex_l1_rst_n_pdd5, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33cc, N, N), 2416 PINGROUP(pex_l1_rst_n_pdd5, PCIE, HDA, RSVD3, RSVD4, 0x33cc, N, N),
2426 PINGROUP(pex_l1_clkreq_n_pdd6, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33d0, N, N), 2417 PINGROUP(pex_l1_clkreq_n_pdd6, PCIE, HDA, RSVD3, RSVD4, 0x33d0, N, N),
2427 PINGROUP(pex_l2_prsnt_n_pdd7, PCIE, HDA, RSVD3, RSVD4, RSVD4, 0x33d4, N, N), 2418 PINGROUP(pex_l2_prsnt_n_pdd7, PCIE, HDA, RSVD3, RSVD4, 0x33d4, N, N),
2428 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31b8, N, N), 2419 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N),
2429 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31bc, N, N), 2420 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N),
2430 PINGROUP(clk1_req_pee2, DAP, HDA, RSVD3, RSVD4, RSVD4, 0x3348, N, N), 2421 PINGROUP(clk1_req_pee2, DAP, HDA, RSVD3, RSVD4, 0x3348, N, N),
2431 PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, RSVD4, 0x33e0, Y, N), 2422 PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N),
2432 PINGROUP(clk_32k_in, CLK_32K_IN, RSVD2, RSVD3, RSVD4, RSVD4, 0x3330, N, N), 2423 PINGROUP(clk_32k_in, CLK_32K_IN, RSVD2, RSVD3, RSVD4, 0x3330, N, N),
2433 PINGROUP(core_pwr_req, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4, RSVD4, 0x3324, N, N), 2424 PINGROUP(core_pwr_req, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3324, N, N),
2434 PINGROUP(cpu_pwr_req, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4, RSVD4, 0x3328, N, N), 2425 PINGROUP(cpu_pwr_req, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3328, N, N),
2435 PINGROUP(owr, OWR, CEC, RSVD3, RSVD4, RSVD4, 0x3334, N, N), 2426 PINGROUP(owr, OWR, CEC, RSVD3, RSVD4, 0x3334, N, N),
2436 PINGROUP(pwr_int_n, PWR_INT_N, RSVD2, RSVD3, RSVD4, RSVD4, 0x332c, N, N), 2427 PINGROUP(pwr_int_n, PWR_INT_N, RSVD2, RSVD3, RSVD4, 0x332c, N, N),
2437 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */ 2428 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
2438 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2), 2429 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
2439 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2), 2430 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 9248ce4efed4..051e8592990e 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -391,14 +391,16 @@ int pinmux_enable_setting(struct pinctrl_setting const *setting)
391 struct pinctrl_dev *pctldev = setting->pctldev; 391 struct pinctrl_dev *pctldev = setting->pctldev;
392 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 392 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
393 const struct pinmux_ops *ops = pctldev->desc->pmxops; 393 const struct pinmux_ops *ops = pctldev->desc->pmxops;
394 int ret; 394 int ret = 0;
395 const unsigned *pins; 395 const unsigned *pins = NULL;
396 unsigned num_pins; 396 unsigned num_pins = 0;
397 int i; 397 int i;
398 struct pin_desc *desc; 398 struct pin_desc *desc;
399 399
400 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, 400 if (pctlops->get_group_pins)
401 &pins, &num_pins); 401 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group,
402 &pins, &num_pins);
403
402 if (ret) { 404 if (ret) {
403 const char *gname; 405 const char *gname;
404 406
@@ -470,14 +472,15 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
470 struct pinctrl_dev *pctldev = setting->pctldev; 472 struct pinctrl_dev *pctldev = setting->pctldev;
471 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 473 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
472 const struct pinmux_ops *ops = pctldev->desc->pmxops; 474 const struct pinmux_ops *ops = pctldev->desc->pmxops;
473 int ret; 475 int ret = 0;
474 const unsigned *pins; 476 const unsigned *pins = NULL;
475 unsigned num_pins; 477 unsigned num_pins = 0;
476 int i; 478 int i;
477 struct pin_desc *desc; 479 struct pin_desc *desc;
478 480
479 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, 481 if (pctlops->get_group_pins)
480 &pins, &num_pins); 482 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group,
483 &pins, &num_pins);
481 if (ret) { 484 if (ret) {
482 const char *gname; 485 const char *gname;
483 486
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index d39ca87353e4..ce9fb7aa8ba3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -20,7 +20,10 @@
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/pinctrl/pinconf-generic.h> 22#include <linux/pinctrl/pinconf-generic.h>
23
24#ifndef CONFIG_ARCH_MULTIPLATFORM
23#include <mach/irqs.h> 25#include <mach/irqs.h>
26#endif
24 27
25#include "core.h" 28#include "core.h"
26#include "sh_pfc.h" 29#include "sh_pfc.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 6c83ce43a940..e4c1ef477053 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -22,7 +22,9 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/pinctrl/pinconf-generic.h> 23#include <linux/pinctrl/pinconf-generic.h>
24 24
25#ifndef CONFIG_ARCH_MULTIPLATFORM
25#include <mach/irqs.h> 26#include <mach/irqs.h>
27#endif
26 28
27#include "core.h" 29#include "core.h"
28#include "sh_pfc.h" 30#include "sh_pfc.h"
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index f5cd3f961808..9a179c94b4dc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -782,7 +782,8 @@ enum {
782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, 782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
783 TCLK1_B_MARK, 783 TCLK1_B_MARK,
784 784
785 I2C3_SCL_MARK, I2C3_SDA_MARK, 785 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
786 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
786 PINMUX_MARK_END, 787 PINMUX_MARK_END,
787}; 788};
788 789
@@ -1722,6 +1723,13 @@ static const u16 pinmux_data[] = {
1722 PINMUX_IPSR_DATA(IP16_7, USB1_OVC), 1723 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1723 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), 1724 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
1724 1725
1726 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1727 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1728 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1729 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1730
1731 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1732 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1725 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1), 1733 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1726 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), 1734 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1727}; 1735};
@@ -1735,8 +1743,10 @@ static const struct sh_pfc_pin pinmux_pins[] = {
1735 PINMUX_GPIO_GP_ALL(), 1743 PINMUX_GPIO_GP_ALL(),
1736 1744
1737 /* Pins not associated with a GPIO port */ 1745 /* Pins not associated with a GPIO port */
1738 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15), 1746 SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
1747 SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), 1748 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1749 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1740}; 1750};
1741 1751
1742/* - AUDIO CLOCK ------------------------------------------------------------ */ 1752/* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -2054,6 +2064,14 @@ static const unsigned int hscif1_ctrl_b_pins[] = {
2054static const unsigned int hscif1_ctrl_b_mux[] = { 2064static const unsigned int hscif1_ctrl_b_mux[] = {
2055 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2065 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2056}; 2066};
2067/* - I2C0 ------------------------------------------------------------------- */
2068static const unsigned int i2c0_pins[] = {
2069 /* SCL, SDA */
2070 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2071};
2072static const unsigned int i2c0_mux[] = {
2073 I2C0_SCL_MARK, I2C0_SDA_MARK,
2074};
2057/* - I2C1 ------------------------------------------------------------------- */ 2075/* - I2C1 ------------------------------------------------------------------- */
2058static const unsigned int i2c1_pins[] = { 2076static const unsigned int i2c1_pins[] = {
2059 /* SCL, SDA */ 2077 /* SCL, SDA */
@@ -2120,6 +2138,80 @@ static const unsigned int i2c3_pins[] = {
2120static const unsigned int i2c3_mux[] = { 2138static const unsigned int i2c3_mux[] = {
2121 I2C3_SCL_MARK, I2C3_SDA_MARK, 2139 I2C3_SCL_MARK, I2C3_SDA_MARK,
2122}; 2140};
2141/* - IIC0 (I2C4) ------------------------------------------------------------ */
2142static const unsigned int iic0_pins[] = {
2143 /* SCL, SDA */
2144 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2145};
2146static const unsigned int iic0_mux[] = {
2147 IIC0_SCL_MARK, IIC0_SDA_MARK,
2148};
2149/* - IIC1 (I2C5) ------------------------------------------------------------ */
2150static const unsigned int iic1_pins[] = {
2151 /* SCL, SDA */
2152 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2153};
2154static const unsigned int iic1_mux[] = {
2155 IIC1_SCL_MARK, IIC1_SDA_MARK,
2156};
2157static const unsigned int iic1_b_pins[] = {
2158 /* SCL, SDA */
2159 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2160};
2161static const unsigned int iic1_b_mux[] = {
2162 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2163};
2164static const unsigned int iic1_c_pins[] = {
2165 /* SCL, SDA */
2166 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2167};
2168static const unsigned int iic1_c_mux[] = {
2169 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2170};
2171/* - IIC2 (I2C6) ------------------------------------------------------------ */
2172static const unsigned int iic2_pins[] = {
2173 /* SCL, SDA */
2174 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2175};
2176static const unsigned int iic2_mux[] = {
2177 IIC2_SCL_MARK, IIC2_SDA_MARK,
2178};
2179static const unsigned int iic2_b_pins[] = {
2180 /* SCL, SDA */
2181 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2182};
2183static const unsigned int iic2_b_mux[] = {
2184 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2185};
2186static const unsigned int iic2_c_pins[] = {
2187 /* SCL, SDA */
2188 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2189};
2190static const unsigned int iic2_c_mux[] = {
2191 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2192};
2193static const unsigned int iic2_d_pins[] = {
2194 /* SCL, SDA */
2195 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2196};
2197static const unsigned int iic2_d_mux[] = {
2198 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2199};
2200static const unsigned int iic2_e_pins[] = {
2201 /* SCL, SDA */
2202 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2203};
2204static const unsigned int iic2_e_mux[] = {
2205 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2206};
2207/* - IIC3 (I2C7) ------------------------------------------------------------ */
2208static const unsigned int iic3_pins[] = {
2209/* SCL, SDA */
2210 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2211};
2212static const unsigned int iic3_mux[] = {
2213 IIC3_SCL_MARK, IIC3_SDA_MARK,
2214};
2123/* - INTC ------------------------------------------------------------------- */ 2215/* - INTC ------------------------------------------------------------------- */
2124static const unsigned int intc_irq0_pins[] = { 2216static const unsigned int intc_irq0_pins[] = {
2125 /* IRQ */ 2217 /* IRQ */
@@ -3757,6 +3849,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3757 SH_PFC_PIN_GROUP(hscif1_data_b), 3849 SH_PFC_PIN_GROUP(hscif1_data_b),
3758 SH_PFC_PIN_GROUP(hscif1_clk_b), 3850 SH_PFC_PIN_GROUP(hscif1_clk_b),
3759 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3851 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3852 SH_PFC_PIN_GROUP(i2c0),
3760 SH_PFC_PIN_GROUP(i2c1), 3853 SH_PFC_PIN_GROUP(i2c1),
3761 SH_PFC_PIN_GROUP(i2c1_b), 3854 SH_PFC_PIN_GROUP(i2c1_b),
3762 SH_PFC_PIN_GROUP(i2c1_c), 3855 SH_PFC_PIN_GROUP(i2c1_c),
@@ -3766,6 +3859,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3766 SH_PFC_PIN_GROUP(i2c2_d), 3859 SH_PFC_PIN_GROUP(i2c2_d),
3767 SH_PFC_PIN_GROUP(i2c2_e), 3860 SH_PFC_PIN_GROUP(i2c2_e),
3768 SH_PFC_PIN_GROUP(i2c3), 3861 SH_PFC_PIN_GROUP(i2c3),
3862 SH_PFC_PIN_GROUP(iic0),
3863 SH_PFC_PIN_GROUP(iic1),
3864 SH_PFC_PIN_GROUP(iic1_b),
3865 SH_PFC_PIN_GROUP(iic1_c),
3866 SH_PFC_PIN_GROUP(iic2),
3867 SH_PFC_PIN_GROUP(iic2_b),
3868 SH_PFC_PIN_GROUP(iic2_c),
3869 SH_PFC_PIN_GROUP(iic2_d),
3870 SH_PFC_PIN_GROUP(iic2_e),
3871 SH_PFC_PIN_GROUP(iic3),
3769 SH_PFC_PIN_GROUP(intc_irq0), 3872 SH_PFC_PIN_GROUP(intc_irq0),
3770 SH_PFC_PIN_GROUP(intc_irq1), 3873 SH_PFC_PIN_GROUP(intc_irq1),
3771 SH_PFC_PIN_GROUP(intc_irq2), 3874 SH_PFC_PIN_GROUP(intc_irq2),
@@ -4044,6 +4147,10 @@ static const char * const hscif1_groups[] = {
4044 "hscif1_ctrl_b", 4147 "hscif1_ctrl_b",
4045}; 4148};
4046 4149
4150static const char * const i2c0_groups[] = {
4151 "i2c0",
4152};
4153
4047static const char * const i2c1_groups[] = { 4154static const char * const i2c1_groups[] = {
4048 "i2c1", 4155 "i2c1",
4049 "i2c1_b", 4156 "i2c1_b",
@@ -4062,6 +4169,28 @@ static const char * const i2c3_groups[] = {
4062 "i2c3", 4169 "i2c3",
4063}; 4170};
4064 4171
4172static const char * const iic0_groups[] = {
4173 "iic0",
4174};
4175
4176static const char * const iic1_groups[] = {
4177 "iic1",
4178 "iic1_b",
4179 "iic1_c",
4180};
4181
4182static const char * const iic2_groups[] = {
4183 "iic2",
4184 "iic2_b",
4185 "iic2_c",
4186 "iic2_d",
4187 "iic2_e",
4188};
4189
4190static const char * const iic3_groups[] = {
4191 "iic3",
4192};
4193
4065static const char * const intc_groups[] = { 4194static const char * const intc_groups[] = {
4066 "intc_irq0", 4195 "intc_irq0",
4067 "intc_irq1", 4196 "intc_irq1",
@@ -4373,9 +4502,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
4373 SH_PFC_FUNCTION(eth), 4502 SH_PFC_FUNCTION(eth),
4374 SH_PFC_FUNCTION(hscif0), 4503 SH_PFC_FUNCTION(hscif0),
4375 SH_PFC_FUNCTION(hscif1), 4504 SH_PFC_FUNCTION(hscif1),
4505 SH_PFC_FUNCTION(i2c0),
4376 SH_PFC_FUNCTION(i2c1), 4506 SH_PFC_FUNCTION(i2c1),
4377 SH_PFC_FUNCTION(i2c2), 4507 SH_PFC_FUNCTION(i2c2),
4378 SH_PFC_FUNCTION(i2c3), 4508 SH_PFC_FUNCTION(i2c3),
4509 SH_PFC_FUNCTION(iic0),
4510 SH_PFC_FUNCTION(iic1),
4511 SH_PFC_FUNCTION(iic2),
4512 SH_PFC_FUNCTION(iic3),
4379 SH_PFC_FUNCTION(intc), 4513 SH_PFC_FUNCTION(intc),
4380 SH_PFC_FUNCTION(mmc0), 4514 SH_PFC_FUNCTION(mmc0),
4381 SH_PFC_FUNCTION(mmc1), 4515 SH_PFC_FUNCTION(mmc1),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 7868bf3a0f91..2e688dc4a3c8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -1680,6 +1680,53 @@ static const struct sh_pfc_pin pinmux_pins[] = {
1680 PINMUX_GPIO_GP_ALL(), 1680 PINMUX_GPIO_GP_ALL(),
1681}; 1681};
1682 1682
1683/* - Audio Clock ------------------------------------------------------------ */
1684static const unsigned int audio_clk_a_pins[] = {
1685 /* CLK */
1686 RCAR_GP_PIN(2, 28),
1687};
1688
1689static const unsigned int audio_clk_a_mux[] = {
1690 AUDIO_CLKA_MARK,
1691};
1692
1693static const unsigned int audio_clk_b_pins[] = {
1694 /* CLK */
1695 RCAR_GP_PIN(2, 29),
1696};
1697
1698static const unsigned int audio_clk_b_mux[] = {
1699 AUDIO_CLKB_MARK,
1700};
1701
1702static const unsigned int audio_clk_b_b_pins[] = {
1703 /* CLK */
1704 RCAR_GP_PIN(7, 20),
1705};
1706
1707static const unsigned int audio_clk_b_b_mux[] = {
1708 AUDIO_CLKB_B_MARK,
1709};
1710
1711static const unsigned int audio_clk_c_pins[] = {
1712 /* CLK */
1713 RCAR_GP_PIN(2, 30),
1714};
1715
1716static const unsigned int audio_clk_c_mux[] = {
1717 AUDIO_CLKC_MARK,
1718};
1719
1720static const unsigned int audio_clkout_pins[] = {
1721 /* CLK */
1722 RCAR_GP_PIN(2, 31),
1723};
1724
1725static const unsigned int audio_clkout_mux[] = {
1726 AUDIO_CLKOUT_MARK,
1727};
1728
1729
1683/* - DU --------------------------------------------------------------------- */ 1730/* - DU --------------------------------------------------------------------- */
1684static const unsigned int du_rgb666_pins[] = { 1731static const unsigned int du_rgb666_pins[] = {
1685 /* R[7:2], G[7:2], B[7:2] */ 1732 /* R[7:2], G[7:2], B[7:2] */
@@ -1733,19 +1780,32 @@ static const unsigned int du_clk_out_1_mux[] = {
1733 DU1_DOTCLKOUT1_MARK 1780 DU1_DOTCLKOUT1_MARK
1734}; 1781};
1735static const unsigned int du_sync_pins[] = { 1782static const unsigned int du_sync_pins[] = {
1736 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */ 1783 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1737 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), 1784 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1738}; 1785};
1739static const unsigned int du_sync_mux[] = { 1786static const unsigned int du_sync_mux[] = {
1740 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1741 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK 1787 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1742}; 1788};
1743static const unsigned int du_cde_disp_pins[] = { 1789static const unsigned int du_oddf_pins[] = {
1744 /* CDE DISP */ 1790 /* EXDISP/EXODDF/EXCDE */
1745 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30), 1791 RCAR_GP_PIN(3, 29),
1792};
1793static const unsigned int du_oddf_mux[] = {
1794 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1795};
1796static const unsigned int du_cde_pins[] = {
1797 /* CDE */
1798 RCAR_GP_PIN(3, 31),
1746}; 1799};
1747static const unsigned int du_cde_disp_mux[] = { 1800static const unsigned int du_cde_mux[] = {
1748 DU1_CDE_MARK, DU1_DISP_MARK 1801 DU1_CDE_MARK,
1802};
1803static const unsigned int du_disp_pins[] = {
1804 /* DISP */
1805 RCAR_GP_PIN(3, 30),
1806};
1807static const unsigned int du_disp_mux[] = {
1808 DU1_DISP_MARK,
1749}; 1809};
1750static const unsigned int du0_clk_in_pins[] = { 1810static const unsigned int du0_clk_in_pins[] = {
1751 /* CLKIN */ 1811 /* CLKIN */
@@ -3246,6 +3306,260 @@ static const unsigned int sdhi2_wp_pins[] = {
3246static const unsigned int sdhi2_wp_mux[] = { 3306static const unsigned int sdhi2_wp_mux[] = {
3247 SD2_WP_MARK, 3307 SD2_WP_MARK,
3248}; 3308};
3309
3310/* - SSI -------------------------------------------------------------------- */
3311static const unsigned int ssi0_data_pins[] = {
3312 /* SDATA */
3313 RCAR_GP_PIN(2, 2),
3314};
3315
3316static const unsigned int ssi0_data_mux[] = {
3317 SSI_SDATA0_MARK,
3318};
3319
3320static const unsigned int ssi0_data_b_pins[] = {
3321 /* SDATA */
3322 RCAR_GP_PIN(3, 4),
3323};
3324
3325static const unsigned int ssi0_data_b_mux[] = {
3326 SSI_SDATA0_B_MARK,
3327};
3328
3329static const unsigned int ssi0129_ctrl_pins[] = {
3330 /* SCK, WS */
3331 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3332};
3333
3334static const unsigned int ssi0129_ctrl_mux[] = {
3335 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3336};
3337
3338static const unsigned int ssi0129_ctrl_b_pins[] = {
3339 /* SCK, WS */
3340 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3341};
3342
3343static const unsigned int ssi0129_ctrl_b_mux[] = {
3344 SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3345};
3346
3347static const unsigned int ssi1_data_pins[] = {
3348 /* SDATA */
3349 RCAR_GP_PIN(2, 5),
3350};
3351
3352static const unsigned int ssi1_data_mux[] = {
3353 SSI_SDATA1_MARK,
3354};
3355
3356static const unsigned int ssi1_data_b_pins[] = {
3357 /* SDATA */
3358 RCAR_GP_PIN(3, 7),
3359};
3360
3361static const unsigned int ssi1_data_b_mux[] = {
3362 SSI_SDATA1_B_MARK,
3363};
3364
3365static const unsigned int ssi1_ctrl_pins[] = {
3366 /* SCK, WS */
3367 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3368};
3369
3370static const unsigned int ssi1_ctrl_mux[] = {
3371 SSI_SCK1_MARK, SSI_WS1_MARK,
3372};
3373
3374static const unsigned int ssi1_ctrl_b_pins[] = {
3375 /* SCK, WS */
3376 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3377};
3378
3379static const unsigned int ssi1_ctrl_b_mux[] = {
3380 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3381};
3382
3383static const unsigned int ssi2_data_pins[] = {
3384 /* SDATA */
3385 RCAR_GP_PIN(2, 8),
3386};
3387
3388static const unsigned int ssi2_data_mux[] = {
3389 SSI_SDATA2_MARK,
3390};
3391
3392static const unsigned int ssi2_ctrl_pins[] = {
3393 /* SCK, WS */
3394 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3395};
3396
3397static const unsigned int ssi2_ctrl_mux[] = {
3398 SSI_SCK2_MARK, SSI_WS2_MARK,
3399};
3400
3401static const unsigned int ssi3_data_pins[] = {
3402 /* SDATA */
3403 RCAR_GP_PIN(2, 11),
3404};
3405
3406static const unsigned int ssi3_data_mux[] = {
3407 SSI_SDATA3_MARK,
3408};
3409
3410static const unsigned int ssi34_ctrl_pins[] = {
3411 /* SCK, WS */
3412 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3413};
3414
3415static const unsigned int ssi34_ctrl_mux[] = {
3416 SSI_SCK34_MARK, SSI_WS34_MARK,
3417};
3418
3419static const unsigned int ssi4_data_pins[] = {
3420 /* SDATA */
3421 RCAR_GP_PIN(2, 14),
3422};
3423
3424static const unsigned int ssi4_data_mux[] = {
3425 SSI_SDATA4_MARK,
3426};
3427
3428static const unsigned int ssi4_ctrl_pins[] = {
3429 /* SCK, WS */
3430 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3431};
3432
3433static const unsigned int ssi4_ctrl_mux[] = {
3434 SSI_SCK4_MARK, SSI_WS4_MARK,
3435};
3436
3437static const unsigned int ssi5_data_pins[] = {
3438 /* SDATA */
3439 RCAR_GP_PIN(2, 17),
3440};
3441
3442static const unsigned int ssi5_data_mux[] = {
3443 SSI_SDATA5_MARK,
3444};
3445
3446static const unsigned int ssi5_ctrl_pins[] = {
3447 /* SCK, WS */
3448 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3449};
3450
3451static const unsigned int ssi5_ctrl_mux[] = {
3452 SSI_SCK5_MARK, SSI_WS5_MARK,
3453};
3454
3455static const unsigned int ssi6_data_pins[] = {
3456 /* SDATA */
3457 RCAR_GP_PIN(2, 20),
3458};
3459
3460static const unsigned int ssi6_data_mux[] = {
3461 SSI_SDATA6_MARK,
3462};
3463
3464static const unsigned int ssi6_ctrl_pins[] = {
3465 /* SCK, WS */
3466 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
3467};
3468
3469static const unsigned int ssi6_ctrl_mux[] = {
3470 SSI_SCK6_MARK, SSI_WS6_MARK,
3471};
3472
3473static const unsigned int ssi7_data_pins[] = {
3474 /* SDATA */
3475 RCAR_GP_PIN(2, 23),
3476};
3477
3478static const unsigned int ssi7_data_mux[] = {
3479 SSI_SDATA7_MARK,
3480};
3481
3482static const unsigned int ssi7_data_b_pins[] = {
3483 /* SDATA */
3484 RCAR_GP_PIN(3, 12),
3485};
3486
3487static const unsigned int ssi7_data_b_mux[] = {
3488 SSI_SDATA7_B_MARK,
3489};
3490
3491static const unsigned int ssi78_ctrl_pins[] = {
3492 /* SCK, WS */
3493 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3494};
3495
3496static const unsigned int ssi78_ctrl_mux[] = {
3497 SSI_SCK78_MARK, SSI_WS78_MARK,
3498};
3499
3500static const unsigned int ssi78_ctrl_b_pins[] = {
3501 /* SCK, WS */
3502 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3503};
3504
3505static const unsigned int ssi78_ctrl_b_mux[] = {
3506 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3507};
3508
3509static const unsigned int ssi8_data_pins[] = {
3510 /* SDATA */
3511 RCAR_GP_PIN(2, 24),
3512};
3513
3514static const unsigned int ssi8_data_mux[] = {
3515 SSI_SDATA8_MARK,
3516};
3517
3518static const unsigned int ssi8_data_b_pins[] = {
3519 /* SDATA */
3520 RCAR_GP_PIN(3, 13),
3521};
3522
3523static const unsigned int ssi8_data_b_mux[] = {
3524 SSI_SDATA8_B_MARK,
3525};
3526
3527static const unsigned int ssi9_data_pins[] = {
3528 /* SDATA */
3529 RCAR_GP_PIN(2, 27),
3530};
3531
3532static const unsigned int ssi9_data_mux[] = {
3533 SSI_SDATA9_MARK,
3534};
3535
3536static const unsigned int ssi9_data_b_pins[] = {
3537 /* SDATA */
3538 RCAR_GP_PIN(3, 18),
3539};
3540
3541static const unsigned int ssi9_data_b_mux[] = {
3542 SSI_SDATA9_B_MARK,
3543};
3544
3545static const unsigned int ssi9_ctrl_pins[] = {
3546 /* SCK, WS */
3547 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
3548};
3549
3550static const unsigned int ssi9_ctrl_mux[] = {
3551 SSI_SCK9_MARK, SSI_WS9_MARK,
3552};
3553
3554static const unsigned int ssi9_ctrl_b_pins[] = {
3555 /* SCK, WS */
3556 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3557};
3558
3559static const unsigned int ssi9_ctrl_b_mux[] = {
3560 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3561};
3562
3249/* - USB0 ------------------------------------------------------------------- */ 3563/* - USB0 ------------------------------------------------------------------- */
3250static const unsigned int usb0_pins[] = { 3564static const unsigned int usb0_pins[] = {
3251 RCAR_GP_PIN(7, 23), /* PWEN */ 3565 RCAR_GP_PIN(7, 23), /* PWEN */
@@ -3550,12 +3864,19 @@ static const unsigned int vin2_clk_mux[] = {
3550}; 3864};
3551 3865
3552static const struct sh_pfc_pin_group pinmux_groups[] = { 3866static const struct sh_pfc_pin_group pinmux_groups[] = {
3867 SH_PFC_PIN_GROUP(audio_clk_a),
3868 SH_PFC_PIN_GROUP(audio_clk_b),
3869 SH_PFC_PIN_GROUP(audio_clk_b_b),
3870 SH_PFC_PIN_GROUP(audio_clk_c),
3871 SH_PFC_PIN_GROUP(audio_clkout),
3553 SH_PFC_PIN_GROUP(du_rgb666), 3872 SH_PFC_PIN_GROUP(du_rgb666),
3554 SH_PFC_PIN_GROUP(du_rgb888), 3873 SH_PFC_PIN_GROUP(du_rgb888),
3555 SH_PFC_PIN_GROUP(du_clk_out_0), 3874 SH_PFC_PIN_GROUP(du_clk_out_0),
3556 SH_PFC_PIN_GROUP(du_clk_out_1), 3875 SH_PFC_PIN_GROUP(du_clk_out_1),
3557 SH_PFC_PIN_GROUP(du_sync), 3876 SH_PFC_PIN_GROUP(du_sync),
3558 SH_PFC_PIN_GROUP(du_cde_disp), 3877 SH_PFC_PIN_GROUP(du_oddf),
3878 SH_PFC_PIN_GROUP(du_cde),
3879 SH_PFC_PIN_GROUP(du_disp),
3559 SH_PFC_PIN_GROUP(du0_clk_in), 3880 SH_PFC_PIN_GROUP(du0_clk_in),
3560 SH_PFC_PIN_GROUP(du1_clk_in), 3881 SH_PFC_PIN_GROUP(du1_clk_in),
3561 SH_PFC_PIN_GROUP(du1_clk_in_b), 3882 SH_PFC_PIN_GROUP(du1_clk_in_b),
@@ -3762,6 +4083,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3762 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4083 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3763 SH_PFC_PIN_GROUP(sdhi2_cd), 4084 SH_PFC_PIN_GROUP(sdhi2_cd),
3764 SH_PFC_PIN_GROUP(sdhi2_wp), 4085 SH_PFC_PIN_GROUP(sdhi2_wp),
4086 SH_PFC_PIN_GROUP(ssi0_data),
4087 SH_PFC_PIN_GROUP(ssi0_data_b),
4088 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4089 SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4090 SH_PFC_PIN_GROUP(ssi1_data),
4091 SH_PFC_PIN_GROUP(ssi1_data_b),
4092 SH_PFC_PIN_GROUP(ssi1_ctrl),
4093 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4094 SH_PFC_PIN_GROUP(ssi2_data),
4095 SH_PFC_PIN_GROUP(ssi2_ctrl),
4096 SH_PFC_PIN_GROUP(ssi3_data),
4097 SH_PFC_PIN_GROUP(ssi34_ctrl),
4098 SH_PFC_PIN_GROUP(ssi4_data),
4099 SH_PFC_PIN_GROUP(ssi4_ctrl),
4100 SH_PFC_PIN_GROUP(ssi5_data),
4101 SH_PFC_PIN_GROUP(ssi5_ctrl),
4102 SH_PFC_PIN_GROUP(ssi6_data),
4103 SH_PFC_PIN_GROUP(ssi6_ctrl),
4104 SH_PFC_PIN_GROUP(ssi7_data),
4105 SH_PFC_PIN_GROUP(ssi7_data_b),
4106 SH_PFC_PIN_GROUP(ssi78_ctrl),
4107 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4108 SH_PFC_PIN_GROUP(ssi8_data),
4109 SH_PFC_PIN_GROUP(ssi8_data_b),
4110 SH_PFC_PIN_GROUP(ssi9_data),
4111 SH_PFC_PIN_GROUP(ssi9_data_b),
4112 SH_PFC_PIN_GROUP(ssi9_ctrl),
4113 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3765 SH_PFC_PIN_GROUP(usb0), 4114 SH_PFC_PIN_GROUP(usb0),
3766 SH_PFC_PIN_GROUP(usb1), 4115 SH_PFC_PIN_GROUP(usb1),
3767 VIN_DATA_PIN_GROUP(vin0_data, 24), 4116 VIN_DATA_PIN_GROUP(vin0_data, 24),
@@ -3798,13 +4147,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3798 SH_PFC_PIN_GROUP(vin2_clk), 4147 SH_PFC_PIN_GROUP(vin2_clk),
3799}; 4148};
3800 4149
4150static const char * const audio_clk_groups[] = {
4151 "audio_clk_a",
4152 "audio_clk_b",
4153 "audio_clk_b_b",
4154 "audio_clk_c",
4155 "audio_clkout",
4156};
4157
3801static const char * const du_groups[] = { 4158static const char * const du_groups[] = {
3802 "du_rgb666", 4159 "du_rgb666",
3803 "du_rgb888", 4160 "du_rgb888",
3804 "du_clk_out_0", 4161 "du_clk_out_0",
3805 "du_clk_out_1", 4162 "du_clk_out_1",
3806 "du_sync", 4163 "du_sync",
3807 "du_cde_disp", 4164 "du_oddf",
4165 "du_cde",
4166 "du_disp",
3808}; 4167};
3809 4168
3810static const char * const du0_groups[] = { 4169static const char * const du0_groups[] = {
@@ -4103,6 +4462,37 @@ static const char * const sdhi2_groups[] = {
4103 "sdhi2_wp", 4462 "sdhi2_wp",
4104}; 4463};
4105 4464
4465static const char * const ssi_groups[] = {
4466 "ssi0_data",
4467 "ssi0_data_b",
4468 "ssi0129_ctrl",
4469 "ssi0129_ctrl_b",
4470 "ssi1_data",
4471 "ssi1_data_b",
4472 "ssi1_ctrl",
4473 "ssi1_ctrl_b",
4474 "ssi2_data",
4475 "ssi2_ctrl",
4476 "ssi3_data",
4477 "ssi34_ctrl",
4478 "ssi4_data",
4479 "ssi4_ctrl",
4480 "ssi5_data",
4481 "ssi5_ctrl",
4482 "ssi6_data",
4483 "ssi6_ctrl",
4484 "ssi7_data",
4485 "ssi7_data_b",
4486 "ssi78_ctrl",
4487 "ssi78_ctrl_b",
4488 "ssi8_data",
4489 "ssi8_data_b",
4490 "ssi9_data",
4491 "ssi9_data_b",
4492 "ssi9_ctrl",
4493 "ssi9_ctrl_b",
4494};
4495
4106static const char * const usb0_groups[] = { 4496static const char * const usb0_groups[] = {
4107 "usb0", 4497 "usb0",
4108}; 4498};
@@ -4152,6 +4542,7 @@ static const char * const vin2_groups[] = {
4152}; 4542};
4153 4543
4154static const struct sh_pfc_function pinmux_functions[] = { 4544static const struct sh_pfc_function pinmux_functions[] = {
4545 SH_PFC_FUNCTION(audio_clk),
4155 SH_PFC_FUNCTION(du), 4546 SH_PFC_FUNCTION(du),
4156 SH_PFC_FUNCTION(du0), 4547 SH_PFC_FUNCTION(du0),
4157 SH_PFC_FUNCTION(du1), 4548 SH_PFC_FUNCTION(du1),
@@ -4187,6 +4578,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4187 SH_PFC_FUNCTION(sdhi0), 4578 SH_PFC_FUNCTION(sdhi0),
4188 SH_PFC_FUNCTION(sdhi1), 4579 SH_PFC_FUNCTION(sdhi1),
4189 SH_PFC_FUNCTION(sdhi2), 4580 SH_PFC_FUNCTION(sdhi2),
4581 SH_PFC_FUNCTION(ssi),
4190 SH_PFC_FUNCTION(usb0), 4582 SH_PFC_FUNCTION(usb0),
4191 SH_PFC_FUNCTION(usb1), 4583 SH_PFC_FUNCTION(usb1),
4192 SH_PFC_FUNCTION(vin0), 4584 SH_PFC_FUNCTION(vin0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 6f6ba100994d..ee370de4609a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -26,7 +26,9 @@
26#include <linux/regulator/machine.h> 26#include <linux/regulator/machine.h>
27#include <linux/slab.h> 27#include <linux/slab.h>
28 28
29#ifndef CONFIG_ARCH_MULTIPLATFORM
29#include <mach/irqs.h> 30#include <mach/irqs.h>
31#endif
30 32
31#include "core.h" 33#include "core.h"
32#include "sh_pfc.h" 34#include "sh_pfc.h"
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index ab8fd258d9ed..d482c40b012a 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -98,8 +98,13 @@ struct pinmux_irq {
98 const short *gpios; 98 const short *gpios;
99}; 99};
100 100
101#ifdef CONFIG_ARCH_MULTIPLATFORM
102#define PINMUX_IRQ(irq_nr, ids...) \
103 { .gpios = (const short []) { ids, -1 } }
104#else
101#define PINMUX_IRQ(irq_nr, ids...) \ 105#define PINMUX_IRQ(irq_nr, ids...) \
102 { .irq = irq_nr, .gpios = (const short []) { ids, -1 } } 106 { .irq = irq_nr, .gpios = (const short []) { ids, -1 } }
107#endif
103 108
104struct pinmux_range { 109struct pinmux_range {
105 u16 begin; 110 u16 begin;
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 76502aab2cb1..014f5b1fee55 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -14,8 +14,6 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/slab.h> 15#include <linux/slab.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/irqdomain.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/pinctrl/pinctrl.h> 17#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h> 18#include <linux/pinctrl/pinmux.h>
21#include <linux/pinctrl/consumer.h> 19#include <linux/pinctrl/consumer.h>
@@ -27,22 +25,23 @@
27#include <linux/bitops.h> 25#include <linux/bitops.h>
28#include <linux/gpio.h> 26#include <linux/gpio.h>
29#include <linux/of_gpio.h> 27#include <linux/of_gpio.h>
30#include <asm/mach/irq.h>
31 28
32#include "pinctrl-sirf.h" 29#include "pinctrl-sirf.h"
33 30
34#define DRIVER_NAME "pinmux-sirf" 31#define DRIVER_NAME "pinmux-sirf"
35 32
36struct sirfsoc_gpio_bank { 33struct sirfsoc_gpio_bank {
37 struct of_mm_gpio_chip chip;
38 struct irq_domain *domain;
39 int id; 34 int id;
40 int parent_irq; 35 int parent_irq;
41 spinlock_t lock; 36 spinlock_t lock;
37};
38
39struct sirfsoc_gpio_chip {
40 struct of_mm_gpio_chip chip;
42 bool is_marco; /* for marco, some registers are different with prima2 */ 41 bool is_marco; /* for marco, some registers are different with prima2 */
42 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
43}; 43};
44 44
45static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
46static DEFINE_SPINLOCK(sgpio_lock); 45static DEFINE_SPINLOCK(sgpio_lock);
47 46
48static struct sirfsoc_pin_group *sirfsoc_pin_groups; 47static struct sirfsoc_pin_group *sirfsoc_pin_groups;
@@ -255,37 +254,6 @@ static struct pinctrl_desc sirfsoc_pinmux_desc = {
255 .owner = THIS_MODULE, 254 .owner = THIS_MODULE,
256}; 255};
257 256
258/*
259 * Todo: bind irq_chip to every pinctrl_gpio_range
260 */
261static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
262 {
263 .name = "sirfsoc-gpio*",
264 .id = 0,
265 .base = 0,
266 .pin_base = 0,
267 .npins = 32,
268 }, {
269 .name = "sirfsoc-gpio*",
270 .id = 1,
271 .base = 32,
272 .pin_base = 32,
273 .npins = 32,
274 }, {
275 .name = "sirfsoc-gpio*",
276 .id = 2,
277 .base = 64,
278 .pin_base = 64,
279 .npins = 32,
280 }, {
281 .name = "sirfsoc-gpio*",
282 .id = 3,
283 .base = 96,
284 .pin_base = 96,
285 .npins = 19,
286 },
287};
288
289static void __iomem *sirfsoc_rsc_of_iomap(void) 257static void __iomem *sirfsoc_rsc_of_iomap(void)
290{ 258{
291 const struct of_device_id rsc_ids[] = { 259 const struct of_device_id rsc_ids[] = {
@@ -303,19 +271,16 @@ static void __iomem *sirfsoc_rsc_of_iomap(void)
303} 271}
304 272
305static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, 273static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
306 const struct of_phandle_args *gpiospec, 274 const struct of_phandle_args *gpiospec,
307 u32 *flags) 275 u32 *flags)
308{ 276{
309 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) 277 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
310 return -EINVAL;
311
312 if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
313 return -EINVAL; 278 return -EINVAL;
314 279
315 if (flags) 280 if (flags)
316 *flags = gpiospec->args[1]; 281 *flags = gpiospec->args[1];
317 282
318 return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE; 283 return gpiospec->args[0];
319} 284}
320 285
321static const struct of_device_id pinmux_ids[] = { 286static const struct of_device_id pinmux_ids[] = {
@@ -331,7 +296,6 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev)
331 struct sirfsoc_pmx *spmx; 296 struct sirfsoc_pmx *spmx;
332 struct device_node *np = pdev->dev.of_node; 297 struct device_node *np = pdev->dev.of_node;
333 const struct sirfsoc_pinctrl_data *pdata; 298 const struct sirfsoc_pinctrl_data *pdata;
334 int i;
335 299
336 /* Create state holders etc for this driver */ 300 /* Create state holders etc for this driver */
337 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); 301 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
@@ -375,11 +339,6 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev)
375 goto out_no_pmx; 339 goto out_no_pmx;
376 } 340 }
377 341
378 for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
379 sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
380 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
381 }
382
383 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); 342 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
384 343
385 return 0; 344 return 0;
@@ -464,34 +423,28 @@ static int __init sirfsoc_pinmux_init(void)
464} 423}
465arch_initcall(sirfsoc_pinmux_init); 424arch_initcall(sirfsoc_pinmux_init);
466 425
467static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 426static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc)
468{ 427{
469 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip), 428 return container_of(gc, struct sirfsoc_gpio_chip, chip.gc);
470 struct sirfsoc_gpio_bank, chip);
471
472 return irq_create_mapping(bank->domain, offset + bank->id *
473 SIRFSOC_GPIO_BANK_SIZE);
474}
475
476static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
477{
478 return gpio % SIRFSOC_GPIO_BANK_SIZE;
479} 429}
480 430
481static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio) 431static inline struct sirfsoc_gpio_bank *
432sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
482{ 433{
483 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE]; 434 return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
484} 435}
485 436
486static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip) 437static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
487{ 438{
488 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip); 439 return offset % SIRFSOC_GPIO_BANK_SIZE;
489} 440}
490 441
491static void sirfsoc_gpio_irq_ack(struct irq_data *d) 442static void sirfsoc_gpio_irq_ack(struct irq_data *d)
492{ 443{
493 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); 444 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
494 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; 445 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
446 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
447 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
495 u32 val, offset; 448 u32 val, offset;
496 unsigned long flags; 449 unsigned long flags;
497 450
@@ -499,14 +452,16 @@ static void sirfsoc_gpio_irq_ack(struct irq_data *d)
499 452
500 spin_lock_irqsave(&sgpio_lock, flags); 453 spin_lock_irqsave(&sgpio_lock, flags);
501 454
502 val = readl(bank->chip.regs + offset); 455 val = readl(sgpio->chip.regs + offset);
503 456
504 writel(val, bank->chip.regs + offset); 457 writel(val, sgpio->chip.regs + offset);
505 458
506 spin_unlock_irqrestore(&sgpio_lock, flags); 459 spin_unlock_irqrestore(&sgpio_lock, flags);
507} 460}
508 461
509static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx) 462static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
463 struct sirfsoc_gpio_bank *bank,
464 int idx)
510{ 465{
511 u32 val, offset; 466 u32 val, offset;
512 unsigned long flags; 467 unsigned long flags;
@@ -515,25 +470,29 @@ static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
515 470
516 spin_lock_irqsave(&sgpio_lock, flags); 471 spin_lock_irqsave(&sgpio_lock, flags);
517 472
518 val = readl(bank->chip.regs + offset); 473 val = readl(sgpio->chip.regs + offset);
519 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; 474 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
520 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 475 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
521 writel(val, bank->chip.regs + offset); 476 writel(val, sgpio->chip.regs + offset);
522 477
523 spin_unlock_irqrestore(&sgpio_lock, flags); 478 spin_unlock_irqrestore(&sgpio_lock, flags);
524} 479}
525 480
526static void sirfsoc_gpio_irq_mask(struct irq_data *d) 481static void sirfsoc_gpio_irq_mask(struct irq_data *d)
527{ 482{
528 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); 483 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
484 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
485 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
529 486
530 __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); 487 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
531} 488}
532 489
533static void sirfsoc_gpio_irq_unmask(struct irq_data *d) 490static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
534{ 491{
535 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); 492 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
536 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; 493 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
494 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
495 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
537 u32 val, offset; 496 u32 val, offset;
538 unsigned long flags; 497 unsigned long flags;
539 498
@@ -541,18 +500,20 @@ static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
541 500
542 spin_lock_irqsave(&sgpio_lock, flags); 501 spin_lock_irqsave(&sgpio_lock, flags);
543 502
544 val = readl(bank->chip.regs + offset); 503 val = readl(sgpio->chip.regs + offset);
545 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 504 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
546 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; 505 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
547 writel(val, bank->chip.regs + offset); 506 writel(val, sgpio->chip.regs + offset);
548 507
549 spin_unlock_irqrestore(&sgpio_lock, flags); 508 spin_unlock_irqrestore(&sgpio_lock, flags);
550} 509}
551 510
552static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) 511static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
553{ 512{
554 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); 513 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
555 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; 514 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
515 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
516 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
556 u32 val, offset; 517 u32 val, offset;
557 unsigned long flags; 518 unsigned long flags;
558 519
@@ -560,7 +521,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
560 521
561 spin_lock_irqsave(&sgpio_lock, flags); 522 spin_lock_irqsave(&sgpio_lock, flags);
562 523
563 val = readl(bank->chip.regs + offset); 524 val = readl(sgpio->chip.regs + offset);
564 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); 525 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
565 526
566 switch (type) { 527 switch (type) {
@@ -588,53 +549,41 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
588 break; 549 break;
589 } 550 }
590 551
591 writel(val, bank->chip.regs + offset); 552 writel(val, sgpio->chip.regs + offset);
592 553
593 spin_unlock_irqrestore(&sgpio_lock, flags); 554 spin_unlock_irqrestore(&sgpio_lock, flags);
594 555
595 return 0; 556 return 0;
596} 557}
597 558
598static int sirfsoc_gpio_irq_reqres(struct irq_data *d)
599{
600 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
601
602 if (gpio_lock_as_irq(&bank->chip.gc, d->hwirq % SIRFSOC_GPIO_BANK_SIZE)) {
603 dev_err(bank->chip.gc.dev,
604 "unable to lock HW IRQ %lu for IRQ\n",
605 d->hwirq);
606 return -EINVAL;
607 }
608 return 0;
609}
610
611static void sirfsoc_gpio_irq_relres(struct irq_data *d)
612{
613 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
614
615 gpio_unlock_as_irq(&bank->chip.gc, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
616}
617
618static struct irq_chip sirfsoc_irq_chip = { 559static struct irq_chip sirfsoc_irq_chip = {
619 .name = "sirf-gpio-irq", 560 .name = "sirf-gpio-irq",
620 .irq_ack = sirfsoc_gpio_irq_ack, 561 .irq_ack = sirfsoc_gpio_irq_ack,
621 .irq_mask = sirfsoc_gpio_irq_mask, 562 .irq_mask = sirfsoc_gpio_irq_mask,
622 .irq_unmask = sirfsoc_gpio_irq_unmask, 563 .irq_unmask = sirfsoc_gpio_irq_unmask,
623 .irq_set_type = sirfsoc_gpio_irq_type, 564 .irq_set_type = sirfsoc_gpio_irq_type,
624 .irq_request_resources = sirfsoc_gpio_irq_reqres,
625 .irq_release_resources = sirfsoc_gpio_irq_relres,
626}; 565};
627 566
628static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) 567static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
629{ 568{
630 struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq); 569 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
570 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
571 struct sirfsoc_gpio_bank *bank;
631 u32 status, ctrl; 572 u32 status, ctrl;
632 int idx = 0; 573 int idx = 0;
633 struct irq_chip *chip = irq_get_chip(irq); 574 struct irq_chip *chip = irq_get_chip(irq);
575 int i;
576
577 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
578 bank = &sgpio->sgpio_bank[i];
579 if (bank->parent_irq == irq)
580 break;
581 }
582 BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
634 583
635 chained_irq_enter(chip, desc); 584 chained_irq_enter(chip, desc);
636 585
637 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); 586 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
638 if (!status) { 587 if (!status) {
639 printk(KERN_WARNING 588 printk(KERN_WARNING
640 "%s: gpio id %d status %#x no interrupt is flaged\n", 589 "%s: gpio id %d status %#x no interrupt is flaged\n",
@@ -644,7 +593,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
644 } 593 }
645 594
646 while (status) { 595 while (status) {
647 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); 596 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
648 597
649 /* 598 /*
650 * Here we must check whether the corresponding GPIO's interrupt 599 * Here we must check whether the corresponding GPIO's interrupt
@@ -653,7 +602,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
653 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { 602 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
654 pr_debug("%s: gpio id %d idx %d happens\n", 603 pr_debug("%s: gpio id %d idx %d happens\n",
655 __func__, bank->id, idx); 604 __func__, bank->id, idx);
656 generic_handle_irq(irq_find_mapping(bank->domain, idx + 605 generic_handle_irq(irq_find_mapping(gc->irqdomain, idx +
657 bank->id * SIRFSOC_GPIO_BANK_SIZE)); 606 bank->id * SIRFSOC_GPIO_BANK_SIZE));
658 } 607 }
659 608
@@ -664,18 +613,20 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
664 chained_irq_exit(chip, desc); 613 chained_irq_exit(chip, desc);
665} 614}
666 615
667static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset) 616static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
617 unsigned ctrl_offset)
668{ 618{
669 u32 val; 619 u32 val;
670 620
671 val = readl(bank->chip.regs + ctrl_offset); 621 val = readl(sgpio->chip.regs + ctrl_offset);
672 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; 622 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
673 writel(val, bank->chip.regs + ctrl_offset); 623 writel(val, sgpio->chip.regs + ctrl_offset);
674} 624}
675 625
676static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) 626static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
677{ 627{
678 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); 628 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
629 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
679 unsigned long flags; 630 unsigned long flags;
680 631
681 if (pinctrl_request_gpio(chip->base + offset)) 632 if (pinctrl_request_gpio(chip->base + offset))
@@ -687,8 +638,8 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
687 * default status: 638 * default status:
688 * set direction as input and mask irq 639 * set direction as input and mask irq
689 */ 640 */
690 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); 641 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
691 __sirfsoc_gpio_irq_mask(bank, offset); 642 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
692 643
693 spin_unlock_irqrestore(&bank->lock, flags); 644 spin_unlock_irqrestore(&bank->lock, flags);
694 645
@@ -697,13 +648,14 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
697 648
698static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) 649static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
699{ 650{
700 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); 651 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
652 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
701 unsigned long flags; 653 unsigned long flags;
702 654
703 spin_lock_irqsave(&bank->lock, flags); 655 spin_lock_irqsave(&bank->lock, flags);
704 656
705 __sirfsoc_gpio_irq_mask(bank, offset); 657 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
706 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); 658 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
707 659
708 spin_unlock_irqrestore(&bank->lock, flags); 660 spin_unlock_irqrestore(&bank->lock, flags);
709 661
@@ -712,8 +664,9 @@ static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
712 664
713static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 665static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
714{ 666{
715 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); 667 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
716 int idx = sirfsoc_gpio_to_offset(gpio); 668 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
669 int idx = sirfsoc_gpio_to_bankoff(gpio);
717 unsigned long flags; 670 unsigned long flags;
718 unsigned offset; 671 unsigned offset;
719 672
@@ -721,22 +674,24 @@ static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
721 674
722 spin_lock_irqsave(&bank->lock, flags); 675 spin_lock_irqsave(&bank->lock, flags);
723 676
724 sirfsoc_gpio_set_input(bank, offset); 677 sirfsoc_gpio_set_input(sgpio, offset);
725 678
726 spin_unlock_irqrestore(&bank->lock, flags); 679 spin_unlock_irqrestore(&bank->lock, flags);
727 680
728 return 0; 681 return 0;
729} 682}
730 683
731static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset, 684static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
732 int value) 685 struct sirfsoc_gpio_bank *bank,
686 unsigned offset,
687 int value)
733{ 688{
734 u32 out_ctrl; 689 u32 out_ctrl;
735 unsigned long flags; 690 unsigned long flags;
736 691
737 spin_lock_irqsave(&bank->lock, flags); 692 spin_lock_irqsave(&bank->lock, flags);
738 693
739 out_ctrl = readl(bank->chip.regs + offset); 694 out_ctrl = readl(sgpio->chip.regs + offset);
740 if (value) 695 if (value)
741 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; 696 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
742 else 697 else
@@ -744,15 +699,16 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsig
744 699
745 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; 700 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
746 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; 701 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
747 writel(out_ctrl, bank->chip.regs + offset); 702 writel(out_ctrl, sgpio->chip.regs + offset);
748 703
749 spin_unlock_irqrestore(&bank->lock, flags); 704 spin_unlock_irqrestore(&bank->lock, flags);
750} 705}
751 706
752static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) 707static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
753{ 708{
754 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); 709 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
755 int idx = sirfsoc_gpio_to_offset(gpio); 710 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
711 int idx = sirfsoc_gpio_to_bankoff(gpio);
756 u32 offset; 712 u32 offset;
757 unsigned long flags; 713 unsigned long flags;
758 714
@@ -760,7 +716,7 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
760 716
761 spin_lock_irqsave(&sgpio_lock, flags); 717 spin_lock_irqsave(&sgpio_lock, flags);
762 718
763 sirfsoc_gpio_set_output(bank, offset, value); 719 sirfsoc_gpio_set_output(sgpio, bank, offset, value);
764 720
765 spin_unlock_irqrestore(&sgpio_lock, flags); 721 spin_unlock_irqrestore(&sgpio_lock, flags);
766 722
@@ -769,13 +725,14 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
769 725
770static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) 726static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
771{ 727{
772 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); 728 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
729 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
773 u32 val; 730 u32 val;
774 unsigned long flags; 731 unsigned long flags;
775 732
776 spin_lock_irqsave(&bank->lock, flags); 733 spin_lock_irqsave(&bank->lock, flags);
777 734
778 val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 735 val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
779 736
780 spin_unlock_irqrestore(&bank->lock, flags); 737 spin_unlock_irqrestore(&bank->lock, flags);
781 738
@@ -785,44 +742,25 @@ static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
785static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, 742static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
786 int value) 743 int value)
787{ 744{
788 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); 745 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
746 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
789 u32 ctrl; 747 u32 ctrl;
790 unsigned long flags; 748 unsigned long flags;
791 749
792 spin_lock_irqsave(&bank->lock, flags); 750 spin_lock_irqsave(&bank->lock, flags);
793 751
794 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 752 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
795 if (value) 753 if (value)
796 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; 754 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
797 else 755 else
798 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; 756 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
799 writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 757 writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
800 758
801 spin_unlock_irqrestore(&bank->lock, flags); 759 spin_unlock_irqrestore(&bank->lock, flags);
802} 760}
803 761
804static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq, 762static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
805 irq_hw_number_t hwirq) 763 const u32 *pullups)
806{
807 struct sirfsoc_gpio_bank *bank = d->host_data;
808
809 if (!bank)
810 return -EINVAL;
811
812 irq_set_chip(irq, &sirfsoc_irq_chip);
813 irq_set_handler(irq, handle_level_irq);
814 irq_set_chip_data(irq, bank + hwirq / SIRFSOC_GPIO_BANK_SIZE);
815 set_irq_flags(irq, IRQF_VALID);
816
817 return 0;
818}
819
820static const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
821 .map = sirfsoc_gpio_irq_map,
822 .xlate = irq_domain_xlate_twocell,
823};
824
825static void sirfsoc_gpio_set_pullup(const u32 *pullups)
826{ 764{
827 int i, n; 765 int i, n;
828 const unsigned long *p = (const unsigned long *)pullups; 766 const unsigned long *p = (const unsigned long *)pullups;
@@ -830,15 +768,16 @@ static void sirfsoc_gpio_set_pullup(const u32 *pullups)
830 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 768 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
831 for_each_set_bit(n, p + i, BITS_PER_LONG) { 769 for_each_set_bit(n, p + i, BITS_PER_LONG) {
832 u32 offset = SIRFSOC_GPIO_CTRL(i, n); 770 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
833 u32 val = readl(sgpio_bank[i].chip.regs + offset); 771 u32 val = readl(sgpio->chip.regs + offset);
834 val |= SIRFSOC_GPIO_CTL_PULL_MASK; 772 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
835 val |= SIRFSOC_GPIO_CTL_PULL_HIGH; 773 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
836 writel(val, sgpio_bank[i].chip.regs + offset); 774 writel(val, sgpio->chip.regs + offset);
837 } 775 }
838 } 776 }
839} 777}
840 778
841static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns) 779static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
780 const u32 *pulldowns)
842{ 781{
843 int i, n; 782 int i, n;
844 const unsigned long *p = (const unsigned long *)pulldowns; 783 const unsigned long *p = (const unsigned long *)pulldowns;
@@ -846,10 +785,10 @@ static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
846 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 785 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
847 for_each_set_bit(n, p + i, BITS_PER_LONG) { 786 for_each_set_bit(n, p + i, BITS_PER_LONG) {
848 u32 offset = SIRFSOC_GPIO_CTRL(i, n); 787 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
849 u32 val = readl(sgpio_bank[i].chip.regs + offset); 788 u32 val = readl(sgpio->chip.regs + offset);
850 val |= SIRFSOC_GPIO_CTL_PULL_MASK; 789 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
851 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; 790 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
852 writel(val, sgpio_bank[i].chip.regs + offset); 791 writel(val, sgpio->chip.regs + offset);
853 } 792 }
854 } 793 }
855} 794}
@@ -857,10 +796,10 @@ static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
857static int sirfsoc_gpio_probe(struct device_node *np) 796static int sirfsoc_gpio_probe(struct device_node *np)
858{ 797{
859 int i, err = 0; 798 int i, err = 0;
799 static struct sirfsoc_gpio_chip *sgpio;
860 struct sirfsoc_gpio_bank *bank; 800 struct sirfsoc_gpio_bank *bank;
861 void __iomem *regs; 801 void __iomem *regs;
862 struct platform_device *pdev; 802 struct platform_device *pdev;
863 struct irq_domain *domain;
864 bool is_marco = false; 803 bool is_marco = false;
865 804
866 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; 805 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
@@ -869,6 +808,10 @@ static int sirfsoc_gpio_probe(struct device_node *np)
869 if (!pdev) 808 if (!pdev)
870 return -ENODEV; 809 return -ENODEV;
871 810
811 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
812 if (!sgpio)
813 return -ENOMEM;
814
872 regs = of_iomap(np, 0); 815 regs = of_iomap(np, 0);
873 if (!regs) 816 if (!regs)
874 return -ENOMEM; 817 return -ENOMEM;
@@ -876,63 +819,76 @@ static int sirfsoc_gpio_probe(struct device_node *np)
876 if (of_device_is_compatible(np, "sirf,marco-pinctrl")) 819 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
877 is_marco = 1; 820 is_marco = 1;
878 821
879 domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS, 822 sgpio->chip.gc.request = sirfsoc_gpio_request;
880 &sirfsoc_gpio_irq_simple_ops, sgpio_bank); 823 sgpio->chip.gc.free = sirfsoc_gpio_free;
881 if (!domain) { 824 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
882 pr_err("%s: Failed to create irqdomain\n", np->full_name); 825 sgpio->chip.gc.get = sirfsoc_gpio_get_value;
883 err = -ENOSYS; 826 sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
827 sgpio->chip.gc.set = sirfsoc_gpio_set_value;
828 sgpio->chip.gc.base = 0;
829 sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
830 sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
831 sgpio->chip.gc.of_node = np;
832 sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
833 sgpio->chip.gc.of_gpio_n_cells = 2;
834 sgpio->chip.gc.dev = &pdev->dev;
835 sgpio->chip.regs = regs;
836 sgpio->is_marco = is_marco;
837
838 err = gpiochip_add(&sgpio->chip.gc);
839 if (err) {
840 dev_err(&pdev->dev, "%s: error in probe function with status %d\n",
841 np->full_name, err);
842 goto out;
843 }
844
845 err = gpiochip_irqchip_add(&sgpio->chip.gc,
846 &sirfsoc_irq_chip,
847 0, handle_level_irq,
848 IRQ_TYPE_NONE);
849 if (err) {
850 dev_err(&pdev->dev,
851 "could not connect irqchip to gpiochip\n");
884 goto out; 852 goto out;
885 } 853 }
886 854
887 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 855 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
888 bank = &sgpio_bank[i]; 856 bank = &sgpio->sgpio_bank[i];
889 spin_lock_init(&bank->lock); 857 spin_lock_init(&bank->lock);
890 bank->chip.gc.request = sirfsoc_gpio_request;
891 bank->chip.gc.free = sirfsoc_gpio_free;
892 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
893 bank->chip.gc.get = sirfsoc_gpio_get_value;
894 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
895 bank->chip.gc.set = sirfsoc_gpio_set_value;
896 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
897 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
898 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
899 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
900 bank->chip.gc.of_node = np;
901 bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
902 bank->chip.gc.of_gpio_n_cells = 2;
903 bank->chip.gc.dev = &pdev->dev;
904 bank->chip.regs = regs;
905 bank->id = i;
906 bank->is_marco = is_marco;
907 bank->parent_irq = platform_get_irq(pdev, i); 858 bank->parent_irq = platform_get_irq(pdev, i);
908 if (bank->parent_irq < 0) { 859 if (bank->parent_irq < 0) {
909 err = bank->parent_irq; 860 err = bank->parent_irq;
910 goto out; 861 goto out_banks;
911 } 862 }
912 863
913 err = gpiochip_add(&bank->chip.gc); 864 gpiochip_set_chained_irqchip(&sgpio->chip.gc,
914 if (err) { 865 &sirfsoc_irq_chip,
915 pr_err("%s: error in probe function with status %d\n", 866 bank->parent_irq,
916 np->full_name, err); 867 sirfsoc_gpio_handle_irq);
917 goto out; 868 }
918 }
919
920 bank->domain = domain;
921 869
922 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq); 870 err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
923 irq_set_handler_data(bank->parent_irq, bank); 871 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
872 if (err) {
873 dev_err(&pdev->dev,
874 "could not add gpiochip pin range\n");
875 goto out_no_range;
924 } 876 }
925 877
926 if (!of_property_read_u32_array(np, "sirf,pullups", pullups, 878 if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
927 SIRFSOC_GPIO_NO_OF_BANKS)) 879 SIRFSOC_GPIO_NO_OF_BANKS))
928 sirfsoc_gpio_set_pullup(pullups); 880 sirfsoc_gpio_set_pullup(sgpio, pullups);
929 881
930 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, 882 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
931 SIRFSOC_GPIO_NO_OF_BANKS)) 883 SIRFSOC_GPIO_NO_OF_BANKS))
932 sirfsoc_gpio_set_pulldown(pulldowns); 884 sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
933 885
934 return 0; 886 return 0;
935 887
888out_no_range:
889out_banks:
890 if (gpiochip_remove(&sgpio->chip.gc))
891 dev_err(&pdev->dev, "could not remove gpio chip\n");
936out: 892out:
937 iounmap(regs); 893 iounmap(regs);
938 return err; 894 return err;
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
new file mode 100644
index 000000000000..73e0a305ea13
--- /dev/null
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -0,0 +1,36 @@
1if ARCH_SUNXI
2
3config PINCTRL_SUNXI
4 bool
5
6config PINCTRL_SUNXI_COMMON
7 bool
8 select PINMUX
9 select GENERIC_PINCONF
10
11config PINCTRL_SUN4I_A10
12 def_bool PINCTRL_SUNXI || MACH_SUN4I
13 select PINCTRL_SUNXI_COMMON
14
15config PINCTRL_SUN5I_A10S
16 def_bool PINCTRL_SUNXI || MACH_SUN5I
17 select PINCTRL_SUNXI_COMMON
18
19config PINCTRL_SUN5I_A13
20 def_bool PINCTRL_SUNXI || MACH_SUN5I
21 select PINCTRL_SUNXI_COMMON
22
23config PINCTRL_SUN6I_A31
24 def_bool PINCTRL_SUNXI || MACH_SUN6I
25 select PINCTRL_SUNXI_COMMON
26
27config PINCTRL_SUN6I_A31_R
28 def_bool PINCTRL_SUNXI || MACH_SUN6I
29 depends on RESET_CONTROLLER
30 select PINCTRL_SUNXI_COMMON
31
32config PINCTRL_SUN7I_A20
33 def_bool PINCTRL_SUNXI || MACH_SUN7I
34 select PINCTRL_SUNXI_COMMON
35
36endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
new file mode 100644
index 000000000000..0f4461cbe11d
--- /dev/null
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -0,0 +1,10 @@
1# Core
2obj-$(CONFIG_PINCTRL_SUNXI_COMMON) += pinctrl-sunxi.o
3
4# SoC Drivers
5obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
6obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
7obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
new file mode 100644
index 000000000000..fa1ff7c7e357
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -0,0 +1,1039 @@
1/*
2 * Allwinner A10 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun4i_a10_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
26 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
27 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
32 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
33 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
38 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
39 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
44 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
45 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
50 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
51 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
52 SUNXI_FUNCTION(0x0, "gpio_in"),
53 SUNXI_FUNCTION(0x1, "gpio_out"),
54 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
55 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
56 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
57 SUNXI_FUNCTION(0x0, "gpio_in"),
58 SUNXI_FUNCTION(0x1, "gpio_out"),
59 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
60 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
65 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
66 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
67 SUNXI_FUNCTION(0x0, "gpio_in"),
68 SUNXI_FUNCTION(0x1, "gpio_out"),
69 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
70 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
71 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
72 SUNXI_FUNCTION(0x0, "gpio_in"),
73 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
75 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
76 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
77 SUNXI_FUNCTION(0x0, "gpio_in"),
78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
80 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
82 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"),
84 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
85 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
90 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
91 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
93 SUNXI_FUNCTION(0x0, "gpio_in"),
94 SUNXI_FUNCTION(0x1, "gpio_out"),
95 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
96 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
97 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
98 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
99 SUNXI_FUNCTION(0x0, "gpio_in"),
100 SUNXI_FUNCTION(0x1, "gpio_out"),
101 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
102 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
103 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
104 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
105 SUNXI_FUNCTION(0x0, "gpio_in"),
106 SUNXI_FUNCTION(0x1, "gpio_out"),
107 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
108 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
109 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
114 SUNXI_FUNCTION(0x3, "can"), /* TX */
115 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
116 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
117 SUNXI_FUNCTION(0x0, "gpio_in"),
118 SUNXI_FUNCTION(0x1, "gpio_out"),
119 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
120 SUNXI_FUNCTION(0x3, "can"), /* RX */
121 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
122 /* Hole */
123 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
124 SUNXI_FUNCTION(0x0, "gpio_in"),
125 SUNXI_FUNCTION(0x1, "gpio_out"),
126 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
128 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
131 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
132 SUNXI_FUNCTION(0x0, "gpio_in"),
133 SUNXI_FUNCTION(0x1, "gpio_out"),
134 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
135 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
136 SUNXI_FUNCTION(0x0, "gpio_in"),
137 SUNXI_FUNCTION(0x1, "gpio_out"),
138 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
139 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
140 SUNXI_FUNCTION(0x0, "gpio_in"),
141 SUNXI_FUNCTION(0x1, "gpio_out"),
142 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
144 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
147 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
148 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
149 SUNXI_FUNCTION(0x0, "gpio_in"),
150 SUNXI_FUNCTION(0x1, "gpio_out"),
151 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
152 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
153 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
154 SUNXI_FUNCTION(0x0, "gpio_in"),
155 SUNXI_FUNCTION(0x1, "gpio_out"),
156 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
157 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
158 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
159 SUNXI_FUNCTION(0x0, "gpio_in"),
160 SUNXI_FUNCTION(0x1, "gpio_out"),
161 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
162 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
171 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
172 SUNXI_FUNCTION(0x0, "gpio_in"),
173 SUNXI_FUNCTION(0x1, "gpio_out"),
174 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
179 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
188 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
189 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
190 SUNXI_FUNCTION(0x0, "gpio_in"),
191 SUNXI_FUNCTION(0x1, "gpio_out"),
192 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
193 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
194 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
195 SUNXI_FUNCTION(0x0, "gpio_in"),
196 SUNXI_FUNCTION(0x1, "gpio_out"),
197 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
198 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
203 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
205 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
209 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
212 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
213 SUNXI_FUNCTION(0x0, "gpio_in"),
214 SUNXI_FUNCTION(0x1, "gpio_out"),
215 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
216 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
217 SUNXI_FUNCTION(0x0, "gpio_in"),
218 SUNXI_FUNCTION(0x1, "gpio_out"),
219 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
220 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
221 SUNXI_FUNCTION(0x0, "gpio_in"),
222 SUNXI_FUNCTION(0x1, "gpio_out"),
223 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
224 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
229 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
230 /* Hole */
231 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
232 SUNXI_FUNCTION(0x0, "gpio_in"),
233 SUNXI_FUNCTION(0x1, "gpio_out"),
234 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
235 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
236 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
237 SUNXI_FUNCTION(0x0, "gpio_in"),
238 SUNXI_FUNCTION(0x1, "gpio_out"),
239 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
240 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
241 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
242 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out"),
244 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
245 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
246 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
247 SUNXI_FUNCTION(0x0, "gpio_in"),
248 SUNXI_FUNCTION(0x1, "gpio_out"),
249 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
250 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
251 SUNXI_FUNCTION(0x0, "gpio_in"),
252 SUNXI_FUNCTION(0x1, "gpio_out"),
253 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
254 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
255 SUNXI_FUNCTION(0x0, "gpio_in"),
256 SUNXI_FUNCTION(0x1, "gpio_out"),
257 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
258 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
259 SUNXI_FUNCTION(0x0, "gpio_in"),
260 SUNXI_FUNCTION(0x1, "gpio_out"),
261 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
262 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
263 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
264 SUNXI_FUNCTION(0x0, "gpio_in"),
265 SUNXI_FUNCTION(0x1, "gpio_out"),
266 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
267 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
268 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
269 SUNXI_FUNCTION(0x0, "gpio_in"),
270 SUNXI_FUNCTION(0x1, "gpio_out"),
271 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
272 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
273 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
274 SUNXI_FUNCTION(0x0, "gpio_in"),
275 SUNXI_FUNCTION(0x1, "gpio_out"),
276 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
277 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
279 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out"),
281 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
282 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
283 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
284 SUNXI_FUNCTION(0x0, "gpio_in"),
285 SUNXI_FUNCTION(0x1, "gpio_out"),
286 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
287 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
288 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
289 SUNXI_FUNCTION(0x0, "gpio_in"),
290 SUNXI_FUNCTION(0x1, "gpio_out"),
291 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
292 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
293 SUNXI_FUNCTION(0x0, "gpio_in"),
294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
296 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
297 SUNXI_FUNCTION(0x0, "gpio_in"),
298 SUNXI_FUNCTION(0x1, "gpio_out"),
299 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
300 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
301 SUNXI_FUNCTION(0x0, "gpio_in"),
302 SUNXI_FUNCTION(0x1, "gpio_out"),
303 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
304 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
305 SUNXI_FUNCTION(0x0, "gpio_in"),
306 SUNXI_FUNCTION(0x1, "gpio_out"),
307 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
308 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
309 SUNXI_FUNCTION(0x0, "gpio_in"),
310 SUNXI_FUNCTION(0x1, "gpio_out"),
311 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
316 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
317 SUNXI_FUNCTION(0x0, "gpio_in"),
318 SUNXI_FUNCTION(0x1, "gpio_out"),
319 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
320 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
321 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
322 SUNXI_FUNCTION(0x0, "gpio_in"),
323 SUNXI_FUNCTION(0x1, "gpio_out"),
324 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
325 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
330 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
335 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
336 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
337 SUNXI_FUNCTION(0x0, "gpio_in"),
338 SUNXI_FUNCTION(0x1, "gpio_out"),
339 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
340 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
341 SUNXI_FUNCTION(0x0, "gpio_in"),
342 SUNXI_FUNCTION(0x1, "gpio_out"),
343 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
344 /* Hole */
345 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
346 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out"),
348 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
349 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
350 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
351 SUNXI_FUNCTION(0x0, "gpio_in"),
352 SUNXI_FUNCTION(0x1, "gpio_out"),
353 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
354 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
355 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
356 SUNXI_FUNCTION(0x0, "gpio_in"),
357 SUNXI_FUNCTION(0x1, "gpio_out"),
358 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
359 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out"),
363 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
364 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
365 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
366 SUNXI_FUNCTION(0x0, "gpio_in"),
367 SUNXI_FUNCTION(0x1, "gpio_out"),
368 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
369 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
370 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
371 SUNXI_FUNCTION(0x0, "gpio_in"),
372 SUNXI_FUNCTION(0x1, "gpio_out"),
373 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
374 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
379 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
380 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
381 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"),
383 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
384 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
385 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
386 SUNXI_FUNCTION(0x0, "gpio_in"),
387 SUNXI_FUNCTION(0x1, "gpio_out"),
388 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
389 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
390 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
391 SUNXI_FUNCTION(0x0, "gpio_in"),
392 SUNXI_FUNCTION(0x1, "gpio_out"),
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
394 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
395 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
396 SUNXI_FUNCTION(0x0, "gpio_in"),
397 SUNXI_FUNCTION(0x1, "gpio_out"),
398 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
399 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
400 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
401 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out"),
403 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
404 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
405 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
406 SUNXI_FUNCTION(0x0, "gpio_in"),
407 SUNXI_FUNCTION(0x1, "gpio_out"),
408 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
409 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
410 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out"),
413 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
414 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
415 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
416 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out"),
418 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
419 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
420 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
421 SUNXI_FUNCTION(0x0, "gpio_in"),
422 SUNXI_FUNCTION(0x1, "gpio_out"),
423 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
424 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out"),
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
429 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
430 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
434 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
435 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
439 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
444 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
449 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
454 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
459 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
464 SUNXI_FUNCTION(0x3, "sim")), /* DET */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
469 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
474 SUNXI_FUNCTION(0x3, "sim")), /* RST */
475 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
479 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
484 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
485 /* Hole */
486 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
487 SUNXI_FUNCTION(0x0, "gpio_in"),
488 SUNXI_FUNCTION(0x1, "gpio_out"),
489 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
490 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
491 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
492 SUNXI_FUNCTION(0x0, "gpio_in"),
493 SUNXI_FUNCTION(0x1, "gpio_out"),
494 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
495 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
496 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
497 SUNXI_FUNCTION(0x0, "gpio_in"),
498 SUNXI_FUNCTION(0x1, "gpio_out"),
499 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
500 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
501 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
502 SUNXI_FUNCTION(0x0, "gpio_in"),
503 SUNXI_FUNCTION(0x1, "gpio_out"),
504 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
505 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
506 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
507 SUNXI_FUNCTION(0x0, "gpio_in"),
508 SUNXI_FUNCTION(0x1, "gpio_out"),
509 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
510 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
511 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
512 SUNXI_FUNCTION(0x0, "gpio_in"),
513 SUNXI_FUNCTION(0x1, "gpio_out"),
514 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
515 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
516 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
517 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
518 SUNXI_FUNCTION(0x0, "gpio_in"),
519 SUNXI_FUNCTION(0x1, "gpio_out"),
520 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
521 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
522 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
523 SUNXI_FUNCTION(0x0, "gpio_in"),
524 SUNXI_FUNCTION(0x1, "gpio_out"),
525 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
526 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
527 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
528 SUNXI_FUNCTION(0x0, "gpio_in"),
529 SUNXI_FUNCTION(0x1, "gpio_out"),
530 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
531 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
532 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
533 SUNXI_FUNCTION(0x0, "gpio_in"),
534 SUNXI_FUNCTION(0x1, "gpio_out"),
535 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
536 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
537 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
538 SUNXI_FUNCTION(0x0, "gpio_in"),
539 SUNXI_FUNCTION(0x1, "gpio_out"),
540 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
541 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
542 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
543 SUNXI_FUNCTION(0x0, "gpio_in"),
544 SUNXI_FUNCTION(0x1, "gpio_out"),
545 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
546 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
547 /* Hole */
548 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
549 SUNXI_FUNCTION(0x0, "gpio_in"),
550 SUNXI_FUNCTION(0x1, "gpio_out"),
551 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
552 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
553 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
554 SUNXI_FUNCTION(0x0, "gpio_in"),
555 SUNXI_FUNCTION(0x1, "gpio_out"),
556 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
557 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
558 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
559 SUNXI_FUNCTION(0x0, "gpio_in"),
560 SUNXI_FUNCTION(0x1, "gpio_out"),
561 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
562 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
563 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
564 SUNXI_FUNCTION(0x0, "gpio_in"),
565 SUNXI_FUNCTION(0x1, "gpio_out"),
566 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
567 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
572 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
573 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
574 SUNXI_FUNCTION(0x0, "gpio_in"),
575 SUNXI_FUNCTION(0x1, "gpio_out"),
576 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
577 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
578 /* Hole */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
580 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x1, "gpio_out"),
582 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
583 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
584 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
585 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
586 SUNXI_FUNCTION(0x0, "gpio_in"),
587 SUNXI_FUNCTION(0x1, "gpio_out"),
588 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
589 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
590 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
591 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
592 SUNXI_FUNCTION(0x0, "gpio_in"),
593 SUNXI_FUNCTION(0x1, "gpio_out"),
594 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
595 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
596 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
597 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
598 SUNXI_FUNCTION(0x0, "gpio_in"),
599 SUNXI_FUNCTION(0x1, "gpio_out"),
600 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
601 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
602 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
607 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
608 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
609 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
610 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
611 SUNXI_FUNCTION(0x0, "gpio_in"),
612 SUNXI_FUNCTION(0x1, "gpio_out"),
613 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
614 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
615 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
616 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
617 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
618 SUNXI_FUNCTION(0x0, "gpio_in"),
619 SUNXI_FUNCTION(0x1, "gpio_out"),
620 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
621 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
622 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
623 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
624 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
625 SUNXI_FUNCTION(0x0, "gpio_in"),
626 SUNXI_FUNCTION(0x1, "gpio_out"),
627 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
628 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
629 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
630 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
631 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
632 SUNXI_FUNCTION(0x0, "gpio_in"),
633 SUNXI_FUNCTION(0x1, "gpio_out"),
634 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
635 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
636 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
637 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
638 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
639 SUNXI_FUNCTION(0x0, "gpio_in"),
640 SUNXI_FUNCTION(0x1, "gpio_out"),
641 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
642 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
643 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
644 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
645 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
646 SUNXI_FUNCTION(0x0, "gpio_in"),
647 SUNXI_FUNCTION(0x1, "gpio_out"),
648 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
649 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
650 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
651 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
652 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
653 SUNXI_FUNCTION(0x0, "gpio_in"),
654 SUNXI_FUNCTION(0x1, "gpio_out"),
655 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
656 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
657 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
658 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
659 /* Hole */
660 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
661 SUNXI_FUNCTION(0x0, "gpio_in"),
662 SUNXI_FUNCTION(0x1, "gpio_out"),
663 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
664 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
665 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
666 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
667 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
668 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
669 SUNXI_FUNCTION(0x0, "gpio_in"),
670 SUNXI_FUNCTION(0x1, "gpio_out"),
671 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
672 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
673 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
674 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
675 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
676 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
677 SUNXI_FUNCTION(0x0, "gpio_in"),
678 SUNXI_FUNCTION(0x1, "gpio_out"),
679 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
680 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
681 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
682 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
683 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
684 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
685 SUNXI_FUNCTION(0x0, "gpio_in"),
686 SUNXI_FUNCTION(0x1, "gpio_out"),
687 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
688 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
689 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
690 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
691 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
692 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
693 SUNXI_FUNCTION(0x0, "gpio_in"),
694 SUNXI_FUNCTION(0x1, "gpio_out"),
695 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
696 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
697 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
698 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
699 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
700 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
701 SUNXI_FUNCTION(0x0, "gpio_in"),
702 SUNXI_FUNCTION(0x1, "gpio_out"),
703 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
704 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
705 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
706 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
707 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
708 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
709 SUNXI_FUNCTION(0x0, "gpio_in"),
710 SUNXI_FUNCTION(0x1, "gpio_out"),
711 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
712 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
713 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
714 SUNXI_FUNCTION(0x5, "ms"), /* BS */
715 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
716 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
717 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
718 SUNXI_FUNCTION(0x0, "gpio_in"),
719 SUNXI_FUNCTION(0x1, "gpio_out"),
720 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
721 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
722 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
723 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
724 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
725 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
726 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
727 SUNXI_FUNCTION(0x0, "gpio_in"),
728 SUNXI_FUNCTION(0x1, "gpio_out"),
729 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
730 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
731 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
732 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
733 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
734 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
735 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
736 SUNXI_FUNCTION(0x0, "gpio_in"),
737 SUNXI_FUNCTION(0x1, "gpio_out"),
738 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
739 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
740 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
741 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
742 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
743 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
744 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
745 SUNXI_FUNCTION(0x0, "gpio_in"),
746 SUNXI_FUNCTION(0x1, "gpio_out"),
747 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
748 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
749 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
750 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
751 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
752 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
753 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
754 SUNXI_FUNCTION(0x0, "gpio_in"),
755 SUNXI_FUNCTION(0x1, "gpio_out"),
756 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
757 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
758 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
759 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
760 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
761 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
762 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
763 SUNXI_FUNCTION(0x0, "gpio_in"),
764 SUNXI_FUNCTION(0x1, "gpio_out"),
765 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
766 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
767 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
768 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
769 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
770 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
771 SUNXI_FUNCTION(0x0, "gpio_in"),
772 SUNXI_FUNCTION(0x1, "gpio_out"),
773 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
774 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
775 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
776 SUNXI_FUNCTION(0x5, "sim"), /* RST */
777 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
778 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
779 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
780 SUNXI_FUNCTION(0x0, "gpio_in"),
781 SUNXI_FUNCTION(0x1, "gpio_out"),
782 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
783 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
784 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
785 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
786 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
787 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
788 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
789 SUNXI_FUNCTION(0x0, "gpio_in"),
790 SUNXI_FUNCTION(0x1, "gpio_out"),
791 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
792 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
793 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
794 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
795 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
796 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
797 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
798 SUNXI_FUNCTION(0x0, "gpio_in"),
799 SUNXI_FUNCTION(0x1, "gpio_out"),
800 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
801 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
802 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
803 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
804 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
805 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
806 SUNXI_FUNCTION(0x0, "gpio_in"),
807 SUNXI_FUNCTION(0x1, "gpio_out"),
808 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
809 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
810 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
811 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
812 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
813 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
814 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
815 SUNXI_FUNCTION(0x0, "gpio_in"),
816 SUNXI_FUNCTION(0x1, "gpio_out"),
817 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
818 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
819 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
820 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
821 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
822 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
823 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
824 SUNXI_FUNCTION(0x0, "gpio_in"),
825 SUNXI_FUNCTION(0x1, "gpio_out"),
826 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
827 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
828 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
829 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
830 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
831 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
832 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
833 SUNXI_FUNCTION(0x0, "gpio_in"),
834 SUNXI_FUNCTION(0x1, "gpio_out"),
835 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
836 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
837 SUNXI_FUNCTION(0x4, "can"), /* TX */
838 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
839 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
840 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
841 SUNXI_FUNCTION(0x0, "gpio_in"),
842 SUNXI_FUNCTION(0x1, "gpio_out"),
843 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
844 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
845 SUNXI_FUNCTION(0x4, "can"), /* RX */
846 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
847 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
848 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
849 SUNXI_FUNCTION(0x0, "gpio_in"),
850 SUNXI_FUNCTION(0x1, "gpio_out"),
851 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
852 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
853 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
854 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
855 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
856 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
857 SUNXI_FUNCTION(0x0, "gpio_in"),
858 SUNXI_FUNCTION(0x1, "gpio_out"),
859 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
860 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
861 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
862 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
863 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
864 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
865 SUNXI_FUNCTION(0x0, "gpio_in"),
866 SUNXI_FUNCTION(0x1, "gpio_out"),
867 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
868 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
869 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
870 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
871 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
872 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
873 SUNXI_FUNCTION(0x0, "gpio_in"),
874 SUNXI_FUNCTION(0x1, "gpio_out"),
875 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
876 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
877 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
878 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
879 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
880 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
881 SUNXI_FUNCTION(0x0, "gpio_in"),
882 SUNXI_FUNCTION(0x1, "gpio_out"),
883 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
884 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
885 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
886 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
887 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
888 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
889 SUNXI_FUNCTION(0x0, "gpio_in"),
890 SUNXI_FUNCTION(0x1, "gpio_out"),
891 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
892 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
893 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
894 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
895 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
896 /* Hole */
897 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
898 SUNXI_FUNCTION(0x0, "gpio_in"),
899 SUNXI_FUNCTION(0x1, "gpio_out")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out")),
903 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out")),
906 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
907 SUNXI_FUNCTION(0x0, "gpio_in"),
908 SUNXI_FUNCTION(0x1, "gpio_out"),
909 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
910 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
911 SUNXI_FUNCTION(0x0, "gpio_in"),
912 SUNXI_FUNCTION(0x1, "gpio_out"),
913 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
914 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
915 SUNXI_FUNCTION(0x0, "gpio_in"),
916 SUNXI_FUNCTION(0x1, "gpio_out"),
917 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
918 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
919 SUNXI_FUNCTION(0x0, "gpio_in"),
920 SUNXI_FUNCTION(0x1, "gpio_out"),
921 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
922 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
923 SUNXI_FUNCTION(0x0, "gpio_in"),
924 SUNXI_FUNCTION(0x1, "gpio_out"),
925 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
926 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
927 SUNXI_FUNCTION(0x0, "gpio_in"),
928 SUNXI_FUNCTION(0x1, "gpio_out"),
929 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
930 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
931 SUNXI_FUNCTION(0x0, "gpio_in"),
932 SUNXI_FUNCTION(0x1, "gpio_out"),
933 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
934 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
935 SUNXI_FUNCTION(0x0, "gpio_in"),
936 SUNXI_FUNCTION(0x1, "gpio_out"),
937 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
938 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
939 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
940 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
941 SUNXI_FUNCTION(0x0, "gpio_in"),
942 SUNXI_FUNCTION(0x1, "gpio_out"),
943 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
944 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
945 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
946 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
947 SUNXI_FUNCTION(0x0, "gpio_in"),
948 SUNXI_FUNCTION(0x1, "gpio_out"),
949 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
950 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
951 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
952 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
953 SUNXI_FUNCTION(0x0, "gpio_in"),
954 SUNXI_FUNCTION(0x1, "gpio_out"),
955 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
956 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
957 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
958 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
959 SUNXI_FUNCTION(0x0, "gpio_in"),
960 SUNXI_FUNCTION(0x1, "gpio_out"),
961 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
962 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
963 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
964 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
965 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
966 SUNXI_FUNCTION(0x0, "gpio_in"),
967 SUNXI_FUNCTION(0x1, "gpio_out"),
968 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
969 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
970 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
971 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
972 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
973 SUNXI_FUNCTION(0x0, "gpio_in"),
974 SUNXI_FUNCTION(0x1, "gpio_out"),
975 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
976 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
977 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
978 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
979 SUNXI_FUNCTION(0x0, "gpio_in"),
980 SUNXI_FUNCTION(0x1, "gpio_out"),
981 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
982 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
983 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
984 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
985 SUNXI_FUNCTION(0x0, "gpio_in"),
986 SUNXI_FUNCTION(0x1, "gpio_out"),
987 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
988 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
989 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
990 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
991 SUNXI_FUNCTION(0x0, "gpio_in"),
992 SUNXI_FUNCTION(0x1, "gpio_out"),
993 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
994 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
995 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
996 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
997 SUNXI_FUNCTION(0x0, "gpio_in"),
998 SUNXI_FUNCTION(0x1, "gpio_out"),
999 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
1000 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
1001 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
1002 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
1003 SUNXI_FUNCTION(0x0, "gpio_in"),
1004 SUNXI_FUNCTION(0x1, "gpio_out"),
1005 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1006 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1007 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1008};
1009
1010static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1011 .pins = sun4i_a10_pins,
1012 .npins = ARRAY_SIZE(sun4i_a10_pins),
1013};
1014
1015static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
1016{
1017 return sunxi_pinctrl_init(pdev,
1018 &sun4i_a10_pinctrl_data);
1019}
1020
1021static struct of_device_id sun4i_a10_pinctrl_match[] = {
1022 { .compatible = "allwinner,sun4i-a10-pinctrl", },
1023 {}
1024};
1025MODULE_DEVICE_TABLE(of, sun4i_a10_pinctrl_match);
1026
1027static struct platform_driver sun4i_a10_pinctrl_driver = {
1028 .probe = sun4i_a10_pinctrl_probe,
1029 .driver = {
1030 .name = "sun4i-pinctrl",
1031 .owner = THIS_MODULE,
1032 .of_match_table = sun4i_a10_pinctrl_match,
1033 },
1034};
1035module_platform_driver(sun4i_a10_pinctrl_driver);
1036
1037MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
1038MODULE_DESCRIPTION("Allwinner A10 pinctrl driver");
1039MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
new file mode 100644
index 000000000000..164d743f526c
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
@@ -0,0 +1,690 @@
1/*
2 * Allwinner A10s SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
26 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
27 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
32 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
33 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
38 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
39 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
44 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
45 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
50 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
51 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
53 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
56 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
57 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
62 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
63 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
65 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
68 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
69 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
74 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
75 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
76 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
77 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
78 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out"),
80 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
81 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
82 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
83 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
84 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
85 SUNXI_FUNCTION(0x0, "gpio_in"),
86 SUNXI_FUNCTION(0x1, "gpio_out"),
87 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
88 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
89 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
90 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
91 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
92 SUNXI_FUNCTION(0x0, "gpio_in"),
93 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
95 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
96 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
97 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
98 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
99 SUNXI_FUNCTION(0x0, "gpio_in"),
100 SUNXI_FUNCTION(0x1, "gpio_out"),
101 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
102 SUNXI_FUNCTION(0x3, "uart1"), /* TX */
103 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
104 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
105 SUNXI_FUNCTION(0x0, "gpio_in"),
106 SUNXI_FUNCTION(0x1, "gpio_out"),
107 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
108 SUNXI_FUNCTION(0x3, "uart1"), /* RX */
109 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
114 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
115 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
116 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
121 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
122 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
123 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
128 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
129 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
130 SUNXI_FUNCTION(0x0, "gpio_in"),
131 SUNXI_FUNCTION(0x1, "gpio_out"),
132 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
133 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
134 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
135 /* Hole */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
144 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
145 SUNXI_FUNCTION(0x0, "gpio_in"),
146 SUNXI_FUNCTION(0x1, "gpio_out"),
147 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
148 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
153 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out"),
157 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
158 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
159 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
160 SUNXI_FUNCTION(0x0, "gpio_in"),
161 SUNXI_FUNCTION(0x1, "gpio_out"),
162 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
163 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
168 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
169 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
170 SUNXI_FUNCTION(0x0, "gpio_in"),
171 SUNXI_FUNCTION(0x1, "gpio_out"),
172 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
173 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
174 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
175 SUNXI_FUNCTION(0x0, "gpio_in"),
176 SUNXI_FUNCTION(0x1, "gpio_out"),
177 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
178 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
179 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
180 SUNXI_FUNCTION(0x0, "gpio_in"),
181 SUNXI_FUNCTION(0x1, "gpio_out"),
182 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
183 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
188 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
189 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
190 SUNXI_FUNCTION(0x0, "gpio_in"),
191 SUNXI_FUNCTION(0x1, "gpio_out"),
192 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
193 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
194 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
199 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
200 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
205 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
206 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
207 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
208 SUNXI_FUNCTION(0x0, "gpio_in"),
209 SUNXI_FUNCTION(0x1, "gpio_out"),
210 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
211 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
212 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
221 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
222 SUNXI_FUNCTION(0x0, "gpio_in"),
223 SUNXI_FUNCTION(0x1, "gpio_out"),
224 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
230 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out"),
232 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
233 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
234 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
238 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
239 /* Hole */
240 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
241 SUNXI_FUNCTION(0x0, "gpio_in"),
242 SUNXI_FUNCTION(0x1, "gpio_out"),
243 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
244 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
245 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
246 SUNXI_FUNCTION(0x0, "gpio_in"),
247 SUNXI_FUNCTION(0x1, "gpio_out"),
248 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
249 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
250 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
251 SUNXI_FUNCTION(0x0, "gpio_in"),
252 SUNXI_FUNCTION(0x1, "gpio_out"),
253 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
254 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
259 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
264 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
265 SUNXI_FUNCTION(0x0, "gpio_in"),
266 SUNXI_FUNCTION(0x1, "gpio_out"),
267 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
268 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
269 SUNXI_FUNCTION(0x0, "gpio_in"),
270 SUNXI_FUNCTION(0x1, "gpio_out"),
271 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
272 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
273 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
274 SUNXI_FUNCTION(0x0, "gpio_in"),
275 SUNXI_FUNCTION(0x1, "gpio_out"),
276 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
277 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
279 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out"),
281 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
282 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
283 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
284 SUNXI_FUNCTION(0x0, "gpio_in"),
285 SUNXI_FUNCTION(0x1, "gpio_out"),
286 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
287 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
288 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
289 SUNXI_FUNCTION(0x0, "gpio_in"),
290 SUNXI_FUNCTION(0x1, "gpio_out"),
291 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
292 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
297 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
298 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
299 SUNXI_FUNCTION(0x0, "gpio_in"),
300 SUNXI_FUNCTION(0x1, "gpio_out"),
301 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
302 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
303 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
304 SUNXI_FUNCTION(0x0, "gpio_in"),
305 SUNXI_FUNCTION(0x1, "gpio_out"),
306 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
307 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
308 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
309 SUNXI_FUNCTION(0x0, "gpio_in"),
310 SUNXI_FUNCTION(0x1, "gpio_out"),
311 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
312 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
317 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
322 SUNXI_FUNCTION(0x4, "uart3")), /* TX */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
327 SUNXI_FUNCTION(0x4, "uart3")), /* RX */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
332 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
333 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
334 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
335 SUNXI_FUNCTION(0x0, "gpio_in"),
336 SUNXI_FUNCTION(0x1, "gpio_out"),
337 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
338 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
339 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
340 /* Hole */
341 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
342 SUNXI_FUNCTION(0x0, "gpio_in"),
343 SUNXI_FUNCTION(0x1, "gpio_out"),
344 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
345 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
346 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out"),
348 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
349 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
350 SUNXI_FUNCTION(0x0, "gpio_in"),
351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
353 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
354 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
355 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out"),
357 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
358 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
359 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
360 SUNXI_FUNCTION(0x0, "gpio_in"),
361 SUNXI_FUNCTION(0x1, "gpio_out"),
362 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
363 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
364 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
365 SUNXI_FUNCTION(0x0, "gpio_in"),
366 SUNXI_FUNCTION(0x1, "gpio_out"),
367 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
368 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
369 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
370 SUNXI_FUNCTION(0x0, "gpio_in"),
371 SUNXI_FUNCTION(0x1, "gpio_out"),
372 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
373 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
374 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
375 SUNXI_FUNCTION(0x0, "gpio_in"),
376 SUNXI_FUNCTION(0x1, "gpio_out"),
377 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
378 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
379 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
380 SUNXI_FUNCTION(0x0, "gpio_in"),
381 SUNXI_FUNCTION(0x1, "gpio_out"),
382 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
391 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
396 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
401 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
406 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
411 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
416 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
421 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
422 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out"),
424 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out"),
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
429 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
430 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
434 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
435 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
439 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
444 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
449 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
454 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
459 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
464 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
469 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
474 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
475 /* Hole */
476 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
477 SUNXI_FUNCTION(0x0, "gpio_in"),
478 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
479 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
480 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
481 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
482 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
483 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
485 SUNXI_FUNCTION(0x3, "csi0"), /* CK */
486 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
487 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
491 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
492 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
497 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
498 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
499 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
500 SUNXI_FUNCTION(0x0, "gpio_in"),
501 SUNXI_FUNCTION(0x1, "gpio_out"),
502 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
503 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
504 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
505 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
509 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
510 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
511 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
512 SUNXI_FUNCTION(0x0, "gpio_in"),
513 SUNXI_FUNCTION(0x1, "gpio_out"),
514 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
515 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
516 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
517 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
518 SUNXI_FUNCTION(0x0, "gpio_in"),
519 SUNXI_FUNCTION(0x1, "gpio_out"),
520 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
521 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
522 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
523 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
524 SUNXI_FUNCTION(0x0, "gpio_in"),
525 SUNXI_FUNCTION(0x1, "gpio_out"),
526 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
527 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
528 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
533 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
534 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
535 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
536 SUNXI_FUNCTION(0x0, "gpio_in"),
537 SUNXI_FUNCTION(0x1, "gpio_out"),
538 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
539 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
540 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
541 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
542 SUNXI_FUNCTION(0x0, "gpio_in"),
543 SUNXI_FUNCTION(0x1, "gpio_out"),
544 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
545 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
546 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
547 /* Hole */
548 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
549 SUNXI_FUNCTION(0x0, "gpio_in"),
550 SUNXI_FUNCTION(0x1, "gpio_out"),
551 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
552 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
553 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
554 SUNXI_FUNCTION(0x0, "gpio_in"),
555 SUNXI_FUNCTION(0x1, "gpio_out"),
556 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
557 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
558 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
559 SUNXI_FUNCTION(0x0, "gpio_in"),
560 SUNXI_FUNCTION(0x1, "gpio_out"),
561 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
562 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
563 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
564 SUNXI_FUNCTION(0x0, "gpio_in"),
565 SUNXI_FUNCTION(0x1, "gpio_out"),
566 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
567 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
572 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
573 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
574 SUNXI_FUNCTION(0x0, "gpio_in"),
575 SUNXI_FUNCTION(0x1, "gpio_out"),
576 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
577 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
578 /* Hole */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
580 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
582 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
583 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
584 SUNXI_FUNCTION(0x0, "gpio_in"),
585 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
586 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
587 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
588 SUNXI_FUNCTION(0x0, "gpio_in"),
589 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
590 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
591 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
592 SUNXI_FUNCTION(0x0, "gpio_in"),
593 SUNXI_FUNCTION(0x1, "gpio_out"),
594 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
595 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
596 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
597 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
598 SUNXI_FUNCTION(0x0, "gpio_in"),
599 SUNXI_FUNCTION(0x1, "gpio_out"),
600 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
601 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
602 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
607 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
608 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
609 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out"),
612 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
613 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
614 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
615 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
616 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
617 SUNXI_FUNCTION(0x0, "gpio_in"),
618 SUNXI_FUNCTION(0x1, "gpio_out"),
619 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
620 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
621 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
622 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
623 SUNXI_FUNCTION(0x0, "gpio_in"),
624 SUNXI_FUNCTION(0x1, "gpio_out"),
625 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
626 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
627 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
632 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
633 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
634 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
635 SUNXI_FUNCTION(0x0, "gpio_in"),
636 SUNXI_FUNCTION(0x1, "gpio_out"),
637 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
638 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
639 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
640 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
641 SUNXI_FUNCTION(0x0, "gpio_in"),
642 SUNXI_FUNCTION(0x1, "gpio_out"),
643 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
644 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
645 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
646 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
647 SUNXI_FUNCTION(0x0, "gpio_in"),
648 SUNXI_FUNCTION(0x1, "gpio_out"),
649 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
650 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
651 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
652 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
653 SUNXI_FUNCTION(0x0, "gpio_in"),
654 SUNXI_FUNCTION(0x1, "gpio_out"),
655 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
656 SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */
657 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
658 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
659};
660
661static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
662 .pins = sun5i_a10s_pins,
663 .npins = ARRAY_SIZE(sun5i_a10s_pins),
664};
665
666static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev)
667{
668 return sunxi_pinctrl_init(pdev,
669 &sun5i_a10s_pinctrl_data);
670}
671
672static struct of_device_id sun5i_a10s_pinctrl_match[] = {
673 { .compatible = "allwinner,sun5i-a10s-pinctrl", },
674 {}
675};
676MODULE_DEVICE_TABLE(of, sun5i_a10s_pinctrl_match);
677
678static struct platform_driver sun5i_a10s_pinctrl_driver = {
679 .probe = sun5i_a10s_pinctrl_probe,
680 .driver = {
681 .name = "sun5i-a10s-pinctrl",
682 .owner = THIS_MODULE,
683 .of_match_table = sun5i_a10s_pinctrl_match,
684 },
685};
686module_platform_driver(sun5i_a10s_pinctrl_driver);
687
688MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
689MODULE_DESCRIPTION("Allwinner A10s pinctrl driver");
690MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
new file mode 100644
index 000000000000..1188a2b7b988
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
@@ -0,0 +1,411 @@
1/*
2 * Allwinner A13 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun5i_a13_pins[] = {
22 /* Hole */
23 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
24 SUNXI_FUNCTION(0x0, "gpio_in"),
25 SUNXI_FUNCTION(0x1, "gpio_out"),
26 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
27 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
28 SUNXI_FUNCTION(0x0, "gpio_in"),
29 SUNXI_FUNCTION(0x1, "gpio_out"),
30 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "pwm"),
35 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
36 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
37 SUNXI_FUNCTION(0x0, "gpio_in"),
38 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
40 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
41 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
42 SUNXI_FUNCTION(0x0, "gpio_in"),
43 SUNXI_FUNCTION(0x1, "gpio_out"),
44 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
45 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
46 /* Hole */
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
48 SUNXI_FUNCTION(0x0, "gpio_in"),
49 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
51 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
52 /* Hole */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
57 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
58 SUNXI_FUNCTION(0x0, "gpio_in"),
59 SUNXI_FUNCTION(0x1, "gpio_out"),
60 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
69 /* Hole */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
74 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
76 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
79 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
84 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
85 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
86 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
89 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
90 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
91 SUNXI_FUNCTION(0x0, "gpio_in"),
92 SUNXI_FUNCTION(0x1, "gpio_out"),
93 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
94 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
95 SUNXI_FUNCTION(0x0, "gpio_in"),
96 SUNXI_FUNCTION(0x1, "gpio_out"),
97 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
98 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
99 SUNXI_FUNCTION(0x0, "gpio_in"),
100 SUNXI_FUNCTION(0x1, "gpio_out"),
101 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
102 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
103 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
104 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out"),
106 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
107 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
108 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
109 SUNXI_FUNCTION(0x0, "gpio_in"),
110 SUNXI_FUNCTION(0x1, "gpio_out"),
111 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
112 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
117 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
118 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
119 SUNXI_FUNCTION(0x0, "gpio_in"),
120 SUNXI_FUNCTION(0x1, "gpio_out"),
121 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
122 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
123 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
124 SUNXI_FUNCTION(0x0, "gpio_in"),
125 SUNXI_FUNCTION(0x1, "gpio_out"),
126 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
127 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
132 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
133 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
134 SUNXI_FUNCTION(0x0, "gpio_in"),
135 SUNXI_FUNCTION(0x1, "gpio_out"),
136 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
137 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
138 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
139 SUNXI_FUNCTION(0x0, "gpio_in"),
140 SUNXI_FUNCTION(0x1, "gpio_out"),
141 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
142 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
144 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
147 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
148 /* Hole */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
153 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
154 /* Hole */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
159 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
160 SUNXI_FUNCTION(0x0, "gpio_in"),
161 SUNXI_FUNCTION(0x1, "gpio_out"),
162 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
171 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
172 SUNXI_FUNCTION(0x0, "gpio_in"),
173 SUNXI_FUNCTION(0x1, "gpio_out"),
174 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
179 /* Hole */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
188 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
189 SUNXI_FUNCTION(0x0, "gpio_in"),
190 SUNXI_FUNCTION(0x1, "gpio_out"),
191 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
192 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
193 SUNXI_FUNCTION(0x0, "gpio_in"),
194 SUNXI_FUNCTION(0x1, "gpio_out"),
195 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
200 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
201 SUNXI_FUNCTION(0x0, "gpio_in"),
202 SUNXI_FUNCTION(0x1, "gpio_out"),
203 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
204 /* Hole */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
221 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
222 SUNXI_FUNCTION(0x0, "gpio_in"),
223 SUNXI_FUNCTION(0x1, "gpio_out"),
224 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
230 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out"),
232 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
241 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
242 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out"),
244 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
245 /* Hole */
246 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
247 SUNXI_FUNCTION(0x0, "gpio_in"),
248 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
249 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
250 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
254 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
255 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
256 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
257 SUNXI_FUNCTION(0x0, "gpio_in"),
258 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
259 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
264 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
269 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
274 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
279 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
284 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
289 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
290 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
291 SUNXI_FUNCTION(0x0, "gpio_in"),
292 SUNXI_FUNCTION(0x1, "gpio_out"),
293 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
294 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
295 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
296 SUNXI_FUNCTION(0x0, "gpio_in"),
297 SUNXI_FUNCTION(0x1, "gpio_out"),
298 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
299 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
300 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
301 SUNXI_FUNCTION(0x0, "gpio_in"),
302 SUNXI_FUNCTION(0x1, "gpio_out"),
303 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
304 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
305 /* Hole */
306 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
307 SUNXI_FUNCTION(0x0, "gpio_in"),
308 SUNXI_FUNCTION(0x1, "gpio_out"),
309 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
310 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
311 SUNXI_FUNCTION(0x0, "gpio_in"),
312 SUNXI_FUNCTION(0x1, "gpio_out"),
313 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
314 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
315 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out"),
317 SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
330 /* Hole */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
335 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
336 SUNXI_FUNCTION(0x0, "gpio_in"),
337 SUNXI_FUNCTION(0x1, "gpio_out"),
338 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
340 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out"),
342 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
344 SUNXI_FUNCTION(0x0, "gpio_in"),
345 SUNXI_FUNCTION(0x1, "gpio_out"),
346 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
347 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
348 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
349 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
350 SUNXI_FUNCTION(0x0, "gpio_in"),
351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
353 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
354 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
355 /* Hole */
356 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
357 SUNXI_FUNCTION(0x0, "gpio_in"),
358 SUNXI_FUNCTION(0x1, "gpio_out"),
359 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
360 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
361 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
366 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
367 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
368 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
369 SUNXI_FUNCTION(0x0, "gpio_in"),
370 SUNXI_FUNCTION(0x1, "gpio_out"),
371 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
372 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
373 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
374 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
375 SUNXI_FUNCTION(0x0, "gpio_in"),
376 SUNXI_FUNCTION(0x1, "gpio_out"),
377 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
378 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
379 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
380};
381
382static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
383 .pins = sun5i_a13_pins,
384 .npins = ARRAY_SIZE(sun5i_a13_pins),
385};
386
387static int sun5i_a13_pinctrl_probe(struct platform_device *pdev)
388{
389 return sunxi_pinctrl_init(pdev,
390 &sun5i_a13_pinctrl_data);
391}
392
393static struct of_device_id sun5i_a13_pinctrl_match[] = {
394 { .compatible = "allwinner,sun5i-a13-pinctrl", },
395 {}
396};
397MODULE_DEVICE_TABLE(of, sun5i_a13_pinctrl_match);
398
399static struct platform_driver sun5i_a13_pinctrl_driver = {
400 .probe = sun5i_a13_pinctrl_probe,
401 .driver = {
402 .name = "sun5i-a13-pinctrl",
403 .owner = THIS_MODULE,
404 .of_match_table = sun5i_a13_pinctrl_match,
405 },
406};
407module_platform_driver(sun5i_a13_pinctrl_driver);
408
409MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
410MODULE_DESCRIPTION("Allwinner A13 pinctrl driver");
411MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
new file mode 100644
index 000000000000..8fcba48e0a42
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
@@ -0,0 +1,141 @@
1/*
2 * Allwinner A31 SoCs special pins pinctrl driver.
3 *
4 * Copyright (C) 2014 Boris Brezillon
5 * Boris Brezillon <boris.brezillon@free-electrons.com>
6 *
7 * Copyright (C) 2014 Maxime Ripard
8 * Maxime Ripard <maxime.ripard@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/reset.h>
21
22#include "pinctrl-sunxi.h"
23
24static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
25 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
29 SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
30 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
31 SUNXI_FUNCTION(0x0, "gpio_in"),
32 SUNXI_FUNCTION(0x1, "gpio_out"),
33 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
34 SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
35 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
36 SUNXI_FUNCTION(0x0, "gpio_in"),
37 SUNXI_FUNCTION(0x1, "gpio_out"),
38 SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
39 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
40 SUNXI_FUNCTION(0x0, "gpio_in"),
41 SUNXI_FUNCTION(0x1, "gpio_out"),
42 SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
48 SUNXI_FUNCTION(0x0, "gpio_in"),
49 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
51 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
52 SUNXI_FUNCTION(0x0, "gpio_in"),
53 SUNXI_FUNCTION(0x1, "gpio_out"),
54 SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
59 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
60 SUNXI_FUNCTION(0x0, "gpio_in"),
61 SUNXI_FUNCTION(0x1, "gpio_out"),
62 SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
63 /* Hole */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
65 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out")),
67 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
68 SUNXI_FUNCTION(0x0, "gpio_in"),
69 SUNXI_FUNCTION(0x1, "gpio_out")),
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x3, "1wire")),
74 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
75 SUNXI_FUNCTION(0x0, "gpio_in"),
76 SUNXI_FUNCTION(0x1, "gpio_out")),
77 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
78 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out")),
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out")),
83 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out")),
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
90};
91
92static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
93 .pins = sun6i_a31_r_pins,
94 .npins = ARRAY_SIZE(sun6i_a31_r_pins),
95 .pin_base = PL_BASE,
96};
97
98static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
99{
100 struct reset_control *rstc;
101 int ret;
102
103 rstc = devm_reset_control_get(&pdev->dev, NULL);
104 if (IS_ERR(rstc)) {
105 dev_err(&pdev->dev, "Reset controller missing\n");
106 return PTR_ERR(rstc);
107 }
108
109 ret = reset_control_deassert(rstc);
110 if (ret)
111 return ret;
112
113 ret = sunxi_pinctrl_init(pdev,
114 &sun6i_a31_r_pinctrl_data);
115
116 if (ret)
117 reset_control_assert(rstc);
118
119 return ret;
120}
121
122static struct of_device_id sun6i_a31_r_pinctrl_match[] = {
123 { .compatible = "allwinner,sun6i-a31-r-pinctrl", },
124 {}
125};
126MODULE_DEVICE_TABLE(of, sun6i_a31_r_pinctrl_match);
127
128static struct platform_driver sun6i_a31_r_pinctrl_driver = {
129 .probe = sun6i_a31_r_pinctrl_probe,
130 .driver = {
131 .name = "sun6i-a31-r-pinctrl",
132 .owner = THIS_MODULE,
133 .of_match_table = sun6i_a31_r_pinctrl_match,
134 },
135};
136module_platform_driver(sun6i_a31_r_pinctrl_driver);
137
138MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com");
139MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
140MODULE_DESCRIPTION("Allwinner A31 R_PIO pinctrl driver");
141MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
new file mode 100644
index 000000000000..8dea5856458b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -0,0 +1,865 @@
1/*
2 * Allwinner A31 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun6i_a31_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
27 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
32 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
33 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
38 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
39 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
44 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
45 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
50 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
51 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
53 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
56 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
57 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
62 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
63 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
65 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
68 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
69 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
74 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
76 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
79 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
80 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
81 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */
82 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
83 SUNXI_FUNCTION(0x0, "gpio_in"),
84 SUNXI_FUNCTION(0x1, "gpio_out"),
85 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
86 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
87 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
88 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
93 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
94 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
95 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
97 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
100 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
101 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
102 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */
103 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
104 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out"),
106 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
107 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
108 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
109 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
114 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
115 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
116 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
121 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */
122 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
123 SUNXI_FUNCTION(0x0, "gpio_in"),
124 SUNXI_FUNCTION(0x1, "gpio_out"),
125 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
126 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
128 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
131 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
136 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */
137 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
138 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
141 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
142 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
144 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
147 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
148 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
153 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
154 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
159 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
160 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */
161 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
162 SUNXI_FUNCTION(0x0, "gpio_in"),
163 SUNXI_FUNCTION(0x1, "gpio_out"),
164 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
165 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
166 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
171 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
172 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */
173 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
174 SUNXI_FUNCTION(0x0, "gpio_in"),
175 SUNXI_FUNCTION(0x1, "gpio_out"),
176 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
177 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
178 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */
179 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
180 SUNXI_FUNCTION(0x0, "gpio_in"),
181 SUNXI_FUNCTION(0x1, "gpio_out"),
182 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
183 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
188 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */
189 /* Hole */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
194 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
195 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */
200 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
201 SUNXI_FUNCTION(0x0, "gpio_in"),
202 SUNXI_FUNCTION(0x1, "gpio_out"),
203 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
205 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
209 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
212 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
217 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
218 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */
219 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
220 SUNXI_FUNCTION(0x0, "gpio_in"),
221 SUNXI_FUNCTION(0x1, "gpio_out"),
222 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
223 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
224 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */
229 /* Hole */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
231 SUNXI_FUNCTION(0x0, "gpio_in"),
232 SUNXI_FUNCTION(0x1, "gpio_out"),
233 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
234 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
235 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
236 SUNXI_FUNCTION(0x0, "gpio_in"),
237 SUNXI_FUNCTION(0x1, "gpio_out"),
238 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
239 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
240 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
241 SUNXI_FUNCTION(0x0, "gpio_in"),
242 SUNXI_FUNCTION(0x1, "gpio_out"),
243 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
244 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
245 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
246 SUNXI_FUNCTION(0x0, "gpio_in"),
247 SUNXI_FUNCTION(0x1, "gpio_out"),
248 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
249 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
250 SUNXI_FUNCTION(0x0, "gpio_in"),
251 SUNXI_FUNCTION(0x1, "gpio_out"),
252 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
253 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
254 SUNXI_FUNCTION(0x0, "gpio_in"),
255 SUNXI_FUNCTION(0x1, "gpio_out"),
256 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
261 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
262 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
263 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
264 SUNXI_FUNCTION(0x0, "gpio_in"),
265 SUNXI_FUNCTION(0x1, "gpio_out"),
266 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
267 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
268 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
269 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
270 SUNXI_FUNCTION(0x0, "gpio_in"),
271 SUNXI_FUNCTION(0x1, "gpio_out"),
272 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
273 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
274 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
279 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
280 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
281 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
282 SUNXI_FUNCTION(0x0, "gpio_in"),
283 SUNXI_FUNCTION(0x1, "gpio_out"),
284 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
285 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
286 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
287 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
288 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out"),
290 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
291 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
292 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
297 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
298 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
299 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
300 SUNXI_FUNCTION(0x0, "gpio_in"),
301 SUNXI_FUNCTION(0x1, "gpio_out"),
302 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
303 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
304 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
309 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
310 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
311 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
312 SUNXI_FUNCTION(0x0, "gpio_in"),
313 SUNXI_FUNCTION(0x1, "gpio_out"),
314 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
315 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
316 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
317 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
318 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
321 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
326 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
327 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
328 SUNXI_FUNCTION(0x0, "gpio_in"),
329 SUNXI_FUNCTION(0x1, "gpio_out"),
330 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
331 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out"),
335 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
336 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
341 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
346 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
351 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
356 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
361 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
362 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
364 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out"),
366 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
375 /* Hole */
376 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
377 SUNXI_FUNCTION(0x0, "gpio_in"),
378 SUNXI_FUNCTION(0x1, "gpio_out"),
379 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
380 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
381 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
382 SUNXI_FUNCTION(0x0, "gpio_in"),
383 SUNXI_FUNCTION(0x1, "gpio_out"),
384 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
385 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
386 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
387 SUNXI_FUNCTION(0x0, "gpio_in"),
388 SUNXI_FUNCTION(0x1, "gpio_out"),
389 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
390 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
391 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out"),
394 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
395 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
396 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
397 SUNXI_FUNCTION(0x0, "gpio_in"),
398 SUNXI_FUNCTION(0x1, "gpio_out"),
399 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
400 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
401 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
402 SUNXI_FUNCTION(0x0, "gpio_in"),
403 SUNXI_FUNCTION(0x1, "gpio_out"),
404 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
405 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
406 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
407 SUNXI_FUNCTION(0x0, "gpio_in"),
408 SUNXI_FUNCTION(0x1, "gpio_out"),
409 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
410 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
411 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
412 SUNXI_FUNCTION(0x0, "gpio_in"),
413 SUNXI_FUNCTION(0x1, "gpio_out"),
414 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
415 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
416 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
417 SUNXI_FUNCTION(0x0, "gpio_in"),
418 SUNXI_FUNCTION(0x1, "gpio_out"),
419 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
420 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
421 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
422 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out"),
424 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
425 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
426 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
427 SUNXI_FUNCTION(0x0, "gpio_in"),
428 SUNXI_FUNCTION(0x1, "gpio_out"),
429 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
430 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
431 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
432 SUNXI_FUNCTION(0x0, "gpio_in"),
433 SUNXI_FUNCTION(0x1, "gpio_out"),
434 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
435 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
436 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
437 SUNXI_FUNCTION(0x0, "gpio_in"),
438 SUNXI_FUNCTION(0x1, "gpio_out"),
439 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
440 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
441 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
442 SUNXI_FUNCTION(0x0, "gpio_in"),
443 SUNXI_FUNCTION(0x1, "gpio_out"),
444 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
445 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
446 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
447 SUNXI_FUNCTION(0x0, "gpio_in"),
448 SUNXI_FUNCTION(0x1, "gpio_out"),
449 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
450 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
451 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
452 SUNXI_FUNCTION(0x0, "gpio_in"),
453 SUNXI_FUNCTION(0x1, "gpio_out"),
454 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
455 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
456 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
457 SUNXI_FUNCTION(0x0, "gpio_in"),
458 SUNXI_FUNCTION(0x1, "gpio_out"),
459 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
460 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
461 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
462 SUNXI_FUNCTION(0x0, "gpio_in"),
463 SUNXI_FUNCTION(0x1, "gpio_out"),
464 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
465 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
466 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
467 SUNXI_FUNCTION(0x0, "gpio_in"),
468 SUNXI_FUNCTION(0x1, "gpio_out"),
469 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
470 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
471 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
472 SUNXI_FUNCTION(0x0, "gpio_in"),
473 SUNXI_FUNCTION(0x1, "gpio_out"),
474 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
475 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
476 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
477 SUNXI_FUNCTION(0x0, "gpio_in"),
478 SUNXI_FUNCTION(0x1, "gpio_out"),
479 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
484 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
485 SUNXI_FUNCTION(0x0, "gpio_in"),
486 SUNXI_FUNCTION(0x1, "gpio_out"),
487 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out"),
491 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
492 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
493 SUNXI_FUNCTION(0x0, "gpio_in"),
494 SUNXI_FUNCTION(0x1, "gpio_out"),
495 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
496 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
497 SUNXI_FUNCTION(0x0, "gpio_in"),
498 SUNXI_FUNCTION(0x1, "gpio_out"),
499 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
504 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
505 SUNXI_FUNCTION(0x0, "gpio_in"),
506 SUNXI_FUNCTION(0x1, "gpio_out"),
507 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
508 /* Hole */
509 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
510 SUNXI_FUNCTION(0x0, "gpio_in"),
511 SUNXI_FUNCTION(0x1, "gpio_out"),
512 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
513 SUNXI_FUNCTION(0x3, "ts")), /* CLK */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
515 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
518 SUNXI_FUNCTION(0x3, "ts")), /* ERR */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
520 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
523 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
528 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
533 SUNXI_FUNCTION(0x3, "uart5")), /* TX */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
538 SUNXI_FUNCTION(0x3, "uart5")), /* RX */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
543 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */
544 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
545 SUNXI_FUNCTION(0x0, "gpio_in"),
546 SUNXI_FUNCTION(0x1, "gpio_out"),
547 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
548 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */
549 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
550 SUNXI_FUNCTION(0x0, "gpio_in"),
551 SUNXI_FUNCTION(0x1, "gpio_out"),
552 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
553 SUNXI_FUNCTION(0x3, "ts")), /* D0 */
554 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
555 SUNXI_FUNCTION(0x0, "gpio_in"),
556 SUNXI_FUNCTION(0x1, "gpio_out"),
557 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
558 SUNXI_FUNCTION(0x3, "ts")), /* D1 */
559 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
560 SUNXI_FUNCTION(0x0, "gpio_in"),
561 SUNXI_FUNCTION(0x1, "gpio_out"),
562 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
563 SUNXI_FUNCTION(0x3, "ts")), /* D2 */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
565 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
568 SUNXI_FUNCTION(0x3, "ts")), /* D3 */
569 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
570 SUNXI_FUNCTION(0x0, "gpio_in"),
571 SUNXI_FUNCTION(0x1, "gpio_out"),
572 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
573 SUNXI_FUNCTION(0x3, "ts")), /* D4 */
574 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
575 SUNXI_FUNCTION(0x0, "gpio_in"),
576 SUNXI_FUNCTION(0x1, "gpio_out"),
577 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
578 SUNXI_FUNCTION(0x3, "ts")), /* D5 */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
580 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x1, "gpio_out"),
582 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
583 SUNXI_FUNCTION(0x3, "ts")), /* D6 */
584 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
585 SUNXI_FUNCTION(0x0, "gpio_in"),
586 SUNXI_FUNCTION(0x1, "gpio_out"),
587 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
588 SUNXI_FUNCTION(0x3, "ts")), /* D7 */
589 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
590 SUNXI_FUNCTION(0x0, "gpio_in"),
591 SUNXI_FUNCTION(0x1, "gpio_out"),
592 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */
593 /* Hole */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
595 SUNXI_FUNCTION(0x0, "gpio_in"),
596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
598 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
599 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
600 SUNXI_FUNCTION(0x0, "gpio_in"),
601 SUNXI_FUNCTION(0x1, "gpio_out"),
602 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
603 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
604 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
605 SUNXI_FUNCTION(0x0, "gpio_in"),
606 SUNXI_FUNCTION(0x1, "gpio_out"),
607 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
608 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
609 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out"),
612 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
613 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
618 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
619 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
620 SUNXI_FUNCTION(0x0, "gpio_in"),
621 SUNXI_FUNCTION(0x1, "gpio_out"),
622 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
623 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
624 /* Hole */
625 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
626 SUNXI_FUNCTION(0x0, "gpio_in"),
627 SUNXI_FUNCTION(0x1, "gpio_out"),
628 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */
629 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
630 SUNXI_FUNCTION(0x0, "gpio_in"),
631 SUNXI_FUNCTION(0x1, "gpio_out"),
632 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */
633 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
634 SUNXI_FUNCTION(0x0, "gpio_in"),
635 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */
637 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
638 SUNXI_FUNCTION(0x0, "gpio_in"),
639 SUNXI_FUNCTION(0x1, "gpio_out"),
640 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */
641 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
642 SUNXI_FUNCTION(0x0, "gpio_in"),
643 SUNXI_FUNCTION(0x1, "gpio_out"),
644 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */
645 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
646 SUNXI_FUNCTION(0x0, "gpio_in"),
647 SUNXI_FUNCTION(0x1, "gpio_out"),
648 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "uart2")), /* TX */
653 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
654 SUNXI_FUNCTION(0x0, "gpio_in"),
655 SUNXI_FUNCTION(0x1, "gpio_out"),
656 SUNXI_FUNCTION(0x2, "uart2")), /* RX */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
658 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */
661 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
662 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
666 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
669 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */
670 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
671 SUNXI_FUNCTION(0x0, "gpio_in"),
672 SUNXI_FUNCTION(0x1, "gpio_out"),
673 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
674 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */
675 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
676 SUNXI_FUNCTION(0x0, "gpio_in"),
677 SUNXI_FUNCTION(0x1, "gpio_out"),
678 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
679 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */
680 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
681 SUNXI_FUNCTION(0x0, "gpio_in"),
682 SUNXI_FUNCTION(0x1, "gpio_out"),
683 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
684 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */
685 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
686 SUNXI_FUNCTION(0x0, "gpio_in"),
687 SUNXI_FUNCTION(0x1, "gpio_out"),
688 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
689 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */
690 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
691 SUNXI_FUNCTION(0x0, "gpio_in"),
692 SUNXI_FUNCTION(0x1, "gpio_out"),
693 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
694 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
695 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
696 SUNXI_FUNCTION(0x0, "gpio_in"),
697 SUNXI_FUNCTION(0x1, "gpio_out"),
698 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
699 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
700 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
701 SUNXI_FUNCTION(0x0, "gpio_in"),
702 SUNXI_FUNCTION(0x1, "gpio_out"),
703 SUNXI_FUNCTION(0x2, "uart4")), /* TX */
704 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
705 SUNXI_FUNCTION(0x0, "gpio_in"),
706 SUNXI_FUNCTION(0x1, "gpio_out"),
707 SUNXI_FUNCTION(0x2, "uart4")), /* RX */
708 /* Hole */
709 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
710 SUNXI_FUNCTION(0x0, "gpio_in"),
711 SUNXI_FUNCTION(0x1, "gpio_out"),
712 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
713 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
714 SUNXI_FUNCTION(0x0, "gpio_in"),
715 SUNXI_FUNCTION(0x1, "gpio_out"),
716 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
717 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
718 SUNXI_FUNCTION(0x0, "gpio_in"),
719 SUNXI_FUNCTION(0x1, "gpio_out"),
720 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
721 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
722 SUNXI_FUNCTION(0x0, "gpio_in"),
723 SUNXI_FUNCTION(0x1, "gpio_out"),
724 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
725 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
726 SUNXI_FUNCTION(0x0, "gpio_in"),
727 SUNXI_FUNCTION(0x1, "gpio_out"),
728 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
729 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
730 SUNXI_FUNCTION(0x0, "gpio_in"),
731 SUNXI_FUNCTION(0x1, "gpio_out"),
732 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
733 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
734 SUNXI_FUNCTION(0x0, "gpio_in"),
735 SUNXI_FUNCTION(0x1, "gpio_out"),
736 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
737 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
738 SUNXI_FUNCTION(0x0, "gpio_in"),
739 SUNXI_FUNCTION(0x1, "gpio_out"),
740 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
741 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out"),
744 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
745 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
746 SUNXI_FUNCTION(0x0, "gpio_in"),
747 SUNXI_FUNCTION(0x1, "gpio_out"),
748 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
749 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
750 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
751 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
752 SUNXI_FUNCTION(0x0, "gpio_in"),
753 SUNXI_FUNCTION(0x1, "gpio_out"),
754 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
755 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
756 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
757 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
758 SUNXI_FUNCTION(0x0, "gpio_in"),
759 SUNXI_FUNCTION(0x1, "gpio_out"),
760 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
761 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
762 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
763 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
764 SUNXI_FUNCTION(0x0, "gpio_in"),
765 SUNXI_FUNCTION(0x1, "gpio_out"),
766 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
767 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
768 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
769 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
770 SUNXI_FUNCTION(0x0, "gpio_in"),
771 SUNXI_FUNCTION(0x1, "gpio_out"),
772 SUNXI_FUNCTION(0x2, "pwm0")),
773 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
774 SUNXI_FUNCTION(0x0, "gpio_in"),
775 SUNXI_FUNCTION(0x1, "gpio_out"),
776 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
777 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
778 SUNXI_FUNCTION(0x0, "gpio_in"),
779 SUNXI_FUNCTION(0x1, "gpio_out"),
780 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
781 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
782 SUNXI_FUNCTION(0x0, "gpio_in"),
783 SUNXI_FUNCTION(0x1, "gpio_out"),
784 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
785 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
786 SUNXI_FUNCTION(0x0, "gpio_in"),
787 SUNXI_FUNCTION(0x1, "gpio_out"),
788 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
789 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
790 SUNXI_FUNCTION(0x0, "gpio_in"),
791 SUNXI_FUNCTION(0x1, "gpio_out"),
792 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
793 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
794 SUNXI_FUNCTION(0x0, "gpio_in"),
795 SUNXI_FUNCTION(0x1, "gpio_out"),
796 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
797 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
798 SUNXI_FUNCTION(0x0, "gpio_in"),
799 SUNXI_FUNCTION(0x1, "gpio_out"),
800 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
801 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
802 SUNXI_FUNCTION(0x0, "gpio_in"),
803 SUNXI_FUNCTION(0x1, "gpio_out"),
804 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
805 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
806 SUNXI_FUNCTION(0x0, "gpio_in"),
807 SUNXI_FUNCTION(0x1, "gpio_out")),
808 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
809 SUNXI_FUNCTION(0x0, "gpio_in"),
810 SUNXI_FUNCTION(0x1, "gpio_out")),
811 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out")),
814 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
815 SUNXI_FUNCTION(0x0, "gpio_in"),
816 SUNXI_FUNCTION(0x1, "gpio_out")),
817 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
818 SUNXI_FUNCTION(0x0, "gpio_in"),
819 SUNXI_FUNCTION(0x1, "gpio_out")),
820 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
821 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out")),
823 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
824 SUNXI_FUNCTION(0x0, "gpio_in"),
825 SUNXI_FUNCTION(0x1, "gpio_out")),
826 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 29),
827 SUNXI_FUNCTION(0x0, "gpio_in"),
828 SUNXI_FUNCTION(0x1, "gpio_out"),
829 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
830 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 30),
831 SUNXI_FUNCTION(0x0, "gpio_in"),
832 SUNXI_FUNCTION(0x1, "gpio_out"),
833 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
834};
835
836static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
837 .pins = sun6i_a31_pins,
838 .npins = ARRAY_SIZE(sun6i_a31_pins),
839};
840
841static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
842{
843 return sunxi_pinctrl_init(pdev,
844 &sun6i_a31_pinctrl_data);
845}
846
847static struct of_device_id sun6i_a31_pinctrl_match[] = {
848 { .compatible = "allwinner,sun6i-a31-pinctrl", },
849 {}
850};
851MODULE_DEVICE_TABLE(of, sun6i_a31_pinctrl_match);
852
853static struct platform_driver sun6i_a31_pinctrl_driver = {
854 .probe = sun6i_a31_pinctrl_probe,
855 .driver = {
856 .name = "sun6i-a31-pinctrl",
857 .owner = THIS_MODULE,
858 .of_match_table = sun6i_a31_pinctrl_match,
859 },
860};
861module_platform_driver(sun6i_a31_pinctrl_driver);
862
863MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
864MODULE_DESCRIPTION("Allwinner A31 pinctrl driver");
865MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
new file mode 100644
index 000000000000..d8577ce5f1a4
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -0,0 +1,1065 @@
1/*
2 * Allwinner A20 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun7i_a20_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
26 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
27 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
28 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
30 SUNXI_FUNCTION(0x0, "gpio_in"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
32 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
33 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
34 SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
35 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
36 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
37 SUNXI_FUNCTION(0x0, "gpio_in"),
38 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
40 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
41 SUNXI_FUNCTION(0x4, "uart2"), /* TX */
42 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
47 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
48 SUNXI_FUNCTION(0x4, "uart2"), /* RX */
49 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
54 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
55 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
56 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
57 SUNXI_FUNCTION(0x0, "gpio_in"),
58 SUNXI_FUNCTION(0x1, "gpio_out"),
59 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
60 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
61 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */
62 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
63 SUNXI_FUNCTION(0x0, "gpio_in"),
64 SUNXI_FUNCTION(0x1, "gpio_out"),
65 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
66 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
67 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
72 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
73 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */
74 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
75 SUNXI_FUNCTION(0x0, "gpio_in"),
76 SUNXI_FUNCTION(0x1, "gpio_out"),
77 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
78 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
79 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
84 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
85 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */
86 SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */
87 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
88 SUNXI_FUNCTION(0x0, "gpio_in"),
89 SUNXI_FUNCTION(0x1, "gpio_out"),
90 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
91 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
92 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */
93 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
94 SUNXI_FUNCTION(0x0, "gpio_in"),
95 SUNXI_FUNCTION(0x1, "gpio_out"),
96 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
97 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
98 SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */
99 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
100 SUNXI_FUNCTION(0x0, "gpio_in"),
101 SUNXI_FUNCTION(0x1, "gpio_out"),
102 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
103 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
104 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
105 SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
107 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out"),
109 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
110 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
111 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
112 SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
117 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
118 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
119 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */
120 SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */
121 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
122 SUNXI_FUNCTION(0x0, "gpio_in"),
123 SUNXI_FUNCTION(0x1, "gpio_out"),
124 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
125 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
126 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
127 SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */
128 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
129 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
130 SUNXI_FUNCTION(0x0, "gpio_in"),
131 SUNXI_FUNCTION(0x1, "gpio_out"),
132 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
133 SUNXI_FUNCTION(0x3, "can"), /* TX */
134 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
135 SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */
136 SUNXI_FUNCTION(0x6, "i2s1")), /* DO */
137 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
138 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
141 SUNXI_FUNCTION(0x3, "can"), /* RX */
142 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
143 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */
144 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
145 /* Hole */
146 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
147 SUNXI_FUNCTION(0x0, "gpio_in"),
148 SUNXI_FUNCTION(0x1, "gpio_out"),
149 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out"),
157 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
158 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
159 SUNXI_FUNCTION(0x0, "gpio_in"),
160 SUNXI_FUNCTION(0x1, "gpio_out"),
161 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
162 SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
171 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
176 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
181 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
182 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
183 SUNXI_FUNCTION(0x0, "gpio_in"),
184 SUNXI_FUNCTION(0x1, "gpio_out"),
185 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
186 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
187 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
188 SUNXI_FUNCTION(0x0, "gpio_in"),
189 SUNXI_FUNCTION(0x1, "gpio_out"),
190 SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
203 SUNXI_FUNCTION(0x3, "ac97"), /* DI */
204 SUNXI_FUNCTION(0x4, "spdif")), /* DI */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
209 SUNXI_FUNCTION(0x4, "spdif")), /* DO */
210 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
211 SUNXI_FUNCTION(0x0, "gpio_in"),
212 SUNXI_FUNCTION(0x1, "gpio_out"),
213 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
214 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
215 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
216 SUNXI_FUNCTION(0x0, "gpio_in"),
217 SUNXI_FUNCTION(0x1, "gpio_out"),
218 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
219 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
220 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
221 SUNXI_FUNCTION(0x0, "gpio_in"),
222 SUNXI_FUNCTION(0x1, "gpio_out"),
223 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
224 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
229 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
231 SUNXI_FUNCTION(0x0, "gpio_in"),
232 SUNXI_FUNCTION(0x1, "gpio_out"),
233 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
234 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
242 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
246 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
247 SUNXI_FUNCTION(0x0, "gpio_in"),
248 SUNXI_FUNCTION(0x1, "gpio_out"),
249 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
250 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
255 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
256 /* Hole */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
261 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
266 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
267 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
268 SUNXI_FUNCTION(0x0, "gpio_in"),
269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
271 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
276 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
277 SUNXI_FUNCTION(0x0, "gpio_in"),
278 SUNXI_FUNCTION(0x1, "gpio_out"),
279 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
284 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
285 SUNXI_FUNCTION(0x0, "gpio_in"),
286 SUNXI_FUNCTION(0x1, "gpio_out"),
287 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
288 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
293 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
294 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
295 SUNXI_FUNCTION(0x0, "gpio_in"),
296 SUNXI_FUNCTION(0x1, "gpio_out"),
297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
298 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
299 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
300 SUNXI_FUNCTION(0x0, "gpio_in"),
301 SUNXI_FUNCTION(0x1, "gpio_out"),
302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
303 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
304 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
305 SUNXI_FUNCTION(0x0, "gpio_in"),
306 SUNXI_FUNCTION(0x1, "gpio_out"),
307 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
308 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
313 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
314 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
315 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out"),
317 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
330 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
331 SUNXI_FUNCTION(0x0, "gpio_in"),
332 SUNXI_FUNCTION(0x1, "gpio_out"),
333 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
334 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
335 SUNXI_FUNCTION(0x0, "gpio_in"),
336 SUNXI_FUNCTION(0x1, "gpio_out"),
337 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
338 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
339 SUNXI_FUNCTION(0x0, "gpio_in"),
340 SUNXI_FUNCTION(0x1, "gpio_out"),
341 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
346 SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
347 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
348 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
349 SUNXI_FUNCTION(0x0, "gpio_in"),
350 SUNXI_FUNCTION(0x1, "gpio_out"),
351 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
352 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
353 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
354 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
355 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out"),
357 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
358 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
359 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out"),
363 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
364 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
365 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
366 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
367 SUNXI_FUNCTION(0x0, "gpio_in"),
368 SUNXI_FUNCTION(0x1, "gpio_out"),
369 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
370 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
371 SUNXI_FUNCTION(0x0, "gpio_in"),
372 SUNXI_FUNCTION(0x1, "gpio_out"),
373 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
374 /* Hole */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
379 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
380 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
381 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"),
383 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
384 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
385 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
386 SUNXI_FUNCTION(0x0, "gpio_in"),
387 SUNXI_FUNCTION(0x1, "gpio_out"),
388 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
389 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
390 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
391 SUNXI_FUNCTION(0x0, "gpio_in"),
392 SUNXI_FUNCTION(0x1, "gpio_out"),
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
394 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
395 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
396 SUNXI_FUNCTION(0x0, "gpio_in"),
397 SUNXI_FUNCTION(0x1, "gpio_out"),
398 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
399 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
400 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
401 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out"),
403 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
404 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
405 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
406 SUNXI_FUNCTION(0x0, "gpio_in"),
407 SUNXI_FUNCTION(0x1, "gpio_out"),
408 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
409 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
410 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out"),
413 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
414 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
415 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
416 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out"),
418 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
419 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
420 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
421 SUNXI_FUNCTION(0x0, "gpio_in"),
422 SUNXI_FUNCTION(0x1, "gpio_out"),
423 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
424 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out"),
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
429 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
430 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
434 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
435 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
439 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
444 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
449 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
454 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
459 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
464 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
469 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
474 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
475 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
479 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
484 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out"),
488 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
489 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
494 SUNXI_FUNCTION(0x3, "sim")), /* DET */
495 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
496 SUNXI_FUNCTION(0x0, "gpio_in"),
497 SUNXI_FUNCTION(0x1, "gpio_out"),
498 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
499 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
504 SUNXI_FUNCTION(0x3, "sim")), /* RST */
505 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
509 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
510 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
511 SUNXI_FUNCTION(0x0, "gpio_in"),
512 SUNXI_FUNCTION(0x1, "gpio_out"),
513 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
514 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
515 /* Hole */
516 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out"),
519 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
520 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
521 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
522 SUNXI_FUNCTION(0x0, "gpio_in"),
523 SUNXI_FUNCTION(0x1, "gpio_out"),
524 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
525 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
526 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
527 SUNXI_FUNCTION(0x0, "gpio_in"),
528 SUNXI_FUNCTION(0x1, "gpio_out"),
529 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
530 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
531 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
532 SUNXI_FUNCTION(0x0, "gpio_in"),
533 SUNXI_FUNCTION(0x1, "gpio_out"),
534 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
535 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
536 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
537 SUNXI_FUNCTION(0x0, "gpio_in"),
538 SUNXI_FUNCTION(0x1, "gpio_out"),
539 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
540 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
541 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
542 SUNXI_FUNCTION(0x0, "gpio_in"),
543 SUNXI_FUNCTION(0x1, "gpio_out"),
544 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
545 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
546 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
547 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
548 SUNXI_FUNCTION(0x0, "gpio_in"),
549 SUNXI_FUNCTION(0x1, "gpio_out"),
550 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
551 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
552 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
553 SUNXI_FUNCTION(0x0, "gpio_in"),
554 SUNXI_FUNCTION(0x1, "gpio_out"),
555 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
556 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
557 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
558 SUNXI_FUNCTION(0x0, "gpio_in"),
559 SUNXI_FUNCTION(0x1, "gpio_out"),
560 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
561 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
562 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
563 SUNXI_FUNCTION(0x0, "gpio_in"),
564 SUNXI_FUNCTION(0x1, "gpio_out"),
565 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
566 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
567 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
568 SUNXI_FUNCTION(0x0, "gpio_in"),
569 SUNXI_FUNCTION(0x1, "gpio_out"),
570 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
571 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
572 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
573 SUNXI_FUNCTION(0x0, "gpio_in"),
574 SUNXI_FUNCTION(0x1, "gpio_out"),
575 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
576 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
577 /* Hole */
578 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
579 SUNXI_FUNCTION(0x0, "gpio_in"),
580 SUNXI_FUNCTION(0x1, "gpio_out"),
581 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
582 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
583 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
584 SUNXI_FUNCTION(0x0, "gpio_in"),
585 SUNXI_FUNCTION(0x1, "gpio_out"),
586 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
587 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
588 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
589 SUNXI_FUNCTION(0x0, "gpio_in"),
590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
592 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
593 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
594 SUNXI_FUNCTION(0x0, "gpio_in"),
595 SUNXI_FUNCTION(0x1, "gpio_out"),
596 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
597 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
598 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
599 SUNXI_FUNCTION(0x0, "gpio_in"),
600 SUNXI_FUNCTION(0x1, "gpio_out"),
601 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
602 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
607 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
608 /* Hole */
609 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out"),
612 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
613 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
614 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
615 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
616 SUNXI_FUNCTION(0x0, "gpio_in"),
617 SUNXI_FUNCTION(0x1, "gpio_out"),
618 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
619 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
620 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
621 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
625 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
626 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
627 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
628 SUNXI_FUNCTION(0x0, "gpio_in"),
629 SUNXI_FUNCTION(0x1, "gpio_out"),
630 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
631 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
632 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
633 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
634 SUNXI_FUNCTION(0x0, "gpio_in"),
635 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
637 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
638 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
639 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
640 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
641 SUNXI_FUNCTION(0x0, "gpio_in"),
642 SUNXI_FUNCTION(0x1, "gpio_out"),
643 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
644 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
645 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
646 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
647 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
648 SUNXI_FUNCTION(0x0, "gpio_in"),
649 SUNXI_FUNCTION(0x1, "gpio_out"),
650 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
651 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
652 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
653 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
654 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
655 SUNXI_FUNCTION(0x0, "gpio_in"),
656 SUNXI_FUNCTION(0x1, "gpio_out"),
657 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
658 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
659 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
660 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
661 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
662 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
665 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
666 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
667 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
668 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
669 SUNXI_FUNCTION(0x0, "gpio_in"),
670 SUNXI_FUNCTION(0x1, "gpio_out"),
671 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
672 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
673 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
674 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
675 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
676 SUNXI_FUNCTION(0x0, "gpio_in"),
677 SUNXI_FUNCTION(0x1, "gpio_out"),
678 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
679 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
680 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
681 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
682 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
683 SUNXI_FUNCTION(0x0, "gpio_in"),
684 SUNXI_FUNCTION(0x1, "gpio_out"),
685 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
686 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
687 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
688 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
689 /* Hole */
690 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
691 SUNXI_FUNCTION(0x0, "gpio_in"),
692 SUNXI_FUNCTION(0x1, "gpio_out"),
693 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
694 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
695 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
701 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
702 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
703 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
704 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
705 SUNXI_FUNCTION(0x0, "gpio_in"),
706 SUNXI_FUNCTION(0x1, "gpio_out"),
707 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
708 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
709 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
710 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
711 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
712 SUNXI_FUNCTION(0x0, "gpio_in"),
713 SUNXI_FUNCTION(0x1, "gpio_out"),
714 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
715 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
716 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
717 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
718 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
719 SUNXI_FUNCTION(0x0, "gpio_in"),
720 SUNXI_FUNCTION(0x1, "gpio_out"),
721 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
722 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
723 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
724 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
725 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
726 SUNXI_FUNCTION(0x0, "gpio_in"),
727 SUNXI_FUNCTION(0x1, "gpio_out"),
728 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
729 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
730 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
731 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
732 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
736 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
737 SUNXI_FUNCTION(0x5, "ms"), /* BS */
738 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
739 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
740 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
741 SUNXI_FUNCTION(0x0, "gpio_in"),
742 SUNXI_FUNCTION(0x1, "gpio_out"),
743 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
744 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
745 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
746 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
747 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
748 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
749 SUNXI_FUNCTION(0x0, "gpio_in"),
750 SUNXI_FUNCTION(0x1, "gpio_out"),
751 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
752 SUNXI_FUNCTION(0x3, "emac"), /* ERXD3 */
753 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
754 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
755 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
756 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
757 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
758 SUNXI_FUNCTION(0x0, "gpio_in"),
759 SUNXI_FUNCTION(0x1, "gpio_out"),
760 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
761 SUNXI_FUNCTION(0x3, "emac"), /* ERXD2 */
762 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
763 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
764 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
765 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
766 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
767 SUNXI_FUNCTION(0x0, "gpio_in"),
768 SUNXI_FUNCTION(0x1, "gpio_out"),
769 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
770 SUNXI_FUNCTION(0x3, "emac"), /* ERXD1 */
771 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
772 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
773 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
774 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
775 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
776 SUNXI_FUNCTION(0x0, "gpio_in"),
777 SUNXI_FUNCTION(0x1, "gpio_out"),
778 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
779 SUNXI_FUNCTION(0x3, "emac"), /* ERXD0 */
780 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
781 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
782 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
783 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
784 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
785 SUNXI_FUNCTION(0x0, "gpio_in"),
786 SUNXI_FUNCTION(0x1, "gpio_out"),
787 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
788 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
789 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
790 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
791 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
792 SUNXI_FUNCTION(0x0, "gpio_in"),
793 SUNXI_FUNCTION(0x1, "gpio_out"),
794 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
795 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
796 SUNXI_FUNCTION(0x5, "sim"), /* RST */
797 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
798 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
799 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
800 SUNXI_FUNCTION(0x0, "gpio_in"),
801 SUNXI_FUNCTION(0x1, "gpio_out"),
802 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
803 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
804 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
805 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
806 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
807 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
808 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
809 SUNXI_FUNCTION(0x0, "gpio_in"),
810 SUNXI_FUNCTION(0x1, "gpio_out"),
811 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
812 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
813 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
814 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
815 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
816 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
817 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
818 SUNXI_FUNCTION(0x0, "gpio_in"),
819 SUNXI_FUNCTION(0x1, "gpio_out"),
820 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
821 SUNXI_FUNCTION(0x3, "emac"), /* ETXD2 */
822 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
823 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
824 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
825 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
826 SUNXI_FUNCTION(0x0, "gpio_in"),
827 SUNXI_FUNCTION(0x1, "gpio_out"),
828 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
829 SUNXI_FUNCTION(0x3, "emac"), /* ETXD1 */
830 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
831 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
832 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
833 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
834 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
835 SUNXI_FUNCTION(0x0, "gpio_in"),
836 SUNXI_FUNCTION(0x1, "gpio_out"),
837 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
838 SUNXI_FUNCTION(0x3, "emac"), /* ETXD0 */
839 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
840 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
841 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
842 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
843 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
844 SUNXI_FUNCTION(0x0, "gpio_in"),
845 SUNXI_FUNCTION(0x1, "gpio_out"),
846 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
847 SUNXI_FUNCTION(0x3, "emac"), /* ERXERR */
848 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
849 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
850 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
851 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
852 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
853 SUNXI_FUNCTION(0x0, "gpio_in"),
854 SUNXI_FUNCTION(0x1, "gpio_out"),
855 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
856 SUNXI_FUNCTION(0x3, "emac"), /* ERXDV */
857 SUNXI_FUNCTION(0x4, "can"), /* TX */
858 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
859 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
860 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
861 SUNXI_FUNCTION(0x0, "gpio_in"),
862 SUNXI_FUNCTION(0x1, "gpio_out"),
863 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
864 SUNXI_FUNCTION(0x3, "emac"), /* EMDC */
865 SUNXI_FUNCTION(0x4, "can"), /* RX */
866 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
867 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
868 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
869 SUNXI_FUNCTION(0x0, "gpio_in"),
870 SUNXI_FUNCTION(0x1, "gpio_out"),
871 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
872 SUNXI_FUNCTION(0x3, "emac"), /* EMDIO */
873 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
874 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
875 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
876 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
877 SUNXI_FUNCTION(0x0, "gpio_in"),
878 SUNXI_FUNCTION(0x1, "gpio_out"),
879 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
880 SUNXI_FUNCTION(0x3, "emac"), /* ETXEN */
881 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
882 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
883 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
884 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
885 SUNXI_FUNCTION(0x0, "gpio_in"),
886 SUNXI_FUNCTION(0x1, "gpio_out"),
887 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
888 SUNXI_FUNCTION(0x3, "emac"), /* ETXCK */
889 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
890 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
891 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
892 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
893 SUNXI_FUNCTION(0x0, "gpio_in"),
894 SUNXI_FUNCTION(0x1, "gpio_out"),
895 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
896 SUNXI_FUNCTION(0x3, "emac"), /* ECRS */
897 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
898 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
899 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
900 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out"),
903 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
904 SUNXI_FUNCTION(0x3, "emac"), /* ECOL */
905 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
906 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
907 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
908 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
909 SUNXI_FUNCTION(0x0, "gpio_in"),
910 SUNXI_FUNCTION(0x1, "gpio_out"),
911 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
912 SUNXI_FUNCTION(0x3, "emac"), /* ETXERR */
913 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
914 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
915 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
916 /* Hole */
917 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
918 SUNXI_FUNCTION(0x0, "gpio_in"),
919 SUNXI_FUNCTION(0x1, "gpio_out"),
920 SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */
921 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
922 SUNXI_FUNCTION(0x0, "gpio_in"),
923 SUNXI_FUNCTION(0x1, "gpio_out"),
924 SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */
925 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
926 SUNXI_FUNCTION(0x0, "gpio_in"),
927 SUNXI_FUNCTION(0x1, "gpio_out"),
928 SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */
929 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
930 SUNXI_FUNCTION(0x0, "gpio_in"),
931 SUNXI_FUNCTION(0x1, "gpio_out"),
932 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
933 SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */
934 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
935 SUNXI_FUNCTION(0x0, "gpio_in"),
936 SUNXI_FUNCTION(0x1, "gpio_out"),
937 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
938 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
939 SUNXI_FUNCTION(0x0, "gpio_in"),
940 SUNXI_FUNCTION(0x1, "gpio_out"),
941 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
942 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
943 SUNXI_FUNCTION(0x0, "gpio_in"),
944 SUNXI_FUNCTION(0x1, "gpio_out"),
945 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
946 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
947 SUNXI_FUNCTION(0x0, "gpio_in"),
948 SUNXI_FUNCTION(0x1, "gpio_out"),
949 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
950 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
951 SUNXI_FUNCTION(0x0, "gpio_in"),
952 SUNXI_FUNCTION(0x1, "gpio_out"),
953 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
954 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
955 SUNXI_FUNCTION(0x0, "gpio_in"),
956 SUNXI_FUNCTION(0x1, "gpio_out"),
957 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
958 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
959 SUNXI_FUNCTION(0x0, "gpio_in"),
960 SUNXI_FUNCTION(0x1, "gpio_out"),
961 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
962 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
963 SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
964 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
965 SUNXI_FUNCTION(0x0, "gpio_in"),
966 SUNXI_FUNCTION(0x1, "gpio_out"),
967 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
968 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
969 SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
970 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
971 SUNXI_FUNCTION(0x0, "gpio_in"),
972 SUNXI_FUNCTION(0x1, "gpio_out"),
973 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
974 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
975 SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
976 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
977 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
978 SUNXI_FUNCTION(0x0, "gpio_in"),
979 SUNXI_FUNCTION(0x1, "gpio_out"),
980 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
981 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
982 SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
983 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
984 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
985 SUNXI_FUNCTION(0x0, "gpio_in"),
986 SUNXI_FUNCTION(0x1, "gpio_out"),
987 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
988 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
989 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
990 SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
991 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
992 SUNXI_FUNCTION(0x0, "gpio_in"),
993 SUNXI_FUNCTION(0x1, "gpio_out"),
994 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
995 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
996 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
997 SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
998 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
999 SUNXI_FUNCTION(0x0, "gpio_in"),
1000 SUNXI_FUNCTION(0x1, "gpio_out"),
1001 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1002 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
1003 SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
1004 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
1005 SUNXI_FUNCTION(0x0, "gpio_in"),
1006 SUNXI_FUNCTION(0x1, "gpio_out"),
1007 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1008 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
1009 SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
1010 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
1011 SUNXI_FUNCTION(0x0, "gpio_in"),
1012 SUNXI_FUNCTION(0x1, "gpio_out"),
1013 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1014 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
1015 SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
1016 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
1017 SUNXI_FUNCTION(0x0, "gpio_in"),
1018 SUNXI_FUNCTION(0x1, "gpio_out"),
1019 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1020 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1021 SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
1022 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
1023 SUNXI_FUNCTION(0x0, "gpio_in"),
1024 SUNXI_FUNCTION(0x1, "gpio_out"),
1025 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
1026 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
1027 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
1028 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
1029 SUNXI_FUNCTION(0x0, "gpio_in"),
1030 SUNXI_FUNCTION(0x1, "gpio_out"),
1031 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1032 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1033 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1034};
1035
1036static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
1037 .pins = sun7i_a20_pins,
1038 .npins = ARRAY_SIZE(sun7i_a20_pins),
1039};
1040
1041static int sun7i_a20_pinctrl_probe(struct platform_device *pdev)
1042{
1043 return sunxi_pinctrl_init(pdev,
1044 &sun7i_a20_pinctrl_data);
1045}
1046
1047static struct of_device_id sun7i_a20_pinctrl_match[] = {
1048 { .compatible = "allwinner,sun7i-a20-pinctrl", },
1049 {}
1050};
1051MODULE_DEVICE_TABLE(of, sun7i_a20_pinctrl_match);
1052
1053static struct platform_driver sun7i_a20_pinctrl_driver = {
1054 .probe = sun7i_a20_pinctrl_probe,
1055 .driver = {
1056 .name = "sun7i-a20-pinctrl",
1057 .owner = THIS_MODULE,
1058 .of_match_table = sun7i_a20_pinctrl_match,
1059 },
1060};
1061module_platform_driver(sun7i_a20_pinctrl_driver);
1062
1063MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
1064MODULE_DESCRIPTION("Allwinner A20 pinctrl driver");
1065MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index f9fabe9bf47d..f1ca75e6d7b1 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -28,9 +28,8 @@
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30 30
31#include "core.h" 31#include "../core.h"
32#include "pinctrl-sunxi.h" 32#include "pinctrl-sunxi.h"
33#include "pinctrl-sunxi-pins.h"
34 33
35static struct sunxi_pinctrl_group * 34static struct sunxi_pinctrl_group *
36sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 35sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
@@ -281,6 +280,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
281 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 280 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
282 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 281 struct sunxi_pinctrl_group *g = &pctl->groups[group];
283 unsigned long flags; 282 unsigned long flags;
283 unsigned pin = g->pin - pctl->desc->pin_base;
284 u32 val, mask; 284 u32 val, mask;
285 u16 strength; 285 u16 strength;
286 u8 dlevel; 286 u8 dlevel;
@@ -304,23 +304,23 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
304 * 3: 40mA 304 * 3: 40mA
305 */ 305 */
306 dlevel = strength / 10 - 1; 306 dlevel = strength / 10 - 1;
307 val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); 307 val = readl(pctl->membase + sunxi_dlevel_reg(pin));
308 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); 308 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
309 writel((val & ~mask) 309 writel((val & ~mask)
310 | dlevel << sunxi_dlevel_offset(g->pin), 310 | dlevel << sunxi_dlevel_offset(pin),
311 pctl->membase + sunxi_dlevel_reg(g->pin)); 311 pctl->membase + sunxi_dlevel_reg(pin));
312 break; 312 break;
313 case PIN_CONFIG_BIAS_PULL_UP: 313 case PIN_CONFIG_BIAS_PULL_UP:
314 val = readl(pctl->membase + sunxi_pull_reg(g->pin)); 314 val = readl(pctl->membase + sunxi_pull_reg(pin));
315 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); 315 mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
316 writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), 316 writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
317 pctl->membase + sunxi_pull_reg(g->pin)); 317 pctl->membase + sunxi_pull_reg(pin));
318 break; 318 break;
319 case PIN_CONFIG_BIAS_PULL_DOWN: 319 case PIN_CONFIG_BIAS_PULL_DOWN:
320 val = readl(pctl->membase + sunxi_pull_reg(g->pin)); 320 val = readl(pctl->membase + sunxi_pull_reg(pin));
321 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); 321 mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
322 writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), 322 writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
323 pctl->membase + sunxi_pull_reg(g->pin)); 323 pctl->membase + sunxi_pull_reg(pin));
324 break; 324 break;
325 default: 325 default:
326 break; 326 break;
@@ -377,6 +377,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
377 377
378 spin_lock_irqsave(&pctl->lock, flags); 378 spin_lock_irqsave(&pctl->lock, flags);
379 379
380 pin -= pctl->desc->pin_base;
380 val = readl(pctl->membase + sunxi_mux_reg(pin)); 381 val = readl(pctl->membase + sunxi_mux_reg(pin));
381 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 382 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
382 writel((val & ~mask) | config << sunxi_mux_offset(pin), 383 writel((val & ~mask) | config << sunxi_mux_offset(pin),
@@ -437,12 +438,6 @@ static const struct pinmux_ops sunxi_pmx_ops = {
437 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 438 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
438}; 439};
439 440
440static struct pinctrl_desc sunxi_pctrl_desc = {
441 .confops = &sunxi_pconf_ops,
442 .pctlops = &sunxi_pctrl_ops,
443 .pmxops = &sunxi_pmx_ops,
444};
445
446static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) 441static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
447{ 442{
448 return pinctrl_request_gpio(chip->base + offset); 443 return pinctrl_request_gpio(chip->base + offset);
@@ -530,27 +525,12 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
530 if (!desc) 525 if (!desc)
531 return -EINVAL; 526 return -EINVAL;
532 527
533 pctl->irq_array[desc->irqnum] = offset;
534
535 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 528 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
536 chip->label, offset + chip->base, desc->irqnum); 529 chip->label, offset + chip->base, desc->irqnum);
537 530
538 return irq_find_mapping(pctl->domain, desc->irqnum); 531 return irq_find_mapping(pctl->domain, desc->irqnum);
539} 532}
540 533
541static struct gpio_chip sunxi_pinctrl_gpio_chip = {
542 .owner = THIS_MODULE,
543 .request = sunxi_pinctrl_gpio_request,
544 .free = sunxi_pinctrl_gpio_free,
545 .direction_input = sunxi_pinctrl_gpio_direction_input,
546 .direction_output = sunxi_pinctrl_gpio_direction_output,
547 .get = sunxi_pinctrl_gpio_get,
548 .set = sunxi_pinctrl_gpio_set,
549 .of_xlate = sunxi_pinctrl_gpio_of_xlate,
550 .to_irq = sunxi_pinctrl_gpio_to_irq,
551 .of_gpio_n_cells = 3,
552 .can_sleep = false,
553};
554 534
555static int sunxi_pinctrl_irq_set_type(struct irq_data *d, 535static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
556 unsigned int type) 536 unsigned int type)
@@ -685,16 +665,6 @@ static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
685 } 665 }
686} 666}
687 667
688static struct of_device_id sunxi_pinctrl_match[] = {
689 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
690 { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
691 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
692 { .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
693 { .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
694 {}
695};
696MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
697
698static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 668static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
699 const char *name) 669 const char *name)
700{ 670{
@@ -755,6 +725,9 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev)
755 struct sunxi_desc_function *func = pin->functions; 725 struct sunxi_desc_function *func = pin->functions;
756 726
757 while (func->name) { 727 while (func->name) {
728 /* Create interrupt mapping while we're at it */
729 if (!strcmp(func->name, "irq"))
730 pctl->irq_array[func->irqnum] = pin->pin.number;
758 sunxi_pinctrl_add_function(pctl, func->name); 731 sunxi_pinctrl_add_function(pctl, func->name);
759 func++; 732 func++;
760 } 733 }
@@ -798,12 +771,14 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev)
798 return 0; 771 return 0;
799} 772}
800 773
801static int sunxi_pinctrl_probe(struct platform_device *pdev) 774int sunxi_pinctrl_init(struct platform_device *pdev,
775 const struct sunxi_pinctrl_desc *desc)
802{ 776{
803 struct device_node *node = pdev->dev.of_node; 777 struct device_node *node = pdev->dev.of_node;
804 const struct of_device_id *device; 778 struct pinctrl_desc *pctrl_desc;
805 struct pinctrl_pin_desc *pins; 779 struct pinctrl_pin_desc *pins;
806 struct sunxi_pinctrl *pctl; 780 struct sunxi_pinctrl *pctl;
781 struct resource *res;
807 int i, ret, last_pin; 782 int i, ret, last_pin;
808 struct clk *clk; 783 struct clk *clk;
809 784
@@ -814,15 +789,13 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
814 789
815 spin_lock_init(&pctl->lock); 790 spin_lock_init(&pctl->lock);
816 791
817 pctl->membase = of_iomap(node, 0); 792 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 if (!pctl->membase) 793 pctl->membase = devm_ioremap_resource(&pdev->dev, res);
819 return -ENOMEM; 794 if (IS_ERR(pctl->membase))
820 795 return PTR_ERR(pctl->membase);
821 device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
822 if (!device)
823 return -ENODEV;
824 796
825 pctl->desc = (struct sunxi_pinctrl_desc *)device->data; 797 pctl->dev = &pdev->dev;
798 pctl->desc = desc;
826 799
827 ret = sunxi_pinctrl_build_state(pdev); 800 ret = sunxi_pinctrl_build_state(pdev);
828 if (ret) { 801 if (ret) {
@@ -839,12 +812,21 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
839 for (i = 0; i < pctl->desc->npins; i++) 812 for (i = 0; i < pctl->desc->npins; i++)
840 pins[i] = pctl->desc->pins[i].pin; 813 pins[i] = pctl->desc->pins[i].pin;
841 814
842 sunxi_pctrl_desc.name = dev_name(&pdev->dev); 815 pctrl_desc = devm_kzalloc(&pdev->dev,
843 sunxi_pctrl_desc.owner = THIS_MODULE; 816 sizeof(*pctrl_desc),
844 sunxi_pctrl_desc.pins = pins; 817 GFP_KERNEL);
845 sunxi_pctrl_desc.npins = pctl->desc->npins; 818 if (!pctrl_desc)
846 pctl->dev = &pdev->dev; 819 return -ENOMEM;
847 pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc, 820
821 pctrl_desc->name = dev_name(&pdev->dev);
822 pctrl_desc->owner = THIS_MODULE;
823 pctrl_desc->pins = pins;
824 pctrl_desc->npins = pctl->desc->npins;
825 pctrl_desc->confops = &sunxi_pconf_ops;
826 pctrl_desc->pctlops = &sunxi_pctrl_ops;
827 pctrl_desc->pmxops = &sunxi_pmx_ops;
828
829 pctl->pctl_dev = pinctrl_register(pctrl_desc,
848 &pdev->dev, pctl); 830 &pdev->dev, pctl);
849 if (!pctl->pctl_dev) { 831 if (!pctl->pctl_dev) {
850 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 832 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
@@ -858,11 +840,22 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
858 } 840 }
859 841
860 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 842 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
861 pctl->chip = &sunxi_pinctrl_gpio_chip; 843 pctl->chip->owner = THIS_MODULE;
862 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK); 844 pctl->chip->request = sunxi_pinctrl_gpio_request,
845 pctl->chip->free = sunxi_pinctrl_gpio_free,
846 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
847 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
848 pctl->chip->get = sunxi_pinctrl_gpio_get,
849 pctl->chip->set = sunxi_pinctrl_gpio_set,
850 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
851 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
852 pctl->chip->of_gpio_n_cells = 3,
853 pctl->chip->can_sleep = false,
854 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
855 pctl->desc->pin_base;
863 pctl->chip->label = dev_name(&pdev->dev); 856 pctl->chip->label = dev_name(&pdev->dev);
864 pctl->chip->dev = &pdev->dev; 857 pctl->chip->dev = &pdev->dev;
865 pctl->chip->base = 0; 858 pctl->chip->base = pctl->desc->pin_base;
866 859
867 ret = gpiochip_add(pctl->chip); 860 ret = gpiochip_add(pctl->chip);
868 if (ret) 861 if (ret)
@@ -884,12 +877,14 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
884 goto gpiochip_error; 877 goto gpiochip_error;
885 } 878 }
886 879
887 clk_prepare_enable(clk); 880 ret = clk_prepare_enable(clk);
881 if (ret)
882 goto gpiochip_error;
888 883
889 pctl->irq = irq_of_parse_and_map(node, 0); 884 pctl->irq = irq_of_parse_and_map(node, 0);
890 if (!pctl->irq) { 885 if (!pctl->irq) {
891 ret = -EINVAL; 886 ret = -EINVAL;
892 goto gpiochip_error; 887 goto clk_error;
893 } 888 }
894 889
895 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, 890 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
@@ -897,7 +892,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
897 if (!pctl->domain) { 892 if (!pctl->domain) {
898 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 893 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
899 ret = -ENOMEM; 894 ret = -ENOMEM;
900 goto gpiochip_error; 895 goto clk_error;
901 } 896 }
902 897
903 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { 898 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
@@ -915,6 +910,8 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
915 910
916 return 0; 911 return 0;
917 912
913clk_error:
914 clk_disable_unprepare(clk);
918gpiochip_error: 915gpiochip_error:
919 if (gpiochip_remove(pctl->chip)) 916 if (gpiochip_remove(pctl->chip))
920 dev_err(&pdev->dev, "failed to remove gpio chip\n"); 917 dev_err(&pdev->dev, "failed to remove gpio chip\n");
@@ -922,17 +919,3 @@ pinctrl_error:
922 pinctrl_unregister(pctl->pctl_dev); 919 pinctrl_unregister(pctl->pctl_dev);
923 return ret; 920 return ret;
924} 921}
925
926static struct platform_driver sunxi_pinctrl_driver = {
927 .probe = sunxi_pinctrl_probe,
928 .driver = {
929 .name = "sunxi-pinctrl",
930 .owner = THIS_MODULE,
931 .of_match_table = sunxi_pinctrl_match,
932 },
933};
934module_platform_driver(sunxi_pinctrl_driver);
935
936MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
937MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
938MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
new file mode 100644
index 000000000000..8169ba598876
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -0,0 +1,258 @@
1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_SUNXI_H
14#define __PINCTRL_SUNXI_H
15
16#include <linux/kernel.h>
17#include <linux/spinlock.h>
18
19#define PA_BASE 0
20#define PB_BASE 32
21#define PC_BASE 64
22#define PD_BASE 96
23#define PE_BASE 128
24#define PF_BASE 160
25#define PG_BASE 192
26#define PH_BASE 224
27#define PI_BASE 256
28#define PL_BASE 352
29#define PM_BASE 384
30
31#define SUNXI_PINCTRL_PIN(bank, pin) \
32 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
33
34#define SUNXI_PIN_NAME_MAX_LEN 5
35
36#define BANK_MEM_SIZE 0x24
37#define MUX_REGS_OFFSET 0x0
38#define DATA_REGS_OFFSET 0x10
39#define DLEVEL_REGS_OFFSET 0x14
40#define PULL_REGS_OFFSET 0x1c
41
42#define PINS_PER_BANK 32
43#define MUX_PINS_PER_REG 8
44#define MUX_PINS_BITS 4
45#define MUX_PINS_MASK 0x0f
46#define DATA_PINS_PER_REG 32
47#define DATA_PINS_BITS 1
48#define DATA_PINS_MASK 0x01
49#define DLEVEL_PINS_PER_REG 16
50#define DLEVEL_PINS_BITS 2
51#define DLEVEL_PINS_MASK 0x03
52#define PULL_PINS_PER_REG 16
53#define PULL_PINS_BITS 2
54#define PULL_PINS_MASK 0x03
55
56#define SUNXI_IRQ_NUMBER 32
57
58#define IRQ_CFG_REG 0x200
59#define IRQ_CFG_IRQ_PER_REG 8
60#define IRQ_CFG_IRQ_BITS 4
61#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
62#define IRQ_CTRL_REG 0x210
63#define IRQ_CTRL_IRQ_PER_REG 32
64#define IRQ_CTRL_IRQ_BITS 1
65#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
66#define IRQ_STATUS_REG 0x214
67#define IRQ_STATUS_IRQ_PER_REG 32
68#define IRQ_STATUS_IRQ_BITS 1
69#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
70
71#define IRQ_EDGE_RISING 0x00
72#define IRQ_EDGE_FALLING 0x01
73#define IRQ_LEVEL_HIGH 0x02
74#define IRQ_LEVEL_LOW 0x03
75#define IRQ_EDGE_BOTH 0x04
76
77struct sunxi_desc_function {
78 const char *name;
79 u8 muxval;
80 u8 irqnum;
81};
82
83struct sunxi_desc_pin {
84 struct pinctrl_pin_desc pin;
85 struct sunxi_desc_function *functions;
86};
87
88struct sunxi_pinctrl_desc {
89 const struct sunxi_desc_pin *pins;
90 int npins;
91 unsigned pin_base;
92};
93
94struct sunxi_pinctrl_function {
95 const char *name;
96 const char **groups;
97 unsigned ngroups;
98};
99
100struct sunxi_pinctrl_group {
101 const char *name;
102 unsigned long config;
103 unsigned pin;
104};
105
106struct sunxi_pinctrl {
107 void __iomem *membase;
108 struct gpio_chip *chip;
109 const struct sunxi_pinctrl_desc *desc;
110 struct device *dev;
111 struct irq_domain *domain;
112 struct sunxi_pinctrl_function *functions;
113 unsigned nfunctions;
114 struct sunxi_pinctrl_group *groups;
115 unsigned ngroups;
116 int irq;
117 int irq_array[SUNXI_IRQ_NUMBER];
118 spinlock_t lock;
119 struct pinctrl_dev *pctl_dev;
120};
121
122#define SUNXI_PIN(_pin, ...) \
123 { \
124 .pin = _pin, \
125 .functions = (struct sunxi_desc_function[]){ \
126 __VA_ARGS__, { } }, \
127 }
128
129#define SUNXI_FUNCTION(_val, _name) \
130 { \
131 .name = _name, \
132 .muxval = _val, \
133 }
134
135#define SUNXI_FUNCTION_IRQ(_val, _irq) \
136 { \
137 .name = "irq", \
138 .muxval = _val, \
139 .irqnum = _irq, \
140 }
141
142/*
143 * The sunXi PIO registers are organized as is:
144 * 0x00 - 0x0c Muxing values.
145 * 8 pins per register, each pin having a 4bits value
146 * 0x10 Pin values
147 * 32 bits per register, each pin corresponding to one bit
148 * 0x14 - 0x18 Drive level
149 * 16 pins per register, each pin having a 2bits value
150 * 0x1c - 0x20 Pull-Up values
151 * 16 pins per register, each pin having a 2bits value
152 *
153 * This is for the first bank. Each bank will have the same layout,
154 * with an offset being a multiple of 0x24.
155 *
156 * The following functions calculate from the pin number the register
157 * and the bit offset that we should access.
158 */
159static inline u32 sunxi_mux_reg(u16 pin)
160{
161 u8 bank = pin / PINS_PER_BANK;
162 u32 offset = bank * BANK_MEM_SIZE;
163 offset += MUX_REGS_OFFSET;
164 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
165 return round_down(offset, 4);
166}
167
168static inline u32 sunxi_mux_offset(u16 pin)
169{
170 u32 pin_num = pin % MUX_PINS_PER_REG;
171 return pin_num * MUX_PINS_BITS;
172}
173
174static inline u32 sunxi_data_reg(u16 pin)
175{
176 u8 bank = pin / PINS_PER_BANK;
177 u32 offset = bank * BANK_MEM_SIZE;
178 offset += DATA_REGS_OFFSET;
179 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
180 return round_down(offset, 4);
181}
182
183static inline u32 sunxi_data_offset(u16 pin)
184{
185 u32 pin_num = pin % DATA_PINS_PER_REG;
186 return pin_num * DATA_PINS_BITS;
187}
188
189static inline u32 sunxi_dlevel_reg(u16 pin)
190{
191 u8 bank = pin / PINS_PER_BANK;
192 u32 offset = bank * BANK_MEM_SIZE;
193 offset += DLEVEL_REGS_OFFSET;
194 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
195 return round_down(offset, 4);
196}
197
198static inline u32 sunxi_dlevel_offset(u16 pin)
199{
200 u32 pin_num = pin % DLEVEL_PINS_PER_REG;
201 return pin_num * DLEVEL_PINS_BITS;
202}
203
204static inline u32 sunxi_pull_reg(u16 pin)
205{
206 u8 bank = pin / PINS_PER_BANK;
207 u32 offset = bank * BANK_MEM_SIZE;
208 offset += PULL_REGS_OFFSET;
209 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
210 return round_down(offset, 4);
211}
212
213static inline u32 sunxi_pull_offset(u16 pin)
214{
215 u32 pin_num = pin % PULL_PINS_PER_REG;
216 return pin_num * PULL_PINS_BITS;
217}
218
219static inline u32 sunxi_irq_cfg_reg(u16 irq)
220{
221 u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
222 return reg + IRQ_CFG_REG;
223}
224
225static inline u32 sunxi_irq_cfg_offset(u16 irq)
226{
227 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
228 return irq_num * IRQ_CFG_IRQ_BITS;
229}
230
231static inline u32 sunxi_irq_ctrl_reg(u16 irq)
232{
233 u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
234 return reg + IRQ_CTRL_REG;
235}
236
237static inline u32 sunxi_irq_ctrl_offset(u16 irq)
238{
239 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
240 return irq_num * IRQ_CTRL_IRQ_BITS;
241}
242
243static inline u32 sunxi_irq_status_reg(u16 irq)
244{
245 u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
246 return reg + IRQ_STATUS_REG;
247}
248
249static inline u32 sunxi_irq_status_offset(u16 irq)
250{
251 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
252 return irq_num * IRQ_STATUS_IRQ_BITS;
253}
254
255int sunxi_pinctrl_init(struct platform_device *pdev,
256 const struct sunxi_pinctrl_desc *desc);
257
258#endif /* __PINCTRL_SUNXI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 07:15:24 -0400