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authorDavid Howells <dhowells@redhat.com>2012-03-28 13:30:03 -0400
committerDavid Howells <dhowells@redhat.com>2012-03-28 13:30:03 -0400
commitbd119c69239322caafdb64517a806037d0d0c70a (patch)
treeb0f03cfa94bd35597302f42644b9220eb71baf5a
parentd550bbd40c0e10aefa05103dadbe0ae42e683707 (diff)
Disintegrate asm/system.h for Tile
Disintegrate asm/system.h for Tile. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat
-rw-r--r--arch/tile/include/asm/atomic.h2
-rw-r--r--arch/tile/include/asm/atomic_32.h1
-rw-r--r--arch/tile/include/asm/atomic_64.h1
-rw-r--r--arch/tile/include/asm/barrier.h148
-rw-r--r--arch/tile/include/asm/bitops_32.h1
-rw-r--r--arch/tile/include/asm/bitops_64.h1
-rw-r--r--arch/tile/include/asm/cacheflush.h11
-rw-r--r--arch/tile/include/asm/exec.h20
-rw-r--r--arch/tile/include/asm/pgtable.h1
-rw-r--r--arch/tile/include/asm/setup.h22
-rw-r--r--arch/tile/include/asm/spinlock_32.h1
-rw-r--r--arch/tile/include/asm/switch_to.h76
-rw-r--r--arch/tile/include/asm/system.h265
-rw-r--r--arch/tile/include/asm/timex.h2
-rw-r--r--arch/tile/include/asm/unaligned.h15
-rw-r--r--arch/tile/kernel/early_printk.c1
-rw-r--r--arch/tile/kernel/proc.c1
-rw-r--r--arch/tile/kernel/process.c3
-rw-r--r--arch/tile/kernel/regs_32.S2
-rw-r--r--arch/tile/kernel/regs_64.S2
-rw-r--r--arch/tile/kernel/single_step.c1
-rw-r--r--arch/tile/kernel/traps.c1
-rw-r--r--arch/tile/mm/elf.c1
-rw-r--r--arch/tile/mm/fault.c1
-rw-r--r--arch/tile/mm/init.c1
-rw-r--r--arch/tile/mm/pgtable.c1
26 files changed, 309 insertions, 273 deletions
diff --git a/arch/tile/include/asm/atomic.h b/arch/tile/include/asm/atomic.h
index 921dbeb8a70c..bb696da5d7cd 100644
--- a/arch/tile/include/asm/atomic.h
+++ b/arch/tile/include/asm/atomic.h
@@ -20,7 +20,7 @@
20#ifndef __ASSEMBLY__ 20#ifndef __ASSEMBLY__
21 21
22#include <linux/compiler.h> 22#include <linux/compiler.h>
23#include <asm/system.h> 23#include <linux/types.h>
24 24
25#define ATOMIC_INIT(i) { (i) } 25#define ATOMIC_INIT(i) { (i) }
26 26
diff --git a/arch/tile/include/asm/atomic_32.h b/arch/tile/include/asm/atomic_32.h
index c03349e0ca9f..466dc4a39a4f 100644
--- a/arch/tile/include/asm/atomic_32.h
+++ b/arch/tile/include/asm/atomic_32.h
@@ -17,6 +17,7 @@
17#ifndef _ASM_TILE_ATOMIC_32_H 17#ifndef _ASM_TILE_ATOMIC_32_H
18#define _ASM_TILE_ATOMIC_32_H 18#define _ASM_TILE_ATOMIC_32_H
19 19
20#include <asm/barrier.h>
20#include <arch/chip.h> 21#include <arch/chip.h>
21 22
22#ifndef __ASSEMBLY__ 23#ifndef __ASSEMBLY__
diff --git a/arch/tile/include/asm/atomic_64.h b/arch/tile/include/asm/atomic_64.h
index 27fe667fddfe..f4500c688ffa 100644
--- a/arch/tile/include/asm/atomic_64.h
+++ b/arch/tile/include/asm/atomic_64.h
@@ -19,6 +19,7 @@
19 19
20#ifndef __ASSEMBLY__ 20#ifndef __ASSEMBLY__
21 21
22#include <asm/barrier.h>
22#include <arch/spr_def.h> 23#include <arch/spr_def.h>
23 24
24/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */ 25/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */
diff --git a/arch/tile/include/asm/barrier.h b/arch/tile/include/asm/barrier.h
new file mode 100644
index 000000000000..990a217a0b72
--- /dev/null
+++ b/arch/tile/include/asm/barrier.h
@@ -0,0 +1,148 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_BARRIER_H
16#define _ASM_TILE_BARRIER_H
17
18#ifndef __ASSEMBLY__
19
20#include <linux/types.h>
21#include <arch/chip.h>
22#include <arch/spr_def.h>
23#include <asm/timex.h>
24
25/*
26 * read_barrier_depends - Flush all pending reads that subsequents reads
27 * depend on.
28 *
29 * No data-dependent reads from memory-like regions are ever reordered
30 * over this barrier. All reads preceding this primitive are guaranteed
31 * to access memory (but not necessarily other CPUs' caches) before any
32 * reads following this primitive that depend on the data return by
33 * any of the preceding reads. This primitive is much lighter weight than
34 * rmb() on most CPUs, and is never heavier weight than is
35 * rmb().
36 *
37 * These ordering constraints are respected by both the local CPU
38 * and the compiler.
39 *
40 * Ordering is not guaranteed by anything other than these primitives,
41 * not even by data dependencies. See the documentation for
42 * memory_barrier() for examples and URLs to more information.
43 *
44 * For example, the following code would force ordering (the initial
45 * value of "a" is zero, "b" is one, and "p" is "&a"):
46 *
47 * <programlisting>
48 * CPU 0 CPU 1
49 *
50 * b = 2;
51 * memory_barrier();
52 * p = &b; q = p;
53 * read_barrier_depends();
54 * d = *q;
55 * </programlisting>
56 *
57 * because the read of "*q" depends on the read of "p" and these
58 * two reads are separated by a read_barrier_depends(). However,
59 * the following code, with the same initial values for "a" and "b":
60 *
61 * <programlisting>
62 * CPU 0 CPU 1
63 *
64 * a = 2;
65 * memory_barrier();
66 * b = 3; y = b;
67 * read_barrier_depends();
68 * x = a;
69 * </programlisting>
70 *
71 * does not enforce ordering, since there is no data dependency between
72 * the read of "a" and the read of "b". Therefore, on some CPUs, such
73 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
74 * in cases like this where there are no data dependencies.
75 */
76#define read_barrier_depends() do { } while (0)
77
78#define __sync() __insn_mf()
79
80#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
81#include <hv/syscall_public.h>
82/*
83 * Issue an uncacheable load to each memory controller, then
84 * wait until those loads have completed.
85 */
86static inline void __mb_incoherent(void)
87{
88 long clobber_r10;
89 asm volatile("swint2"
90 : "=R10" (clobber_r10)
91 : "R10" (HV_SYS_fence_incoherent)
92 : "r0", "r1", "r2", "r3", "r4",
93 "r5", "r6", "r7", "r8", "r9",
94 "r11", "r12", "r13", "r14",
95 "r15", "r16", "r17", "r18", "r19",
96 "r20", "r21", "r22", "r23", "r24",
97 "r25", "r26", "r27", "r28", "r29");
98}
99#endif
100
101/* Fence to guarantee visibility of stores to incoherent memory. */
102static inline void
103mb_incoherent(void)
104{
105 __insn_mf();
106
107#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
108 {
109#if CHIP_HAS_TILE_WRITE_PENDING()
110 const unsigned long WRITE_TIMEOUT_CYCLES = 400;
111 unsigned long start = get_cycles_low();
112 do {
113 if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
114 return;
115 } while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
116#endif /* CHIP_HAS_TILE_WRITE_PENDING() */
117 (void) __mb_incoherent();
118 }
119#endif /* CHIP_HAS_MF_WAITS_FOR_VICTIMS() */
120}
121
122#define fast_wmb() __sync()
123#define fast_rmb() __sync()
124#define fast_mb() __sync()
125#define fast_iob() mb_incoherent()
126
127#define wmb() fast_wmb()
128#define rmb() fast_rmb()
129#define mb() fast_mb()
130#define iob() fast_iob()
131
132#ifdef CONFIG_SMP
133#define smp_mb() mb()
134#define smp_rmb() rmb()
135#define smp_wmb() wmb()
136#define smp_read_barrier_depends() read_barrier_depends()
137#else
138#define smp_mb() barrier()
139#define smp_rmb() barrier()
140#define smp_wmb() barrier()
141#define smp_read_barrier_depends() do { } while (0)
142#endif
143
144#define set_mb(var, value) \
145 do { var = value; mb(); } while (0)
146
147#endif /* !__ASSEMBLY__ */
148#endif /* _ASM_TILE_BARRIER_H */
diff --git a/arch/tile/include/asm/bitops_32.h b/arch/tile/include/asm/bitops_32.h
index 571b118bfd9b..ddc4c1efde43 100644
--- a/arch/tile/include/asm/bitops_32.h
+++ b/arch/tile/include/asm/bitops_32.h
@@ -17,7 +17,6 @@
17 17
18#include <linux/compiler.h> 18#include <linux/compiler.h>
19#include <linux/atomic.h> 19#include <linux/atomic.h>
20#include <asm/system.h>
21 20
22/* Tile-specific routines to support <asm/bitops.h>. */ 21/* Tile-specific routines to support <asm/bitops.h>. */
23unsigned long _atomic_or(volatile unsigned long *p, unsigned long mask); 22unsigned long _atomic_or(volatile unsigned long *p, unsigned long mask);
diff --git a/arch/tile/include/asm/bitops_64.h b/arch/tile/include/asm/bitops_64.h
index e9c8e381ee0e..58d021a9834f 100644
--- a/arch/tile/include/asm/bitops_64.h
+++ b/arch/tile/include/asm/bitops_64.h
@@ -17,7 +17,6 @@
17 17
18#include <linux/compiler.h> 18#include <linux/compiler.h>
19#include <linux/atomic.h> 19#include <linux/atomic.h>
20#include <asm/system.h>
21 20
22/* See <asm/bitops.h> for API comments. */ 21/* See <asm/bitops.h> for API comments. */
23 22
diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h
index e925f4bb498f..0fc63c488edf 100644
--- a/arch/tile/include/asm/cacheflush.h
+++ b/arch/tile/include/asm/cacheflush.h
@@ -20,7 +20,6 @@
20/* Keep includes the same across arches. */ 20/* Keep includes the same across arches. */
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/cache.h> 22#include <linux/cache.h>
23#include <asm/system.h>
24#include <arch/icache.h> 23#include <arch/icache.h>
25 24
26/* Caches are physically-indexed and so don't need special treatment */ 25/* Caches are physically-indexed and so don't need special treatment */
@@ -152,4 +151,14 @@ static inline void finv_buffer_local(void *buffer, size_t size)
152 */ 151 */
153void finv_buffer_remote(void *buffer, size_t size, int hfh); 152void finv_buffer_remote(void *buffer, size_t size, int hfh);
154 153
154/*
155 * On SMP systems, when the scheduler does migration-cost autodetection,
156 * it needs a way to flush as much of the CPU's caches as possible:
157 *
158 * TODO: fill this in!
159 */
160static inline void sched_cacheflush(void)
161{
162}
163
155#endif /* _ASM_TILE_CACHEFLUSH_H */ 164#endif /* _ASM_TILE_CACHEFLUSH_H */
diff --git a/arch/tile/include/asm/exec.h b/arch/tile/include/asm/exec.h
new file mode 100644
index 000000000000..a714e1950867
--- /dev/null
+++ b/arch/tile/include/asm/exec.h
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_EXEC_H
16#define _ASM_TILE_EXEC_H
17
18#define arch_align_stack(x) (x)
19
20#endif /* _ASM_TILE_EXEC_H */
diff --git a/arch/tile/include/asm/pgtable.h b/arch/tile/include/asm/pgtable.h
index 1a20b7ef8ea2..67490910774d 100644
--- a/arch/tile/include/asm/pgtable.h
+++ b/arch/tile/include/asm/pgtable.h
@@ -29,7 +29,6 @@
29#include <linux/spinlock.h> 29#include <linux/spinlock.h>
30#include <asm/processor.h> 30#include <asm/processor.h>
31#include <asm/fixmap.h> 31#include <asm/fixmap.h>
32#include <asm/system.h>
33 32
34struct mm_struct; 33struct mm_struct;
35struct vm_area_struct; 34struct vm_area_struct;
diff --git a/arch/tile/include/asm/setup.h b/arch/tile/include/asm/setup.h
index 7caf0f36b030..e58613e0752f 100644
--- a/arch/tile/include/asm/setup.h
+++ b/arch/tile/include/asm/setup.h
@@ -31,6 +31,28 @@ void early_panic(const char *fmt, ...);
31void warn_early_printk(void); 31void warn_early_printk(void);
32void __init disable_early_printk(void); 32void __init disable_early_printk(void);
33 33
34/* Init-time routine to do tile-specific per-cpu setup. */
35void setup_cpu(int boot);
36
37/* User-level DMA management functions */
38void grant_dma_mpls(void);
39void restrict_dma_mpls(void);
40
41#ifdef CONFIG_HARDWALL
42/* User-level network management functions */
43void reset_network_state(void);
44void grant_network_mpls(void);
45void restrict_network_mpls(void);
46struct task_struct;
47int hardwall_deactivate(struct task_struct *task);
48
49/* Hook hardwall code into changes in affinity. */
50#define arch_set_cpus_allowed(p, new_mask) do { \
51 if (p->thread.hardwall && !cpumask_equal(&p->cpus_allowed, new_mask)) \
52 hardwall_deactivate(p); \
53} while (0)
54#endif
55
34#endif /* __KERNEL__ */ 56#endif /* __KERNEL__ */
35 57
36#endif /* _ASM_TILE_SETUP_H */ 58#endif /* _ASM_TILE_SETUP_H */
diff --git a/arch/tile/include/asm/spinlock_32.h b/arch/tile/include/asm/spinlock_32.h
index a5e4208d34f9..c0a77b38d39a 100644
--- a/arch/tile/include/asm/spinlock_32.h
+++ b/arch/tile/include/asm/spinlock_32.h
@@ -19,7 +19,6 @@
19 19
20#include <linux/atomic.h> 20#include <linux/atomic.h>
21#include <asm/page.h> 21#include <asm/page.h>
22#include <asm/system.h>
23#include <linux/compiler.h> 22#include <linux/compiler.h>
24 23
25/* 24/*
diff --git a/arch/tile/include/asm/switch_to.h b/arch/tile/include/asm/switch_to.h
new file mode 100644
index 000000000000..1d48c5fee8b7
--- /dev/null
+++ b/arch/tile/include/asm/switch_to.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SWITCH_TO_H
16#define _ASM_TILE_SWITCH_TO_H
17
18#include <arch/sim_def.h>
19
20/*
21 * switch_to(n) should switch tasks to task nr n, first
22 * checking that n isn't the current task, in which case it does nothing.
23 * The number of callee-saved registers saved on the kernel stack
24 * is defined here for use in copy_thread() and must agree with __switch_to().
25 */
26#define CALLEE_SAVED_FIRST_REG 30
27#define CALLEE_SAVED_REGS_COUNT 24 /* r30 to r52, plus an empty to align */
28
29#ifndef __ASSEMBLY__
30
31struct task_struct;
32
33/*
34 * Pause the DMA engine and static network before task switching.
35 */
36#define prepare_arch_switch(next) _prepare_arch_switch(next)
37void _prepare_arch_switch(struct task_struct *next);
38
39struct task_struct;
40#define switch_to(prev, next, last) ((last) = _switch_to((prev), (next)))
41extern struct task_struct *_switch_to(struct task_struct *prev,
42 struct task_struct *next);
43
44/* Helper function for _switch_to(). */
45extern struct task_struct *__switch_to(struct task_struct *prev,
46 struct task_struct *next,
47 unsigned long new_system_save_k_0);
48
49/* Address that switched-away from tasks are at. */
50extern unsigned long get_switch_to_pc(void);
51
52/*
53 * Kernel threads can check to see if they need to migrate their
54 * stack whenever they return from a context switch; for user
55 * threads, we defer until they are returning to user-space.
56 */
57#define finish_arch_switch(prev) do { \
58 if (unlikely((prev)->state == TASK_DEAD)) \
59 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_EXIT | \
60 ((prev)->pid << _SIM_CONTROL_OPERATOR_BITS)); \
61 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_SWITCH | \
62 (current->pid << _SIM_CONTROL_OPERATOR_BITS)); \
63 if (current->mm == NULL && !kstack_hash && \
64 current_thread_info()->homecache_cpu != smp_processor_id()) \
65 homecache_migrate_kthread(); \
66} while (0)
67
68/* Support function for forking a new task. */
69void ret_from_fork(void);
70
71/* Called from ret_from_fork() when a new process starts up. */
72struct task_struct *sim_notify_fork(struct task_struct *prev);
73
74#endif /* !__ASSEMBLY__ */
75
76#endif /* _ASM_TILE_SWITCH_TO_H */
diff --git a/arch/tile/include/asm/system.h b/arch/tile/include/asm/system.h
index 23d1842f4839..5b190b48fcd0 100644
--- a/arch/tile/include/asm/system.h
+++ b/arch/tile/include/asm/system.h
@@ -1,261 +1,4 @@
1/* 1/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 2#include <asm/barrier.h>
3 * 3#include <asm/exec.h>
4 * This program is free software; you can redistribute it and/or 4#include <asm/switch_to.h>
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_SYSTEM_H
16#define _ASM_TILE_SYSTEM_H
17
18#ifndef __ASSEMBLY__
19
20#include <linux/types.h>
21#include <linux/irqflags.h>
22
23/* NOTE: we can't include <linux/ptrace.h> due to #include dependencies. */
24#include <asm/ptrace.h>
25
26#include <arch/chip.h>
27#include <arch/sim_def.h>
28#include <arch/spr_def.h>
29
30/*
31 * read_barrier_depends - Flush all pending reads that subsequents reads
32 * depend on.
33 *
34 * No data-dependent reads from memory-like regions are ever reordered
35 * over this barrier. All reads preceding this primitive are guaranteed
36 * to access memory (but not necessarily other CPUs' caches) before any
37 * reads following this primitive that depend on the data return by
38 * any of the preceding reads. This primitive is much lighter weight than
39 * rmb() on most CPUs, and is never heavier weight than is
40 * rmb().
41 *
42 * These ordering constraints are respected by both the local CPU
43 * and the compiler.
44 *
45 * Ordering is not guaranteed by anything other than these primitives,
46 * not even by data dependencies. See the documentation for
47 * memory_barrier() for examples and URLs to more information.
48 *
49 * For example, the following code would force ordering (the initial
50 * value of "a" is zero, "b" is one, and "p" is "&a"):
51 *
52 * <programlisting>
53 * CPU 0 CPU 1
54 *
55 * b = 2;
56 * memory_barrier();
57 * p = &b; q = p;
58 * read_barrier_depends();
59 * d = *q;
60 * </programlisting>
61 *
62 * because the read of "*q" depends on the read of "p" and these
63 * two reads are separated by a read_barrier_depends(). However,
64 * the following code, with the same initial values for "a" and "b":
65 *
66 * <programlisting>
67 * CPU 0 CPU 1
68 *
69 * a = 2;
70 * memory_barrier();
71 * b = 3; y = b;
72 * read_barrier_depends();
73 * x = a;
74 * </programlisting>
75 *
76 * does not enforce ordering, since there is no data dependency between
77 * the read of "a" and the read of "b". Therefore, on some CPUs, such
78 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
79 * in cases like this where there are no data dependencies.
80 */
81
82#define read_barrier_depends() do { } while (0)
83
84#define __sync() __insn_mf()
85
86#if CHIP_HAS_SPLIT_CYCLE()
87#define get_cycles_low() __insn_mfspr(SPR_CYCLE_LOW)
88#else
89#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */
90#endif
91
92#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
93#include <hv/syscall_public.h>
94/*
95 * Issue an uncacheable load to each memory controller, then
96 * wait until those loads have completed.
97 */
98static inline void __mb_incoherent(void)
99{
100 long clobber_r10;
101 asm volatile("swint2"
102 : "=R10" (clobber_r10)
103 : "R10" (HV_SYS_fence_incoherent)
104 : "r0", "r1", "r2", "r3", "r4",
105 "r5", "r6", "r7", "r8", "r9",
106 "r11", "r12", "r13", "r14",
107 "r15", "r16", "r17", "r18", "r19",
108 "r20", "r21", "r22", "r23", "r24",
109 "r25", "r26", "r27", "r28", "r29");
110}
111#endif
112
113/* Fence to guarantee visibility of stores to incoherent memory. */
114static inline void
115mb_incoherent(void)
116{
117 __insn_mf();
118
119#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
120 {
121#if CHIP_HAS_TILE_WRITE_PENDING()
122 const unsigned long WRITE_TIMEOUT_CYCLES = 400;
123 unsigned long start = get_cycles_low();
124 do {
125 if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
126 return;
127 } while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
128#endif /* CHIP_HAS_TILE_WRITE_PENDING() */
129 (void) __mb_incoherent();
130 }
131#endif /* CHIP_HAS_MF_WAITS_FOR_VICTIMS() */
132}
133
134#define fast_wmb() __sync()
135#define fast_rmb() __sync()
136#define fast_mb() __sync()
137#define fast_iob() mb_incoherent()
138
139#define wmb() fast_wmb()
140#define rmb() fast_rmb()
141#define mb() fast_mb()
142#define iob() fast_iob()
143
144#ifdef CONFIG_SMP
145#define smp_mb() mb()
146#define smp_rmb() rmb()
147#define smp_wmb() wmb()
148#define smp_read_barrier_depends() read_barrier_depends()
149#else
150#define smp_mb() barrier()
151#define smp_rmb() barrier()
152#define smp_wmb() barrier()
153#define smp_read_barrier_depends() do { } while (0)
154#endif
155
156#define set_mb(var, value) \
157 do { var = value; mb(); } while (0)
158
159/*
160 * Pause the DMA engine and static network before task switching.
161 */
162#define prepare_arch_switch(next) _prepare_arch_switch(next)
163void _prepare_arch_switch(struct task_struct *next);
164
165
166/*
167 * switch_to(n) should switch tasks to task nr n, first
168 * checking that n isn't the current task, in which case it does nothing.
169 * The number of callee-saved registers saved on the kernel stack
170 * is defined here for use in copy_thread() and must agree with __switch_to().
171 */
172#endif /* !__ASSEMBLY__ */
173#define CALLEE_SAVED_FIRST_REG 30
174#define CALLEE_SAVED_REGS_COUNT 24 /* r30 to r52, plus an empty to align */
175#ifndef __ASSEMBLY__
176struct task_struct;
177#define switch_to(prev, next, last) ((last) = _switch_to((prev), (next)))
178extern struct task_struct *_switch_to(struct task_struct *prev,
179 struct task_struct *next);
180
181/* Helper function for _switch_to(). */
182extern struct task_struct *__switch_to(struct task_struct *prev,
183 struct task_struct *next,
184 unsigned long new_system_save_k_0);
185
186/* Address that switched-away from tasks are at. */
187extern unsigned long get_switch_to_pc(void);
188
189/*
190 * On SMP systems, when the scheduler does migration-cost autodetection,
191 * it needs a way to flush as much of the CPU's caches as possible:
192 *
193 * TODO: fill this in!
194 */
195static inline void sched_cacheflush(void)
196{
197}
198
199#define arch_align_stack(x) (x)
200
201/*
202 * Is the kernel doing fixups of unaligned accesses? If <0, no kernel
203 * intervention occurs and SIGBUS is delivered with no data address
204 * info. If 0, the kernel single-steps the instruction to discover
205 * the data address to provide with the SIGBUS. If 1, the kernel does
206 * a fixup.
207 */
208extern int unaligned_fixup;
209
210/* Is the kernel printing on each unaligned fixup? */
211extern int unaligned_printk;
212
213/* Number of unaligned fixups performed */
214extern unsigned int unaligned_fixup_count;
215
216/* Init-time routine to do tile-specific per-cpu setup. */
217void setup_cpu(int boot);
218
219/* User-level DMA management functions */
220void grant_dma_mpls(void);
221void restrict_dma_mpls(void);
222
223#ifdef CONFIG_HARDWALL
224/* User-level network management functions */
225void reset_network_state(void);
226void grant_network_mpls(void);
227void restrict_network_mpls(void);
228int hardwall_deactivate(struct task_struct *task);
229
230/* Hook hardwall code into changes in affinity. */
231#define arch_set_cpus_allowed(p, new_mask) do { \
232 if (p->thread.hardwall && !cpumask_equal(&p->cpus_allowed, new_mask)) \
233 hardwall_deactivate(p); \
234} while (0)
235#endif
236
237/*
238 * Kernel threads can check to see if they need to migrate their
239 * stack whenever they return from a context switch; for user
240 * threads, we defer until they are returning to user-space.
241 */
242#define finish_arch_switch(prev) do { \
243 if (unlikely((prev)->state == TASK_DEAD)) \
244 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_EXIT | \
245 ((prev)->pid << _SIM_CONTROL_OPERATOR_BITS)); \
246 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_SWITCH | \
247 (current->pid << _SIM_CONTROL_OPERATOR_BITS)); \
248 if (current->mm == NULL && !kstack_hash && \
249 current_thread_info()->homecache_cpu != smp_processor_id()) \
250 homecache_migrate_kthread(); \
251} while (0)
252
253/* Support function for forking a new task. */
254void ret_from_fork(void);
255
256/* Called from ret_from_fork() when a new process starts up. */
257struct task_struct *sim_notify_fork(struct task_struct *prev);
258
259#endif /* !__ASSEMBLY__ */
260
261#endif /* _ASM_TILE_SYSTEM_H */
diff --git a/arch/tile/include/asm/timex.h b/arch/tile/include/asm/timex.h
index 29921f0b86da..dc987d53e2a9 100644
--- a/arch/tile/include/asm/timex.h
+++ b/arch/tile/include/asm/timex.h
@@ -29,11 +29,13 @@ typedef unsigned long long cycles_t;
29 29
30#if CHIP_HAS_SPLIT_CYCLE() 30#if CHIP_HAS_SPLIT_CYCLE()
31cycles_t get_cycles(void); 31cycles_t get_cycles(void);
32#define get_cycles_low() __insn_mfspr(SPR_CYCLE_LOW)
32#else 33#else
33static inline cycles_t get_cycles(void) 34static inline cycles_t get_cycles(void)
34{ 35{
35 return __insn_mfspr(SPR_CYCLE); 36 return __insn_mfspr(SPR_CYCLE);
36} 37}
38#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */
37#endif 39#endif
38 40
39cycles_t get_clock_rate(void); 41cycles_t get_clock_rate(void);
diff --git a/arch/tile/include/asm/unaligned.h b/arch/tile/include/asm/unaligned.h
index 137e2de5b102..37dfbe598872 100644
--- a/arch/tile/include/asm/unaligned.h
+++ b/arch/tile/include/asm/unaligned.h
@@ -21,4 +21,19 @@
21#define get_unaligned __get_unaligned_le 21#define get_unaligned __get_unaligned_le
22#define put_unaligned __put_unaligned_le 22#define put_unaligned __put_unaligned_le
23 23
24/*
25 * Is the kernel doing fixups of unaligned accesses? If <0, no kernel
26 * intervention occurs and SIGBUS is delivered with no data address
27 * info. If 0, the kernel single-steps the instruction to discover
28 * the data address to provide with the SIGBUS. If 1, the kernel does
29 * a fixup.
30 */
31extern int unaligned_fixup;
32
33/* Is the kernel printing on each unaligned fixup? */
34extern int unaligned_printk;
35
36/* Number of unaligned fixups performed */
37extern unsigned int unaligned_fixup_count;
38
24#endif /* _ASM_TILE_UNALIGNED_H */ 39#endif /* _ASM_TILE_UNALIGNED_H */
diff --git a/arch/tile/kernel/early_printk.c b/arch/tile/kernel/early_printk.c
index 493a0e66d916..afb9c9a0d887 100644
--- a/arch/tile/kernel/early_printk.c
+++ b/arch/tile/kernel/early_printk.c
@@ -16,6 +16,7 @@
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/string.h> 18#include <linux/string.h>
19#include <linux/irqflags.h>
19#include <asm/setup.h> 20#include <asm/setup.h>
20#include <hv/hypervisor.h> 21#include <hv/hypervisor.h>
21 22
diff --git a/arch/tile/kernel/proc.c b/arch/tile/kernel/proc.c
index 62d820833c68..7a9327046404 100644
--- a/arch/tile/kernel/proc.c
+++ b/arch/tile/kernel/proc.c
@@ -23,6 +23,7 @@
23#include <linux/sysctl.h> 23#include <linux/sysctl.h>
24#include <linux/hardirq.h> 24#include <linux/hardirq.h>
25#include <linux/mman.h> 25#include <linux/mman.h>
26#include <asm/unaligned.h>
26#include <asm/pgtable.h> 27#include <asm/pgtable.h>
27#include <asm/processor.h> 28#include <asm/processor.h>
28#include <asm/sections.h> 29#include <asm/sections.h>
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index 6ae495ef2b99..30caecac94dc 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -27,16 +27,17 @@
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/tracehook.h> 28#include <linux/tracehook.h>
29#include <linux/signal.h> 29#include <linux/signal.h>
30#include <asm/system.h>
31#include <asm/stack.h> 30#include <asm/stack.h>
32#include <asm/homecache.h> 31#include <asm/homecache.h>
33#include <asm/syscalls.h> 32#include <asm/syscalls.h>
34#include <asm/traps.h> 33#include <asm/traps.h>
34#include <asm/setup.h>
35#ifdef CONFIG_HARDWALL 35#ifdef CONFIG_HARDWALL
36#include <asm/hardwall.h> 36#include <asm/hardwall.h>
37#endif 37#endif
38#include <arch/chip.h> 38#include <arch/chip.h>
39#include <arch/abi.h> 39#include <arch/abi.h>
40#include <arch/sim_def.h>
40 41
41 42
42/* 43/*
diff --git a/arch/tile/kernel/regs_32.S b/arch/tile/kernel/regs_32.S
index caa13101c264..c12280c2d904 100644
--- a/arch/tile/kernel/regs_32.S
+++ b/arch/tile/kernel/regs_32.S
@@ -13,11 +13,11 @@
13 */ 13 */
14 14
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <asm/system.h>
17#include <asm/ptrace.h> 16#include <asm/ptrace.h>
18#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
19#include <arch/spr_def.h> 18#include <arch/spr_def.h>
20#include <asm/processor.h> 19#include <asm/processor.h>
20#include <asm/switch_to.h>
21 21
22/* 22/*
23 * See <asm/system.h>; called with prev and next task_struct pointers. 23 * See <asm/system.h>; called with prev and next task_struct pointers.
diff --git a/arch/tile/kernel/regs_64.S b/arch/tile/kernel/regs_64.S
index f748c1e85285..0829fd01fa30 100644
--- a/arch/tile/kernel/regs_64.S
+++ b/arch/tile/kernel/regs_64.S
@@ -13,11 +13,11 @@
13 */ 13 */
14 14
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <asm/system.h>
17#include <asm/ptrace.h> 16#include <asm/ptrace.h>
18#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
19#include <arch/spr_def.h> 18#include <arch/spr_def.h>
20#include <asm/processor.h> 19#include <asm/processor.h>
20#include <asm/switch_to.h>
21 21
22/* 22/*
23 * See <asm/system.h>; called with prev and next task_struct pointers. 23 * See <asm/system.h>; called with prev and next task_struct pointers.
diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c
index b7a879504086..bc1eb586e24d 100644
--- a/arch/tile/kernel/single_step.c
+++ b/arch/tile/kernel/single_step.c
@@ -25,6 +25,7 @@
25#include <linux/types.h> 25#include <linux/types.h>
26#include <linux/err.h> 26#include <linux/err.h>
27#include <asm/cacheflush.h> 27#include <asm/cacheflush.h>
28#include <asm/unaligned.h>
28#include <arch/abi.h> 29#include <arch/abi.h>
29#include <arch/opcode.h> 30#include <arch/opcode.h>
30 31
diff --git a/arch/tile/kernel/traps.c b/arch/tile/kernel/traps.c
index 4f47b8a356df..2bb6602a1ee7 100644
--- a/arch/tile/kernel/traps.c
+++ b/arch/tile/kernel/traps.c
@@ -21,6 +21,7 @@
21#include <linux/ptrace.h> 21#include <linux/ptrace.h>
22#include <asm/stack.h> 22#include <asm/stack.h>
23#include <asm/traps.h> 23#include <asm/traps.h>
24#include <asm/setup.h>
24 25
25#include <arch/interrupts.h> 26#include <arch/interrupts.h>
26#include <arch/spr_def.h> 27#include <arch/spr_def.h>
diff --git a/arch/tile/mm/elf.c b/arch/tile/mm/elf.c
index 55e58e93bfc5..33368d1aea93 100644
--- a/arch/tile/mm/elf.c
+++ b/arch/tile/mm/elf.c
@@ -21,6 +21,7 @@
21#include <asm/pgtable.h> 21#include <asm/pgtable.h>
22#include <asm/pgalloc.h> 22#include <asm/pgalloc.h>
23#include <asm/sections.h> 23#include <asm/sections.h>
24#include <arch/sim_def.h>
24 25
25/* Notify a running simulator, if any, that an exec just occurred. */ 26/* Notify a running simulator, if any, that an exec just occurred. */
26static void sim_notify_exec(const char *binary_name) 27static void sim_notify_exec(const char *binary_name)
diff --git a/arch/tile/mm/fault.c b/arch/tile/mm/fault.c
index c1eaaa1fcc20..cba30e9547b4 100644
--- a/arch/tile/mm/fault.c
+++ b/arch/tile/mm/fault.c
@@ -35,7 +35,6 @@
35#include <linux/syscalls.h> 35#include <linux/syscalls.h>
36#include <linux/uaccess.h> 36#include <linux/uaccess.h>
37 37
38#include <asm/system.h>
39#include <asm/pgalloc.h> 38#include <asm/pgalloc.h>
40#include <asm/sections.h> 39#include <asm/sections.h>
41#include <asm/traps.h> 40#include <asm/traps.h>
diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c
index 7309988c9794..830c4908ea76 100644
--- a/arch/tile/mm/init.c
+++ b/arch/tile/mm/init.c
@@ -38,7 +38,6 @@
38#include <linux/uaccess.h> 38#include <linux/uaccess.h>
39#include <asm/mmu_context.h> 39#include <asm/mmu_context.h>
40#include <asm/processor.h> 40#include <asm/processor.h>
41#include <asm/system.h>
42#include <asm/pgtable.h> 41#include <asm/pgtable.h>
43#include <asm/pgalloc.h> 42#include <asm/pgalloc.h>
44#include <asm/dma.h> 43#include <asm/dma.h>
diff --git a/arch/tile/mm/pgtable.c b/arch/tile/mm/pgtable.c
index de7d8e21e01d..87303693a072 100644
--- a/arch/tile/mm/pgtable.c
+++ b/arch/tile/mm/pgtable.c
@@ -27,7 +27,6 @@
27#include <linux/vmalloc.h> 27#include <linux/vmalloc.h>
28#include <linux/smp.h> 28#include <linux/smp.h>
29 29
30#include <asm/system.h>
31#include <asm/pgtable.h> 30#include <asm/pgtable.h>
32#include <asm/pgalloc.h> 31#include <asm/pgalloc.h>
33#include <asm/fixmap.h> 32#include <asm/fixmap.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 11:33:12 -0400