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authorThierry Reding <treding@nvidia.com>2014-03-14 09:02:28 -0400
committerThierry Reding <treding@nvidia.com>2014-06-05 17:09:27 -0400
commitbcfc7acbca8d9f40c4b55c6f0dad1519287f81fa (patch)
tree46113e02b90a1ed2e31c6015402179a86ccc9677
parentf7d6889b79aa93c0dde8e30d3e0f2f9acf0812b2 (diff)
drm/tegra: dsi - Remove unneeded code
A bunch of registers are initialized to 0 upon during driver probe. It turns out that none of these are actually needed, so they can simply be dropped. Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/gpu/drm/tegra/dsi.c85
1 files changed, 0 insertions, 85 deletions
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 71c1b1a64ccf..5e2bd843dbe2 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -644,7 +644,6 @@ static int tegra_dsi_init(struct host1x_client *client)
644{ 644{
645 struct tegra_drm *tegra = dev_get_drvdata(client->parent); 645 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
646 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 646 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
647 unsigned long value, i;
648 int err; 647 int err;
649 648
650 dsi->output.type = TEGRA_OUTPUT_DSI; 649 dsi->output.type = TEGRA_OUTPUT_DSI;
@@ -663,40 +662,12 @@ static int tegra_dsi_init(struct host1x_client *client)
663 dev_err(dsi->dev, "debugfs setup failed: %d\n", err); 662 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
664 } 663 }
665 664
666 /*
667 * enable high-speed mode, checksum generation, ECC generation and
668 * disable raw mode
669 */
670 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
671 value |= DSI_HOST_CONTROL_ECC | DSI_HOST_CONTROL_CS |
672 DSI_HOST_CONTROL_HS;
673 value &= ~DSI_HOST_CONTROL_RAW;
674 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
675
676 tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY);
677 tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD);
678
679 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
680
681 for (i = 0; i < 8; i++) {
682 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i);
683 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i);
684 }
685
686 for (i = 0; i < 12; i++)
687 tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i);
688
689 tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS);
690
691 err = tegra_dsi_pad_calibrate(dsi); 665 err = tegra_dsi_pad_calibrate(dsi);
692 if (err < 0) { 666 if (err < 0) {
693 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); 667 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
694 return err; 668 return err;
695 } 669 }
696 670
697 tegra_dsi_writel(dsi, DSI_POWER_CONTROL_ENABLE, DSI_POWER_CONTROL);
698 usleep_range(300, 1000);
699
700 return 0; 671 return 0;
701} 672}
702 673
@@ -747,60 +718,6 @@ static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
747 return 0; 718 return 0;
748} 719}
749 720
750static void tegra_dsi_initialize(struct tegra_dsi *dsi)
751{
752 unsigned int i;
753
754 tegra_dsi_writel(dsi, 0, DSI_POWER_CONTROL);
755
756 tegra_dsi_writel(dsi, 0, DSI_INT_ENABLE);
757 tegra_dsi_writel(dsi, 0, DSI_INT_STATUS);
758 tegra_dsi_writel(dsi, 0, DSI_INT_MASK);
759
760 tegra_dsi_writel(dsi, 0, DSI_HOST_CONTROL);
761 tegra_dsi_writel(dsi, 0, DSI_CONTROL);
762
763 tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY);
764 tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD);
765
766 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
767
768 for (i = 0; i < 8; i++) {
769 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i);
770 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i);
771 }
772
773 for (i = 0; i < 12; i++)
774 tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i);
775
776 tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS);
777
778 for (i = 0; i < 4; i++)
779 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1 + i);
780
781 tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_0);
782 tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_1);
783 tegra_dsi_writel(dsi, 0x000000ff, DSI_PHY_TIMING_2);
784 tegra_dsi_writel(dsi, 0x00000000, DSI_BTA_TIMING);
785
786 tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_0);
787 tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_1);
788 tegra_dsi_writel(dsi, 0, DSI_TO_TALLY);
789
790 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
791 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_CD);
792 tegra_dsi_writel(dsi, 0, DSI_PAD_CD_STATUS);
793 tegra_dsi_writel(dsi, 0, DSI_VIDEO_MODE_CONTROL);
794 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
795 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
796 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
797 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
798
799 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
800 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
801 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
802}
803
804static int tegra_dsi_host_attach(struct mipi_dsi_host *host, 721static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
805 struct mipi_dsi_device *device) 722 struct mipi_dsi_device *device)
806{ 723{
@@ -915,8 +832,6 @@ static int tegra_dsi_probe(struct platform_device *pdev)
915 if (IS_ERR(dsi->regs)) 832 if (IS_ERR(dsi->regs))
916 return PTR_ERR(dsi->regs); 833 return PTR_ERR(dsi->regs);
917 834
918 tegra_dsi_initialize(dsi);
919
920 dsi->mipi = tegra_mipi_request(&pdev->dev); 835 dsi->mipi = tegra_mipi_request(&pdev->dev);
921 if (IS_ERR(dsi->mipi)) 836 if (IS_ERR(dsi->mipi))
922 return PTR_ERR(dsi->mipi); 837 return PTR_ERR(dsi->mipi);