IIO: Add basic MXS LRADC driver

This driver is very basic. It supports userland trigger, buffer and
raw access to channels. The support for delay channels is missing
altogether.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Juergen Beisert <jbe@pengutronix.de>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Wolfgang Denk <wd@denx.de>

4 files changed, 618 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt b/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt
new file mode 100644
index 000000000000..801d58cb6d4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt
@@ -0,0 +1,15 @@
+* Freescale i.MX28 LRADC device driver
+
+Required properties:
+- compatible: Should be "fsl,imx28-lradc"
+- reg: Address and length of the register set for the device
+- interrupts: Should contain the LRADC interrupts
+
+Examples:
+
+        lradc@80050000 {
+                compatible = "fsl,imx28-lradc";
+                reg = <0x80050000 0x2000>;
+                interrupts = <10 14 15 16 17 18 19
+                                20 21 22 23 24 25>;
+        };
diff --git a/drivers/staging/iio/adc/Kconfig b/drivers/staging/iio/adc/Kconfig
index 67711b7d718a..845fb6c70ca3 100644
--- a/drivers/staging/iio/adc/Kconfig
+++ b/drivers/staging/iio/adc/Kconfig
@@ -200,6 +200,18 @@ config LPC32XX_ADC
           activate only one via device tree selection.  Provides direct access
           via sysfs.
 
+config MXS_LRADC
+        tristate "Freescale i.MX28 LRADC"
+        depends on ARCH_MXS
+        select IIO_BUFFER
+        select IIO_TRIGGERED_BUFFER
+        help
+          Say yes here to build support for i.MX28 LRADC convertor
+          built into these chips.
+
+          To compile this driver as a module, choose M here: the
+          module will be called mxs-lradc.
+
 config SPEAR_ADC
         tristate "ST SPEAr ADC"
         depends on PLAT_SPEAR
diff --git a/drivers/staging/iio/adc/Makefile b/drivers/staging/iio/adc/Makefile
index 14e98b62b70a..ecac9a0bb358 100644
--- a/drivers/staging/iio/adc/Makefile
+++ b/drivers/staging/iio/adc/Makefile
@@ -38,4 +38,5 @@ obj-$(CONFIG_ADT7310) += adt7310.o
 obj-$(CONFIG_ADT7410) += adt7410.o
 obj-$(CONFIG_AD7280) += ad7280a.o
 obj-$(CONFIG_LPC32XX_ADC) += lpc32xx_adc.o
+obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
 obj-$(CONFIG_SPEAR_ADC) += spear_adc.o
diff --git a/drivers/staging/iio/adc/mxs-lradc.c b/drivers/staging/iio/adc/mxs-lradc.c
new file mode 100644
index 000000000000..ae549e572e5d
--- /dev/null
+++ b/drivers/staging/iio/adc/mxs-lradc.c
@@ -0,0 +1,590 @@
+/*
+ * Freescale i.MX28 LRADC driver
+ *
+ * Copyright (c) 2012 DENX Software Engineering, GmbH.
+ * Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/sysfs.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/stmp_device.h>
+#include <linux/bitops.h>
+#include <linux/completion.h>
+
+#include <mach/mxs.h>
+#include <mach/common.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/buffer.h>
+#include <linux/iio/trigger.h>
+#include <linux/iio/trigger_consumer.h>
+#include <linux/iio/triggered_buffer.h>
+
+#define DRIVER_NAME             "mxs-lradc"
+
+#define LRADC_MAX_DELAY_CHANS   4
+#define LRADC_MAX_MAPPED_CHANS  8
+#define LRADC_MAX_TOTAL_CHANS   16
+
+#define LRADC_DELAY_TIMER_HZ    2000
+
+/*
+ * Make this runtime configurable if necessary. Currently, if the buffered mode
+ * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
+ * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
+ * seconds. The result is that the samples arrive every 500mS.
+ */
+#define LRADC_DELAY_TIMER_PER   200
+#define LRADC_DELAY_TIMER_LOOP  5
+
+static const char * const mxs_lradc_irq_name[] = {
+        "mxs-lradc-touchscreen",
+        "mxs-lradc-thresh0",
+        "mxs-lradc-thresh1",
+        "mxs-lradc-channel0",
+        "mxs-lradc-channel1",
+        "mxs-lradc-channel2",
+        "mxs-lradc-channel3",
+        "mxs-lradc-channel4",
+        "mxs-lradc-channel5",
+        "mxs-lradc-channel6",
+        "mxs-lradc-channel7",
+        "mxs-lradc-button0",
+        "mxs-lradc-button1",
+};
+
+struct mxs_lradc_chan {
+        uint8_t                         slot;
+        uint8_t                         flags;
+};
+
+struct mxs_lradc {
+        struct device           *dev;
+        void __iomem            *base;
+        int                     irq[13];
+
+        uint32_t                *buffer;
+        struct iio_trigger      *trig;
+
+        struct mutex            lock;
+
+        uint8_t                 enable;
+
+        struct completion       completion;
+};
+
+#define LRADC_CTRL0                             0x00
+#define LRADC_CTRL0_TOUCH_DETECT_ENABLE         (1 << 23)
+#define LRADC_CTRL0_TOUCH_SCREEN_TYPE           (1 << 22)
+
+#define LRADC_CTRL1                             0x10
+#define LRADC_CTRL1_LRADC_IRQ(n)                (1 << (n))
+#define LRADC_CTRL1_LRADC_IRQ_MASK              0x1fff
+#define LRADC_CTRL1_LRADC_IRQ_EN(n)             (1 << ((n) + 16))
+#define LRADC_CTRL1_LRADC_IRQ_EN_MASK           (0x1fff << 16)
+
+#define LRADC_CTRL2                             0x20
+#define LRADC_CTRL2_TEMPSENSE_PWD               (1 << 15)
+
+#define LRADC_CH(n)                             (0x50 + (0x10 * (n)))
+#define LRADC_CH_ACCUMULATE                     (1 << 29)
+#define LRADC_CH_NUM_SAMPLES_MASK               (0x1f << 24)
+#define LRADC_CH_NUM_SAMPLES_OFFSET             24
+#define LRADC_CH_VALUE_MASK                     0x3ffff
+#define LRADC_CH_VALUE_OFFSET                   0
+
+#define LRADC_DELAY(n)                          (0xd0 + (0x10 * (n)))
+#define LRADC_DELAY_TRIGGER_LRADCS_MASK         (0xff << 24)
+#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET       24
+#define LRADC_DELAY_KICK                        (1 << 20)
+#define LRADC_DELAY_TRIGGER_DELAYS_MASK         (0xf << 16)
+#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET       16
+#define LRADC_DELAY_LOOP_COUNT_MASK             (0x1f << 11)
+#define LRADC_DELAY_LOOP_COUNT_OFFSET           11
+#define LRADC_DELAY_DELAY_MASK                  0x7ff
+#define LRADC_DELAY_DELAY_OFFSET                0
+
+#define LRADC_CTRL4                             0x140
+#define LRADC_CTRL4_LRADCSELECT_MASK(n)         (0xf << ((n) * 4))
+#define LRADC_CTRL4_LRADCSELECT_OFFSET(n)       ((n) * 4)
+
+/*