ARM: u300: move the gated system controller clocks to DT

This moves the slow, fast, AHB bridge and "rest" clocks on
the U300 system controller over to registration from the
device tree.

Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

4 files changed, 418 insertions, 110 deletions

diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
new file mode 100644
index 000000000000..b6a30f5eb580
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -0,0 +1,57 @@
+Clock bindings for ST-Ericsson U300 System Controller Clocks
+
+Bindings for the gated system controller clocks:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-clk"
+- #clock-cells: must be <0>
+- clock-type: specifies the type of clock:
+  0 = slow clock
+  1 = fast clock
+  2 = rest/remaining clock
+- clock-id: specifies the clock in the type range
+
+Optional properties:
+- clocks: parent clock(s)
+
+The available clocks per type are as follows:
+
+Type:  ID:   Clock:
+-------------------
+0      0     Slow peripheral bridge clock
+0      1     UART0 clock
+0      4     GPIO clock
+0      6     RTC clock
+0      7     Application timer clock
+0      8     Access timer clock
+
+1      0     Fast peripheral bridge clock
+1      1     I2C bus 0 clock
+1      2     I2C bus 1 clock
+1      5     MMC interface peripheral (silicon) clock
+1      6     SPI clock
+
+2      3     CPU clock
+2      4     DMA controller clock
+2      5     External Memory Interface (EMIF) clock
+2      6     NAND flask interface clock
+2      8     XGAM graphics engine clock
+2      9     Shared External Memory Interface (SEMI) clock
+2      10    AHB Subsystem Bridge clock
+2      12    Interrupt controller clock
+
+Example:
+
+gpio_clk: gpio_clk@13M {
+        #clock-cells = <0>;
+        compatible = "stericsson,u300-syscon-clk";
+        clock-type = <0>; /* Slow */
+        clock-id = <4>;
+        clocks = <&slow_clk>;
+};
+
+gpio: gpio@c0016000 {
+        compatible = "stericsson,gpio-coh901";
+        (...)
+        clocks = <&gpio_clk>;
+};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 203ec1fcbc10..7edc5e58a5a5 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -43,6 +43,49 @@
                         compatible = "fixed-clock";
                         clock-frequency = <13000000>;
                 };
+                /* Slow bridge clocks under PLL13 */
+                slow_clk: slow_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <0>;
+                        clocks = <&pll13>;
+                };
+                uart0_clk: uart0_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <1>;
+                        clocks = <&slow_clk>;
+                };
+                gpio_clk: gpio_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <4>;
+                        clocks = <&slow_clk>;
+                };
+                rtc_clk: rtc_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <6>;
+                        clocks = <&slow_clk>;
+                };
+                apptimer_clk: app_tmr_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <7>;
+                        clocks = <&slow_clk>;
+                };
+                acc_tmr_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <8>;
+                        clocks = <&slow_clk>;
+                };
                 pll208: pll208@208M {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
@@ -55,6 +98,13 @@
                         clock-mult = <1>;
                         clocks = <&pll208>;
                 };
+                cpu_clk@208M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <3>;
+                        clocks = <&app208>;
+                };
                 app104: app_104_clk@104M {
                         #clock-cells = <0>;
                         compatible = "fixed-factor-clock";
@@ -62,6 +112,13 @@
                         clock-mult = <1>;
                         clocks = <&pll208>;
                 };
+                semi_clk@104M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <9>;
+                        clocks = <&app104>;
+                };
                 app52: app_52_clk@52M {
                         #clock-cells = <0>;
                         compatible = "fixed-factor-clock";
@@ -69,6 +126,49 @@
                         clock-mult = <1>;
                         clocks = <&pll208>;
                 };
+                /* AHB subsystem clocks */
+                ahb_clk: ahb_subsys_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <10>;
+                        clocks = <&app52>;
+                };
+                intcon_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <12>;
+                        clocks = <&ahb_clk>;
+                };
+                emif_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <5>;
+                        clocks = <&ahb_clk>;
+                };
+                dmac_clk: dmac_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <4>;