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authorOlof Johansson <olof@lixom.net>2012-07-18 01:43:53 -0400
committerOlof Johansson <olof@lixom.net>2012-07-18 01:43:53 -0400
commitbae7641ba0c4a0026c2f7e67a0436c890fe16ce3 (patch)
tree85089fe07e95eadafe11a6ff6acef1a9aa9e428c
parent84a1caf1453c3d44050bd22db958af4a7f99315c (diff)
parent69c7e3772eaee5d2097725cdb79bc3ef867c0d9e (diff)
Merge branch 'for-3.5-spear-fixes' of http://git.stlinux.com/spear/linux-2.6 into fixes
* 'for-3.5-spear-fixes' of http://git.stlinux.com/spear/linux-2.6: ARM: SPEAr600: Fix timer interrupt definition in spear600.dtsi ARM: dts: SPEAr320: Boot the board in EXTENDED_MODE ARM: dts: SPEAr320: Fix compatible string Clk: SPEAr1340: Update sys clock parent array clk: SPEAr1340: Fix clk enable register for uart1 and i2c1. ARM: SPEAr13xx: Fix Interrupt bindings Clk:spear6xx:Fix: Rename clk ids within predefined limit Clk:spear3xx:Fix: Rename clk ids within predefined limit clk:spear1310:Fix: Rename clk ids within predefined limit clk:spear1340:Fix: Rename clk ids within predefined limit
Diffstat
-rw-r--r--arch/arm/boot/dts/spear13xx.dtsi11
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts6
-rw-r--r--arch/arm/boot/dts/spear600.dtsi1
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c2
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c2
-rw-r--r--drivers/clk/spear/spear1310_clock.c312
-rw-r--r--drivers/clk/spear/spear1340_clock.c279
-rw-r--r--drivers/clk/spear/spear3xx_clock.c180
-rw-r--r--drivers/clk/spear/spear6xx_clock.c122
9 files changed, 451 insertions, 464 deletions
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 10dcec7e7321..f7b84aced654 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -43,8 +43,8 @@
43 43
44 pmu { 44 pmu {
45 compatible = "arm,cortex-a9-pmu"; 45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 8 0x04 46 interrupts = <0 6 0x04
47 0 9 0x04>; 47 0 7 0x04>;
48 }; 48 };
49 49
50 L2: l2-cache { 50 L2: l2-cache {
@@ -119,8 +119,8 @@
119 gmac0: eth@e2000000 { 119 gmac0: eth@e2000000 {
120 compatible = "st,spear600-gmac"; 120 compatible = "st,spear600-gmac";
121 reg = <0xe2000000 0x8000>; 121 reg = <0xe2000000 0x8000>;
122 interrupts = <0 23 0x4 122 interrupts = <0 33 0x4
123 0 24 0x4>; 123 0 34 0x4>;
124 interrupt-names = "macirq", "eth_wake_irq"; 124 interrupt-names = "macirq", "eth_wake_irq";
125 status = "disabled"; 125 status = "disabled";
126 }; 126 };
@@ -202,6 +202,7 @@
202 kbd@e0300000 { 202 kbd@e0300000 {
203 compatible = "st,spear300-kbd"; 203 compatible = "st,spear300-kbd";
204 reg = <0xe0300000 0x1000>; 204 reg = <0xe0300000 0x1000>;
205 interrupts = <0 52 0x4>;
205 status = "disabled"; 206 status = "disabled";
206 }; 207 };
207 208
@@ -224,7 +225,7 @@
224 serial@e0000000 { 225 serial@e0000000 {
225 compatible = "arm,pl011", "arm,primecell"; 226 compatible = "arm,pl011", "arm,primecell";
226 reg = <0xe0000000 0x1000>; 227 reg = <0xe0000000 0x1000>;
227 interrupts = <0 36 0x4>; 228 interrupts = <0 35 0x4>;
228 status = "disabled"; 229 status = "disabled";
229 }; 230 };
230 231
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index c13fd1f3b09f..e4e912f95024 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -15,8 +15,8 @@
15/include/ "spear320.dtsi" 15/include/ "spear320.dtsi"
16 16
17/ { 17/ {
18 model = "ST SPEAr300 Evaluation Board"; 18 model = "ST SPEAr320 Evaluation Board";
19 compatible = "st,spear300-evb", "st,spear300"; 19 compatible = "st,spear320-evb", "st,spear320";
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <1>; 21 #size-cells = <1>;
22 22
@@ -26,7 +26,7 @@
26 26
27 ahb { 27 ahb {
28 pinmux@b3000000 { 28 pinmux@b3000000 {
29 st,pinmux-mode = <3>; 29 st,pinmux-mode = <4>;
30 pinctrl-names = "default"; 30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>; 31 pinctrl-0 = <&state_default>;
32 32
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 089f0a42c50e..a3c36e47d7ef 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -181,6 +181,7 @@
181 timer@f0000000 { 181 timer@f0000000 {
182 compatible = "st,spear-timer"; 182 compatible = "st,spear-timer";
183 reg = <0xf0000000 0x400>; 183 reg = <0xf0000000 0x400>;
184 interrupt-parent = <&vic0>;
184 interrupts = <16>; 185 interrupts = <16>;
185 }; 186 };
186 }; 187 };
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 0f41bd1c47c3..66db5f13af84 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -87,7 +87,7 @@ void __init spear3xx_map_io(void)
87 87
88static void __init spear3xx_timer_init(void) 88static void __init spear3xx_timer_init(void)
89{ 89{
90 char pclk_name[] = "pll3_48m_clk"; 90 char pclk_name[] = "pll3_clk";
91 struct clk *gpt_clk, *pclk; 91 struct clk *gpt_clk, *pclk;
92 92
93 spear3xx_clk_init(); 93 spear3xx_clk_init();
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2e2e3596583e..9af67d003c62 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -423,7 +423,7 @@ void __init spear6xx_map_io(void)
423 423
424static void __init spear6xx_timer_init(void) 424static void __init spear6xx_timer_init(void)
425{ 425{
426 char pclk_name[] = "pll3_48m_clk"; 426 char pclk_name[] = "pll3_clk";
427 struct clk *gpt_clk, *pclk; 427 struct clk *gpt_clk, *pclk;
428 428
429 spear6xx_clk_init(); 429 spear6xx_clk_init();
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 8f05652d53e6..0fcec2aae19c 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -345,31 +345,30 @@ static struct frac_rate_tbl gen_rtbl[] = {
345/* clock parents */ 345/* clock parents */
346static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 346static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
347static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; 347static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
348static const char *uart0_parents[] = { "pll5_clk", "uart_synth_gate_clk", }; 348static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", };
349static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", }; 349static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
350static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk", 350static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
351 "osc_25m_clk", }; 351 "osc_25m_clk", };
352static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk", 352static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
353 "gmac_phy_synth_gate_clk", };
354static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", }; 353static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
355static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", }; 354static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
356static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk", 355static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
357 "i2s_src_pad_clk", }; 356 "i2s_src_pad_clk", };
358static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", }; 357static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
359static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", 358static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
360 "pll3_clk", }; 359 "pll3_clk", };
361static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk", 360static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
362 "pll2_clk", }; 361 "pll2_clk", };
363static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none", 362static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
364 "ras_pll2_clk", "ras_synth0_clk", }; 363 "ras_pll2_clk", "ras_syn0_clk", };
365static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk", 364static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
366 "ras_pll2_clk", "ras_synth0_clk", }; 365 "ras_pll2_clk", "ras_syn0_clk", };
367static const char *uart_parents[] = { "ras_apb_clk", "gen_synth3_clk", }; 366static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", };
368static const char *i2c_parents[] = { "ras_apb_clk", "gen_synth1_clk", }; 367static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", };
369static const char *ssp1_parents[] = { "ras_apb_clk", "gen_synth1_clk", 368static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
370 "ras_plclk0_clk", }; 369 "ras_plclk0_clk", };
371static const char *pci_parents[] = { "ras_pll3_clk", "gen_synth2_clk", }; 370static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
372static const char *tdm_parents[] = { "ras_pll3_clk", "gen_synth1_clk", }; 371static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
373 372
374void __init spear1310_clk_init(void) 373void __init spear1310_clk_init(void)
375{ 374{
@@ -390,9 +389,9 @@ void __init spear1310_clk_init(void)
390 25000000); 389 25000000);
391 clk_register_clkdev(clk, "osc_25m_clk", NULL); 390 clk_register_clkdev(clk, "osc_25m_clk", NULL);
392 391
393 clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL, 392 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT,
394 CLK_IS_ROOT, 125000000); 393 125000000);
395 clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL); 394 clk_register_clkdev(clk, "gmii_pad_clk", NULL);
396 395
397 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 396 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
398 CLK_IS_ROOT, 12288000); 397 CLK_IS_ROOT, 12288000);
@@ -406,34 +405,34 @@ void __init spear1310_clk_init(void)
406 405
407 /* clock derived from 24 or 25 MHz osc clk */ 406 /* clock derived from 24 or 25 MHz osc clk */
408 /* vco-pll */ 407 /* vco-pll */
409 clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents, 408 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
410 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 409 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
411 SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 410 SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
412 &_lock); 411 &_lock);
413 clk_register_clkdev(clk, "vco1_mux_clk", NULL); 412 clk_register_clkdev(clk, "vco1_mclk", NULL);
414 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk", 413 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
415 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl, 414 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
416 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 415 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
417 clk_register_clkdev(clk, "vco1_clk", NULL); 416 clk_register_clkdev(clk, "vco1_clk", NULL);
418 clk_register_clkdev(clk1, "pll1_clk", NULL); 417 clk_register_clkdev(clk1, "pll1_clk", NULL);
419 418
420 clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents, 419 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
421 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 420 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
422 SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 421 SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
423 &_lock); 422 &_lock);
424 clk_register_clkdev(clk, "vco2_mux_clk", NULL); 423 clk_register_clkdev(clk, "vco2_mclk", NULL);
425 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk", 424 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
426 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl, 425 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
427 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 426 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
428 clk_register_clkdev(clk, "vco2_clk", NULL); 427 clk_register_clkdev(clk, "vco2_clk", NULL);
429 clk_register_clkdev(clk1, "pll2_clk", NULL); 428 clk_register_clkdev(clk1, "pll2_clk", NULL);
430 429
431 clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents, 430 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
432 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 431 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
433 SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 432 SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
434 &_lock); 433 &_lock);
435 clk_register_clkdev(clk, "vco3_mux_clk", NULL); 434 clk_register_clkdev(clk, "vco3_mclk", NULL);
436 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk", 435 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
437 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl, 436 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
438 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 437 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
439 clk_register_clkdev(clk, "vco3_clk", NULL); 438 clk_register_clkdev(clk, "vco3_clk", NULL);
@@ -473,7 +472,7 @@ void __init spear1310_clk_init(void)
473 /* peripherals */ 472 /* peripherals */
474 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 473 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
475 128); 474 128);
476 clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0, 475 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
477 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0, 476 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
478 &_lock); 477 &_lock);
479 clk_register_clkdev(clk, NULL, "spear_thermal"); 478 clk_register_clkdev(clk, NULL, "spear_thermal");
@@ -500,177 +499,176 @@ void __init spear1310_clk_init(void)
500 clk_register_clkdev(clk, "apb_clk", NULL); 499 clk_register_clkdev(clk, "apb_clk", NULL);
501 500
502 /* gpt clocks */ 501 /* gpt clocks */
503 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents, 502 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
504 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 503 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
505 SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 504 SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
506 &_lock); 505 &_lock);
507 clk_register_clkdev(clk, "gpt0_mux_clk", NULL); 506 clk_register_clkdev(clk, "gpt0_mclk", NULL);
508 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0, 507 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
509 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0, 508 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
510 &_lock); 509 &_lock);
511 clk_register_clkdev(clk, NULL, "gpt0"); 510 clk_register_clkdev(clk, NULL, "gpt0");
512 511
513 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents, 512 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
514 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 513 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
515 SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 514 SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
516 &_lock); 515 &_lock);
517 clk_register_clkdev(clk, "gpt1_mux_clk", NULL); 516 clk_register_clkdev(clk, "gpt1_mclk", NULL);
518 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0, 517 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
519 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0, 518 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
520 &_lock); 519 &_lock);
521 clk_register_clkdev(clk, NULL, "gpt1"); 520 clk_register_clkdev(clk, NULL, "gpt1");
522 521
523 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents, 522 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
524 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 523 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
525 SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 524 SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
526 &_lock); 525 &_lock);
527 clk_register_clkdev(clk, "gpt2_mux_clk", NULL); 526 clk_register_clkdev(clk, "gpt2_mclk", NULL);
528 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0, 527 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
529 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0, 528 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
530 &_lock); 529 &_lock);
531 clk_register_clkdev(clk, NULL, "gpt2"); 530 clk_register_clkdev(clk, NULL, "gpt2");
532 531
533 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents, 532 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
534 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 533 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
535 SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 534 SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
536 &_lock); 535 &_lock);
537 clk_register_clkdev(clk, "gpt3_mux_clk", NULL); 536 clk_register_clkdev(clk, "gpt3_mclk", NULL);
538 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0, 537 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
539 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0, 538 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
540 &_lock); 539 &_lock);
541 clk_register_clkdev(clk, NULL, "gpt3"); 540 clk_register_clkdev(clk, NULL, "gpt3");
542 541
543 /* others */ 542 /* others */
544 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk", 543 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
545 "vco1div2_clk", 0, SPEAR1310_UART_CLK_SYNT, NULL, 544 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
546 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 545 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
547 clk_register_clkdev(clk, "uart_synth_clk", NULL); 546 clk_register_clkdev(clk, "uart_syn_clk", NULL);
548 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL); 547 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
549 548
550 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents, 549 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
551 ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG, 550 ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG,
552 SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0, 551 SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0,
553 &_lock); 552 &_lock);
554 clk_register_clkdev(clk, "uart0_mux_clk", NULL); 553 clk_register_clkdev(clk, "uart0_mclk", NULL);
555 554
556 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0, 555 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 0,
557 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0, 556 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0,
558 &_lock); 557 &_lock);
559 clk_register_clkdev(clk, NULL, "e0000000.serial"); 558 clk_register_clkdev(clk, NULL, "e0000000.serial");
560 559
561 clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk", 560 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
562 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL, 561 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
563 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 562 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
564 clk_register_clkdev(clk, "sdhci_synth_clk", NULL); 563 clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
565 clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL); 564 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
566 565
567 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0, 566 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 0,
568 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0, 567 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0,
569 &_lock); 568 &_lock);
570 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); 569 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
571 570
572 clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk", 571 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
573 "vco1div2_clk", 0, SPEAR1310_CFXD_CLK_SYNT, NULL, 572 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
574 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 573 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
575 clk_register_clkdev(clk, "cfxd_synth_clk", NULL); 574 clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
576 clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL); 575 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
577 576
578 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0, 577 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 0,
579 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0, 578 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0,
580 &_lock); 579 &_lock);
581 clk_register_clkdev(clk, NULL, "b2800000.cf"); 580 clk_register_clkdev(clk, NULL, "b2800000.cf");
582 clk_register_clkdev(clk, NULL, "arasan_xd"); 581 clk_register_clkdev(clk, NULL, "arasan_xd");
583 582
584 clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk", 583 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
585 "vco1div2_clk", 0, SPEAR1310_C3_CLK_SYNT, NULL, 584 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
586 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 585 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
587 clk_register_clkdev(clk, "c3_synth_clk", NULL); 586 clk_register_clkdev(clk, "c3_syn_clk", NULL);
588 clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL); 587 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
589 588
590 clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents, 589 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
591 ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG, 590 ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG,
592 SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0, 591 SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0,
593 &_lock); 592 &_lock);
594 clk_register_clkdev(clk, "c3_mux_clk", NULL); 593 clk_register_clkdev(clk, "c3_mclk", NULL);
595 594
596 clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0, 595 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
597 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0, 596 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
598 &_lock); 597 &_lock);
599 clk_register_clkdev(clk, NULL, "c3"); 598 clk_register_clkdev(clk, NULL, "c3");
600 599
601 /* gmac */ 600 /* gmac */
602 clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk", 601 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
603 gmac_phy_input_parents,
604 ARRAY_SIZE(gmac_phy_input_parents), 0, 602 ARRAY_SIZE(gmac_phy_input_parents), 0,
605 SPEAR1310_GMAC_CLK_CFG, 603 SPEAR1310_GMAC_CLK_CFG,
606 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT, 604 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
607 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 605 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
608 clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL); 606 clk_register_clkdev(clk, "phy_input_mclk", NULL);
609 607
610 clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk", 608 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
611 "gmac_phy_input_mux_clk", 0, SPEAR1310_GMAC_CLK_SYNT, 609 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl,
612 NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); 610 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
613 clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL); 611 clk_register_clkdev(clk, "phy_syn_clk", NULL);
614 clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL); 612 clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
615 613
616 clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents, 614 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
617 ARRAY_SIZE(gmac_phy_parents), 0, 615 ARRAY_SIZE(gmac_phy_parents), 0,
618 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, 616 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
619 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); 617 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
620 clk_register_clkdev(clk, NULL, "stmmacphy.0"); 618 clk_register_clkdev(clk, NULL, "stmmacphy.0");
621 619
622 /* clcd */ 620 /* clcd */
623 clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents, 621 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
624 ARRAY_SIZE(clcd_synth_parents), 0, 622 ARRAY_SIZE(clcd_synth_parents), 0,
625 SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT, 623 SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
626 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock); 624 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
627 clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL); 625 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
628 626
629 clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0, 627 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
630 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl, 628 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
631 ARRAY_SIZE(clcd_rtbl), &_lock); 629 ARRAY_SIZE(clcd_rtbl), &_lock);
632 clk_register_clkdev(clk, "clcd_synth_clk", NULL); 630 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
633 631
634 clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents, 632 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
635 ARRAY_SIZE(clcd_pixel_parents), 0, 633 ARRAY_SIZE(clcd_pixel_parents), 0,
636 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, 634 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
637 SPEAR1310_CLCD_CLK_MASK, 0, &_lock); 635 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
638 clk_register_clkdev(clk, "clcd_pixel_clk", NULL); 636 clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
639 637
640 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0, 638 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
641 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0, 639 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
642 &_lock); 640 &_lock);
643 clk_register_clkdev(clk, "clcd_clk", NULL); 641 clk_register_clkdev(clk, "clcd_clk", NULL);
644 642
645 /* i2s */ 643 /* i2s */
646 clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents, 644 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
647 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG, 645 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
648 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK, 646 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
649 0, &_lock); 647 0, &_lock);
650 clk_register_clkdev(clk, "i2s_src_clk", NULL); 648 clk_register_clkdev(clk, "i2s_src_clk", NULL);
651 649
652 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0, 650 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
653 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, 651 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
654 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); 652 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
655 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 653 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
656 654
657 clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents, 655 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
658 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG, 656 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG,
659 SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0, 657 SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0,
660 &_lock); 658 &_lock);
661 clk_register_clkdev(clk, "i2s_ref_clk", NULL); 659 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
662 660
663 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0, 661 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
664 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, 662 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
665 0, &_lock); 663 0, &_lock);
666 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); 664 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
667 665
668 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk", 666 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
669 "i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG, 667 "i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG,
670 &i2s_sclk_masks, i2s_sclk_rtbl, 668 &i2s_sclk_masks, i2s_sclk_rtbl,
671 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); 669 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
672 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); 670 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
673 clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL); 671 clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
674 672
675 /* clock derived from ahb clk */ 673 /* clock derived from ahb clk */
676 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, 674 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
@@ -747,13 +745,13 @@ void __init spear1310_clk_init(void)
747 &_lock); 745 &_lock);
748 clk_register_clkdev(clk, "sysram1_clk", NULL); 746 clk_register_clkdev(clk, "sysram1_clk", NULL);
749 747
750 clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk", 748 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
751 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl, 749 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
752 ARRAY_SIZE(adc_rtbl), &_lock, &clk1); 750 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
753 clk_register_clkdev(clk, "adc_synth_clk", NULL); 751 clk_register_clkdev(clk, "adc_syn_clk", NULL);
754 clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL); 752 clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
755 753
756 clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0, 754 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0,
757 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0, 755 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0,
758 &_lock); 756 &_lock);
759 clk_register_clkdev(clk, NULL, "adc_clk"); 757 clk_register_clkdev(clk, NULL, "adc_clk");
@@ -790,37 +788,37 @@ void __init spear1310_clk_init(void)
790 clk_register_clkdev(clk, NULL, "e0300000.kbd"); 788 clk_register_clkdev(clk, NULL, "e0300000.kbd");
791 789
792 /* RAS clks */ 790 /* RAS clks */
793 clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk", 791 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
794 gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents), 792 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG,
795 0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT0_1_CLK_SHIFT, 793 SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
796 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 794 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
797 clk_register_clkdev(clk, "gen_synth0_1_clk", NULL); 795 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
798 796
799 clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk", 797 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
800 gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents), 798 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG,
801 0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT2_3_CLK_SHIFT, 799 SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
802 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 800 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
803 clk_register_clkdev(clk, "gen_synth2_3_clk", NULL); 801 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
804 802
805 clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0, 803 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
806 SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), 804 SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
807 &_lock); 805 &_lock);
808 clk_register_clkdev(clk, "gen_synth0_clk", NULL); 806 clk_register_clkdev(clk, "gen_syn0_clk", NULL);
809 807
810 clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0, 808 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
811 SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), 809 SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
812 &_lock); 810 &_lock);
813 clk_register_clkdev(clk, "gen_synth1_clk", NULL); 811 clk_register_clkdev(clk, "gen_syn1_clk", NULL);
814 812
815 clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0, 813 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
816 SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), 814 SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
817 &_lock); 815 &_lock);
818 clk_register_clkdev(clk, "gen_synth2_clk", NULL); 816 clk_register_clkdev(clk, "gen_syn2_clk", NULL);
819 817
820 clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0, 818 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
821 SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), 819 SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
822 &_lock); 820 &_lock);
823 clk_register_clkdev(clk, "gen_synth3_clk", NULL); 821 clk_register_clkdev(clk, "gen_syn3_clk", NULL);
824 822
825 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0, 823 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
826 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0, 824 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
@@ -847,7 +845,7 @@ void __init spear1310_clk_init(void)
847 &_lock); 845 &_lock);
848 clk_register_clkdev(clk, "ras_pll3_clk", NULL); 846 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
849 847
850 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_125m_pad_clk", 0, 848 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0,
851 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0, 849 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
852 &_lock); 850 &_lock);
853 clk_register_clkdev(clk, "ras_tx125_clk", NULL); 851 clk_register_clkdev(clk, "ras_tx125_clk", NULL);
@@ -912,7 +910,7 @@ void __init spear1310_clk_init(void)
912 &_lock); 910 &_lock);
913 clk_register_clkdev(clk, NULL, "5c700000.eth"); 911 clk_register_clkdev(clk, NULL, "5c700000.eth");
914 912
915 clk = clk_register_mux(NULL, "smii_rgmii_phy_mux_clk", 913 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
916 smii_rgmii_phy_parents, 914 smii_rgmii_phy_parents,
917 ARRAY_SIZE(smii_rgmii_phy_parents), 0, 915 ARRAY_SIZE(smii_rgmii_phy_parents), 0,
918 SPEAR1310_RAS_CTRL_REG1, 916 SPEAR1310_RAS_CTRL_REG1,
@@ -922,184 +920,184 @@ void __init spear1310_clk_init(void)
922 clk_register_clkdev(clk, NULL, "stmmacphy.2"); 920 clk_register_clkdev(clk, NULL, "stmmacphy.2");
923 clk_register_clkdev(clk, NULL, "stmmacphy.4"); 921 clk_register_clkdev(clk, NULL, "stmmacphy.4");
924 922
925 clk = clk_register_mux(NULL, "rmii_phy_mux_clk", rmii_phy_parents, 923 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
926 ARRAY_SIZE(rmii_phy_parents), 0, 924 ARRAY_SIZE(rmii_phy_parents), 0,
927 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, 925 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
928 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 926 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
929 clk_register_clkdev(clk, NULL, "stmmacphy.3"); 927 clk_register_clkdev(clk, NULL, "stmmacphy.3");
930 928
931 clk = clk_register_mux(NULL, "uart1_mux_clk", uart_parents, 929 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
932 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 930 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
933 SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 931 SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
934 0, &_lock); 932 0, &_lock);
935 clk_register_clkdev(clk, "uart1_mux_clk", NULL); 933 clk_register_clkdev(clk, "uart1_mclk", NULL);
936 934
937 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0, 935 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
938 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0, 936 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
939 &_lock); 937 &_lock);
940 clk_register_clkdev(clk, NULL, "5c800000.serial"); 938 clk_register_clkdev(clk, NULL, "5c800000.serial");
941 939
942 clk = clk_register_mux(NULL, "uart2_mux_clk", uart_parents, 940 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
943 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 941 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
944 SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 942 SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
945 0, &_lock); 943 0, &_lock);
946 clk_register_clkdev(clk, "uart2_mux_clk", NULL); 944 clk_register_clkdev(clk, "uart2_mclk", NULL);
947 945
948 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mux_clk", 0, 946 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
949 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0, 947 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
950 &_lock); 948 &_lock);
951 clk_register_clkdev(clk, NULL, "5c900000.serial"); 949 clk_register_clkdev(clk, NULL, "5c900000.serial");
952 950
953 clk = clk_register_mux(NULL, "uart3_mux_clk", uart_parents, 951 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
954 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 952 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
955 SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 953 SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
956 0, &_lock); 954 0, &_lock);
957 clk_register_clkdev(clk, "uart3_mux_clk", NULL); 955 clk_register_clkdev(clk, "uart3_mclk", NULL);
958 956
959 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mux_clk", 0, 957 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
960 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0, 958 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
961 &_lock); 959 &_lock);
962 clk_register_clkdev(clk, NULL, "5ca00000.serial"); 960 clk_register_clkdev(clk, NULL, "5ca00000.serial");
963 961
964 clk = clk_register_mux(NULL, "uart4_mux_clk", uart_parents, 962 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
965 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 963 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
966 SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 964 SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
967 0, &_lock); 965 0, &_lock);
968 clk_register_clkdev(clk, "uart4_mux_clk", NULL); 966 clk_register_clkdev(clk, "uart4_mclk", NULL);
969 967
970 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mux_clk", 0, 968 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
971 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0, 969 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
972 &_lock); 970 &_lock);
973 clk_register_clkdev(clk, NULL, "5cb00000.serial"); 971 clk_register_clkdev(clk, NULL, "5cb00000.serial");
974 972
975 clk = clk_register_mux(NULL, "uart5_mux_clk", uart_parents, 973 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
976 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 974 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
977 SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 975 SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
978 0, &_lock); 976 0, &_lock);
979 clk_register_clkdev(clk, "uart5_mux_clk", NULL); 977 clk_register_clkdev(clk, "uart5_mclk", NULL);
980 978
981 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mux_clk", 0, 979 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
982 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0, 980 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
983 &_lock); 981 &_lock);
984 clk_register_clkdev(clk, NULL, "5cc00000.serial"); 982 clk_register_clkdev(clk, NULL, "5cc00000.serial");
985 983
986 clk = clk_register_mux(NULL, "i2c1_mux_clk", i2c_parents, 984 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
987 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 985 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
988 SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 986 SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
989 &_lock); 987 &_lock);
990 clk_register_clkdev(clk, "i2c1_mux_clk", NULL); 988 clk_register_clkdev(clk, "i2c1_mclk", NULL);
991 989
992 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mux_clk", 0, 990 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
993 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0, 991 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
994 &_lock); 992 &_lock);
995 clk_register_clkdev(clk, NULL, "5cd00000.i2c"); 993 clk_register_clkdev(clk, NULL, "5cd00000.i2c");
996 994
997 clk = clk_register_mux(NULL, "i2c2_mux_clk", i2c_parents, 995 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
998 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 996 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
999 SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 997 SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1000 &_lock); 998 &_lock);
1001 clk_register_clkdev(clk, "i2c2_mux_clk", NULL); 999 clk_register_clkdev(clk, "i2c2_mclk", NULL);
1002 1000
1003 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mux_clk", 0, 1001 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
1004 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0, 1002 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1005 &_lock); 1003 &_lock);
1006 clk_register_clkdev(clk, NULL, "5ce00000.i2c"); 1004 clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1007 1005
1008 clk = clk_register_mux(NULL, "i2c3_mux_clk", i2c_parents, 1006 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
1009 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1007 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1010 SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1008 SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1011 &_lock); 1009 &_lock);
1012 clk_register_clkdev(clk, "i2c3_mux_clk", NULL); 1010 clk_register_clkdev(clk, "i2c3_mclk", NULL);
1013 1011
1014 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mux_clk", 0, 1012 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
1015 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0, 1013 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1016 &_lock); 1014 &_lock);
1017 clk_register_clkdev(clk, NULL, "5cf00000.i2c"); 1015 clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1018 1016
1019 clk = clk_register_mux(NULL, "i2c4_mux_clk", i2c_parents, 1017 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
1020 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1018 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1021 SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1019 SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1022 &_lock); 1020 &_lock);
1023 clk_register_clkdev(clk, "i2c4_mux_clk", NULL); 1021 clk_register_clkdev(clk, "i2c4_mclk", NULL);
1024 1022
1025 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mux_clk", 0, 1023 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
1026 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0, 1024 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1027 &_lock); 1025 &_lock);
1028 clk_register_clkdev(clk, NULL, "5d000000.i2c"); 1026 clk_register_clkdev(clk, NULL, "5d000000.i2c");
1029 1027
1030 clk = clk_register_mux(NULL, "i2c5_mux_clk", i2c_parents, 1028 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
1031 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1029 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1032 SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1030 SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1033 &_lock); 1031 &_lock);
1034 clk_register_clkdev(clk, "i2c5_mux_clk", NULL); 1032 clk_register_clkdev(clk, "i2c5_mclk", NULL);
1035 1033
1036 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mux_clk", 0, 1034 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
1037 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0, 1035 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1038 &_lock); 1036 &_lock);
1039 clk_register_clkdev(clk, NULL, "5d100000.i2c"); 1037 clk_register_clkdev(clk, NULL, "5d100000.i2c");
1040 1038
1041 clk = clk_register_mux(NULL, "i2c6_mux_clk", i2c_parents, 1039 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
1042 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1040 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1043 SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1041 SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1044 &_lock); 1042 &_lock);
1045 clk_register_clkdev(clk, "i2c6_mux_clk", NULL); 1043 clk_register_clkdev(clk, "i2c6_mclk", NULL);
1046 1044
1047 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mux_clk", 0, 1045 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
1048 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0, 1046 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1049 &_lock); 1047 &_lock);
1050 clk_register_clkdev(clk, NULL, "5d200000.i2c"); 1048 clk_register_clkdev(clk, NULL, "5d200000.i2c");
1051 1049
1052 clk = clk_register_mux(NULL, "i2c7_mux_clk", i2c_parents, 1050 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
1053 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1051 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1054 SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1052 SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1055 &_lock); 1053 &_lock);
1056 clk_register_clkdev(clk, "i2c7_mux_clk", NULL); 1054 clk_register_clkdev(clk, "i2c7_mclk", NULL);
1057 1055
1058 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mux_clk", 0, 1056 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
1059 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0, 1057 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1060 &_lock); 1058 &_lock);
1061 clk_register_clkdev(clk, NULL, "5d300000.i2c"); 1059 clk_register_clkdev(clk, NULL, "5d300000.i2c");
1062 1060
1063 clk = clk_register_mux(NULL, "ssp1_mux_clk", ssp1_parents, 1061 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
1064 ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1062 ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1065 SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0, 1063 SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
1066 &_lock); 1064 &_lock);
1067 clk_register_clkdev(clk, "ssp1_mux_clk", NULL); 1065 clk_register_clkdev(clk, "ssp1_mclk", NULL);
1068 1066
1069 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mux_clk", 0, 1067 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
1070 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0, 1068 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1071 &_lock); 1069 &_lock);
1072 clk_register_clkdev(clk, NULL, "5d400000.spi"); 1070 clk_register_clkdev(clk, NULL, "5d400000.spi");
1073 1071
1074 clk = clk_register_mux(NULL, "pci_mux_clk", pci_parents, 1072 clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
1075 ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1073 ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1076 SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0, 1074 SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
1077 &_lock); 1075 &_lock);
1078 clk_register_clkdev(clk, "pci_mux_clk", NULL); 1076 clk_register_clkdev(clk, "pci_mclk", NULL);
1079 1077
1080 clk = clk_register_gate(NULL, "pci_clk", "pci_mux_clk", 0, 1078 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
1081 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0, 1079 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1082 &_lock); 1080 &_lock);
1083 clk_register_clkdev(clk, NULL, "pci"); 1081 clk_register_clkdev(clk, NULL, "pci");
1084 1082
1085 clk = clk_register_mux(NULL, "tdm1_mux_clk", tdm_parents, 1083 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
1086 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1084 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1087 SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, 1085 SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1088 &_lock); 1086 &_lock);
1089 clk_register_clkdev(clk, "tdm1_mux_clk", NULL); 1087 clk_register_clkdev(clk, "tdm1_mclk", NULL);
1090 1088
1091 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mux_clk", 0, 1089 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
1092 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0, 1090 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1093 &_lock); 1091 &_lock);
1094 clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); 1092 clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1095 1093
1096 clk = clk_register_mux(NULL, "tdm2_mux_clk", tdm_parents, 1094 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
1097 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1095 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1098 SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, 1096 SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1099 &_lock); 1097 &_lock);
1100 clk_register_clkdev(clk, "tdm2_mux_clk", NULL); 1098 clk_register_clkdev(clk, "tdm2_mclk", NULL);
1101 1099
1102 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mux_clk", 0, 1100 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
1103 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0, 1101 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1104 &_lock); 1102 &_lock);
1105 clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); 1103 clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index e3ea72162236..2352cee7f645 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -369,27 +369,25 @@ static struct frac_rate_tbl gen_rtbl[] = {
369 369
370/* clock parents */ 370/* clock parents */
371static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 371static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
372static const char *sys_parents[] = { "none", "pll1_clk", "none", "none", 372static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
373 "sys_synth_clk", "none", "pll2_clk", "pll3_clk", }; 373 "pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk", "pll3_clk", };
374static const char *ahb_parents[] = { "cpu_div3_clk", "amba_synth_clk", }; 374static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
375static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; 375static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
376static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk", 376static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
377 "uart0_synth_gate_clk", }; 377 "uart0_syn_gclk", };
378static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk", 378static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
379 "uart1_synth_gate_clk", }; 379 "uart1_syn_gclk", };
380static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", }; 380static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
381static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk", 381static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
382 "osc_25m_clk", }; 382 "osc_25m_clk", };
383static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk", 383static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
384 "gmac_phy_synth_gate_clk", };
385static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", }; 384static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
386static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", }; 385static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
387static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk", 386static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
388 "i2s_src_pad_clk", }; 387 "i2s_src_pad_clk", };
389static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", }; 388static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
390static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_synth2_clk", 389static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", };
391}; 390static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
392static const char *spdif_in_parents[] = { "pll2_clk", "gen_synth3_clk", };
393 391
394static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", 392static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
395 "pll3_clk", }; 393 "pll3_clk", };
@@ -415,9 +413,9 @@ void __init spear1340_clk_init(void)
415 25000000); 413 25000000);
416 clk_register_clkdev(clk, "osc_25m_clk", NULL); 414 clk_register_clkdev(clk, "osc_25m_clk", NULL);
417 415
418 clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL, 416 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT,
419 CLK_IS_ROOT, 125000000); 417 125000000);
420 clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL); 418 clk_register_clkdev(clk, "gmii_pad_clk", NULL);
421 419
422 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 420 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
423 CLK_IS_ROOT, 12288000); 421 CLK_IS_ROOT, 12288000);
@@ -431,35 +429,35 @@ void __init spear1340_clk_init(void)
431 429
432 /* clock derived from 24 or 25 MHz osc clk */ 430 /* clock derived from 24 or 25 MHz osc clk */
433 /* vco-pll */ 431 /* vco-pll */
434 clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents, 432 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
435 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 433 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
436 SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 434 SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
437 &_lock); 435 &_lock);
438 clk_register_clkdev(clk, "vco1_mux_clk", NULL); 436 clk_register_clkdev(clk, "vco1_mclk", NULL);
439 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk", 437 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
440 0, SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl, 438 SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
441 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 439 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
442 clk_register_clkdev(clk, "vco1_clk", NULL); 440 clk_register_clkdev(clk, "vco1_clk", NULL);
443 clk_register_clkdev(clk1, "pll1_clk", NULL); 441 clk_register_clkdev(clk1, "pll1_clk", NULL);
444 442
445 clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents, 443 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
446 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 444 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
447 SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 445 SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
448 &_lock); 446 &_lock);
449 clk_register_clkdev(clk, "vco2_mux_clk", NULL); 447 clk_register_clkdev(clk, "vco2_mclk", NULL);
450 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk", 448 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
451 0, SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl, 449 SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
452 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 450 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
453 clk_register_clkdev(clk, "vco2_clk", NULL); 451 clk_register_clkdev(clk, "vco2_clk", NULL);
454 clk_register_clkdev(clk1, "pll2_clk", NULL); 452 clk_register_clkdev(clk1, "pll2_clk", NULL);
455 453
456 clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents, 454 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
457 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 455 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
458 SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 456 SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
459 &_lock); 457 &_lock);
460 clk_register_clkdev(clk, "vco3_mux_clk", NULL); 458 clk_register_clkdev(clk, "vco3_mclk", NULL);
461 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk", 459 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
462 0, SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl, 460 SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
463 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 461 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
464 clk_register_clkdev(clk, "vco3_clk", NULL); 462 clk_register_clkdev(clk, "vco3_clk", NULL);
465 clk_register_clkdev(clk1, "pll3_clk", NULL); 463 clk_register_clkdev(clk1, "pll3_clk", NULL);
@@ -498,7 +496,7 @@ void __init spear1340_clk_init(void)
498 /* peripherals */ 496 /* peripherals */
499 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 497 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
500 128); 498 128);
501 clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0, 499 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
502 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0, 500 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
503 &_lock); 501 &_lock);
504 clk_register_clkdev(clk, NULL, "spear_thermal"); 502 clk_register_clkdev(clk, NULL, "spear_thermal");
@@ -509,23 +507,23 @@ void __init spear1340_clk_init(void)
509 clk_register_clkdev(clk, "ddr_clk", NULL); 507 clk_register_clkdev(clk, "ddr_clk", NULL);
510 508
511 /* clock derived from pll1 clk */ 509 /* clock derived from pll1 clk */
512 clk = clk_register_frac("sys_synth_clk", "vco1div2_clk", 0, 510 clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0,
513 SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl, 511 SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
514 ARRAY_SIZE(sys_synth_rtbl), &_lock); 512 ARRAY_SIZE(sys_synth_rtbl), &_lock);
515 clk_register_clkdev(clk, "sys_synth_clk", NULL); 513 clk_register_clkdev(clk, "sys_syn_clk", NULL);
516 514
517 clk = clk_register_frac("amba_synth_clk", "vco1div2_clk", 0, 515 clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0,
518 SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl, 516 SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
519 ARRAY_SIZE(amba_synth_rtbl), &_lock); 517 ARRAY_SIZE(amba_synth_rtbl), &_lock);
520 clk_register_clkdev(clk, "amba_synth_clk", NULL); 518 clk_register_clkdev(clk, "amba_syn_clk", NULL);
521 519
522 clk = clk_register_mux(NULL, "sys_mux_clk", sys_parents, 520 clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
523 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL, 521 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
524 SPEAR1340_SCLK_SRC_SEL_SHIFT, 522 SPEAR1340_SCLK_SRC_SEL_SHIFT,
525 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock); 523 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
526 clk_register_clkdev(clk, "sys_clk", NULL); 524 clk_register_clkdev(clk, "sys_clk", NULL);
527 525
528 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mux_clk", 0, 1, 526 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
529 2); 527 2);
530 clk_register_clkdev(clk, "cpu_clk", NULL); 528 clk_register_clkdev(clk, "cpu_clk", NULL);
531 529
@@ -548,194 +546,193 @@ void __init spear1340_clk_init(void)
548 clk_register_clkdev(clk, "apb_clk", NULL); 546 clk_register_clkdev(clk, "apb_clk", NULL);
549 547
550 /* gpt clocks */ 548 /* gpt clocks */
551 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents, 549 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
552 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 550 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
553 SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 551 SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
554 &_lock); 552 &_lock);
555 clk_register_clkdev(clk, "gpt0_mux_clk", NULL); 553 clk_register_clkdev(clk, "gpt0_mclk", NULL);
556 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0, 554 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
557 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0, 555 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
558 &_lock); 556 &_lock);
559 clk_register_clkdev(clk, NULL, "gpt0"); 557 clk_register_clkdev(clk, NULL, "gpt0");
560 558
561 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents, 559 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
562 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 560 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
563 SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 561 SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
564 &_lock); 562 &_lock);
565 clk_register_clkdev(clk, "gpt1_mux_clk", NULL); 563 clk_register_clkdev(clk, "gpt1_mclk", NULL);
566 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0, 564 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
567 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0, 565 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
568 &_lock); 566 &_lock);
569 clk_register_clkdev(clk, NULL, "gpt1"); 567 clk_register_clkdev(clk, NULL, "gpt1");
570 568
571 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents, 569 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
572 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 570 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
573 SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 571 SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
574 &_lock); 572 &_lock);
575 clk_register_clkdev(clk, "gpt2_mux_clk", NULL); 573 clk_register_clkdev(clk, "gpt2_mclk", NULL);
576 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0, 574 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
577 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0, 575 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
578 &_lock); 576 &_lock);
579 clk_register_clkdev(clk, NULL, "gpt2"); 577 clk_register_clkdev(clk, NULL, "gpt2");
580 578
581 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents, 579 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
582 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 580 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
583 SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 581 SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
584 &_lock); 582 &_lock);
585 clk_register_clkdev(clk, "gpt3_mux_clk", NULL); 583 clk_register_clkdev(clk, "gpt3_mclk", NULL);
586 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0, 584 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
587 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0, 585 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
588 &_lock); 586 &_lock);
589 clk_register_clkdev(clk, NULL, "gpt3"); 587 clk_register_clkdev(clk, NULL, "gpt3");
590 588
591 /* others */ 589 /* others */
592 clk = clk_register_aux("uart0_synth_clk", "uart0_synth_gate_clk", 590 clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk",
593 "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL, 591 "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
594 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 592 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
595 clk_register_clkdev(clk, "uart0_synth_clk", NULL); 593 clk_register_clkdev(clk, "uart0_syn_clk", NULL);
596 clk_register_clkdev(clk1, "uart0_synth_gate_clk", NULL); 594 clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
597 595
598 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents, 596 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
599 ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG, 597 ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG,
600 SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0, 598 SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
601 &_lock); 599 &_lock);
602 clk_register_clkdev(clk, "uart0_mux_clk", NULL); 600 clk_register_clkdev(clk, "uart0_mclk", NULL);
603 601
604 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0, 602 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 0,
605 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0, 603 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0,
606 &_lock); 604 &_lock);
607 clk_register_clkdev(clk, NULL, "e0000000.serial"); 605 clk_register_clkdev(clk, NULL, "e0000000.serial");
608 606
609 clk = clk_register_aux("uart1_synth_clk", "uart1_synth_gate_clk", 607 clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk",
610 "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL, 608 "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
611 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 609 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
612 clk_register_clkdev(clk, "uart1_synth_clk", NULL); 610 clk_register_clkdev(clk, "uart1_syn_clk", NULL);
613 clk_register_clkdev(clk1, "uart1_synth_gate_clk", NULL); 611 clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
614 612
615 clk = clk_register_mux(NULL, "uart1_mux_clk", uart1_parents, 613 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
616 ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG, 614 ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG,
617 SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0, 615 SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
618 &_lock); 616 &_lock);
619 clk_register_clkdev(clk, "uart1_mux_clk", NULL); 617 clk_register_clkdev(clk, "uart1_mclk", NULL);
620 618
621 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0, 619 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
622 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0, 620 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
623 &_lock); 621 &_lock);
624 clk_register_clkdev(clk, NULL, "b4100000.serial"); 622 clk_register_clkdev(clk, NULL, "b4100000.serial");
625 623
626 clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk", 624 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
627 "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL, 625 "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
628 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 626 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
629 clk_register_clkdev(clk, "sdhci_synth_clk", NULL); 627 clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
630 clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL); 628 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
631 629
632 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0, 630 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 0,
633 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0, 631 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0,
634 &_lock); 632 &_lock);
635 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); 633 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
636 634
637 clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk", 635 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
638 "vco1div2_clk", 0, SPEAR1340_CFXD_CLK_SYNT, NULL, 636 0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl,
639 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 637 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
640 clk_register_clkdev(clk, "cfxd_synth_clk", NULL); 638 clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
641 clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL); 639 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
642 640
643 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0, 641 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 0,
644 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0, 642 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0,
645 &_lock); 643 &_lock);
646 clk_register_clkdev(clk, NULL, "b2800000.cf"); 644 clk_register_clkdev(clk, NULL, "b2800000.cf");
647 clk_register_clkdev(clk, NULL, "arasan_xd"); 645 clk_register_clkdev(clk, NULL, "arasan_xd");
648 646
649 clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk", 647 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0,
650 "vco1div2_clk", 0, SPEAR1340_C3_CLK_SYNT, NULL, 648 SPEAR1340_C3_CLK_SYNT, NULL, aux_rtbl,
651 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 649 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
652 clk_register_clkdev(clk, "c3_synth_clk", NULL); 650 clk_register_clkdev(clk, "c3_syn_clk", NULL);
653 clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL); 651 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
654 652
655 clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents, 653 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
656 ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG, 654 ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG,
657 SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0, 655 SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0,
658 &_lock); 656 &_lock);
659 clk_register_clkdev(clk, "c3_mux_clk", NULL); 657 clk_register_clkdev(clk, "c3_mclk", NULL);
660 658
661 clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0, 659 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
662 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0, 660 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
663 &_lock); 661 &_lock);
664 clk_register_clkdev(clk, NULL, "c3"); 662 clk_register_clkdev(clk, NULL, "c3");
665 663
666 /* gmac */ 664 /* gmac */
667 clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk", 665 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
668 gmac_phy_input_parents,
669 ARRAY_SIZE(gmac_phy_input_parents), 0, 666 ARRAY_SIZE(gmac_phy_input_parents), 0,
670 SPEAR1340_GMAC_CLK_CFG, 667 SPEAR1340_GMAC_CLK_CFG,
671 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT, 668 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
672 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 669 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
673 clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL); 670 clk_register_clkdev(clk, "phy_input_mclk", NULL);
674 671
675 clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk", 672 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
676 "gmac_phy_input_mux_clk", 0, SPEAR1340_GMAC_CLK_SYNT, 673 0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl,
677 NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); 674 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
678 clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL); 675 clk_register_clkdev(clk, "phy_syn_clk", NULL);
679 clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL); 676 clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
680 677
681 clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents, 678 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
682 ARRAY_SIZE(gmac_phy_parents), 0, 679 ARRAY_SIZE(gmac_phy_parents), 0,
683 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT, 680 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
684 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock); 681 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
685 clk_register_clkdev(clk, NULL, "stmmacphy.0"); 682 clk_register_clkdev(clk, NULL, "stmmacphy.0");
686 683
687 /* clcd */ 684 /* clcd */
688 clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents, 685 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
689 ARRAY_SIZE(clcd_synth_parents), 0, 686 ARRAY_SIZE(clcd_synth_parents), 0,
690 SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT, 687 SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT,
691 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock); 688 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
692 clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL); 689 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
693 690
694 clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0, 691 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
695 SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl, 692 SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
696 ARRAY_SIZE(clcd_rtbl), &_lock); 693 ARRAY_SIZE(clcd_rtbl), &_lock);
697 clk_register_clkdev(clk, "clcd_synth_clk", NULL); 694 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
698 695
699 clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents, 696 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
700 ARRAY_SIZE(clcd_pixel_parents), 0, 697 ARRAY_SIZE(clcd_pixel_parents), 0,
701 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT, 698 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
702 SPEAR1340_CLCD_CLK_MASK, 0, &_lock); 699 SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
703 clk_register_clkdev(clk, "clcd_pixel_clk", NULL); 700 clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
704 701
705 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0, 702 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
706 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0, 703 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
707 &_lock); 704 &_lock);
708 clk_register_clkdev(clk, "clcd_clk", NULL); 705 clk_register_clkdev(clk, "clcd_clk", NULL);
709 706
710 /* i2s */ 707 /* i2s */
711 clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents, 708 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
712 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG, 709 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
713 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK, 710 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
714 0, &_lock); 711 0, &_lock);
715 clk_register_clkdev(clk, "i2s_src_clk", NULL); 712 clk_register_clkdev(clk, "i2s_src_clk", NULL);
716 713
717 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0, 714 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
718 SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, 715 SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
719 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); 716 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
720 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 717 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
721 718
722 clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents, 719 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
723 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG, 720 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG,
724 SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0, 721 SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0,
725 &_lock); 722 &_lock);
726 clk_register_clkdev(clk, "i2s_ref_clk", NULL); 723 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
727 724
728 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0, 725 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
729 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB, 726 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
730 0, &_lock); 727 0, &_lock);
731 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); 728 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
732 729
733 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk", 730 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk",
734 "i2s_ref_mux_clk", 0, SPEAR1340_I2S_CLK_CFG, 731 0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks,
735 &i2s_sclk_masks, i2s_sclk_rtbl, 732 i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock,
736 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); 733 &clk1);
737 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); 734 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
738 clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL); 735 clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
739 736
740 /* clock derived from ahb clk */ 737 /* clock derived from ahb clk */
741 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, 738 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
@@ -744,7 +741,7 @@ void __init spear1340_clk_init(void)
744 clk_register_clkdev(clk, NULL, "e0280000.i2c"); 741 clk_register_clkdev(clk, NULL, "e0280000.i2c");
745 742
746 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0, 743 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
747 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0, 744 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
748 &_lock); 745 &_lock);
749 clk_register_clkdev(clk, NULL, "b4000000.i2c"); 746 clk_register_clkdev(clk, NULL, "b4000000.i2c");
750 747
@@ -800,13 +797,13 @@ void __init spear1340_clk_init(void)
800 &_lock); 797 &_lock);
801 clk_register_clkdev(clk, "sysram1_clk", NULL); 798 clk_register_clkdev(clk, "sysram1_clk", NULL);
802 799
803 clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk", 800 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
804 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl, 801 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
805 ARRAY_SIZE(adc_rtbl), &_lock, &clk1); 802 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
806 clk_register_clkdev(clk, "adc_synth_clk", NULL); 803 clk_register_clkdev(clk, "adc_syn_clk", NULL);
807 clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL); 804 clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
808 805
809 clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0, 806 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0,
810 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0, 807 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0,
811 &_lock); 808 &_lock);
812 clk_register_clkdev(clk, NULL, "adc_clk"); 809 clk_register_clkdev(clk, NULL, "adc_clk");
@@ -843,39 +840,39 @@ void __init spear1340_clk_init(void)
843 clk_register_clkdev(clk, NULL, "e0300000.kbd"); 840 clk_register_clkdev(clk, NULL, "e0300000.kbd");
844 841
845 /* RAS clks */ 842 /* RAS clks */
846 clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk", 843 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
847 gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents), 844 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1340_PLL_CFG,
848 0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT0_1_CLK_SHIFT, 845 SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
849 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 846 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
850 clk_register_clkdev(clk, "gen_synth0_1_clk", NULL); 847 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
851 848
852 clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk", 849 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
853 gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents), 850 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1340_PLL_CFG,
854 0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT2_3_CLK_SHIFT, 851 SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
855 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 852 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
856 clk_register_clkdev(clk, "gen_synth2_3_clk", NULL); 853 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
857 854
858 clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0, 855 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
859 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), 856 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
860 &_lock); 857 &_lock);
861 clk_register_clkdev(clk, "gen_synth0_clk", NULL); 858 clk_register_clkdev(clk, "gen_syn0_clk", NULL);
862 859
863 clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0, 860 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
864 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), 861 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
865 &_lock); 862 &_lock);
866 clk_register_clkdev(clk, "gen_synth1_clk", NULL); 863 clk_register_clkdev(clk, "gen_syn1_clk", NULL);
867 864
868 clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0, 865 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
869 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), 866 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
870 &_lock); 867 &_lock);
871 clk_register_clkdev(clk, "gen_synth2_clk", NULL); 868 clk_register_clkdev(clk, "gen_syn2_clk", NULL);
872 869
873 clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0, 870 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
874 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), 871 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
875 &_lock); 872 &_lock);
876 clk_register_clkdev(clk, "gen_synth3_clk", NULL); 873 clk_register_clkdev(clk, "gen_syn3_clk", NULL);
877 874
878 clk = clk_register_gate(NULL, "mali_clk", "gen_synth3_clk", 0, 875 clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk", 0,
879 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0, 876 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0,
880 &_lock); 877 &_lock);
881 clk_register_clkdev(clk, NULL, "mali"); 878 clk_register_clkdev(clk, NULL, "mali");
@@ -890,74 +887,74 @@ void __init spear1340_clk_init(void)
890 &_lock); 887 &_lock);
891 clk_register_clkdev(clk, NULL, "spear_cec.1"); 888 clk_register_clkdev(clk, NULL, "spear_cec.1");
892 889
893 clk = clk_register_mux(NULL, "spdif_out_mux_clk", spdif_out_parents, 890 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
894 ARRAY_SIZE(spdif_out_parents), 0, 891 ARRAY_SIZE(spdif_out_parents), 0,
895 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT, 892 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
896 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 893 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
897 clk_register_clkdev(clk, "spdif_out_mux_clk", NULL); 894 clk_register_clkdev(clk, "spdif_out_mclk", NULL);
898 895
899 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mux_clk", 0, 896 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk", 0,
900 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB, 897 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB,
901 0, &_lock); 898 0, &_lock);
902 clk_register_clkdev(clk, NULL, "spdif-out"); 899 clk_register_clkdev(clk, NULL, "spdif-out");
903 900
904 clk = clk_register_mux(NULL, "spdif_in_mux_clk", spdif_in_parents, 901 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
905 ARRAY_SIZE(spdif_in_parents), 0, 902 ARRAY_SIZE(spdif_in_parents), 0,
906 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT, 903 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
907 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 904 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
908 clk_register_clkdev(clk, "spdif_in_mux_clk", NULL); 905 clk_register_clkdev(clk, "spdif_in_mclk", NULL);
909 906
910 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mux_clk", 0, 907 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk", 0,
911 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0, 908 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0,
912 &_lock); 909 &_lock);
913 clk_register_clkdev(clk, NULL, "spdif-in"); 910 clk_register_clkdev(clk, NULL, "spdif-in");
914 911
915 clk = clk_register_gate(NULL, "acp_clk", "acp_mux_clk", 0, 912 clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0,
916 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0, 913 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
917 &_lock); 914 &_lock);
918 clk_register_clkdev(clk, NULL, "acp_clk"); 915 clk_register_clkdev(clk, NULL, "acp_clk");
919 916
920 clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mux_clk", 0, 917 clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mclk", 0,
921 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0, 918 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
922 &_lock); 919 &_lock);
923 clk_register_clkdev(clk, NULL, "plgpio"); 920 clk_register_clkdev(clk, NULL, "plgpio");
924 921
925 clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mux_clk", 0, 922 clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mclk", 0,
926 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB, 923 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
927 0, &_lock); 924 0, &_lock);
928 clk_register_clkdev(clk, NULL, "video_dec"); 925 clk_register_clkdev(clk, NULL, "video_dec");
929 926
930 clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mux_clk", 0, 927 clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mclk", 0,
931 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB, 928 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
932 0, &_lock); 929 0, &_lock);
933 clk_register_clkdev(clk, NULL, "video_enc"); 930 clk_register_clkdev(clk, NULL, "video_enc");
934 931
935 clk = clk_register_gate(NULL, "video_in_clk", "video_in_mux_clk", 0, 932 clk = clk_register_gate(NULL, "video_in_clk", "video_in_mclk", 0,
936 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0, 933 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
937 &_lock); 934 &_lock);
938 clk_register_clkdev(clk, NULL, "spear_vip"); 935 clk_register_clkdev(clk, NULL, "spear_vip");
939 936
940 clk = clk_register_gate(NULL, "cam0_clk", "cam0_mux_clk", 0, 937 clk = clk_register_gate(NULL, "cam0_clk", "cam0_mclk", 0,
941 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0, 938 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
942 &_lock); 939 &_lock);
943 clk_register_clkdev(clk, NULL, "spear_camif.0"); 940 clk_register_clkdev(clk, NULL, "spear_camif.0");
944 941
945 clk = clk_register_gate(NULL, "cam1_clk", "cam1_mux_clk", 0, 942 clk = clk_register_gate(NULL, "cam1_clk", "cam1_mclk", 0,
946 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0, 943 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
947 &_lock); 944 &_lock);
948 clk_register_clkdev(clk, NULL, "spear_camif.1"); 945 clk_register_clkdev(clk, NULL, "spear_camif.1");
949 946
950 clk = clk_register_gate(NULL, "cam2_clk", "cam2_mux_clk", 0, 947 clk = clk_register_gate(NULL, "cam2_clk", "cam2_mclk", 0,
951 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0, 948 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
952 &_lock); 949 &_lock);
953 clk_register_clkdev(clk, NULL, "spear_camif.2"); 950 clk_register_clkdev(clk, NULL, "spear_camif.2");
954 951
955 clk = clk_register_gate(NULL, "cam3_clk", "cam3_mux_clk", 0, 952 clk = clk_register_gate(NULL, "cam3_clk", "cam3_mclk", 0,
956 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0, 953 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
957 &_lock); 954 &_lock);
958 clk_register_clkdev(clk, NULL, "spear_camif.3"); 955 clk_register_clkdev(clk, NULL, "spear_camif.3");
959 956
960 clk = clk_register_gate(NULL, "pwm_clk", "pwm_mux_clk", 0, 957 clk = clk_register_gate(NULL, "pwm_clk", "pwm_mclk", 0,
961 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0, 958 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
962 &_lock); 959 &_lock);
963 clk_register_clkdev(clk, NULL, "pwm"); 960 clk_register_clkdev(clk, NULL, "pwm");
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index 01dd6daff2a1..c3157454bb3f 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -122,12 +122,12 @@ static struct gpt_rate_tbl gpt_rtbl[] = {
122}; 122};
123 123
124/* clock parents */ 124/* clock parents */
125static const char *uart0_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", }; 125static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", };
126static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk", 126static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk",
127}; 127};
128static const char *gpt0_parents[] = { "pll3_48m_clk", "gpt0_synth_clk", }; 128static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", };
129static const char *gpt1_parents[] = { "pll3_48m_clk", "gpt1_synth_clk", }; 129static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", };
130static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", }; 130static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
131static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", }; 131static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
132static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", 132static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
133 "pll2_clk", }; 133 "pll2_clk", };
@@ -137,7 +137,7 @@ static void __init spear300_clk_init(void)
137{ 137{
138 struct clk *clk; 138 struct clk *clk;
139 139
140 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0, 140 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
141 1, 1); 141 1, 1);
142 clk_register_clkdev(clk, NULL, "60000000.clcd"); 142 clk_register_clkdev(clk, NULL, "60000000.clcd");
143 143
@@ -219,15 +219,11 @@ static void __init spear310_clk_init(void)
219 #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0 219 #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0
220 #define SPEAR320_UARTX_PCLK_VAL_APB 0x1 220 #define SPEAR320_UARTX_PCLK_VAL_APB 0x1
221 221
222static const char *i2s_ref_parents[] = { "ras_pll2_clk", 222static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", };
223 "ras_gen2_synth_gate_clk", }; 223static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", };
224static const char *sdhci_parents[] = { "ras_pll3_48m_clk",
225 "ras_gen3_synth_gate_clk",
226};
227static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", 224static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
228 "ras_gen0_synth_gate_clk", }; 225 "ras_syn0_gclk", };
229static const char *uartx_parents[] = { "ras_gen1_synth_gate_clk", "ras_apb_clk", 226static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
230};
231 227
232static void __init spear320_clk_init(void) 228static void __init spear320_clk_init(void)
233{ 229{
@@ -237,7 +233,7 @@ static void __init spear320_clk_init(void)
237 CLK_IS_ROOT, 125000000); 233 CLK_IS_ROOT, 125000000);
238 clk_register_clkdev(clk, "smii_125m_pad", NULL); 234 clk_register_clkdev(clk, "smii_125m_pad", NULL);
239 235
240 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0, 236 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
241 1, 1); 237 1, 1);
242 clk_register_clkdev(clk, NULL, "90000000.clcd"); 238 clk_register_clkdev(clk, NULL, "90000000.clcd");
243 239
@@ -363,9 +359,9 @@ void __init spear3xx_clk_init(void)
363 clk_register_clkdev(clk, NULL, "fc900000.rtc"); 359 clk_register_clkdev(clk, NULL, "fc900000.rtc");
364 360
365 /* clock derived from 24 MHz osc clk */ 361 /* clock derived from 24 MHz osc clk */
366 clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0, 362 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
367 48000000); 363 48000000);
368 clk_register_clkdev(clk, "pll3_48m_clk", NULL); 364 clk_register_clkdev(clk, "pll3_clk", NULL);
369 365
370 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1, 366 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
371 1); 367 1);
@@ -392,98 +388,98 @@ void __init spear3xx_clk_init(void)
392 HCLK_RATIO_MASK, 0, &_lock); 388 HCLK_RATIO_MASK, 0, &_lock);
393 clk_register_clkdev(clk, "ahb_clk", NULL); 389 clk_register_clkdev(clk, "ahb_clk", NULL);
394 390
395 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk", 391 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
396 "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, 392 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
397 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 393 &_lock, &clk1);
398 clk_register_clkdev(clk, "uart_synth_clk", NULL); 394 clk_register_clkdev(clk, "uart_syn_clk", NULL);
399 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL); 395 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
400 396
401 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents, 397 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
402 ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG, 398 ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG,
403 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); 399 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
404 clk_register_clkdev(clk, "uart0_mux_clk", NULL); 400 clk_register_clkdev(clk, "uart0_mclk", NULL);
405 401
406 clk = clk_register_gate(NULL, "uart0", "uart0_mux_clk", 0, 402 clk = clk_register_gate(NULL, "uart0", "uart0_mclk", 0, PERIP1_CLK_ENB,
407 PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock); 403 UART_CLK_ENB, 0, &_lock);
408 clk_register_clkdev(clk, NULL, "d0000000.serial"); 404 clk_register_clkdev(clk, NULL, "d0000000.serial");
409 405
410 clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk", 406 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0,
411 "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, 407 FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
412 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 408 &_lock, &clk1);
413 clk_register_clkdev(clk, "firda_synth_clk", NULL); 409 clk_register_clkdev(clk, "firda_syn_clk", NULL);
414 clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL); 410 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
415 411
416 clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents, 412 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
417 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, 413 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
418 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); 414 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
419 clk_register_clkdev(clk, "firda_mux_clk", NULL); 415 clk_register_clkdev(clk, "firda_mclk", NULL);
420 416
421 clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0, 417 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
422 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); 418 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
423 clk_register_clkdev(clk, NULL, "firda"); 419 clk_register_clkdev(clk, NULL, "firda");
424 420
425 /* gpt clocks */ 421 /* gpt clocks */
426 clk_register_gpt("gpt0_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG, 422 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
427 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 423 ARRAY_SIZE(gpt_rtbl), &_lock);
428 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, 424 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
429 ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG, 425 ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG,
430 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 426 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
431 clk_register_clkdev(clk, NULL, "gpt0"); 427 clk_register_clkdev(clk, NULL, "gpt0");
432 428
433 clk_register_gpt("gpt1_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG, 429 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
434 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 430 ARRAY_SIZE(gpt_rtbl), &_lock);
435 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt1_parents, 431 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
436 ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG, 432 ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG,
437 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 433 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
438 clk_register_clkdev(clk, "gpt1_mux_clk", NULL); 434 clk_register_clkdev(clk, "gpt1_mclk", NULL);
439 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0, 435 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
440 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); 436 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
441 clk_register_clkdev(clk, NULL, "gpt1"); 437 clk_register_clkdev(clk, NULL, "gpt1");
442 438
443 clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG, 439 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
444 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 440 ARRAY_SIZE(gpt_rtbl), &_lock);
445 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents, 441 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
446 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, 442 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
447 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 443 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
448 clk_register_clkdev(clk, "gpt2_mux_clk", NULL); 444 clk_register_clkdev(clk, "gpt2_mclk", NULL);
449 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0, 445 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
450 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); 446 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
451 clk_register_clkdev(clk, NULL, "gpt2"); 447 clk_register_clkdev(clk, NULL, "gpt2");
452 448
453 /* general synths clocks */ 449 /* general synths clocks */
454 clk = clk_register_aux("gen0_synth_clk", "gen0_synth_gate_clk", 450 clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk",
455 "pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl, 451 0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
456 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 452 &_lock, &clk1);
457 clk_register_clkdev(clk, "gen0_synth_clk", NULL); 453 clk_register_clkdev(clk, "gen0_syn_clk", NULL);
458 clk_register_clkdev(clk1, "gen0_synth_gate_clk", NULL); 454 clk_register_clkdev(clk1, "gen0_syn_gclk", NULL);
459 455
460 clk = clk_register_aux("gen1_synth_clk", "gen1_synth_gate_clk", 456 clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk",
461 "pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl, 457 0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
462 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 458 &_lock, &clk1);
463 clk_register_clkdev(clk, "gen1_synth_clk", NULL); 459 clk_register_clkdev(clk, "gen1_syn_clk", NULL);
464 clk_register_clkdev(clk1, "gen1_synth_gate_clk", NULL); 460 clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
465 461
466 clk = clk_register_mux(NULL, "gen2_3_parent_clk", gen2_3_parents, 462 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
467 ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG, 463 ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
468 GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0, 464 GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
469 &_lock); 465 &_lock);
470 clk_register_clkdev(clk, "gen2_3_parent_clk", NULL); 466 clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
471 467
472 clk = clk_register_aux("gen2_synth_clk", "gen2_synth_gate_clk", 468 clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
473 "gen2_3_parent_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl, 469 "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
474 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 470 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
475 clk_register_clkdev(clk, "gen2_synth_clk", NULL); 471 clk_register_clkdev(clk, "gen2_syn_clk", NULL);
476 clk_register_clkdev(clk1, "gen2_synth_gate_clk", NULL); 472 clk_register_clkdev(clk1, "gen2_syn_gclk", NULL);
477 473
478 clk = clk_register_aux("gen3_synth_clk", "gen3_synth_gate_clk", 474 clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk",
479 "gen2_3_parent_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl, 475 "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
480 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 476 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
481 clk_register_clkdev(clk, "gen3_synth_clk", NULL); 477 clk_register_clkdev(clk, "gen3_syn_clk", NULL);
482 clk_register_clkdev(clk1, "gen3_synth_gate_clk", NULL); 478 clk_register_clkdev(clk1, "gen3_syn_gclk", NULL);
483 479
484 /* clock derived from pll3 clk */ 480 /* clock derived from pll3 clk */
485 clk = clk_register_gate(NULL, "usbh_clk", "pll3_48m_clk", 0, 481 clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
486 PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock); 482 USBH_CLK_ENB, 0, &_lock);
487 clk_register_clkdev(clk, "usbh_clk", NULL); 483 clk_register_clkdev(clk, "usbh_clk", NULL);
488 484
489 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, 485 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
@@ -494,8 +490,8 @@ void __init spear3xx_clk_init(void)
494 1); 490 1);
495 clk_register_clkdev(clk, "usbh.1_clk", NULL); 491 clk_register_clkdev(clk, "usbh.1_clk", NULL);
496 492
497 clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0, 493 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
498 PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); 494 USBD_CLK_ENB, 0, &_lock);
499 clk_register_clkdev(clk, NULL, "designware_udc"); 495 clk_register_clkdev(clk, NULL, "designware_udc");
500 496
501 /* clock derived from ahb clk */ 497 /* clock derived from ahb clk */
@@ -579,29 +575,25 @@ void __init spear3xx_clk_init(void)
579 RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock); 575 RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
580 clk_register_clkdev(clk, "ras_pll2_clk", NULL); 576 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
581 577
582 clk = clk_register_gate(NULL, "ras_pll3_48m_clk", "pll3_48m_clk", 0, 578 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
583 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); 579 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
584 clk_register_clkdev(clk, "ras_pll3_48m_clk", NULL); 580 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
585 581
586 clk = clk_register_gate(NULL, "ras_gen0_synth_gate_clk", 582 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", 0,
587 "gen0_synth_gate_clk", 0, RAS_CLK_ENB, 583 RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, &_lock);
588 RAS_SYNT0_CLK_ENB, 0, &_lock); 584 clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
589 clk_register_clkdev(clk, "ras_gen0_synth_gate_clk", NULL); 585
590 586 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", 0,
591 clk = clk_register_gate(NULL, "ras_gen1_synth_gate_clk", 587 RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, &_lock);
592 "gen1_synth_gate_clk", 0, RAS_CLK_ENB, 588 clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
593 RAS_SYNT1_CLK_ENB, 0, &_lock); 589
594 clk_register_clkdev(clk, "ras_gen1_synth_gate_clk", NULL); 590 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", 0,
595 591 RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, &_lock);
596 clk = clk_register_gate(NULL, "ras_gen2_synth_gate_clk", 592 clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
597 "gen2_synth_gate_clk", 0, RAS_CLK_ENB, 593
598 RAS_SYNT2_CLK_ENB, 0, &_lock); 594 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", 0,
599 clk_register_clkdev(clk, "ras_gen2_synth_gate_clk", NULL); 595 RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, &_lock);
600 596 clk_register_clkdev(clk, "ras_syn3_gclk", NULL);
601 clk = clk_register_gate(NULL, "ras_gen3_synth_gate_clk",
602 "gen3_synth_gate_clk", 0, RAS_CLK_ENB,
603 RAS_SYNT3_CLK_ENB, 0, &_lock);
604 clk_register_clkdev(clk, "ras_gen3_synth_gate_clk", NULL);
605 597
606 if (of_machine_is_compatible("st,spear300")) 598 if (of_machine_is_compatible("st,spear300"))
607 spear300_clk_init(); 599 spear300_clk_init();
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index 61026ae564ab..a98d0866f541 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -97,13 +97,12 @@ static struct aux_rate_tbl aux_rtbl[] = {
97 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ 97 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
98}; 98};
99 99
100static const char *clcd_parents[] = { "pll3_48m_clk", "clcd_synth_gate_clk", }; 100static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
101static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk", 101static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
102}; 102static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
103static const char *uart_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", }; 103static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
104static const char *gpt0_1_parents[] = { "pll3_48m_clk", "gpt0_1_synth_clk", }; 104static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
105static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", }; 105static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
106static const char *gpt3_parents[] = { "pll3_48m_clk", "gpt3_synth_clk", };
107static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", 106static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
108 "pll2_clk", }; 107 "pll2_clk", };
109 108
@@ -136,9 +135,9 @@ void __init spear6xx_clk_init(void)
136 clk_register_clkdev(clk, NULL, "rtc-spear"); 135 clk_register_clkdev(clk, NULL, "rtc-spear");
137 136
138 /* clock derived from 30 MHz osc clk */ 137 /* clock derived from 30 MHz osc clk */
139 clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0, 138 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
140 48000000); 139 48000000);
141 clk_register_clkdev(clk, "pll3_48m_clk", NULL); 140 clk_register_clkdev(clk, "pll3_clk", NULL);
142 141
143 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", 142 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
144 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), 143 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
@@ -146,9 +145,9 @@ void __init spear6xx_clk_init(void)
146 clk_register_clkdev(clk, "vco1_clk", NULL); 145 clk_register_clkdev(clk, "vco1_clk", NULL);
147 clk_register_clkdev(clk1, "pll1_clk", NULL); 146 clk_register_clkdev(clk1, "pll1_clk", NULL);
148 147
149 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, 148 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
150 "osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, 149 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
151 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 150 &_lock, &clk1, NULL);
152 clk_register_clkdev(clk, "vco2_clk", NULL); 151 clk_register_clkdev(clk, "vco2_clk", NULL);
153 clk_register_clkdev(clk1, "pll2_clk", NULL); 152 clk_register_clkdev(clk1, "pll2_clk", NULL);
154 153
@@ -165,111 +164,111 @@ void __init spear6xx_clk_init(void)
165 HCLK_RATIO_MASK, 0, &_lock); 164 HCLK_RATIO_MASK, 0, &_lock);
166 clk_register_clkdev(clk, "ahb_clk", NULL); 165 clk_register_clkdev(clk, "ahb_clk", NULL);
167 166
168 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk", 167 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
169 "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, 168 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
170 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 169 &_lock, &clk1);
171 clk_register_clkdev(clk, "uart_synth_clk", NULL); 170 clk_register_clkdev(clk, "uart_syn_clk", NULL);
172 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL); 171 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
173 172
174 clk = clk_register_mux(NULL, "uart_mux_clk", uart_parents, 173 clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
175 ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG, 174 ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG,
176 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); 175 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
177 clk_register_clkdev(clk, "uart_mux_clk", NULL); 176 clk_register_clkdev(clk, "uart_mclk", NULL);
178 177
179 clk = clk_register_gate(NULL, "uart0", "uart_mux_clk", 0, 178 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
180 PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock); 179 UART0_CLK_ENB, 0, &_lock);
181 clk_register_clkdev(clk, NULL, "d0000000.serial"); 180 clk_register_clkdev(clk, NULL, "d0000000.serial");
182 181
183 clk = clk_register_gate(NULL, "uart1", "uart_mux_clk", 0, 182 clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
184 PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock); 183 UART1_CLK_ENB, 0, &_lock);
185 clk_register_clkdev(clk, NULL, "d0080000.serial"); 184 clk_register_clkdev(clk, NULL, "d0080000.serial");
186 185
187 clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk", 186 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
188 "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, 187 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
189 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 188 &_lock, &clk1);
190 clk_register_clkdev(clk, "firda_synth_clk", NULL); 189 clk_register_clkdev(clk, "firda_syn_clk", NULL);
191 clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL); 190 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
192 191
193 clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents, 192 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
194 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, 193 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
195 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); 194 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
196 clk_register_clkdev(clk, "firda_mux_clk", NULL); 195 clk_register_clkdev(clk, "firda_mclk", NULL);
197 196
198 clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0, 197 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
199 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); 198 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
200 clk_register_clkdev(clk, NULL, "firda"); 199 clk_register_clkdev(clk, NULL, "firda");
201 200
202 clk = clk_register_aux("clcd_synth_clk", "clcd_synth_gate_clk", 201 clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
203 "pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl, 202 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
204 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 203 &_lock, &clk1);
205 clk_register_clkdev(clk, "clcd_synth_clk", NULL); 204 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
206 clk_register_clkdev(clk1, "clcd_synth_gate_clk", NULL); 205 clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
207 206
208 clk = clk_register_mux(NULL, "clcd_mux_clk", clcd_parents, 207 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
209 ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG, 208 ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG,
210 CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock); 209 CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock);
211 clk_register_clkdev(clk, "clcd_mux_clk", NULL); 210 clk_register_clkdev(clk, "clcd_mclk", NULL);
212 211
213 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mux_clk", 0, 212 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
214 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); 213 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
215 clk_register_clkdev(clk, NULL, "clcd"); 214 clk_register_clkdev(clk, NULL, "clcd");
216 215
217 /* gpt clocks */ 216 /* gpt clocks */
218 clk = clk_register_gpt("gpt0_1_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG, 217 clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
219 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 218 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
220 clk_register_clkdev(clk, "gpt0_1_synth_clk", NULL); 219 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
221 220
222 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt0_1_parents, 221 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
223 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, 222 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
224 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 223 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
225 clk_register_clkdev(clk, NULL, "gpt0"); 224 clk_register_clkdev(clk, NULL, "gpt0");
226 225
227 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt0_1_parents, 226 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
228 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, 227 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
229 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 228 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
230 clk_register_clkdev(clk, "gpt1_mux_clk", NULL); 229 clk_register_clkdev(clk, "gpt1_mclk", NULL);
231 230
232 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0, 231 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
233 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); 232 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
234 clk_register_clkdev(clk, NULL, "gpt1"); 233 clk_register_clkdev(clk, NULL, "gpt1");
235 234
236 clk = clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG, 235 clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
237 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 236 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
238 clk_register_clkdev(clk, "gpt2_synth_clk", NULL); 237 clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
239 238
240 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents, 239 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
241 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, 240 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
242 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 241 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
243 clk_register_clkdev(clk, "gpt2_mux_clk", NULL); 242 clk_register_clkdev(clk, "gpt2_mclk", NULL);
244 243
245 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0, 244 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
246 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); 245 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
247 clk_register_clkdev(clk, NULL, "gpt2"); 246 clk_register_clkdev(clk, NULL, "gpt2");
248 247
249 clk = clk_register_gpt("gpt3_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG, 248 clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
250 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 249 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
251 clk_register_clkdev(clk, "gpt3_synth_clk", NULL); 250 clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
252 251
253 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt3_parents, 252 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
254 ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG, 253 ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG,
255 GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 254 GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
256 clk_register_clkdev(clk, "gpt3_mux_clk", NULL); 255 clk_register_clkdev(clk, "gpt3_mclk", NULL);
257 256
258 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0, 257 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
259 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); 258 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
260 clk_register_clkdev(clk, NULL, "gpt3"); 259 clk_register_clkdev(clk, NULL, "gpt3");
261 260
262 /* clock derived from pll3 clk */ 261 /* clock derived from pll3 clk */
263 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_48m_clk", 0, 262 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
264 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); 263 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
265 clk_register_clkdev(clk, NULL, "usbh.0_clk"); 264 clk_register_clkdev(clk, NULL, "usbh.0_clk");
266 265
267 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_48m_clk", 0, 266 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
268 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); 267 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
269 clk_register_clkdev(clk, NULL, "usbh.1_clk"); 268 clk_register_clkdev(clk, NULL, "usbh.1_clk");
270 269
271 clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0, 270 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
272 PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); 271 USBD_CLK_ENB, 0, &_lock);
273 clk_register_clkdev(clk, NULL, "designware_udc"); 272 clk_register_clkdev(clk, NULL, "designware_udc");
274 273
275 /* clock derived from ahb clk */ 274 /* clock derived from ahb clk */
@@ -278,9 +277,8 @@ void __init spear6xx_clk_init(void)
278 clk_register_clkdev(clk, "ahbmult2_clk", NULL); 277 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
279 278
280 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, 279 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
281 ARRAY_SIZE(ddr_parents), 280 ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
282 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, 281 MCTR_CLK_MASK, 0, &_lock);
283 &_lock);
284 clk_register_clkdev(clk, "ddr_clk", NULL); 282 clk_register_clkdev(clk, "ddr_clk", NULL);
285 283
286 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", 284 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 11:32:40 -0500