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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-03-26 19:45:00 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-03-27 20:09:34 -0400
commitbaba133ae50e563c5896d39e150b6617857a9d8e (patch)
treebc09bd4cee8fb68dce78f65eb36cb923e0a28d91
parent3600836585e3fdef0a1410d63fe5ce4015007aac (diff)
drm/i915: clean up plane bpp confusion
- There is no 16bpc linear color format in our hw. gen4+ has a 16 bpc float layout, but we don't really support it. - 10bpc is a gen4+ feature, fix up the support for it. - Update_plane should never see a wrong fb bpp value, BUG in the corresponding cases. v2: Rebase on top of Ville's plane pixel layout changes. v3: Actually drop the old gen4 check for 10bpc planes, spotted by Ville Syrjälä. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c20
1 files changed, 8 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e95c469afa6d..70c22b12b7c9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2113,8 +2113,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2113 dspcntr |= DISPPLANE_RGBX101010; 2113 dspcntr |= DISPPLANE_RGBX101010;
2114 break; 2114 break;
2115 default: 2115 default:
2116 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); 2116 BUG();
2117 return -EINVAL;
2118 } 2117 }
2119 2118
2120 if (INTEL_INFO(dev)->gen >= 4) { 2119 if (INTEL_INFO(dev)->gen >= 4) {
@@ -2207,8 +2206,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
2207 dspcntr |= DISPPLANE_RGBX101010; 2206 dspcntr |= DISPPLANE_RGBX101010;
2208 break; 2207 break;
2209 default: 2208 default:
2210 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); 2209 BUG();
2211 return -EINVAL;
2212 } 2210 }
2213 2211
2214 if (obj->tiling_mode != I915_TILING_NONE) 2212 if (obj->tiling_mode != I915_TILING_NONE)
@@ -7400,21 +7398,19 @@ pipe_config_set_bpp(struct drm_crtc *crtc,
7400 bpp = 8*3; 7398 bpp = 8*3;
7401 break; 7399 break;
7402 case 30: 7400 case 30:
7401 if (INTEL_INFO(dev)->gen < 4) {
7402 DRM_DEBUG_KMS("10 bpc not supported on gen2/3\n");
7403 return -EINVAL;
7404 }
7405
7403 bpp = 10*3; 7406 bpp = 10*3;
7404 break; 7407 break;
7405 case 48: 7408 /* TODO: gen4+ supports 16 bpc floating point, too. */
7406 bpp = 12*3;
7407 break;
7408 default: 7409 default:
7409 DRM_DEBUG_KMS("unsupported depth\n"); 7410 DRM_DEBUG_KMS("unsupported depth\n");
7410 return -EINVAL; 7411 return -EINVAL;
7411 } 7412 }
7412 7413
7413 if (fb->depth > 24 && !HAS_PCH_SPLIT(dev)) {
7414 DRM_DEBUG_KMS("high depth not supported on gmch platforms\n");
7415 return -EINVAL;
7416 }
7417
7418 pipe_config->pipe_bpp = bpp; 7414 pipe_config->pipe_bpp = bpp;
7419 7415
7420 /* Clamp display bpp to EDID value */ 7416 /* Clamp display bpp to EDID value */