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authorYuvaraj Kumar C D <yuvaraj.cd@samsung.com>2014-03-17 18:49:14 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-03-17 18:49:14 -0400
commitba0d7ed391b7b3fb5ca98d9cf4d067b7f5ed956b (patch)
treec4ef7983ba455208a9952b39046f9344708efd25
parent183af2522da5d02fd1d682e105ee4d60a685c05e (diff)
ARM: dts: enable ahci sata and sata phy for exynos5250
This patch adds dt entry for ahci sata controller and its corresponding phy controller.phy node has been added w.r.t new generic phy framework. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--Documentation/devicetree/bindings/ata/exynos-sata-phy.txt14
-rw-r--r--Documentation/devicetree/bindings/ata/exynos-sata.txt25
-rw-r--r--Documentation/devicetree/bindings/phy/samsung-phy.txt36
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts21
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts17
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi18
6 files changed, 98 insertions, 33 deletions
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
deleted file mode 100644
index 37824fac688e..000000000000
--- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
+++ /dev/null
@@ -1,14 +0,0 @@
1* Samsung SATA PHY Controller
2
3SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
4Each SATA PHY controller should have its own node.
5
6Required properties:
7- compatible : compatible list, contains "samsung,exynos5-sata-phy"
8- reg : <registers mapping>
9
10Example:
11 sata@ffe07000 {
12 compatible = "samsung,exynos5-sata-phy";
13 reg = <0xffe07000 0x1000>;
14 };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
index 0849f1025e34..b2adb1f3090e 100644
--- a/Documentation/devicetree/bindings/ata/exynos-sata.txt
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -4,14 +4,21 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
4Each SATA controller should have its own node. 4Each SATA controller should have its own node.
5 5
6Required properties: 6Required properties:
7- compatible : compatible list, contains "samsung,exynos5-sata" 7- compatible : compatible list, contains "samsung,exynos5-sata"
8- interrupts : <interrupt mapping for SATA IRQ> 8- interrupts : <interrupt mapping for SATA IRQ>
9- reg : <registers mapping> 9- reg : <registers mapping>
10- samsung,sata-freq : <frequency in MHz> 10- samsung,sata-freq : <frequency in MHz>
11- phys : as mentioned in phy-bindings.txt
12- phy-names : as mentioned in phy-bindings.txt
11 13
12Example: 14Example:
13 sata@ffe08000 { 15 sata@122f0000 {
14 compatible = "samsung,exynos5-sata"; 16 compatible = "snps,dwc-ahci";
15 reg = <0xffe08000 0x1000>; 17 samsung,sata-freq = <66>;
16 interrupts = <115>; 18 reg = <0x122f0000 0x1ff>;
17 }; 19 interrupts = <0 115 0>;
20 clocks = <&clock 277>, <&clock 143>;
21 clock-names = "sata", "sclk_sata";
22 phys = <&sata_phy>;
23 phy-names = "sata-phy";
24 };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa1671e..a937f75d062c 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,39 @@ Required properties:
20- compatible : should be "samsung,exynos5250-dp-video-phy"; 20- compatible : should be "samsung,exynos5250-dp-video-phy";
21- reg : offset and length of the Display Port PHY register set; 21- reg : offset and length of the Display Port PHY register set;
22- #phy-cells : from the generic PHY bindings, must be 0; 22- #phy-cells : from the generic PHY bindings, must be 0;
23
24Samsung SATA PHY Controller
25---------------------------
26
27SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
28Each SATA PHY controller should have its own node.
29
30Required properties:
31- compatible : compatible list, contains "samsung,exynos5250-sata-phy"
32- reg : offset and length of the SATA PHY register set;
33- #phy-cells : from the generic phy bindings;
34
35Example:
36 sata_phy: sata-phy@12170000 {
37 compatible = "samsung,exynos5250-sata-phy";
38 reg = <0x12170000 0x1ff>;
39 clocks = <&clock 287>;
40 clock-names = "sata_phyctrl";
41 #phy-cells = <0>;
42 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
43 samsung,syscon-phandle = <&pmu_syscon>;
44 };
45
46Device-Tree bindings for sataphy i2c client driver
47--------------------------------------------------
48
49Required properties:
50compatible: Should be "samsung,exynos-sataphy-i2c"
51- reg: I2C address of the sataphy i2c device.
52
53Example:
54
55 sata_phy_i2c:sata-phy@38 {
56 compatible = "samsung,exynos-sataphy-i2c";
57 reg = <0x38>;
58 };
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 56c40783c3eb..9a78d96f8477 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -374,6 +374,27 @@
374 }; 374 };
375 }; 375 };
376 376
377 i2c@121D0000 {
378 status = "okay";
379 samsung,i2c-sda-delay = <100>;
380 samsung,i2c-max-bus-freq = <40000>;
381 samsung,i2c-slave-addr = <0x38>;
382
383 sata_phy_i2c:sata-phy@38 {
384 compatible = "samsung,exynos-sataphy-i2c";
385 reg = <0x38>;
386 };
387 };
388
389 sata@122F0000 {
390 status = "okay";
391 };
392
393 sata-phy@12170000 {
394 status = "okay";
395 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
396 };
397
377 mmc_0: mmc@12200000 { 398 mmc_0: mmc@12200000 {
378 status = "okay"; 399 status = "okay";
379 num-slots = <1>; 400 num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 736eb3441bc3..140de8563e94 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -242,16 +242,12 @@
242 samsung,i2c-slave-addr = <0x38>; 242 samsung,i2c-slave-addr = <0x38>;
243 status = "okay"; 243 status = "okay";
244 244
245 sata-phy { 245 sata_phy_i2c:sata-phy@38 {
246 compatible = "samsung,sata-phy"; 246 compatible = "samsung,exynos-sataphy-i2c";
247 reg = <0x38>; 247 reg = <0x38>;
248 }; 248 };
249 }; 249 };
250 250
251 sata@122F0000 {
252 samsung,sata-freq = <66>;
253 };
254
255 i2c@12C80000 { 251 i2c@12C80000 {
256 samsung,i2c-sda-delay = <100>; 252 samsung,i2c-sda-delay = <100>;
257 samsung,i2c-max-bus-freq = <66000>; 253 samsung,i2c-max-bus-freq = <66000>;
@@ -274,6 +270,15 @@
274 }; 270 };
275 }; 271 };
276 272
273 sata@122F0000 {
274 status = "okay";
275 };
276
277 sata-phy@12170000 {
278 status = "okay";
279 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
280 };
281
277 mmc@12200000 { 282 mmc@12200000 {
278 status = "okay"; 283 status = "okay";
279 num-slots = <1>; 284 num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 9ecffcb1fe91..fdeed7c29ac9 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -47,6 +47,7 @@
47 i2c6 = &i2c_6; 47 i2c6 = &i2c_6;
48 i2c7 = &i2c_7; 48 i2c7 = &i2c_7;
49 i2c8 = &i2c_8; 49 i2c8 = &i2c_8;
50 i2c9 = &i2c_9;
50 pinctrl0 = &pinctrl_0; 51 pinctrl0 = &pinctrl_0;
51 pinctrl1 = &pinctrl_1; 52 pinctrl1 = &pinctrl_1;
52 pinctrl2 = &pinctrl_2; 53 pinctrl2 = &pinctrl_2;
@@ -235,16 +236,25 @@
235 }; 236 };
236 237
237 sata@122F0000 { 238 sata@122F0000 {
238 compatible = "samsung,exynos5-sata-ahci"; 239 compatible = "snps,dwc-ahci";
240 samsung,sata-freq = <66>;
239 reg = <0x122F0000 0x1ff>; 241 reg = <0x122F0000 0x1ff>;
240 interrupts = <0 115 0>; 242 interrupts = <0 115 0>;
241 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 243 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
242 clock-names = "sata", "sclk_sata"; 244 clock-names = "sata", "sclk_sata";
245 phys = <&sata_phy>;
246 phy-names = "sata-phy";
247 status = "disabled";
243 }; 248 };
244 249
245 sata-phy@12170000 { 250 sata_phy: sata-phy@12170000 {
246 compatible = "samsung,exynos5-sata-phy"; 251 compatible = "samsung,exynos5250-sata-phy";
247 reg = <0x12170000 0x1ff>; 252 reg = <0x12170000 0x1ff>;
253 clocks = <&clock 287>;
254 clock-names = "sata_phyctrl";
255 #phy-cells = <0>;
256 samsung,syscon-phandle = <&pmu_system_controller>;
257 status = "disabled";
248 }; 258 };
249 259
250 i2c_0: i2c@12C60000 { 260 i2c_0: i2c@12C60000 {
@@ -362,7 +372,7 @@
362 status = "disabled"; 372 status = "disabled";
363 }; 373 };
364 374
365 i2c@121D0000 { 375 i2c_9: i2c@121D0000 {
366 compatible = "samsung,exynos5-sata-phy-i2c"; 376 compatible = "samsung,exynos5-sata-phy-i2c";
367 reg = <0x121D0000 0x100>; 377 reg = <0x121D0000 0x100>;
368 #address-cells = <1>; 378 #address-cells = <1>;