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authorHeiko Stübner <heiko@sntech.de>2014-07-02 20:02:37 -0400
committerMike Turquette <mturquette@linaro.org>2014-07-13 15:17:10 -0400
commitb9e4ba541607e6ee9c6c8493f51198fe3af03aec (patch)
tree886b115b0e14b3224dc196ebb5755946a40ee0d3
parent5775b82e74d1b307b7dab670993b6b838c92f786 (diff)
clk: rockchip: add clock controller for rk3288
Add the clock tree definition for the new rk3288 SoC. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat
-rw-r--r--drivers/clk/rockchip/Makefile1
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c717
-rw-r--r--drivers/clk/rockchip/clk.h9
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h278
4 files changed, 1005 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 3eebf72fe91f..ee6b077381e1 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -8,3 +8,4 @@ obj-y += clk-pll.o
8obj-$(CONFIG_RESET_CONTROLLER) += softrst.o 8obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
9 9
10obj-y += clk-rk3188.o 10obj-y += clk-rk3188.o
11obj-y += clk-rk3288.o
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
new file mode 100644
index 000000000000..0d8c6c59a75e
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -0,0 +1,717 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <dt-bindings/clock/rk3288-cru.h>
20#include "clk.h"
21
22#define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
23#define RK3288_GRF_SOC_STATUS 0x280
24
25enum rk3288_plls {
26 apll, dpll, cpll, gpll, npll,
27};
28
29struct rockchip_pll_rate_table rk3288_pll_rates[] = {
30 RK3066_PLL_RATE(2208000000, 1, 92, 1),
31 RK3066_PLL_RATE(2184000000, 1, 91, 1),
32 RK3066_PLL_RATE(2160000000, 1, 90, 1),
33 RK3066_PLL_RATE(2136000000, 1, 89, 1),
34 RK3066_PLL_RATE(2112000000, 1, 88, 1),
35 RK3066_PLL_RATE(2088000000, 1, 87, 1),
36 RK3066_PLL_RATE(2064000000, 1, 86, 1),
37 RK3066_PLL_RATE(2040000000, 1, 85, 1),
38 RK3066_PLL_RATE(2016000000, 1, 84, 1),
39 RK3066_PLL_RATE(1992000000, 1, 83, 1),
40 RK3066_PLL_RATE(1968000000, 1, 82, 1),
41 RK3066_PLL_RATE(1944000000, 1, 81, 1),
42 RK3066_PLL_RATE(1920000000, 1, 80, 1),
43 RK3066_PLL_RATE(1896000000, 1, 79, 1),
44 RK3066_PLL_RATE(1872000000, 1, 78, 1),
45 RK3066_PLL_RATE(1848000000, 1, 77, 1),
46 RK3066_PLL_RATE(1824000000, 1, 76, 1),
47 RK3066_PLL_RATE(1800000000, 1, 75, 1),
48 RK3066_PLL_RATE(1776000000, 1, 74, 1),
49 RK3066_PLL_RATE(1752000000, 1, 73, 1),
50 RK3066_PLL_RATE(1728000000, 1, 72, 1),
51 RK3066_PLL_RATE(1704000000, 1, 71, 1),
52 RK3066_PLL_RATE(1680000000, 1, 70, 1),
53 RK3066_PLL_RATE(1656000000, 1, 69, 1),
54 RK3066_PLL_RATE(1632000000, 1, 68, 1),
55 RK3066_PLL_RATE(1608000000, 1, 67, 1),
56 RK3066_PLL_RATE(1560000000, 1, 65, 1),
57 RK3066_PLL_RATE(1512000000, 1, 63, 1),
58 RK3066_PLL_RATE(1488000000, 1, 62, 1),
59 RK3066_PLL_RATE(1464000000, 1, 61, 1),
60 RK3066_PLL_RATE(1440000000, 1, 60, 1),
61 RK3066_PLL_RATE(1416000000, 1, 59, 1),
62 RK3066_PLL_RATE(1392000000, 1, 58, 1),
63 RK3066_PLL_RATE(1368000000, 1, 57, 1),
64 RK3066_PLL_RATE(1344000000, 1, 56, 1),
65 RK3066_PLL_RATE(1320000000, 1, 55, 1),
66 RK3066_PLL_RATE(1296000000, 1, 54, 1),
67 RK3066_PLL_RATE(1272000000, 1, 53, 1),
68 RK3066_PLL_RATE(1248000000, 1, 52, 1),
69 RK3066_PLL_RATE(1224000000, 1, 51, 1),
70 RK3066_PLL_RATE(1200000000, 1, 50, 1),
71 RK3066_PLL_RATE(1188000000, 2, 99, 1),
72 RK3066_PLL_RATE(1176000000, 1, 49, 1),
73 RK3066_PLL_RATE(1128000000, 1, 47, 1),
74 RK3066_PLL_RATE(1104000000, 1, 46, 1),
75 RK3066_PLL_RATE(1008000000, 1, 84, 2),
76 RK3066_PLL_RATE( 912000000, 1, 76, 2),
77 RK3066_PLL_RATE( 891000000, 8, 594, 2),
78 RK3066_PLL_RATE( 888000000, 1, 74, 2),
79 RK3066_PLL_RATE( 816000000, 1, 68, 2),
80 RK3066_PLL_RATE( 798000000, 2, 133, 2),
81 RK3066_PLL_RATE( 792000000, 1, 66, 2),
82 RK3066_PLL_RATE( 768000000, 1, 64, 2),
83 RK3066_PLL_RATE( 742500000, 8, 495, 2),
84 RK3066_PLL_RATE( 696000000, 1, 58, 2),
85 RK3066_PLL_RATE( 600000000, 1, 50, 2),
86 RK3066_PLL_RATE( 594000000, 2, 198, 4),
87 RK3066_PLL_RATE( 552000000, 1, 46, 2),
88 RK3066_PLL_RATE( 504000000, 1, 84, 4),
89 RK3066_PLL_RATE( 456000000, 1, 76, 4),
90 RK3066_PLL_RATE( 408000000, 1, 68, 4),
91 RK3066_PLL_RATE( 384000000, 2, 128, 4),
92 RK3066_PLL_RATE( 360000000, 1, 60, 4),
93 RK3066_PLL_RATE( 312000000, 1, 52, 4),
94 RK3066_PLL_RATE( 300000000, 1, 50, 4),
95 RK3066_PLL_RATE( 297000000, 2, 198, 8),
96 RK3066_PLL_RATE( 252000000, 1, 84, 8),
97 RK3066_PLL_RATE( 216000000, 1, 72, 8),
98 RK3066_PLL_RATE( 148500000, 2, 99, 8),
99 RK3066_PLL_RATE( 126000000, 1, 84, 16),
100 RK3066_PLL_RATE( 48000000, 1, 64, 32),
101 { /* sentinel */ },
102};
103
104PNAME(mux_pll_p) = { "xin24m", "xin32k" };
105PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
106PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
107PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
108
109PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
110PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
111PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
112PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
113
114PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
115PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
116PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
117PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
118PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
119PNAME(mux_uart0_pll_p) = { "cpll", "gpll", "usbphy_480m_src", "npll" };
120PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
121PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
122PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
123PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
124PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
125PNAME(mux_cif_out_p) = { "cif_src", "xin24m" };
126PNAME(mux_macref_p) = { "mac_src", "ext_gmac" };
127PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
128PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
129PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
130
131PNAME(mux_usbphy480m_p) = { "sclk_otgphy0", "sclk_otgphy1",
132 "sclk_otgphy2" };
133PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
134PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
135
136static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
137 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
138 RK3288_MODE_CON, 0, 6, rk3288_pll_rates),
139 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
140 RK3288_MODE_CON, 4, 5, NULL),
141 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
142 RK3288_MODE_CON, 8, 7, rk3288_pll_rates),
143 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
144 RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
145 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
146 RK3288_MODE_CON, 14, 9, NULL),
147};
148
149static struct clk_div_table div_hclk_cpu_t[] = {
150 { .val = 0, .div = 1 },
151 { .val = 1, .div = 2 },
152 { .val = 3, .div = 4 },
153 { /* sentinel */},
154};
155
156#define MFLAGS CLK_MUX_HIWORD_MASK
157#define DFLAGS CLK_DIVIDER_HIWORD_MASK
158#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
159
160static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
161 /*
162 * Clock-Architecture Diagram 1
163 */
164
165 GATE(0, "apll_core", "apll", 0,
166 RK3288_CLKGATE_CON(0), 1, GFLAGS),
167 GATE(0, "gpll_core", "gpll", 0,
168 RK3288_CLKGATE_CON(0), 2, GFLAGS),
169 COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
170 RK3288_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
171
172 COMPOSITE_NOMUX(0, "armcore0", "armclk", 0,
173 RK3288_CLKSEL_CON(36), 0, 3, DFLAGS,