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authorStephen George <stephen.george@freescale.com>2011-09-16 11:36:34 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-10-12 00:47:29 -0400
commitb9df02231930c01eaaf3c37b192bd75ea0d1c0bb (patch)
tree6c92b1f1872311e3ae35d4e6366a6032035ae587
parent499ccb27a89ecd08475f73710fe27fb600431a91 (diff)
powerpc/85xx: Adding DCSR node to dtsi device trees
Adding new device tree binding file for the DCSR node. Modifying device tree dtsi files to add DCSR node for P2041, P3041, P4080, & P5020. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt395
-rw-r--r--arch/powerpc/boot/dts/p2041rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/p2041si.dtsi71
-rw-r--r--arch/powerpc/boot/dts/p3041ds.dts4
-rw-r--r--arch/powerpc/boot/dts/p3041si.dtsi71
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts4
-rw-r--r--arch/powerpc/boot/dts/p4080si.dtsi98
-rw-r--r--arch/powerpc/boot/dts/p5020ds.dts4
-rw-r--r--arch/powerpc/boot/dts/p5020si.dtsi68
9 files changed, 713 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt b/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
new file mode 100644
index 000000000000..9d54eb5a295f
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
@@ -0,0 +1,395 @@
1===================================================================
2Debug Control and Status Register (DCSR) Binding
3Copyright 2011 Freescale Semiconductor Inc.
4
5NOTE: The bindings described in this document are preliminary and subject
6to change. Some of the compatible strings that contain only generic names
7may turn out to be inappropriate, or need additional properties to describe
8the integration of the block with the rest of the chip.
9
10=====================================================================
11Debug Control and Status Register Memory Map
12
13Description
14
15This node defines the base address and range for the
16defined DCSR Memory Map. Child nodes will describe the individual
17debug blocks defined within this memory space.
18
19PROPERTIES
20
21 - compatible
22 Usage: required
23 Value type: <string>
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
26
27 - #address-cells
28 Usage: required
29 Value type: <u32>
30 Definition: A standard property. Defines the number of cells
31 or representing physical addresses in child nodes.
32
33 - #size-cells
34 Usage: required
35 Value type: <u32>
36 Definition: A standard property. Defines the number of cells
37 or representing the size of physical addresses in
38 child nodes.
39
40 - ranges
41 Usage: required
42 Value type: <prop-encoded-array>
43 Definition: A standard property. Specifies the physical address
44 range of the DCSR space.
45
46EXAMPLE
47 dcsr: dcsr@f00000000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "fsl,dcsr", "simple-bus";
51 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
52 };
53
54=====================================================================
55Event Processing Unit
56
57This node represents the region of DCSR space allocated to the EPU
58
59PROPERTIES
60
61 - compatible
62 Usage: required
63 Value type: <string>
64 Definition: Must include "fsl,dcsr-epu"
65
66 - interrupts
67 Usage: required
68 Value type: <prop_encoded-array>
69 Definition: Specifies the interrupts generated by the EPU.
70 The value of the interrupts property consists of three
71 interrupt specifiers. The format of the specifier is defined
72 by the binding document describing the node's interrupt parent.
73
74 The EPU counters can be configured to assert the performance
75 monitor interrupt signal based on either counter overflow or value
76 match. Which counter asserted the interrupt is captured in an EPU
77 Counter Interrupt Status Register (EPCPUISR).
78
79 The EPU unit can also be configured to assert either or both of
80 two interrupt signals based on debug event sources within the SoC.
81 The interrupt signals are epu_xt_int0 and epu_xt_int1.
82 Which event source asserted the interrupt is captured in an EPU
83 Interrupt Status Register (EPISR0,EPISR1).
84
85 Interrupt numbers are lised in order (perfmon, event0, event1).
86
87 - interrupt-parent
88 Usage: required
89 Value type: <phandle>
90 Definition: A single <phandle> value that points
91 to the interrupt parent to which the child domain
92 is being mapped. Value must be "&mpic"
93
94 - reg
95 Usage: required
96 Value type: <prop-encoded-array>
97 Definition: A standard property. Specifies the physical address
98 offset and length of the DCSR space registers of the device
99 configuration block.
100
101EXAMPLE
102 dcsr-epu@0 {
103 compatible = "fsl,dcsr-epu";
104 interrupts = <52 2 0 0
105 84 2 0 0
106 85 2 0 0>;
107 interrupt-parent = <&mpic>;
108 reg = <0x0 0x1000>;
109 };
110
111=======================================================================
112Nexus Port Controller
113
114This node represents the region of DCSR space allocated to the NPC
115
116PROPERTIES
117
118 - compatible
119 Usage: required
120 Value type: <string>
121 Definition: Must include "fsl,dcsr-npc"
122
123 - reg
124 Usage: required
125 Value type: <prop-encoded-array>
126 Definition: A standard property. Specifies the physical address
127 offset and length of the DCSR space registers of the device
128 configuration block.
129 The Nexus Port controller occupies two regions in the DCSR space
130 with distinct functionality.
131
132 The first register range describes the Nexus Port Controller
133 control and status registers.
134
135 The second register range describes the Nexus Port Controller
136 internal trace buffer. The NPC trace buffer is a small memory buffer
137 which stages the nexus trace data for transmission via the Aurora port
138 or to a DDR based trace buffer. In some configurations the NPC trace
139 buffer can be the only trace buffer used.
140
141
142EXAMPLE
143 dcsr-npc {
144 compatible = "fsl,dcsr-npc";
145 reg = <0x1000 0x1000 0x1000000 0x8000>;
146 };
147
148=======================================================================
149Nexus Concentrator
150
151This node represents the region of DCSR space allocated to the NXC
152
153PROPERTIES
154
155 - compatible
156 Usage: required
157 Value type: <string>
158 Definition: Must include "fsl,dcsr-nxc"
159
160 - reg
161 Usage: required
162 Value type: <prop-encoded-array>
163 Definition: A standard property. Specifies the physical address
164 offset and length of the DCSR space registers of the device
165 configuration block.
166
167EXAMPLE
168 dcsr-nxc@2000 {
169 compatible = "fsl,dcsr-nxc";
170 reg = <0x2000 0x1000>;
171 };
172=======================================================================
173CoreNet Debug Controller
174
175This node represents the region of DCSR space allocated to
176the CoreNet Debug controller.
177
178PROPERTIES
179
180 - compatible
181 Usage: required
182 Value type: <string>
183 Definition: Must include "fsl,dcsr-corenet"
184
185 - reg
186 Usage: required
187 Value type: <prop-encoded-array>
188 Definition: A standard property. Specifies the physical address
189 offset and length of the DCSR space registers of the device
190 configuration block.
191 The CoreNet Debug controller occupies two regions in the DCSR space
192 with distinct functionality.
193
194 The first register range describes the CoreNet Debug Controller
195 functionalty to perform transaction and transaction attribute matches.
196
197 The second register range describes the CoreNet Debug Controller
198 functionalty to trigger event notifications and debug traces.
199
200EXAMPLE
201 dcsr-corenet {
202 compatible = "fsl,dcsr-corenet";
203 reg = <0x8000 0x1000 0xB0000 0x1000>;
204 };
205
206=======================================================================
207Data Path Debug controller
208
209This node represents the region of DCSR space allocated to
210the DPAA Debug Controller. This controller controls debug configuration
211for the QMAN and FMAN blocks.
212
213PROPERTIES
214
215 - compatible
216 Usage: required
217 Value type: <string>
218 Definition: Must include both an identifier specific to the SoC
219 or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
220 generic compatible string "fsl,dcsr-dpaa".
221
222 - reg
223 Usage: required
224 Value type: <prop-encoded-array>
225 Definition: A standard property. Specifies the physical address
226 offset and length of the DCSR space registers of the device
227 configuration block.
228
229EXAMPLE
230 dcsr-dpaa@9000 {
231 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
232 reg = <0x9000 0x1000>;
233 };
234
235=======================================================================
236OCeaN Debug controller
237
238This node represents the region of DCSR space allocated to
239the OCN Debug Controller.
240
241PROPERTIES
242
243 - compatible
244 Usage: required
245 Value type: <string>
246 Definition: Must include both an identifier specific to the SoC
247 or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
248 generic compatible string "fsl,dcsr-ocn".
249
250 - reg
251 Usage: required
252 Value type: <prop-encoded-array>
253 Definition: A standard property. Specifies the physical address
254 offset and length of the DCSR space registers of the device
255 configuration block.
256
257EXAMPLE
258 dcsr-ocn@11000 {
259 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
260 reg = <0x11000 0x1000>;
261 };
262
263=======================================================================
264DDR Controller Debug controller
265
266This node represents the region of DCSR space allocated to
267the OCN Debug Controller.
268
269PROPERTIES
270
271 - compatible
272 Usage: required
273 Value type: <string>
274 Definition: Must include "fsl,dcsr-ddr"
275
276 - dev-handle
277 Usage: required
278 Definition: A phandle to associate this debug node with its
279 component controller.
280
281 - reg
282 Usage: required
283 Value type: <prop-encoded-array>
284 Definition: A standard property. Specifies the physical address
285 offset and length of the DCSR space registers of the device
286 configuration block.
287
288EXAMPLE
289 dcsr-ddr@12000 {
290 compatible = "fsl,dcsr-ddr";
291 dev-handle = <&ddr1>;
292 reg = <0x12000 0x1000>;
293 };
294
295=======================================================================
296Nexus Aurora Link Controller
297
298This node represents the region of DCSR space allocated to
299the NAL Controller.
300
301PROPERTIES
302
303 - compatible
304 Usage: required
305 Value type: <string>
306 Definition: Must include both an identifier specific to the SoC
307 or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
308 generic compatible string "fsl,dcsr-nal".
309
310 - reg
311 Usage: required
312 Value type: <prop-encoded-array>
313 Definition: A standard property. Specifies the physical address
314 offset and length of the DCSR space registers of the device
315 configuration block.
316
317EXAMPLE
318 dcsr-nal@18000 {
319 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
320 reg = <0x18000 0x1000>;
321 };
322
323
324=======================================================================
325Run Control and Power Management
326
327This node represents the region of DCSR space allocated to
328the RCPM Debug Controller. This functionlity is limited to the
329control the debug operations of the SoC and cores.
330
331PROPERTIES
332
333 - compatible
334 Usage: required
335 Value type: <string>
336 Definition: Must include both an identifier specific to the SoC
337 or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
338 generic compatible string "fsl,dcsr-rcpm".
339
340 - reg
341 Usage: required
342 Value type: <prop-encoded-array>
343 Definition: A standard property. Specifies the physical address
344 offset and length of the DCSR space registers of the device
345 configuration block.
346
347EXAMPLE
348 dcsr-rcpm@22000 {
349 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
350 reg = <0x22000 0x1000>;
351 };
352
353=======================================================================
354Core Service Bridge Proxy
355
356This node represents the region of DCSR space allocated to
357the Core Service Bridge Proxies.
358There is one Core Service Bridge Proxy device for each CPU in the system.
359This functionlity provides access to the debug operations of the CPU.
360
361PROPERTIES
362
363 - compatible
364 Usage: required
365 Value type: <string>
366 Definition: Must include both an identifier specific to the cpu
367 of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
368 generic compatible string "fsl,dcsr-cpu-sb-proxy".
369
370 - cpu-handle
371 Usage: required
372 Definition: A phandle to associate this debug node with its cpu.
373
374 - reg
375 Usage: required
376 Value type: <prop-encoded-array>
377 Definition: A standard property. Specifies the physical address
378 offset and length of the DCSR space registers of the device
379 configuration block.
380
381EXAMPLE
382 dcsr-cpu-sb-proxy@40000 {
383 compatible = "fsl,dcsr-e500mc-sb-proxy",
384 "fsl,dcsr-cpu-sb-proxy";
385 cpu-handle = <&cpu0>;
386 reg = <0x40000 0x1000>;
387 };
388 dcsr-cpu-sb-proxy@41000 {
389 compatible = "fsl,dcsr-e500mc-sb-proxy",
390 "fsl,dcsr-cpu-sb-proxy";
391 cpu-handle = <&cpu1>;
392 reg = <0x41000 0x1000>;
393 };
394
395=======================================================================
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
index 47bb461cf72a..79b6895027c0 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -45,6 +45,10 @@
45 device_type = "memory"; 45 device_type = "memory";
46 }; 46 };
47 47
48 dcsr: dcsr@f00000000 {
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
50 };
51
48 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
49 spi@110000 { 53 spi@110000 {
50 flash@0 { 54 flash@0 {
diff --git a/arch/powerpc/boot/dts/p2041si.dtsi b/arch/powerpc/boot/dts/p2041si.dtsi
index 420cdb0f403d..f7492edd0dfd 100644
--- a/arch/powerpc/boot/dts/p2041si.dtsi
+++ b/arch/powerpc/boot/dts/p2041si.dtsi
@@ -42,6 +42,7 @@
42 42
43 aliases { 43 aliases {
44 ccsr = &soc; 44 ccsr = &soc;
45 dcsr = &dcsr;
45 46
46 serial0 = &serial0; 47 serial0 = &serial0;
47 serial1 = &serial1; 48 serial1 = &serial1;
@@ -109,6 +110,74 @@
109 }; 110 };
110 }; 111 };
111 112
113 dcsr: dcsr@f00000000 {
114 #address-cells = <1>;
115 #size-cells = <1>;
116 compatible = "fsl,dcsr", "simple-bus";
117
118 dcsr-epu@0 {
119 compatible = "fsl,dcsr-epu";
120 interrupts = <52 2 0 0
121 84 2 0 0
122 85 2 0 0>;
123 interrupt-parent = <&mpic>;
124 reg = <0x0 0x1000>;
125 };
126 dcsr-npc {
127 compatible = "fsl,dcsr-npc";
128 reg = <0x1000 0x1000 0x1000000 0x8000>;
129 };
130 dcsr-nxc@2000 {
131 compatible = "fsl,dcsr-nxc";
132 reg = <0x2000 0x1000>;
133 };
134 dcsr-corenet {
135 compatible = "fsl,dcsr-corenet";
136 reg = <0x8000 0x1000 0xB0000 0x1000>;
137 };
138 dcsr-dpaa@9000 {
139 compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
140 reg = <0x9000 0x1000>;
141 };
142 dcsr-ocn@11000 {
143 compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
144 reg = <0x11000 0x1000>;
145 };
146 dcsr-ddr@12000 {
147 compatible = "fsl,dcsr-ddr";
148 dev-handle = <&ddr>;
149 reg = <0x12000 0x1000>;
150 };
151 dcsr-nal@18000 {
152 compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
153 reg = <0x18000 0x1000>;
154 };
155 dcsr-rcpm@22000 {
156 compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
157 reg = <0x22000 0x1000>;
158 };
159 dcsr-cpu-sb-proxy@40000 {
160 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
161 cpu-handle = <&cpu0>;
162 reg = <0x40000 0x1000>;
163 };
164 dcsr-cpu-sb-proxy@41000 {
165 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
166 cpu-handle = <&cpu1>;
167 reg = <0x41000 0x1000>;
168 };
169 dcsr-cpu-sb-proxy@42000 {
170 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
171 cpu-handle = <&cpu2>;
172 reg = <0x42000 0x1000>;
173 };
174 dcsr-cpu-sb-proxy@43000 {
175 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
176 cpu-handle = <&cpu3>;
177 reg = <0x43000 0x1000>;
178 };
179 };
180
112 soc: soc@ffe000000 { 181 soc: soc@ffe000000 {
113 #address-cells = <1>; 182 #address-cells = <1>;
114 #size-cells = <1>; 183 #size-cells = <1>;
@@ -128,7 +197,7 @@
128 fsl,num-laws = <32>; 197 fsl,num-laws = <32>;
129 }; 198 };
130 199
131 memory-controller@8000 { 200 ddr: memory-controller@8000 {
132 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 201 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
133 reg = <0x8000 0x1000>; 202 reg = <0x8000 0x1000>;
134 interrupts = <16 2 1 23>; 203 interrupts = <16 2 1 23>;
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
index 961a74cd1e95..bbd113b49a8f 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -45,6 +45,10 @@
45 device_type = "memory"; 45 device_type = "memory";
46 }; 46 };
47 47
48 dcsr: dcsr@f00000000 {
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
50 };
51
48 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
49 spi@110000 { 53 spi@110000 {
50 flash@0 { 54 flash@0 {
diff --git a/arch/powerpc/boot/dts/p3041si.dtsi b/arch/powerpc/boot/dts/p3041si.dtsi
index 8b695801f505..87130b732bc7 100644
--- a/arch/powerpc/boot/dts/p3041si.dtsi
+++ b/arch/powerpc/boot/dts/p3041si.dtsi
@@ -42,6 +42,7 @@
42 42
43 aliases { 43 aliases {
44 ccsr = &soc; 44 ccsr = &soc;
45 dcsr = &dcsr;
45 46
46 serial0 = &serial0; 47 serial0 = &serial0;
47 serial1 = &serial1; 48 serial1 = &serial1;
@@ -114,6 +115,74 @@
114 }; 115 };
115 }; 116 };
116 117
118 dcsr: dcsr@f00000000 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "fsl,dcsr", "simple-bus";
122
123 dcsr-epu@0 {
124 compatible = "fsl,dcsr-epu";
125 interrupts = <52 2 0 0
126 84 2 0 0
127 85 2 0 0>;
128 interrupt-parent = <&mpic>;
129 reg = <0x0 0x1000>;
130 };
131 dcsr-npc {
132 compatible = "fsl,dcsr-npc";
133 reg = <0x1000 0x1000 0x1000000 0x8000>;
134 };
135 dcsr-nxc@2000 {
136 compatible = "fsl,dcsr-nxc";
137 reg = <0x2000 0x1000>;
138 };
139 dcsr-corenet {
140 compatible = "fsl,dcsr-corenet";
141 reg = <0x8000 0x1000 0xB0000 0x1000>;
142 };
143 dcsr-dpaa@9000 {
144 compatible = "fsl,p43041-dcsr-dpaa", "fsl,dcsr-dpaa";
145 reg = <0x9000 0x1000>;
146 };
147 dcsr-ocn@11000 {
148 compatible = "fsl,p43041-dcsr-ocn", "fsl,dcsr-ocn";
149 reg = <0x11000 0x1000>;
150 };
151 dcsr-ddr@12000 {
152 compatible = "fsl,dcsr-ddr";
153 dev-handle = <&ddr>;
154 reg = <0x12000 0x1000>;
155 };
156 dcsr-nal@18000 {
157 compatible = "fsl,p43041-dcsr-nal", "fsl,dcsr-nal";
158 reg = <0x18000 0x1000>;
159 };
160 dcsr-rcpm@22000 {
161 compatible = "fsl,p43041-dcsr-rcpm", "fsl,dcsr-rcpm";
162 reg = <0x22000 0x1000>;
163 };
164 dcsr-cpu-sb-proxy@40000 {
165 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
166 cpu-handle = <&cpu0>;
167 reg = <0x40000 0x1000>;
168 };
169 dcsr-cpu-sb-proxy@41000 {
170 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
171 cpu-handle = <&cpu1>;
172 reg = <0x41000 0x1000>;
173 };
174 dcsr-cpu-sb-proxy@42000 {
175 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
176 cpu-handle = <&cpu2>;
177 reg = <0x42000 0x1000>;
178 };
179 dcsr-cpu-sb-proxy@43000 {
180 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
181 cpu-handle = <&cpu3>;
182 reg = <0x43000 0x1000>;
183 };
184 };
185
117 soc: soc@ffe000000 { 186 soc: soc@ffe000000 {
118 #address-cells = <1>; 187 #address-cells = <1>;
119 #size-cells = <1>; 188 #size-cells = <1>;
@@ -133,7 +202,7 @@
133 fsl,num-laws = <32>; 202 fsl,num-laws = <32>;
134 }; 203 };
135 204
136 memory-controller@8000 { 205 ddr: memory-controller@8000 {
137 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 206 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
138 reg = <0x8000 0x1000>; 207 reg = <0x8000 0x1000>;
139 interrupts = <16 2 1 23>; 208 interrupts = <16 2 1 23>;
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index ccd53aff0e9a..c7916dc28014 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -45,6 +45,10 @@
45 device_type = "memory"; 45 device_type = "memory";
46 }; 46 };
47 47
48 dcsr: dcsr@f00000000 {
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
50 };
51
48 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
49 spi@110000 { 53 spi@110000 {
50 flash@0 { 54 flash@0 {
diff --git a/arch/powerpc/boot/dts/p4080si.dtsi b/arch/powerpc/boot/dts/p4080si.dtsi
index 4984edbb63a2..f20c01ab2473 100644
--- a/arch/powerpc/boot/dts/p4080si.dtsi
+++ b/arch/powerpc/boot/dts/p4080si.dtsi
@@ -42,6 +42,7 @@
42 42
43 aliases { 43 aliases {
44 ccsr = &soc; 44 ccsr = &soc;
45 dcsr = &dcsr;
45 46
46 serial0 = &serial0; 47 serial0 = &serial0;
47 serial1 = &serial1; 48 serial1 = &serial1;
@@ -143,6 +144,99 @@
143 }; 144 };
144 }; 145 };
145 146
147 dcsr: dcsr@f00000000 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 compatible = "fsl,dcsr", "simple-bus";
151
152 dcsr-epu@0 {
153 compatible = "fsl,dcsr-epu";
154 interrupts = <52 2 0 0
155 84 2 0 0
156 85 2 0 0>;
157 interrupt-parent = <&mpic>;
158 reg = <0x0 0x1000>;
159 };
160 dcsr-npc {
161 compatible = "fsl,dcsr-npc";
162 reg = <0x1000 0x1000 0x1000000 0x8000>;
163 };
164 dcsr-nxc@2000 {
165 compatible = "fsl,dcsr-nxc";
166 reg = <0x2000 0x1000>;
167 };
168 dcsr-corenet {
169 compatible = "fsl,dcsr-corenet";
170 reg = <0x8000 0x1000 0xB0000 0x1000>;
171 };
172 dcsr-dpaa@9000 {
173 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
174 reg = <0x9000 0x1000>;
175 };
176 dcsr-ocn@11000 {
177 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
178 reg = <0x11000 0x1000>;
179 };
180 dcsr-ddr@12000 {
181 compatible = "fsl,dcsr-ddr";
182 dev-handle = <&ddr1>;
183 reg = <0x12000 0x1000>;
184 };
185 dcsr-ddr@13000 {
186 compatible = "fsl,dcsr-ddr";
187 dev-handle = <&ddr2>;
188 reg = <0x13000 0x1000>;
189 };
190 dcsr-nal@18000 {
191 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
192 reg = <0x18000 0x1000>;
193 };
194 dcsr-rcpm@22000 {
195 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
196 reg = <0x22000 0x1000>;
197 };
198 dcsr-cpu-sb-proxy@40000 {
199 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
200 cpu-handle = <&cpu0>;
201 reg = <0x40000 0x1000>;
202 };
203 dcsr-cpu-sb-proxy@41000 {
204 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
205 cpu-handle = <&cpu1>;
206 reg = <0x41000 0x1000>;
207 };
208 dcsr-cpu-sb-proxy@42000 {
209 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
210 cpu-handle = <&cpu2>;
211 reg = <0x42000 0x1000>;
212 };
213 dcsr-cpu-sb-proxy@43000 {
214 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
215 cpu-handle = <&cpu3>;
216 reg = <0x43000 0x1000>;
217 };
218 dcsr-cpu-sb-proxy@44000 {
219 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
220 cpu-handle = <&cpu4>;
221 reg = <0x44000 0x1000>;
222 };
223 dcsr-cpu-sb-proxy@45000 {
224 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
225 cpu-handle = <&cpu5>;
226 reg = <0x45000 0x1000>;
227 };
228 dcsr-cpu-sb-proxy@46000 {
229 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
230 cpu-handle = <&cpu6>;
231 reg = <0x46000 0x1000>;
232 };
233 dcsr-cpu-sb-proxy@47000 {
234 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
235 cpu-handle = <&cpu7>;
236 reg = <0x47000 0x1000>;
237 };
238 };
239
146 soc: soc@ffe000000 { 240 soc: soc@ffe000000 {
147 #address-cells = <1>; 241 #address-cells = <1>;
148 #size-cells = <1>; 242 #size-cells = <1>;
@@ -162,13 +256,13 @@
162 fsl,num-laws = <32>; 256 fsl,num-laws = <32>;
163 }; 257 };
164 258
165 memory-controller@8000 { 259 ddr1: memory-controller@8000 {
166 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller"; 260 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
167 reg = <0x8000 0x1000>; 261 reg = <0x8000 0x1000>;
168 interrupts = <16 2 1 23>; 262 interrupts = <16 2 1 23>;
169 }; 263 };
170 264
171 memory-controller@9000 { 265 ddr2: memory-controller@9000 {
172 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller"; 266 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
173 reg = <0x9000 0x1000>; 267 reg = <0x9000 0x1000>;
174 interrupts = <16 2 1 22>; 268 interrupts = <16 2 1 22>;
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
index ca4d592c91d1..e6d40999ccd7 100644
--- a/arch/powerpc/boot/dts/p5020ds.dts
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -45,6 +45,10 @@
45 device_type = "memory"; 45 device_type = "memory";
46 }; 46 };
47 47
48 dcsr: dcsr@f00000000 {
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
50 };
51
48 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
49 spi@110000 { 53 spi@110000 {
50 flash@0 { 54 flash@0 {
diff --git a/arch/powerpc/boot/dts/p5020si.dtsi b/arch/powerpc/boot/dts/p5020si.dtsi
index 5e6048ec55bb..e7948ad71fa3 100644
--- a/arch/powerpc/boot/dts/p5020si.dtsi
+++ b/arch/powerpc/boot/dts/p5020si.dtsi
@@ -42,6 +42,7 @@
42 42
43 aliases { 43 aliases {
44 ccsr = &soc; 44 ccsr = &soc;
45 dcsr = &dcsr;
45 46
46 serial0 = &serial0; 47 serial0 = &serial0;
47 serial1 = &serial1; 48 serial1 = &serial1;
@@ -98,6 +99,69 @@
98 }; 99 };
99 }; 100 };
100 101
102 dcsr: dcsr@f00000000 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "fsl,dcsr", "simple-bus";
106
107 dcsr-epu@0 {
108 compatible = "fsl,dcsr-epu";
109 interrupts = <52 2 0 0
110 84 2 0 0
111 85 2 0 0>;
112 interrupt-parent = <&mpic>;
113 reg = <0x0 0x1000>;
114 };
115 dcsr-npc {
116 compatible = "fsl,dcsr-npc";
117 reg = <0x1000 0x1000 0x1000000 0x8000>;
118 };
119 dcsr-nxc@2000 {
120 compatible = "fsl,dcsr-nxc";
121 reg = <0x2000 0x1000>;
122 };
123 dcsr-corenet {
124 compatible = "fsl,dcsr-corenet";
125 reg = <0x8000 0x1000 0xB0000 0x1000>;
126 };
127 dcsr-dpaa@9000 {
128 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
129 reg = <0x9000 0x1000>;
130 };
131 dcsr-ocn@11000 {
132 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
133 reg = <0x11000 0x1000>;
134 };
135 dcsr-ddr@12000 {
136 compatible = "fsl,dcsr-ddr";
137 dev-handle = <&ddr1>;
138 reg = <0x12000 0x1000>;
139 };
140 dcsr-ddr@13000 {
141 compatible = "fsl,dcsr-ddr";
142 dev-handle = <&ddr2>;
143 reg = <0x13000 0x1000>;
144 };
145 dcsr-nal@18000 {
146 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
147 reg = <0x18000 0x1000>;
148 };
149 dcsr-rcpm@22000 {
150 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
151 reg = <0x22000 0x1000>;
152 };
153 dcsr-cpu-sb-proxy@40000 {
154 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
155 cpu-handle = <&cpu0>;
156 reg = <0x40000 0x1000>;
157 };
158 dcsr-cpu-sb-proxy@41000 {
159 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
160 cpu-handle = <&cpu1>;
161 reg = <0x41000 0x1000>;
162 };
163 };
164
101 soc: soc@ffe000000 { 165 soc: soc@ffe000000 {
102 #address-cells = <1>; 166 #address-cells = <1>;
103 #size-cells = <1>; 167 #size-cells = <1>;
@@ -117,13 +181,13 @@
117 fsl,num-laws = <32>; 181 fsl,num-laws = <32>;
118 }; 182 };
119 183
120 memory-controller@8000 { 184 ddr1: memory-controller@8000 {
121 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 185 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
122 reg = <0x8000 0x1000>; 186 reg = <0x8000 0x1000>;
123 interrupts = <16 2 1 23>; 187 interrupts = <16 2 1 23>;
124 }; 188 };
125 189
126 memory-controller@9000 { 190 ddr2: memory-controller@9000 {
127 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 191 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
128 reg = <0x9000 0x1000>; 192 reg = <0x9000 0x1000>;
129 interrupts = <16 2 1 22>; 193 interrupts = <16 2 1 22>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-01 00:32:24 -0400