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authorSlava Grigorev <slava.grigorev@amd.com>2015-03-02 11:31:07 -0500
committerAlex Deucher <alexander.deucher@amd.com>2015-03-03 17:28:25 -0500
commitb983a8f45898245c432afcfd7cf1bb34c5c4e577 (patch)
tree0126bd517e2bc374f1e747be56094736faae3517
parent5c046a57a5ecca7950943625a0cf5adfc601e861 (diff)
radeon/audio: fix whitespace
Use proper tabs. Signed-off-by: Slava Grigorev <slava.grigorev@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/radeon/dce6_afmt.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
index 9de14cfc0e80..81a4f5405cd5 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -252,40 +252,40 @@ void dce6_audio_enable(struct radeon_device *rdev,
252void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, 252void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
253 struct radeon_crtc *crtc, unsigned int clock) 253 struct radeon_crtc *crtc, unsigned int clock)
254{ 254{
255 /* Two dtos; generally use dto0 for HDMI */ 255 /* Two dtos; generally use dto0 for HDMI */
256 u32 value = 0; 256 u32 value = 0;
257 257
258 if (crtc) 258 if (crtc)
259 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); 259 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
260 260
261 WREG32(DCCG_AUDIO_DTO_SOURCE, value); 261 WREG32(DCCG_AUDIO_DTO_SOURCE, value);
262 262
263 /* Express [24MHz / target pixel clock] as an exact rational 263 /* Express [24MHz / target pixel clock] as an exact rational
264 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 264 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
265 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 265 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
266 */ 266 */
267 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); 267 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
268 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); 268 WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
269} 269}
270 270
271void dce6_dp_audio_set_dto(struct radeon_device *rdev, 271void dce6_dp_audio_set_dto(struct radeon_device *rdev,
272 struct radeon_crtc *crtc, unsigned int clock) 272 struct radeon_crtc *crtc, unsigned int clock)
273{ 273{
274 /* Two dtos; generally use dto1 for DP */ 274 /* Two dtos; generally use dto1 for DP */
275 u32 value = 0; 275 u32 value = 0;
276 value |= DCCG_AUDIO_DTO_SEL; 276 value |= DCCG_AUDIO_DTO_SEL;
277 277
278 if (crtc) 278 if (crtc)
279 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); 279 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
280 280
281 WREG32(DCCG_AUDIO_DTO_SOURCE, value); 281 WREG32(DCCG_AUDIO_DTO_SOURCE, value);
282 282
283 /* Express [24MHz / target pixel clock] as an exact rational 283 /* Express [24MHz / target pixel clock] as an exact rational
284 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 284 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
285 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 285 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
286 */ 286 */
287 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); 287 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
288 WREG32(DCCG_AUDIO_DTO1_MODULE, clock); 288 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
289} 289}
290 290
291void dce6_dp_enable(struct drm_encoder *encoder, bool enable) 291void dce6_dp_enable(struct drm_encoder *encoder, bool enable)