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authorJohn Crispin <blogic@openwrt.org>2014-10-26 06:26:04 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 01:45:25 -0500
commitb96e6e9fd296b85dbbd863157d00994711924b70 (patch)
tree4e6e65e6f420851920dc30b7f95e0ca2cbfac7ca
parent53263a1c68524fd35e2f2ea7f03d0fef362b944d (diff)
MIPS: ralink: allow loading irq registers from the devicetree
Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8029/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/ralink/irq.c35
1 files changed, 25 insertions, 10 deletions
diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
index 7634dcd88766..7cf91b92e9d1 100644
--- a/arch/mips/ralink/irq.c
+++ b/arch/mips/ralink/irq.c
@@ -20,14 +20,6 @@
20 20
21#include "common.h" 21#include "common.h"
22 22
23/* INTC register offsets */
24#define INTC_REG_STATUS0 0x00
25#define INTC_REG_STATUS1 0x04
26#define INTC_REG_TYPE 0x20
27#define INTC_REG_RAW_STATUS 0x30
28#define INTC_REG_ENABLE 0x34
29#define INTC_REG_DISABLE 0x38
30
31#define INTC_INT_GLOBAL BIT(31) 23#define INTC_INT_GLOBAL BIT(31)
32 24
33#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2) 25#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
@@ -44,17 +36,36 @@
44 36
45#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9) 37#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
46 38
39enum rt_intc_regs_enum {
40 INTC_REG_STATUS0 = 0,
41 INTC_REG_STATUS1,
42 INTC_REG_TYPE,
43 INTC_REG_RAW_STATUS,
44 INTC_REG_ENABLE,
45 INTC_REG_DISABLE,
46};
47
48static u32 rt_intc_regs[] = {
49 [INTC_REG_STATUS0] = 0x00,
50 [INTC_REG_STATUS1] = 0x04,
51 [INTC_REG_TYPE] = 0x20,
52 [INTC_REG_RAW_STATUS] = 0x30,
53 [INTC_REG_ENABLE] = 0x34,
54 [INTC_REG_DISABLE] = 0x38,
55};
56
47static void __iomem *rt_intc_membase; 57static void __iomem *rt_intc_membase;
58
48static int rt_perfcount_irq; 59static int rt_perfcount_irq;
49 60
50static inline void rt_intc_w32(u32 val, unsigned reg) 61static inline void rt_intc_w32(u32 val, unsigned reg)
51{ 62{
52 __raw_writel(val, rt_intc_membase + reg); 63 __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
53} 64}
54 65
55static inline u32 rt_intc_r32(unsigned reg) 66static inline u32 rt_intc_r32(unsigned reg)
56{ 67{
57 return __raw_readl(rt_intc_membase + reg); 68 return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
58} 69}
59 70
60static void ralink_intc_irq_unmask(struct irq_data *d) 71static void ralink_intc_irq_unmask(struct irq_data *d)
@@ -140,6 +151,10 @@ static int __init intc_of_init(struct device_node *node,
140 struct irq_domain *domain; 151 struct irq_domain *domain;
141 int irq; 152 int irq;
142 153
154 if (!of_property_read_u32_array(node, "ralink,intc-registers",
155 rt_intc_regs, 6))
156 pr_info("intc: using register map from devicetree\n");
157
143 irq = irq_of_parse_and_map(node, 0); 158 irq = irq_of_parse_and_map(node, 0);
144 if (!irq) 159 if (!irq)
145 panic("Failed to get INTC IRQ"); 160 panic("Failed to get INTC IRQ");