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authorMagnus Damm <damm@igel.co.jp>2009-03-11 02:41:51 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-04-16 03:00:12 -0400
commitb8b47bfbe4eb1ae0e6891e49c86a5f4fb00413be (patch)
treeea54e39235d29b7f96fd24611ff507dfdaa1d178
parent3ee8da87ba6151ec91b2b8bbd27633bb248ea0d5 (diff)
sh: pass along struct pci_channel
These patches rework the pci code for the sh architecture. Currently each board implements some kind of ioport to address mapping. Some boards use generic_io_base others try passing addresses as io ports. This is the first set of patches that try to unify the pci code as much as possible to avoid duplicated code. This will in the end lead to fewer lines board specific code and more generic code. This patch makes sure a struct pci_channel pointer is passed along to various pci functions such as pci_read_reg(), pci_write_reg(), pci_fixup_pcic(), sh7751_pcic_init() and sh7780_pcic_init(). Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/drivers/pci/fixups-lboxre2.c23
-rw-r--r--arch/sh/drivers/pci/fixups-r7780rp.c33
-rw-r--r--arch/sh/drivers/pci/fixups-rts7751r2d.c23
-rw-r--r--arch/sh/drivers/pci/fixups-sdk7780.c46
-rw-r--r--arch/sh/drivers/pci/fixups-se7780.c32
-rw-r--r--arch/sh/drivers/pci/ops-landisk.c2
-rw-r--r--arch/sh/drivers/pci/ops-lboxre2.c2
-rw-r--r--arch/sh/drivers/pci/ops-r7780rp.c2
-rw-r--r--arch/sh/drivers/pci/ops-rts7751r2d.c2
-rw-r--r--arch/sh/drivers/pci/ops-sdk7780.c2
-rw-r--r--arch/sh/drivers/pci/ops-se7780.c2
-rw-r--r--arch/sh/drivers/pci/ops-sh4.c24
-rw-r--r--arch/sh/drivers/pci/ops-snapgear.c2
-rw-r--r--arch/sh/drivers/pci/ops-titan.c2
-rw-r--r--arch/sh/drivers/pci/pci-sh4.h11
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.c68
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.h3
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.c31
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.h3
19 files changed, 164 insertions, 149 deletions
diff --git a/arch/sh/drivers/pci/fixups-lboxre2.c b/arch/sh/drivers/pci/fixups-lboxre2.c
index 1c1d41255ec0..a82011d03cb0 100644
--- a/arch/sh/drivers/pci/fixups-lboxre2.c
+++ b/arch/sh/drivers/pci/fixups-lboxre2.c
@@ -9,33 +9,34 @@
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details. 10 * for more details.
11 */ 11 */
12#include <linux/pci.h>
12#include "pci-sh4.h" 13#include "pci-sh4.h"
13 14
14#define PCIMCR_MRSET_OFF 0xBFFFFFFF 15#define PCIMCR_MRSET_OFF 0xBFFFFFFF
15#define PCIMCR_RFSH_OFF 0xFFFFFFFB 16#define PCIMCR_RFSH_OFF 0xFFFFFFFB
16 17
17int pci_fixup_pcic(void) 18int pci_fixup_pcic(struct pci_channel *chan)
18{ 19{
19 unsigned long bcr1, mcr; 20 unsigned long bcr1, mcr;
20 21
21 bcr1 = ctrl_inl(SH7751_BCR1); 22 bcr1 = ctrl_inl(SH7751_BCR1);
22 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ 23 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
23 pci_write_reg(bcr1, SH4_PCIBCR1); 24 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
24 25
25 /* Enable all interrupts, so we known what to fix */ 26 /* Enable all interrupts, so we known what to fix */
26 pci_write_reg(0x0000c3ff, SH4_PCIINTM); 27 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
27 pci_write_reg(0x0000380f, SH4_PCIAINTM); 28 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
28 pci_write_reg(0xfb900047, SH7751_PCICONF1); 29 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
29 pci_write_reg(0xab000001, SH7751_PCICONF4); 30 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
30 31
31 mcr = ctrl_inl(SH7751_MCR); 32 mcr = ctrl_inl(SH7751_MCR);
32 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 33 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
33 pci_write_reg(mcr, SH4_PCIMCR); 34 pci_write_reg(chan, mcr, SH4_PCIMCR);
34 35
35 pci_write_reg(0x0c000000, SH7751_PCICONF5); 36 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
36 pci_write_reg(0xd0000000, SH7751_PCICONF6); 37 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
37 pci_write_reg(0x0c000000, SH4_PCILAR0); 38 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
38 pci_write_reg(0x00000000, SH4_PCILAR1); 39 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
39 40
40 return 0; 41 return 0;
41} 42}
diff --git a/arch/sh/drivers/pci/fixups-r7780rp.c b/arch/sh/drivers/pci/fixups-r7780rp.c
index 3e321df65d22..5b25021bbd62 100644
--- a/arch/sh/drivers/pci/fixups-r7780rp.c
+++ b/arch/sh/drivers/pci/fixups-r7780rp.c
@@ -14,32 +14,33 @@
14#include "pci-sh4.h" 14#include "pci-sh4.h"
15#include <asm/io.h> 15#include <asm/io.h>
16 16
17int pci_fixup_pcic(void) 17int pci_fixup_pcic(struct pci_channel *chan)
18{ 18{
19 pci_write_reg(0x000043ff, SH4_PCIINTM); 19 pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
20 pci_write_reg(0x0000380f, SH4_PCIAINTM); 20 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
21 21
22 pci_write_reg(0xfbb00047, SH7780_PCICMD); 22 pci_write_reg(chan, 0xfbb00047, SH7780_PCICMD);
23 pci_write_reg(0x00000000, SH7780_PCIIBAR); 23 pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
24 24
25 pci_write_reg(0x00011912, SH7780_PCISVID); 25 pci_write_reg(chan, 0x00011912, SH7780_PCISVID);
26 pci_write_reg(0x08000000, SH7780_PCICSCR0); 26 pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
27 pci_write_reg(0x0000001b, SH7780_PCICSAR0); 27 pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
28 pci_write_reg(0xfd000000, SH7780_PCICSCR1); 28 pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
29 pci_write_reg(0x0000000f, SH7780_PCICSAR1); 29 pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
30 30
31 pci_write_reg(0xfd000000, SH7780_PCIMBR0); 31 pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
32 pci_write_reg(0x00fc0000, SH7780_PCIMBMR0); 32 pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
33 33
34#ifdef CONFIG_32BIT 34#ifdef CONFIG_32BIT
35 pci_write_reg(0xc0000000, SH7780_PCIMBR2); 35 pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
36 pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2); 36 pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
37#endif 37#endif
38 38
39 /* Set IOBR for windows containing area specified in pci.h */ 39 /* Set IOBR for windows containing area specified in pci.h */
40 pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)), 40 pci_write_reg(chan, (PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
41 SH7780_PCIIOBR); 41 SH7780_PCIIOBR);
42 pci_write_reg(((SH7780_PCI_IO_SIZE-1) & (7<<18)), SH7780_PCIIOBMR); 42 pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
43 SH7780_PCIIOBMR);
43 44
44 return 0; 45 return 0;
45} 46}
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 904bce8768d3..38852334d479 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -10,34 +10,35 @@
10 * License. See the file "COPYING" in the main directory of this archive 10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details. 11 * for more details.
12 */ 12 */
13#include <linux/pci.h>
13#include "pci-sh4.h" 14#include "pci-sh4.h"
14 15
15#define PCIMCR_MRSET_OFF 0xBFFFFFFF 16#define PCIMCR_MRSET_OFF 0xBFFFFFFF
16#define PCIMCR_RFSH_OFF 0xFFFFFFFB 17#define PCIMCR_RFSH_OFF 0xFFFFFFFB
17 18
18int pci_fixup_pcic(void) 19int pci_fixup_pcic(struct pci_channel *chan)
19{ 20{
20 unsigned long bcr1, mcr; 21 unsigned long bcr1, mcr;
21 22
22 bcr1 = ctrl_inl(SH7751_BCR1); 23 bcr1 = ctrl_inl(SH7751_BCR1);
23 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ 24 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
24 pci_write_reg(bcr1, SH4_PCIBCR1); 25 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
25 26
26 /* Enable all interrupts, so we known what to fix */ 27 /* Enable all interrupts, so we known what to fix */
27 pci_write_reg(0x0000c3ff, SH4_PCIINTM); 28 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
28 pci_write_reg(0x0000380f, SH4_PCIAINTM); 29 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
29 30
30 pci_write_reg(0xfb900047, SH7751_PCICONF1); 31 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
31 pci_write_reg(0xab000001, SH7751_PCICONF4); 32 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
32 33
33 mcr = ctrl_inl(SH7751_MCR); 34 mcr = ctrl_inl(SH7751_MCR);
34 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 35 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
35 pci_write_reg(mcr, SH4_PCIMCR); 36 pci_write_reg(chan, mcr, SH4_PCIMCR);
36 37
37 pci_write_reg(0x0c000000, SH7751_PCICONF5); 38 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
38 pci_write_reg(0xd0000000, SH7751_PCICONF6); 39 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
39 pci_write_reg(0x0c000000, SH4_PCILAR0); 40 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
40 pci_write_reg(0x00000000, SH4_PCILAR1); 41 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
41 42
42 return 0; 43 return 0;
43} 44}
diff --git a/arch/sh/drivers/pci/fixups-sdk7780.c b/arch/sh/drivers/pci/fixups-sdk7780.c
index 2f8863099dd1..3f6754a120ed 100644
--- a/arch/sh/drivers/pci/fixups-sdk7780.c
+++ b/arch/sh/drivers/pci/fixups-sdk7780.c
@@ -14,46 +14,48 @@
14#include "pci-sh4.h" 14#include "pci-sh4.h"
15#include <asm/io.h> 15#include <asm/io.h>
16 16
17int pci_fixup_pcic(void) 17int pci_fixup_pcic(struct pci_channel *chan)
18{ 18{
19 ctrl_outl(0x00000001, SH7780_PCI_VCR2); 19 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
20 20
21 /* Enable all interrupts, so we know what to fix */ 21 /* Enable all interrupts, so we know what to fix */
22 pci_write_reg(0x0000C3FF, SH7780_PCIIMR); 22 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
23 pci_write_reg(0x0000380F, SH7780_PCIAINTM); 23 pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);
24 24
25 /* Set up standard PCI config registers */ 25 /* Set up standard PCI config registers */
26 pci_write_reg(0xFB00, SH7780_PCISTATUS); 26 pci_write_reg(chan, 0xFB00, SH7780_PCISTATUS);
27 pci_write_reg(0x0047, SH7780_PCICMD); 27 pci_write_reg(chan, 0x0047, SH7780_PCICMD);
28 pci_write_reg(0x00, SH7780_PCIPIF); 28 pci_write_reg(chan, 0x00, SH7780_PCIPIF);
29 pci_write_reg(0x00, SH7780_PCISUB); 29 pci_write_reg(chan, 0x00, SH7780_PCISUB);
30 pci_write_reg(0x06, SH7780_PCIBCC); 30 pci_write_reg(chan, 0x06, SH7780_PCIBCC);
31 pci_write_reg(0x1912, SH7780_PCISVID); 31 pci_write_reg(chan, 0x1912, SH7780_PCISVID);
32 pci_write_reg(0x0001, SH7780_PCISID); 32 pci_write_reg(chan, 0x0001, SH7780_PCISID);
33 33
34 pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */ 34 pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
35 pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */ 35 pci_write_reg(chan, 0x08000000, SH7780_PCILAR0); /* SHwy */
36 pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */ 36 pci_write_reg(chan, 0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
37 37
38 pci_write_reg(0x00000000, SH7780_PCIMBAR1); 38 pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
39 pci_write_reg(0x00000000, SH7780_PCILAR1); 39 pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);
40 pci_write_reg(0x00000000, SH7780_PCILSR1); 40 pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);
41 41
42 pci_write_reg(0xAB000801, SH7780_PCIIBAR); 42 pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
43 43
44 /* 44 /*
45 * Set the MBR so PCI address is one-to-one with window, 45 * Set the MBR so PCI address is one-to-one with window,
46 * meaning all calls go straight through... use ifdef to 46 * meaning all calls go straight through... use ifdef to
47 * catch erroneous assumption. 47 * catch erroneous assumption.
48 */ 48 */
49 pci_write_reg(0xFD000000 , SH7780_PCIMBR0); 49 pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);
50 pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */ 50 pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
51 51
52 /* Set IOBR for window containing area specified in pci.h */ 52 /* Set IOBR for window containing area specified in pci.h */
53 pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR); 53 pci_write_reg(chan, PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1),
54 pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR); 54 SH7780_PCIIOBR);
55 pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),
56 SH7780_PCIIOBMR);
55 57
56 pci_write_reg(0xA5000C01, SH7780_PCICR); 58 pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);
57 59
58 return 0; 60 return 0;
59} 61}
diff --git a/arch/sh/drivers/pci/fixups-se7780.c b/arch/sh/drivers/pci/fixups-se7780.c
index 880cea1c0d89..b8e735e01c3c 100644
--- a/arch/sh/drivers/pci/fixups-se7780.c
+++ b/arch/sh/drivers/pci/fixups-se7780.c
@@ -15,13 +15,13 @@
15#include "pci-sh4.h" 15#include "pci-sh4.h"
16#include <asm/io.h> 16#include <asm/io.h>
17 17
18int pci_fixup_pcic(void) 18int pci_fixup_pcic(struct pci_channel *chan)
19{ 19{
20 ctrl_outl(0x00000001, SH7780_PCI_VCR2); 20 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
21 21
22 /* Enable all interrupts, so we know what to fix */ 22 /* Enable all interrupts, so we know what to fix */
23 pci_write_reg(0x0000C3FF, SH7780_PCIIMR); 23 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
24 pci_write_reg(0x0000380F, SH7780_PCIAINTM); 24 pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);
25 25
26 /* Set up standard PCI config registers */ 26 /* Set up standard PCI config registers */
27 ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS)); 27 ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
@@ -32,29 +32,31 @@ int pci_fixup_pcic(void)
32 ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID)); 32 ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));
33 ctrl_outw(0x0001, PCI_REG(SH7780_PCISID)); 33 ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));
34 34
35 pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */ 35 pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
36 pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */ 36 pci_write_reg(chan, 0x08000000, SH7780_PCILAR0); /* SHwy */
37 pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */ 37 pci_write_reg(chan, 0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
38 38
39 pci_write_reg(0x00000000, SH7780_PCIMBAR1); 39 pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
40 pci_write_reg(0x00000000, SH7780_PCILAR1); 40 pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);
41 pci_write_reg(0x00000000, SH7780_PCILSR1); 41 pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);
42 42
43 pci_write_reg(0xAB000801, SH7780_PCIIBAR); 43 pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
44 44
45 /* 45 /*
46 * Set the MBR so PCI address is one-to-one with window, 46 * Set the MBR so PCI address is one-to-one with window,
47 * meaning all calls go straight through... use ifdef to 47 * meaning all calls go straight through... use ifdef to
48 * catch erroneous assumption. 48 * catch erroneous assumption.
49 */ 49 */
50 pci_write_reg(0xFD000000 , SH7780_PCIMBR0); 50 pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);
51 pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */ 51 pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
52 52
53 /* Set IOBR for window containing area specified in pci.h */ 53 /* Set IOBR for window containing area specified in pci.h */
54 pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR); 54 pci_write_reg(chan, PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1),
55 pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR); 55 SH7780_PCIIOBR);
56 pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),
57 SH7780_PCIIOBMR);
56 58
57 pci_write_reg(0xA5000C01, SH7780_PCICR); 59 pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);
58 60
59 return 0; 61 return 0;
60} 62}
diff --git a/arch/sh/drivers/pci/ops-landisk.c b/arch/sh/drivers/pci/ops-landisk.c
index bff09ecf3419..343c072a5a79 100644
--- a/arch/sh/drivers/pci/ops-landisk.c
+++ b/arch/sh/drivers/pci/ops-landisk.c
@@ -45,7 +45,7 @@ static struct sh4_pci_address_map sh7751_pci_map = {
45 45
46int __init pcibios_init_platform(void) 46int __init pcibios_init_platform(void)
47{ 47{
48 return sh7751_pcic_init(&sh7751_pci_map); 48 return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
49} 49}
50 50
51int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) 51int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
diff --git a/arch/sh/drivers/pci/ops-lboxre2.c b/arch/sh/drivers/pci/ops-lboxre2.c
index 86c0b6fb7375..8bff32a22101 100644
--- a/arch/sh/drivers/pci/ops-lboxre2.c
+++ b/arch/sh/drivers/pci/ops-lboxre2.c
@@ -59,5 +59,5 @@ static struct sh4_pci_address_map sh7751_pci_map = {
59 59
60int __init pcibios_init_platform(void) 60int __init pcibios_init_platform(void)
61{ 61{
62 return sh7751_pcic_init(&sh7751_pci_map); 62 return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
63} 63}
diff --git a/arch/sh/drivers/pci/ops-r7780rp.c b/arch/sh/drivers/pci/ops-r7780rp.c
index 8555238e63eb..bf32ee8b1321 100644
--- a/arch/sh/drivers/pci/ops-r7780rp.c
+++ b/arch/sh/drivers/pci/ops-r7780rp.c
@@ -64,5 +64,5 @@ static struct sh4_pci_address_map sh7780_pci_map = {
64 64
65int __init pcibios_init_platform(void) 65int __init pcibios_init_platform(void)
66{ 66{
67 return sh7780_pcic_init(&sh7780_pci_map); 67 return sh7780_pcic_init(&board_pci_channels[0], &sh7780_pci_map);
68} 68}
diff --git a/arch/sh/drivers/pci/ops-rts7751r2d.c b/arch/sh/drivers/pci/ops-rts7751r2d.c
index d6ca74b25d5f..e4208a697321 100644
--- a/arch/sh/drivers/pci/ops-rts7751r2d.c
+++ b/arch/sh/drivers/pci/ops-rts7751r2d.c
@@ -69,6 +69,6 @@ static struct sh4_pci_address_map sh7751_pci_map = {
69int __init pcibios_init_platform(void) 69int __init pcibios_init_platform(void)
70{ 70{
71 __set_io_port_base(SH7751_PCI_IO_BASE); 71 __set_io_port_base(SH7751_PCI_IO_BASE);
72 return sh7751_pcic_init(&sh7751_pci_map); 72 return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
73} 73}
74 74
diff --git a/arch/sh/drivers/pci/ops-sdk7780.c b/arch/sh/drivers/pci/ops-sdk7780.c
index 4dcc64184b23..21d59d4a2150 100644
--- a/arch/sh/drivers/pci/ops-sdk7780.c
+++ b/arch/sh/drivers/pci/ops-sdk7780.c
@@ -69,5 +69,5 @@ static struct sh4_pci_address_map sdk7780_pci_map = {
69int __init pcibios_init_platform(void) 69int __init pcibios_init_platform(void)
70{ 70{
71 printk(KERN_INFO "SH7780 PCI: Finished initializing PCI controller\n"); 71 printk(KERN_INFO "SH7780 PCI: Finished initializing PCI controller\n");
72 return sh7780_pcic_init(&sdk7780_pci_map); 72 return sh7780_pcic_init(&board_pci_channels[0], &sdk7780_pci_map);
73} 73}
diff --git a/arch/sh/drivers/pci/ops-se7780.c b/arch/sh/drivers/pci/ops-se7780.c
index 3145c62484d6..78a6f2bc4f12 100644
--- a/arch/sh/drivers/pci/ops-se7780.c
+++ b/arch/sh/drivers/pci/ops-se7780.c
@@ -92,5 +92,5 @@ int __init pcibios_init_platform(void)
92 ctrl_outw(0x0013, FPGA_PCI_INTSEL1); 92 ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
93 ctrl_outw(0xE402, FPGA_PCI_INTSEL2); 93 ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
94 94
95 return sh7780_pcic_init(&se7780_pci_map); 95 return sh7780_pcic_init(&board_pci_channels[0], &se7780_pci_map);
96} 96}
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c
index 710a3b0306e5..92d27f734f2e 100644
--- a/arch/sh/drivers/pci/ops-sh4.c
+++ b/arch/sh/drivers/pci/ops-sh4.c
@@ -34,8 +34,8 @@ static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
34 * so we must do byte alignment by hand 34 * so we must do byte alignment by hand
35 */ 35 */
36 spin_lock_irqsave(&sh4_pci_lock, flags); 36 spin_lock_irqsave(&sh4_pci_lock, flags);
37 pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); 37 pci_write_reg(NULL, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
38 data = pci_read_reg(SH4_PCIPDR); 38 data = pci_read_reg(NULL, SH4_PCIPDR);
39 spin_unlock_irqrestore(&sh4_pci_lock, flags); 39 spin_unlock_irqrestore(&sh4_pci_lock, flags);
40 40
41 switch (size) { 41 switch (size) {
@@ -68,8 +68,8 @@ static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
68 u32 data; 68 u32 data;
69 69
70 spin_lock_irqsave(&sh4_pci_lock, flags); 70 spin_lock_irqsave(&sh4_pci_lock, flags);
71 pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); 71 pci_write_reg(NULL, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
72 data = pci_read_reg(SH4_PCIPDR); 72 data = pci_read_reg(NULL, SH4_PCIPDR);
73 spin_unlock_irqrestore(&sh4_pci_lock, flags); 73 spin_unlock_irqrestore(&sh4_pci_lock, flags);
74 74
75 switch (size) { 75 switch (size) {
@@ -90,7 +90,7 @@ static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
90 return PCIBIOS_FUNC_NOT_SUPPORTED; 90 return PCIBIOS_FUNC_NOT_SUPPORTED;
91 } 91 }
92 92
93 pci_write_reg(data, SH4_PCIPDR); 93 pci_write_reg(NULL, data, SH4_PCIPDR);
94 94
95 return PCIBIOS_SUCCESSFUL; 95 return PCIBIOS_SUCCESSFUL;
96} 96}
@@ -106,25 +106,25 @@ struct pci_ops sh4_pci_ops = {
106 */ 106 */
107static unsigned int pci_probe = PCI_PROBE_CONF1; 107static unsigned int pci_probe = PCI_PROBE_CONF1;
108 108
109int __init sh4_pci_check_direct(void) 109int __init sh4_pci_check_direct(struct pci_channel *chan)
110{ 110{
111 /* 111 /*
112 * Check if configuration works. 112 * Check if configuration works.
113 */ 113 */
114 if (pci_probe & PCI_PROBE_CONF1) { 114 if (pci_probe & PCI_PROBE_CONF1) {
115 unsigned int tmp = pci_read_reg(SH4_PCIPAR); 115 unsigned int tmp = pci_read_reg(chan, SH4_PCIPAR);
116 116
117 pci_write_reg(P1SEG, SH4_PCIPAR); 117 pci_write_reg(chan, P1SEG, SH4_PCIPAR);
118 118
119 if (pci_read_reg(SH4_PCIPAR) == P1SEG) { 119 if (pci_read_reg(chan, SH4_PCIPAR) == P1SEG) {
120 pci_write_reg(tmp, SH4_PCIPAR); 120 pci_write_reg(chan, tmp, SH4_PCIPAR);
121 printk(KERN_INFO "PCI: Using configuration type 1\n"); 121 printk(KERN_INFO "PCI: Using configuration type 1\n");
122 request_region(PCI_REG(SH4_PCIPAR), 8, "PCI conf1"); 122 request_region(PCI_REG(SH4_PCIPAR), 8, "PCI conf1");
123 123
124 return 0; 124 return 0;
125 } 125 }
126 126
127 pci_write_reg(tmp, SH4_PCIPAR); 127 pci_write_reg(chan, tmp, SH4_PCIPAR);
128 } 128 }
129 129
130 pr_debug("PCI: pci_check_direct failed\n"); 130 pr_debug("PCI: pci_check_direct failed\n");
@@ -163,7 +163,7 @@ char * __devinit pcibios_setup(char *str)
163 return str; 163 return str;
164} 164}
165 165
166int __attribute__((weak)) pci_fixup_pcic(void) 166int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
167{ 167{
168 /* Nothing to do. */ 168 /* Nothing to do. */
169 return 0; 169 return 0;
diff --git a/arch/sh/drivers/pci/ops-snapgear.c b/arch/sh/drivers/pci/ops-snapgear.c
index 53dd893d4e54..cba80153dde9 100644
--- a/arch/sh/drivers/pci/ops-snapgear.c
+++ b/arch/sh/drivers/pci/ops-snapgear.c
@@ -66,7 +66,7 @@ static struct sh4_pci_address_map sh7751_pci_map = {
66 */ 66 */
67int __init pcibios_init_platform(void) 67int __init pcibios_init_platform(void)
68{ 68{
69 return sh7751_pcic_init(&sh7751_pci_map); 69 return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
70} 70}
71 71
72int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) 72int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
diff --git a/arch/sh/drivers/pci/ops-titan.c b/arch/sh/drivers/pci/ops-titan.c
index a8f7801a34af..69fcc5c5d520 100644
--- a/arch/sh/drivers/pci/ops-titan.c
+++ b/arch/sh/drivers/pci/ops-titan.c
@@ -73,5 +73,5 @@ static struct sh4_pci_address_map sh7751_pci_map = {
73 73
74int __init pcibios_init_platform(void) 74int __init pcibios_init_platform(void)
75{ 75{
76 return sh7751_pcic_init(&sh7751_pci_map); 76 return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
77} 77}
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index a83dcf70c13b..62ba35056087 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -154,8 +154,8 @@
154 154
155/* arch/sh/kernel/drivers/pci/ops-sh4.c */ 155/* arch/sh/kernel/drivers/pci/ops-sh4.c */
156extern struct pci_ops sh4_pci_ops; 156extern struct pci_ops sh4_pci_ops;
157int sh4_pci_check_direct(void); 157int sh4_pci_check_direct(struct pci_channel *chan);
158int pci_fixup_pcic(void); 158int pci_fixup_pcic(struct pci_channel *chan);
159 159
160struct sh4_pci_address_space { 160struct sh4_pci_address_space {
161 unsigned long base; 161 unsigned long base;
@@ -168,13 +168,16 @@ struct sh4_pci_address_map {
168 unsigned long flags; 168 unsigned long flags;
169}; 169};
170 170
171static inline void pci_write_reg(unsigned long val, unsigned long reg) 171static inline void pci_write_reg(struct pci_channel *chan,
172 unsigned long val, unsigned long reg)
172{ 173{
173 ctrl_outl(val, PCI_REG(reg)); 174 ctrl_outl(val, PCI_REG(reg));
174} 175}
175 176
176static inline unsigned long pci_read_reg(unsigned long reg) 177static inline unsigned long pci_read_reg(struct pci_channel *chan,
178 unsigned long reg)
177{ 179{
178 return ctrl_inl(PCI_REG(reg)); 180 return ctrl_inl(PCI_REG(reg));
179} 181}
182
180#endif /* __PCI_SH4_H */ 183#endif /* __PCI_SH4_H */
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 3065eb184f01..9c2c01490d62 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -40,21 +40,22 @@ static int __init sh7751_pci_init(void)
40 pr_debug("PCI: Starting intialization.\n"); 40 pr_debug("PCI: Starting intialization.\n");
41 41
42 /* check for SH7751/SH7751R hardware */ 42 /* check for SH7751/SH7751R hardware */
43 id = pci_read_reg(SH7751_PCICONF0); 43 id = pci_read_reg(NULL, SH7751_PCICONF0);
44 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) && 44 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
45 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) { 45 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
46 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id); 46 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
47 return -ENODEV; 47 return -ENODEV;
48 } 48 }
49 49
50 if ((ret = sh4_pci_check_direct()) != 0) 50 if ((ret = sh4_pci_check_direct(NULL)) != 0)
51 return ret; 51 return ret;
52 52
53 return pcibios_init_platform(); 53 return pcibios_init_platform();
54} 54}
55subsys_initcall(sh7751_pci_init); 55subsys_initcall(sh7751_pci_init);
56 56
57static int __init __area_sdram_check(unsigned int area) 57static int __init __area_sdram_check(struct pci_channel *chan,
58 unsigned int area)
58{ 59{
59 u32 word; 60 u32 word;
60 61
@@ -65,7 +66,7 @@ static int __init __area_sdram_check(unsigned int area)
65 area, word); 66 area, word);
66 return 0; 67 return 0;
67 } 68 }
68 pci_write_reg(word, SH4_PCIBCR1); 69 pci_write_reg(chan, word, SH4_PCIBCR1);
69 70
70 word = (u16)ctrl_inw(SH7751_BCR2); 71 word = (u16)ctrl_inw(SH7751_BCR2);
71 /* check BCR2 for 32bit SDRAM interface*/ 72 /* check BCR2 for 32bit SDRAM interface*/
@@ -74,12 +75,13 @@ static int __init __area_sdram_check(unsigned int area)
74 area, word); 75 area, word);
75 return 0; 76 return 0;
76 } 77 }
77 pci_write_reg(word, SH4_PCIBCR2); 78 pci_write_reg(chan, word, SH4_PCIBCR2);
78 79
79 return 1; 80 return 1;
80} 81}
81 82
82int __init sh7751_pcic_init(struct sh4_pci_address_map *map) 83int __init sh7751_pcic_init(struct pci_channel *chan,
84 struct sh4_pci_address_map *map)
83{ 85{
84 u32 reg; 86 u32 reg;
85 u32 word; 87 u32 word;
@@ -90,10 +92,10 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
90 ctrl_outl(reg, SH7751_BCR1); 92 ctrl_outl(reg, SH7751_BCR1);
91 93
92 /* Turn the clocks back on (not done in reset)*/ 94 /* Turn the clocks back on (not done in reset)*/
93 pci_write_reg(0, SH4_PCICLKR); 95 pci_write_reg(chan, 0, SH4_PCICLKR);
94 /* Clear Powerdown IRQ's (not done in reset) */ 96 /* Clear Powerdown IRQ's (not done in reset) */
95 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0; 97 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
96 pci_write_reg(word, SH4_PCIPINT); 98 pci_write_reg(chan, word, SH4_PCIPINT);
97 99
98 /* 100 /*
99 * This code is unused for some boards as it is done in the 101 * This code is unused for some boards as it is done in the
@@ -103,11 +105,11 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
103 if (!(map->flags & SH4_PCIC_NO_RESET)) { 105 if (!(map->flags & SH4_PCIC_NO_RESET)) {
104 /* toggle PCI reset pin */ 106 /* toggle PCI reset pin */
105 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST; 107 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
106 pci_write_reg(word, SH4_PCICR); 108 pci_write_reg(chan, word, SH4_PCICR);
107 /* Wait for a long time... not 1 sec. but long enough */ 109 /* Wait for a long time... not 1 sec. but long enough */
108 mdelay(100); 110 mdelay(100);
109 word = SH4_PCICR_PREFIX; 111 word = SH4_PCICR_PREFIX;
110 pci_write_reg(word, SH4_PCICR); 112 pci_write_reg(chan, word, SH4_PCICR);
111 } 113 }
112 114
113 /* set the command/status bits to: 115 /* set the command/status bits to:
@@ -116,11 +118,11 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
116 */ 118 */
117 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER | 119 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
118 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES; 120 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
119 pci_write_reg(word, SH7751_PCICONF1); 121 pci_write_reg(chan, word, SH7751_PCICONF1);
120 122
121 /* define this host as the host bridge */ 123 /* define this host as the host bridge */
122 word = PCI_BASE_CLASS_BRIDGE << 24; 124 word = PCI_BASE_CLASS_BRIDGE << 24;
123 pci_write_reg(word, SH7751_PCICONF2); 125 pci_write_reg(chan, word, SH7751_PCICONF2);
124 126
125 /* Set IO and Mem windows to local address 127 /* Set IO and Mem windows to local address
126 * Make PCI and local address the same for easy 1 to 1 mapping 128 * Make PCI and local address the same for easy 1 to 1 mapping
@@ -128,24 +130,24 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
128 * Window1 = map->window1.size @ cached area base = SDRAM 130 * Window1 = map->window1.size @ cached area base = SDRAM
129 */ 131 */
130 word = map->window0.size - 1; 132 word = map->window0.size - 1;
131 pci_write_reg(word, SH4_PCILSR0); 133 pci_write_reg(chan, word, SH4_PCILSR0);
132 word = map->window1.size - 1; 134 word = map->window1.size - 1;
133 pci_write_reg(word, SH4_PCILSR1); 135 pci_write_reg(chan, word, SH4_PCILSR1);
134 /* Set the values on window 0 PCI config registers */ 136 /* Set the values on window 0 PCI config registers */
135 word = P2SEGADDR(map->window0.base); 137 word = P2SEGADDR(map->window0.base);
136 pci_write_reg(word, SH4_PCILAR0); 138 pci_write_reg(chan, word, SH4_PCILAR0);
137 pci_write_reg(word, SH7751_PCICONF5); 139 pci_write_reg(chan, word, SH7751_PCICONF5);
138 /* Set the values on window 1 PCI config registers */ 140 /* Set the values on window 1 PCI config registers */
139 word = PHYSADDR(map->window1.base); 141 word = PHYSADDR(map->window1.base);
140 pci_write_reg(word, SH4_PCILAR1); 142 pci_write_reg(chan, word, SH4_PCILAR1);
141 pci_write_reg(word, SH7751_PCICONF6); 143 pci_write_reg(chan, word, SH7751_PCICONF6);
142 144
143 /* Set the local 16MB PCI memory space window to 145 /* Set the local 16MB PCI memory space window to
144 * the lowest PCI mapped address 146 * the lowest PCI mapped address
145 */ 147 */
146 word = PCIBIOS_MIN_MEM & SH4_PCIMBR_MASK; 148 word = PCIBIOS_MIN_MEM & SH4_PCIMBR_MASK;
147 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word); 149 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
148 pci_write_reg(word , SH4_PCIMBR); 150 pci_write_reg(chan, word , SH4_PCIMBR);
149 151
150 /* Map IO space into PCI IO window 152 /* Map IO space into PCI IO window
151 * The IO window is 64K-PCIBIOS_MIN_IO in size 153 * The IO window is 64K-PCIBIOS_MIN_IO in size
@@ -160,19 +162,19 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
160 * correctly */ 162 * correctly */
161 word = PCIBIOS_MIN_IO & SH4_PCIIOBR_MASK; 163 word = PCIBIOS_MIN_IO & SH4_PCIIOBR_MASK;
162 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word); 164 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
163 pci_write_reg(word, SH4_PCIIOBR); 165 pci_write_reg(chan, word, SH4_PCIIOBR);
164 166
165 /* Set PCI WCRx, BCRx's, copy from BSC locations */ 167 /* Set PCI WCRx, BCRx's, copy from BSC locations */
166 168
167 /* check BCR for SDRAM in specified area */ 169 /* check BCR for SDRAM in specified area */
168 switch (map->window0.base) { 170 switch (map->window0.base) {
169 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break; 171 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
170 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break; 172 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
171 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break; 173 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
172 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break; 174 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break;
173 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break; 175 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break;
174 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break; 176 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break;
175 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break; 177 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break;
176 } 178 }
177 179
178 if (!word) 180 if (!word)
@@ -180,25 +182,25 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
180 182
181 /* configure the wait control registers */ 183 /* configure the wait control registers */
182 word = ctrl_inl(SH7751_WCR1); 184 word = ctrl_inl(SH7751_WCR1);
183 pci_write_reg(word, SH4_PCIWCR1); 185 pci_write_reg(chan, word, SH4_PCIWCR1);
184 word = ctrl_inl(SH7751_WCR2); 186 word = ctrl_inl(SH7751_WCR2);
185 pci_write_reg(word, SH4_PCIWCR2); 187 pci_write_reg(chan, word, SH4_PCIWCR2);
186 word = ctrl_inl(SH7751_WCR3); 188 word = ctrl_inl(SH7751_WCR3);
187 pci_write_reg(word, SH4_PCIWCR3); 189 pci_write_reg(chan, word, SH4_PCIWCR3);
188 word = ctrl_inl(SH7751_MCR); 190 word = ctrl_inl(SH7751_MCR);
189 pci_write_reg(word, SH4_PCIMCR); 191 pci_write_reg(chan, word, SH4_PCIMCR);
190 192
191 /* NOTE: I'm ignoring the PCI error IRQs for now.. 193 /* NOTE: I'm ignoring the PCI error IRQs for now..
192 * TODO: add support for the internal error interrupts and 194 * TODO: add support for the internal error interrupts and
193 * DMA interrupts... 195 * DMA interrupts...
194 */ 196 */
195 197
196 pci_fixup_pcic(); 198 pci_fixup_pcic(chan);
197 199
198 /* SH7751 init done, set central function init complete */ 200 /* SH7751 init done, set central function init complete */
199 /* use round robin mode to stop a device starving/overruning */ 201 /* use round robin mode to stop a device starving/overruning */
200 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; 202 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
201 pci_write_reg(word, SH4_PCICR); 203 pci_write_reg(chan, word, SH4_PCICR);
202 204
203 return 1; 205 return 1;
204} 206}
diff --git a/arch/sh/drivers/pci/pci-sh7751.h b/arch/sh/drivers/pci/pci-sh7751.h
index 68e3cb5e6bec..6f101e5a6c83 100644
--- a/arch/sh/drivers/pci/pci-sh7751.h
+++ b/arch/sh/drivers/pci/pci-sh7751.h
@@ -130,6 +130,7 @@
130struct sh4_pci_address_map; 130struct sh4_pci_address_map;
131 131
132/* arch/sh/drivers/pci/pci-sh7751.c */ 132/* arch/sh/drivers/pci/pci-sh7751.c */
133int sh7751_pcic_init(struct sh4_pci_address_map *map); 133int sh7751_pcic_init(struct pci_channel *chan,
134 struct sh4_pci_address_map *map);
134 135
135#endif /* _PCI_SH7751_H_ */ 136#endif /* _PCI_SH7751_H_ */
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index bae6a2cf047d..56f673f66cb5 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -55,7 +55,7 @@ static int __init sh7780_pci_init(void)
55 ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */ 55 ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
56 56
57 /* check for SH7780/SH7780R hardware */ 57 /* check for SH7780/SH7780R hardware */
58 id = pci_read_reg(SH7780_PCIVID); 58 id = pci_read_reg(NULL, SH7780_PCIVID);
59 if ((id & 0xffff) == SH7780_VENDOR_ID) { 59 if ((id & 0xffff) == SH7780_VENDOR_ID) {
60 switch ((id >> 16) & 0xffff) { 60 switch ((id >> 16) & 0xffff) {
61 case SH7763_DEVICE_ID: 61 case SH7763_DEVICE_ID:
@@ -82,14 +82,15 @@ static int __init sh7780_pci_init(void)
82 ctrl_outl(0x33333333, INTC_INTPRI); 82 ctrl_outl(0x33333333, INTC_INTPRI);
83 } 83 }
84 84
85 if ((ret = sh4_pci_check_direct()) != 0) 85 if ((ret = sh4_pci_check_direct(NULL)) != 0)
86 return ret; 86 return ret;
87 87
88 return pcibios_init_platform(); 88 return pcibios_init_platform();
89} 89}
90core_initcall(sh7780_pci_init); 90core_initcall(sh7780_pci_init);
91 91
92int __init sh7780_pcic_init(struct sh4_pci_address_map *map) 92int __init sh7780_pcic_init(struct pci_channel *chan,
93 struct sh4_pci_address_map *map)
93{ 94{
94 u32 word; 95 u32 word;
95 96
@@ -101,34 +102,34 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
101 if (!(map->flags & SH4_PCIC_NO_RESET)) { 102 if (!(map->flags & SH4_PCIC_NO_RESET)) {
102 /* toggle PCI reset pin */ 103 /* toggle PCI reset pin */
103 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST; 104 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
104 pci_write_reg(word, SH4_PCICR); 105 pci_write_reg(chan, word, SH4_PCICR);
105 /* Wait for a long time... not 1 sec. but long enough */ 106 /* Wait for a long time... not 1 sec. but long enough */
106 mdelay(100); 107 mdelay(100);
107 word = SH4_PCICR_PREFIX; 108 word = SH4_PCICR_PREFIX;
108 pci_write_reg(word, SH4_PCICR); 109 pci_write_reg(chan, word, SH4_PCICR);
109 } 110 }
110 111
111 /* set the command/status bits to: 112 /* set the command/status bits to:
112 * Wait Cycle Control + Parity Enable + Bus Master + 113 * Wait Cycle Control + Parity Enable + Bus Master +
113 * Mem space enable 114 * Mem space enable
114 */ 115 */
115 pci_write_reg(0x00000046, SH7780_PCICMD); 116 pci_write_reg(chan, 0x00000046, SH7780_PCICMD);
116 117
117 /* define this host as the host bridge */ 118 /* define this host as the host bridge */
118 word = PCI_BASE_CLASS_BRIDGE << 24; 119 word = PCI_BASE_CLASS_BRIDGE << 24;
119 pci_write_reg(word, SH7780_PCIRID); 120 pci_write_reg(chan, word, SH7780_PCIRID);
120 121
121 /* Set IO and Mem windows to local address 122 /* Set IO and Mem windows to local address
122 * Make PCI and local address the same for easy 1 to 1 mapping 123 * Make PCI and local address the same for easy 1 to 1 mapping
123 */ 124 */
124 pci_write_reg(map->window0.size - 0xfffff, SH4_PCILSR0); 125 pci_write_reg(chan, map->window0.size - 0xfffff, SH4_PCILSR0);
125 pci_write_reg(map->window1.size - 0xfffff, SH4_PCILSR1); 126 pci_write_reg(chan, map->window1.size - 0xfffff, SH4_PCILSR1);
126 /* Set the values on window 0 PCI config registers */ 127 /* Set the values on window 0 PCI config registers */
127 pci_write_reg(map->window0.base, SH4_PCILAR0); 128 pci_write_reg(chan, map->window0.base, SH4_PCILAR0);
128 pci_write_reg(map->window0.base, SH7780_PCIMBAR0); 129 pci_write_reg(chan, map->window0.base, SH7780_PCIMBAR0);
129 /* Set the values on window 1 PCI config registers */ 130 /* Set the values on window 1 PCI config registers */
130 pci_write_reg(map->window1.base, SH4_PCILAR1); 131 pci_write_reg(chan, map->window1.base, SH4_PCILAR1);
131 pci_write_reg(map->window1.base, SH7780_PCIMBAR1); 132 pci_write_reg(chan, map->window1.base, SH7780_PCIMBAR1);
132 133
133 /* Map IO space into PCI IO window 134 /* Map IO space into PCI IO window
134 * The IO window is 64K-PCIBIOS_MIN_IO in size 135 * The IO window is 64K-PCIBIOS_MIN_IO in size
@@ -145,12 +146,12 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
145 */ 146 */
146 147
147 /* Apply any last-minute PCIC fixups */ 148 /* Apply any last-minute PCIC fixups */
148 pci_fixup_pcic(); 149 pci_fixup_pcic(chan);
149 150
150 /* SH7780 init done, set central function init complete */ 151 /* SH7780 init done, set central function init complete */
151 /* use round robin mode to stop a device starving/overruning */ 152 /* use round robin mode to stop a device starving/overruning */
152 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO; 153 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
153 pci_write_reg(word, SH4_PCICR); 154 pci_write_reg(chan, word, SH4_PCICR);
154 155
155 return 1; 156 return 1;
156} 157}
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index 93adc7119b79..d34961153d58 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -109,6 +109,7 @@
109struct sh4_pci_address_map; 109struct sh4_pci_address_map;
110 110
111/* arch/sh/drivers/pci/pci-sh7780.c */ 111/* arch/sh/drivers/pci/pci-sh7780.c */
112int sh7780_pcic_init(struct sh4_pci_address_map *map); 112int sh7780_pcic_init(struct pci_channel *chan,
113 struct sh4_pci_address_map *map);
113 114
114#endif /* _PCI_SH7780_H_ */ 115#endif /* _PCI_SH7780_H_ */