diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2014-05-16 21:19:54 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2014-06-11 02:10:43 -0400 |
commit | b8407c9e504f43a50ba0de746c5e8958521165aa (patch) | |
tree | b7694dcc61b4569bc65658563ba59ed52821440a | |
parent | 456b0579fb0af095c24fa9e5867bd3983b842b1a (diff) |
drm/nouveau/disp/dp: create subclass for dp outputs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/gm107.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nv50.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nv50.h | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nv84.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nv94.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nva0.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nva3.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nve0.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c | 144 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h | 49 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c | 19 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c | 11 |
16 files changed, 265 insertions, 9 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index de2eada522a0..2b6156d0e4b5 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile | |||
@@ -224,6 +224,7 @@ nouveau-y += core/engine/device/gm100.o | |||
224 | nouveau-y += core/engine/disp/base.o | 224 | nouveau-y += core/engine/disp/base.o |
225 | nouveau-y += core/engine/disp/conn.o | 225 | nouveau-y += core/engine/disp/conn.o |
226 | nouveau-y += core/engine/disp/outp.o | 226 | nouveau-y += core/engine/disp/outp.o |
227 | nouveau-y += core/engine/disp/outpdp.o | ||
227 | nouveau-y += core/engine/disp/nv04.o | 228 | nouveau-y += core/engine/disp/nv04.o |
228 | nouveau-y += core/engine/disp/nv50.o | 229 | nouveau-y += core/engine/disp/nv50.o |
229 | nouveau-y += core/engine/disp/nv84.o | 230 | nouveau-y += core/engine/disp/nv84.o |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c index cf6f59677b74..a5b0ad6d3bfa 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c | |||
@@ -94,6 +94,7 @@ gm107_disp_oclass = &(struct nv50_disp_impl) { | |||
94 | .init = _nouveau_disp_init, | 94 | .init = _nouveau_disp_init, |
95 | .fini = _nouveau_disp_fini, | 95 | .fini = _nouveau_disp_fini, |
96 | }, | 96 | }, |
97 | .base.outp = nvd0_disp_outp_sclass, | ||
97 | .mthd.core = &nve0_disp_mast_mthd_chan, | 98 | .mthd.core = &nve0_disp_mast_mthd_chan, |
98 | .mthd.base = &nvd0_disp_sync_mthd_chan, | 99 | .mthd.base = &nvd0_disp_sync_mthd_chan, |
99 | .mthd.ovly = &nve0_disp_ovly_mthd_chan, | 100 | .mthd.ovly = &nve0_disp_ovly_mthd_chan, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c index 2956c131cbd9..bba9d4d1d010 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c | |||
@@ -1661,6 +1661,12 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
1661 | } | 1661 | } |
1662 | 1662 | ||
1663 | struct nouveau_oclass * | 1663 | struct nouveau_oclass * |
1664 | nv50_disp_outp_sclass[] = { | ||
1665 | &nv50_pior_dp_impl.base.base, | ||
1666 | NULL | ||
1667 | }; | ||
1668 | |||
1669 | struct nouveau_oclass * | ||
1664 | nv50_disp_oclass = &(struct nv50_disp_impl) { | 1670 | nv50_disp_oclass = &(struct nv50_disp_impl) { |
1665 | .base.base.handle = NV_ENGINE(DISP, 0x50), | 1671 | .base.base.handle = NV_ENGINE(DISP, 0x50), |
1666 | .base.base.ofuncs = &(struct nouveau_ofuncs) { | 1672 | .base.base.ofuncs = &(struct nouveau_ofuncs) { |
@@ -1669,6 +1675,7 @@ nv50_disp_oclass = &(struct nv50_disp_impl) { | |||
1669 | .init = _nouveau_disp_init, | 1675 | .init = _nouveau_disp_init, |
1670 | .fini = _nouveau_disp_fini, | 1676 | .fini = _nouveau_disp_fini, |
1671 | }, | 1677 | }, |
1678 | .base.outp = nv50_disp_outp_sclass, | ||
1672 | .mthd.core = &nv50_disp_mast_mthd_chan, | 1679 | .mthd.core = &nv50_disp_mast_mthd_chan, |
1673 | .mthd.base = &nv50_disp_sync_mthd_chan, | 1680 | .mthd.base = &nv50_disp_sync_mthd_chan, |
1674 | .mthd.ovly = &nv50_disp_ovly_mthd_chan, | 1681 | .mthd.ovly = &nv50_disp_ovly_mthd_chan, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h index 24cb180f73f0..d5468a61f5e0 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h | |||
@@ -12,6 +12,7 @@ | |||
12 | #include "dport.h" | 12 | #include "dport.h" |
13 | #include "priv.h" | 13 | #include "priv.h" |
14 | #include "outp.h" | 14 | #include "outp.h" |
15 | #include "outpdp.h" | ||
15 | 16 | ||
16 | struct nv50_disp_impl { | 17 | struct nv50_disp_impl { |
17 | struct nouveau_disp_impl base; | 18 | struct nouveau_disp_impl base; |
@@ -200,4 +201,13 @@ void nvd0_disp_intr(struct nouveau_subdev *); | |||
200 | extern const struct nv50_disp_mthd_chan nve0_disp_mast_mthd_chan; | 201 | extern const struct nv50_disp_mthd_chan nve0_disp_mast_mthd_chan; |
201 | extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan; | 202 | extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan; |
202 | 203 | ||
204 | extern struct nvkm_output_dp_impl nv50_pior_dp_impl; | ||
205 | extern struct nouveau_oclass *nv50_disp_outp_sclass[]; | ||
206 | |||
207 | extern struct nvkm_output_dp_impl nv94_sor_dp_impl; | ||
208 | extern struct nouveau_oclass *nv94_disp_outp_sclass[]; | ||
209 | |||
210 | extern struct nvkm_output_dp_impl nvd0_sor_dp_impl; | ||
211 | extern struct nouveau_oclass *nvd0_disp_outp_sclass[]; | ||
212 | |||
203 | #endif | 213 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c index 98c5b19bc2b0..436f0a5eb46d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c | |||
@@ -277,6 +277,7 @@ nv84_disp_oclass = &(struct nv50_disp_impl) { | |||
277 | .init = _nouveau_disp_init, | 277 | .init = _nouveau_disp_init, |
278 | .fini = _nouveau_disp_fini, | 278 | .fini = _nouveau_disp_fini, |
279 | }, | 279 | }, |
280 | .base.outp = nv50_disp_outp_sclass, | ||
280 | .mthd.core = &nv84_disp_mast_mthd_chan, | 281 | .mthd.core = &nv84_disp_mast_mthd_chan, |
281 | .mthd.base = &nv84_disp_sync_mthd_chan, | 282 | .mthd.base = &nv84_disp_sync_mthd_chan, |
282 | .mthd.ovly = &nv84_disp_ovly_mthd_chan, | 283 | .mthd.ovly = &nv84_disp_ovly_mthd_chan, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c index 6844061c7e04..14f53143b81b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c | |||
@@ -129,6 +129,13 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
129 | } | 129 | } |
130 | 130 | ||
131 | struct nouveau_oclass * | 131 | struct nouveau_oclass * |
132 | nv94_disp_outp_sclass[] = { | ||
133 | &nv50_pior_dp_impl.base.base, | ||
134 | &nv94_sor_dp_impl.base.base, | ||
135 | NULL | ||
136 | }; | ||
137 | |||
138 | struct nouveau_oclass * | ||
132 | nv94_disp_oclass = &(struct nv50_disp_impl) { | 139 | nv94_disp_oclass = &(struct nv50_disp_impl) { |
133 | .base.base.handle = NV_ENGINE(DISP, 0x88), | 140 | .base.base.handle = NV_ENGINE(DISP, 0x88), |
134 | .base.base.ofuncs = &(struct nouveau_ofuncs) { | 141 | .base.base.ofuncs = &(struct nouveau_ofuncs) { |
@@ -137,6 +144,7 @@ nv94_disp_oclass = &(struct nv50_disp_impl) { | |||
137 | .init = _nouveau_disp_init, | 144 | .init = _nouveau_disp_init, |
138 | .fini = _nouveau_disp_fini, | 145 | .fini = _nouveau_disp_fini, |
139 | }, | 146 | }, |
147 | .base.outp = nv94_disp_outp_sclass, | ||
140 | .mthd.core = &nv94_disp_mast_mthd_chan, | 148 | .mthd.core = &nv94_disp_mast_mthd_chan, |
141 | .mthd.base = &nv84_disp_sync_mthd_chan, | 149 | .mthd.base = &nv84_disp_sync_mthd_chan, |
142 | .mthd.ovly = &nv84_disp_ovly_mthd_chan, | 150 | .mthd.ovly = &nv84_disp_ovly_mthd_chan, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c index 88c96241c02a..b8926200baa7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c | |||
@@ -139,6 +139,7 @@ nva0_disp_oclass = &(struct nv50_disp_impl) { | |||
139 | .init = _nouveau_disp_init, | 139 | .init = _nouveau_disp_init, |
140 | .fini = _nouveau_disp_fini, | 140 | .fini = _nouveau_disp_fini, |
141 | }, | 141 | }, |
142 | .base.outp = nv50_disp_outp_sclass, | ||
142 | .mthd.core = &nv84_disp_mast_mthd_chan, | 143 | .mthd.core = &nv84_disp_mast_mthd_chan, |
143 | .mthd.base = &nv84_disp_sync_mthd_chan, | 144 | .mthd.base = &nv84_disp_sync_mthd_chan, |
144 | .mthd.ovly = &nva0_disp_ovly_mthd_chan, | 145 | .mthd.ovly = &nva0_disp_ovly_mthd_chan, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c index 46cb2ce0e82a..aae561ff838a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c | |||
@@ -111,6 +111,7 @@ nva3_disp_oclass = &(struct nv50_disp_impl) { | |||
111 | .init = _nouveau_disp_init, | 111 | .init = _nouveau_disp_init, |
112 | .fini = _nouveau_disp_fini, | 112 | .fini = _nouveau_disp_fini, |
113 | }, | 113 | }, |
114 | .base.outp = nv94_disp_outp_sclass, | ||
114 | .mthd.core = &nv94_disp_mast_mthd_chan, | 115 | .mthd.core = &nv94_disp_mast_mthd_chan, |
115 | .mthd.base = &nv84_disp_sync_mthd_chan, | 116 | .mthd.base = &nv84_disp_sync_mthd_chan, |
116 | .mthd.ovly = &nv84_disp_ovly_mthd_chan, | 117 | .mthd.ovly = &nv84_disp_ovly_mthd_chan, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c index 7bf54e81275b..e5f5e425e3e2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c | |||
@@ -1357,6 +1357,12 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
1357 | } | 1357 | } |
1358 | 1358 | ||
1359 | struct nouveau_oclass * | 1359 | struct nouveau_oclass * |
1360 | nvd0_disp_outp_sclass[] = { | ||
1361 | &nvd0_sor_dp_impl.base.base, | ||
1362 | NULL | ||
1363 | }; | ||
1364 | |||
1365 | struct nouveau_oclass * | ||
1360 | nvd0_disp_oclass = &(struct nv50_disp_impl) { | 1366 | nvd0_disp_oclass = &(struct nv50_disp_impl) { |
1361 | .base.base.handle = NV_ENGINE(DISP, 0x90), | 1367 | .base.base.handle = NV_ENGINE(DISP, 0x90), |
1362 | .base.base.ofuncs = &(struct nouveau_ofuncs) { | 1368 | .base.base.ofuncs = &(struct nouveau_ofuncs) { |
@@ -1365,6 +1371,7 @@ nvd0_disp_oclass = &(struct nv50_disp_impl) { | |||
1365 | .init = _nouveau_disp_init, | 1371 | .init = _nouveau_disp_init, |
1366 | .fini = _nouveau_disp_fini, | 1372 | .fini = _nouveau_disp_fini, |
1367 | }, | 1373 | }, |
1374 | .base.outp = nvd0_disp_outp_sclass, | ||
1368 | .mthd.core = &nvd0_disp_mast_mthd_chan, | 1375 | .mthd.core = &nvd0_disp_mast_mthd_chan, |
1369 | .mthd.base = &nvd0_disp_sync_mthd_chan, | 1376 | .mthd.base = &nvd0_disp_sync_mthd_chan, |
1370 | .mthd.ovly = &nvd0_disp_ovly_mthd_chan, | 1377 | .mthd.ovly = &nvd0_disp_ovly_mthd_chan, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c index 44e0b8f34c1a..90f79be94bd7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c | |||
@@ -259,6 +259,7 @@ nve0_disp_oclass = &(struct nv50_disp_impl) { | |||
259 | .init = _nouveau_disp_init, | 259 | .init = _nouveau_disp_init, |
260 | .fini = _nouveau_disp_fini, | 260 | .fini = _nouveau_disp_fini, |
261 | }, | 261 | }, |
262 | .base.outp = nvd0_disp_outp_sclass, | ||
262 | .mthd.core = &nve0_disp_mast_mthd_chan, | 263 | .mthd.core = &nve0_disp_mast_mthd_chan, |
263 | .mthd.base = &nvd0_disp_sync_mthd_chan, | 264 | .mthd.base = &nvd0_disp_sync_mthd_chan, |
264 | .mthd.ovly = &nve0_disp_ovly_mthd_chan, | 265 | .mthd.ovly = &nve0_disp_ovly_mthd_chan, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c index 482585d375fa..25a18dffcb44 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c | |||
@@ -94,6 +94,7 @@ nvf0_disp_oclass = &(struct nv50_disp_impl) { | |||
94 | .init = _nouveau_disp_init, | 94 | .init = _nouveau_disp_init, |
95 | .fini = _nouveau_disp_fini, | 95 | .fini = _nouveau_disp_fini, |
96 | }, | 96 | }, |
97 | .base.outp = nvd0_disp_outp_sclass, | ||
97 | .mthd.core = &nve0_disp_mast_mthd_chan, | 98 | .mthd.core = &nve0_disp_mast_mthd_chan, |
98 | .mthd.base = &nvd0_disp_sync_mthd_chan, | 99 | .mthd.base = &nvd0_disp_sync_mthd_chan, |
99 | .mthd.ovly = &nve0_disp_ovly_mthd_chan, | 100 | .mthd.ovly = &nve0_disp_ovly_mthd_chan, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c new file mode 100644 index 000000000000..ea6483d066c1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c | |||
@@ -0,0 +1,144 @@ | |||
1 | /* | ||
2 | * Copyright 2014 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include <subdev/i2c.h> | ||
26 | |||
27 | #include "outpdp.h" | ||
28 | #include "conn.h" | ||
29 | |||
30 | static int | ||
31 | nvkm_output_dp_service(void *data, u32 type, int index) | ||
32 | { | ||
33 | struct nvkm_output_dp *outp = data; | ||
34 | DBG("IRQ: %d\n", type); | ||
35 | return NVKM_EVENT_KEEP; | ||
36 | } | ||
37 | |||
38 | static int | ||
39 | nvkm_output_dp_hotplug(void *data, u32 type, int index) | ||
40 | { | ||
41 | struct nvkm_output_dp *outp = data; | ||
42 | DBG("HPD: %d\n", type); | ||
43 | return NVKM_EVENT_KEEP; | ||
44 | } | ||
45 | |||
46 | int | ||
47 | _nvkm_output_dp_fini(struct nouveau_object *object, bool suspend) | ||
48 | { | ||
49 | struct nvkm_output_dp *outp = (void *)object; | ||
50 | nouveau_event_put(outp->irq); | ||
51 | return nvkm_output_fini(&outp->base, suspend); | ||
52 | } | ||
53 | |||
54 | int | ||
55 | _nvkm_output_dp_init(struct nouveau_object *object) | ||
56 | { | ||
57 | struct nvkm_output_dp *outp = (void *)object; | ||
58 | return nvkm_output_init(&outp->base); | ||
59 | } | ||
60 | |||
61 | void | ||
62 | _nvkm_output_dp_dtor(struct nouveau_object *object) | ||
63 | { | ||
64 | struct nvkm_output_dp *outp = (void *)object; | ||
65 | nouveau_event_ref(NULL, &outp->irq); | ||
66 | nvkm_output_destroy(&outp->base); | ||
67 | } | ||
68 | |||
69 | int | ||
70 | nvkm_output_dp_create_(struct nouveau_object *parent, | ||
71 | struct nouveau_object *engine, | ||
72 | struct nouveau_oclass *oclass, | ||
73 | struct dcb_output *info, int index, | ||
74 | int length, void **pobject) | ||
75 | { | ||
76 | struct nouveau_bios *bios = nouveau_bios(parent); | ||
77 | struct nouveau_i2c *i2c = nouveau_i2c(parent); | ||
78 | struct nvkm_output_dp *outp; | ||
79 | u8 hdr, cnt, len; | ||
80 | u32 data; | ||
81 | int ret; | ||
82 | |||
83 | ret = nvkm_output_create_(parent, engine, oclass, info, index, | ||
84 | length, pobject); | ||
85 | outp = *pobject; | ||
86 | if (ret) | ||
87 | return ret; | ||
88 | |||
89 | nouveau_event_ref(NULL, &outp->base.conn->hpd.event); | ||
90 | |||
91 | /* access to the aux channel is not optional... */ | ||
92 | if (!outp->base.edid) { | ||
93 | ERR("aux channel not found\n"); | ||
94 | return -ENODEV; | ||
95 | } | ||
96 | |||
97 | /* nor is the bios data for this output... */ | ||
98 | data = nvbios_dpout_match(bios, outp->base.info.hasht, | ||
99 | outp->base.info.hashm, &outp->version, | ||
100 | &hdr, &cnt, &len, &outp->info); | ||
101 | if (!data) { | ||
102 | ERR("no bios dp data\n"); | ||
103 | return -ENODEV; | ||
104 | } | ||
105 | |||
106 | DBG("bios dp %02x %02x %02x %02x\n", outp->version, hdr, cnt, len); | ||
107 | |||
108 | /* link maintenance */ | ||
109 | ret = nouveau_event_new(i2c->ntfy, NVKM_I2C_IRQ, outp->base.edid->index, | ||
110 | nvkm_output_dp_service, outp, &outp->irq); | ||
111 | if (ret) { | ||
112 | ERR("error monitoring aux irq event: %d\n", ret); | ||
113 | return ret; | ||
114 | } | ||
115 | |||
116 | /* hotplug detect, replaces gpio-based mechanism with aux events */ | ||
117 | ret = nouveau_event_new(i2c->ntfy, NVKM_I2C_PLUG | NVKM_I2C_UNPLUG, | ||
118 | outp->base.edid->index, | ||
119 | nvkm_output_dp_hotplug, outp, | ||
120 | &outp->base.conn->hpd.event); | ||
121 | if (ret) { | ||
122 | ERR("error monitoring aux hpd events: %d\n", ret); | ||
123 | return ret; | ||
124 | } | ||
125 | |||
126 | return 0; | ||
127 | } | ||
128 | |||
129 | int | ||
130 | _nvkm_output_dp_ctor(struct nouveau_object *parent, | ||
131 | struct nouveau_object *engine, | ||
132 | struct nouveau_oclass *oclass, void *info, u32 index, | ||
133 | struct nouveau_object **pobject) | ||
134 | { | ||
135 | struct nvkm_output_dp *outp; | ||
136 | int ret; | ||
137 | |||
138 | ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp); | ||
139 | *pobject = nv_object(outp); | ||
140 | if (ret) | ||
141 | return ret; | ||
142 | |||
143 | return 0; | ||
144 | } | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h new file mode 100644 index 000000000000..22f692da1b1d --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h | |||
@@ -0,0 +1,49 @@ | |||
1 | #ifndef __NVKM_DISP_OUTP_DP_H__ | ||
2 | #define __NVKM_DISP_OUTP_DP_H__ | ||
3 | |||
4 | #include <subdev/bios.h> | ||
5 | #include <subdev/bios/dp.h> | ||
6 | |||
7 | #include "outp.h" | ||
8 | |||
9 | struct nvkm_output_dp { | ||
10 | struct nvkm_output base; | ||
11 | |||
12 | struct nvbios_dpout info; | ||
13 | u8 version; | ||
14 | |||
15 | struct nouveau_eventh *irq; | ||
16 | struct nouveau_eventh *hpd; | ||
17 | }; | ||
18 | |||
19 | #define nvkm_output_dp_create(p,e,c,b,i,d) \ | ||
20 | nvkm_output_dp_create_((p), (e), (c), (b), (i), sizeof(**d), (void **)d) | ||
21 | #define nvkm_output_dp_destroy(d) ({ \ | ||
22 | struct nvkm_output_dp *_outp = (d); \ | ||
23 | _nvkm_output_dp_dtor(nv_object(_outp)); \ | ||
24 | }) | ||
25 | #define nvkm_output_dp_init(d) ({ \ | ||
26 | struct nvkm_output_dp *_outp = (d); \ | ||
27 | _nvkm_output_dp_init(nv_object(_outp)); \ | ||
28 | }) | ||
29 | #define nvkm_output_dp_fini(d,s) ({ \ | ||
30 | struct nvkm_output_dp *_outp = (d); \ | ||
31 | _nvkm_output_dp_fini(nv_object(_outp), (s)); \ | ||
32 | }) | ||
33 | |||
34 | int nvkm_output_dp_create_(struct nouveau_object *, struct nouveau_object *, | ||
35 | struct nouveau_oclass *, struct dcb_output *, | ||
36 | int, int, void **); | ||
37 | |||
38 | int _nvkm_output_dp_ctor(struct nouveau_object *, struct nouveau_object *, | ||
39 | struct nouveau_oclass *, void *, u32, | ||
40 | struct nouveau_object **); | ||
41 | void _nvkm_output_dp_dtor(struct nouveau_object *); | ||
42 | int _nvkm_output_dp_init(struct nouveau_object *); | ||
43 | int _nvkm_output_dp_fini(struct nouveau_object *, bool); | ||
44 | |||
45 | struct nvkm_output_dp_impl { | ||
46 | struct nvkm_output_impl base; | ||
47 | }; | ||
48 | |||
49 | #endif | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c index c4d36edc3dfb..2c1eacd8019a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c | |||
@@ -141,26 +141,27 @@ nv50_pior_dp_ctor(struct nouveau_object *parent, | |||
141 | struct nouveau_object **pobject) | 141 | struct nouveau_object **pobject) |
142 | { | 142 | { |
143 | struct nouveau_i2c *i2c = nouveau_i2c(parent); | 143 | struct nouveau_i2c *i2c = nouveau_i2c(parent); |
144 | struct nvkm_output *outp; | 144 | struct nvkm_output_dp *outp; |
145 | int ret; | 145 | int ret; |
146 | 146 | ||
147 | ret = nvkm_output_create(parent, engine, oclass, info, index, &outp); | 147 | ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp); |
148 | *pobject = nv_object(outp); | 148 | *pobject = nv_object(outp); |
149 | if (ret) | 149 | if (ret) |
150 | return ret; | 150 | return ret; |
151 | 151 | ||
152 | outp->edid = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(outp->info.extdev)); | 152 | outp->base.edid = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX( |
153 | outp->base.info.extdev)); | ||
153 | return 0; | 154 | return 0; |
154 | } | 155 | } |
155 | 156 | ||
156 | struct nvkm_output_impl | 157 | struct nvkm_output_dp_impl |
157 | nv50_pior_dp_impl = { | 158 | nv50_pior_dp_impl = { |
158 | .base.handle = DCB_OUTPUT_DP | 0x0100, | 159 | .base.base.handle = DCB_OUTPUT_DP | 0x0010, |
159 | .base.ofuncs = &(struct nouveau_ofuncs) { | 160 | .base.base.ofuncs = &(struct nouveau_ofuncs) { |
160 | .ctor = nv50_pior_dp_ctor, | 161 | .ctor = nv50_pior_dp_ctor, |
161 | .dtor = _nvkm_output_dtor, | 162 | .dtor = _nvkm_output_dp_dtor, |
162 | .init = _nvkm_output_init, | 163 | .init = _nvkm_output_dp_init, |
163 | .fini = _nvkm_output_fini, | 164 | .fini = _nvkm_output_dp_fini, |
164 | }, | 165 | }, |
165 | }; | 166 | }; |
166 | 167 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c index eea3ef59693d..ca551eabc1c9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <subdev/bios/init.h> | 31 | #include <subdev/bios/init.h> |
32 | 32 | ||
33 | #include "nv50.h" | 33 | #include "nv50.h" |
34 | #include "outpdp.h" | ||
34 | 35 | ||
35 | static inline u32 | 36 | static inline u32 |
36 | nv94_sor_soff(struct dcb_output *outp) | 37 | nv94_sor_soff(struct dcb_output *outp) |
@@ -129,3 +130,14 @@ nv94_sor_dp_func = { | |||
129 | .lnk_ctl = nv94_sor_dp_lnk_ctl, | 130 | .lnk_ctl = nv94_sor_dp_lnk_ctl, |
130 | .drv_ctl = nv94_sor_dp_drv_ctl, | 131 | .drv_ctl = nv94_sor_dp_drv_ctl, |
131 | }; | 132 | }; |
133 | |||
134 | struct nvkm_output_dp_impl | ||
135 | nv94_sor_dp_impl = { | ||
136 | .base.base.handle = DCB_OUTPUT_DP, | ||
137 | .base.base.ofuncs = &(struct nouveau_ofuncs) { | ||
138 | .ctor = _nvkm_output_dp_ctor, | ||
139 | .dtor = _nvkm_output_dp_dtor, | ||
140 | .init = _nvkm_output_dp_init, | ||
141 | .fini = _nvkm_output_dp_fini, | ||
142 | }, | ||
143 | }; | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c index d2df572f16a3..ffd4531d81bb 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c | |||
@@ -126,3 +126,14 @@ nvd0_sor_dp_func = { | |||
126 | .lnk_ctl = nvd0_sor_dp_lnk_ctl, | 126 | .lnk_ctl = nvd0_sor_dp_lnk_ctl, |
127 | .drv_ctl = nvd0_sor_dp_drv_ctl, | 127 | .drv_ctl = nvd0_sor_dp_drv_ctl, |
128 | }; | 128 | }; |
129 | |||
130 | struct nvkm_output_dp_impl | ||
131 | nvd0_sor_dp_impl = { | ||
132 | .base.base.handle = DCB_OUTPUT_DP, | ||
133 | .base.base.ofuncs = &(struct nouveau_ofuncs) { | ||
134 | .ctor = _nvkm_output_dp_ctor, | ||
135 | .dtor = _nvkm_output_dp_dtor, | ||
136 | .init = _nvkm_output_dp_init, | ||
137 | .fini = _nvkm_output_dp_fini, | ||
138 | }, | ||
139 | }; | ||