Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
very strange place, but the watchdog driver needs to read the clock
rate from it and the setting of rk3288 plls to slow mode upon suspend.

Other than that some more exported clocks and a CLK_SET_RATE_PARENT
flag for the uart clocks.

2 files changed, 39 insertions, 13 deletions

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 11194b8329fe..eeadbb6b5206 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -535,44 +535,44 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
                         RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
                         RK3288_CLKGATE_CON(1), 8, GFLAGS),
-        COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", 0,
+        COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(17), 0,
                         RK3288_CLKGATE_CON(1), 9, GFLAGS),
-        MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, 0,
+        MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(13), 8, 2, MFLAGS),
         MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
                         RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
         COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
                         RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
                         RK3288_CLKGATE_CON(1), 10, GFLAGS),
-        COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", 0,
+        COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(18), 0,
                         RK3288_CLKGATE_CON(1), 11, GFLAGS),
-        MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, 0,
+        MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(14), 8, 2, MFLAGS),
         COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
                         RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
                         RK3288_CLKGATE_CON(1), 12, GFLAGS),
-        COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", 0,
+        COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(19), 0,
                         RK3288_CLKGATE_CON(1), 13, GFLAGS),
-        MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, 0,
+        MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(15), 8, 2, MFLAGS),
         COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
                         RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
                         RK3288_CLKGATE_CON(1), 14, GFLAGS),
-        COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", 0,
+        COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(20), 0,
                         RK3288_CLKGATE_CON(1), 15, GFLAGS),
-        MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, 0,
+        MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(16), 8, 2, MFLAGS),
         COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
                         RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
                         RK3288_CLKGATE_CON(2), 12, GFLAGS),
-        COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", 0,
+        COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(7), 0,
                         RK3288_CLKGATE_CON(2), 13, GFLAGS),
-        MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, 0,
+        MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
                         RK3288_CLKSEL_CON(3), 8, 2, MFLAGS),
 
         COMPOSITE(0, "mac_src", mux_pll_src_npll_cpll_gpll_p, 0,
@@ -598,7 +598,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
         GATE(0, "jtag", "ext_jtag", 0,
                         RK3288_CLKGATE_CON(4), 14, GFLAGS),
 
-        COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
+        COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
                         RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
                         RK3288_CLKGATE_CON(5), 14, GFLAGS),
         COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
@@ -704,8 +704,8 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
         GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
         GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
-        GATE(0, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
-        GATE(0, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
+        GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
+        GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
         GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
 
         /* sclk_gpu gates */
@@ -805,6 +805,20 @@ static int rk3288_clk_suspend(void)
                 rk3288_saved_cru_regs[i] =
                                 readl_relaxed(rk3288_cru_base + reg_id);
         }
+
+        /*
+         * Switch PLLs other than DPLL (for SDRAM) to slow mode to
+         * avoid crashes on resume. The Mask ROM on the system will
+         * put APLL, CPLL, and GPLL into slow mode at resume time
+         * anyway (which is why we restore them), but we might not
+         * even make it to the Mask ROM if this isn't done at suspend
+         * time.
+         *
+         * NOTE: only APLL truly matters here, but we'll do them all.
+         */
+
+        writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
+
         return 0;
 }
 
@@ -866,6 +880,14 @@ static void __init rk3288_clk_init(struct device_node *np)
                 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
                         __func__, PTR_ERR(clk));
 
+        /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
+        clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
+        if (IS_ERR(clk))
+                pr_warn("%s: could not register clock pclk_wdt: %ld\n",
+                        __func__, PTR_ERR(clk));
+        else
+                rockchip_clk_add_lookup(clk, PCLK_WDT);
+
         rockchip_clk_register_plls(rk3288_pll_clks,
                                    ARRAY_SIZE(rk3288_pll_clks),
                                    RK3288_GRF_SOC_STATUS1);
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index f60ce72a2b2c..1e626335acf3 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -80,6 +80,9 @@
 #define SCLK_SDIO0_SAMPLE       119
 #define SCLK_SDIO1_SAMPLE       120
 #define SCLK_EMMC_SAMPLE        121
+#define SCLK_USBPHY480M_SRC     122
+#define SCLK_PVTM_CORE          123
+#define SCLK_PVTM_GPU           124
 
 #define DCLK_VOP0               190
 #define DCLK_VOP1               191
@@ -154,6 +157,7 @@
 #define PCLK_PUBL0              365
 #define PCLK_DDRUPCTL1          366
 #define PCLK_PUBL1              367
+#define PCLK_WDT                368
 
 /* hclk gates */
 #define HCLK_GPS                448