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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2015-03-12 10:54:25 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2015-03-13 10:11:04 -0400
commitb7e9def92345c97f5ad43a150bcbcf8d44e46310 (patch)
treeeca6929f0779f2e88d209a8eec993a6abe1f3886
parent0d3441928b45cc42fdc8949153e8a0b51615300d (diff)
ARM: at91: remove unused _matrix.h headers
The matrix headers are not used anymore, remove them. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260_matrix.h80
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261_matrix.h64
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263_matrix.h129
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h153
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h53
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h96
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h53
7 files changed, 0 insertions, 628 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
deleted file mode 100644
index f459df420629..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9260 datasheet revision B.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9260_MATRIX_H
16#define AT91SAM9260_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
25#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
26#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
27#define AT91_MATRIX_ULBT_FOUR (2 << 0)
28#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
29#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
30
31#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
32#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
33#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
34#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
35#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
39#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
40#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
41#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
42#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45
46#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
52#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
53#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
54#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
55#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
56#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
57
58#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
59#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
60#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
61
62#define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */
63#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
64#define AT91_MATRIX_CS1A_SMC (0 << 1)
65#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
66#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
67#define AT91_MATRIX_CS3A_SMC (0 << 3)
68#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
69#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
70#define AT91_MATRIX_CS4A_SMC (0 << 4)
71#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
72#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
73#define AT91_MATRIX_CS5A_SMC (0 << 5)
74#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
75#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
76#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
77#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
78#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
79
80#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
deleted file mode 100644
index a50cdf8b8ca4..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9261 datasheet revision D.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9261_MATRIX_H
16#define AT91SAM9261_MATRIX_H
17
18#define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */
19#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
20#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
21
22#define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */
23#define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */
24#define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */
25#define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */
26#define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */
27#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
28#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
29#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
30#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
31#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
32#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
33
34#define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */
35#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
36#define AT91_MATRIX_ITCM_0 (0 << 0)
37#define AT91_MATRIX_ITCM_16 (5 << 0)
38#define AT91_MATRIX_ITCM_32 (6 << 0)
39#define AT91_MATRIX_ITCM_64 (7 << 0)
40#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
41#define AT91_MATRIX_DTCM_0 (0 << 4)
42#define AT91_MATRIX_DTCM_16 (5 << 4)
43#define AT91_MATRIX_DTCM_32 (6 << 4)
44#define AT91_MATRIX_DTCM_64 (7 << 4)
45
46#define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */
47#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
48#define AT91_MATRIX_CS1A_SMC (0 << 1)
49#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
50#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
51#define AT91_MATRIX_CS3A_SMC (0 << 3)
52#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
53#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
54#define AT91_MATRIX_CS4A_SMC (0 << 4)
55#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
56#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
57#define AT91_MATRIX_CS5A_SMC (0 << 5)
58#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
59#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
60
61#define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */
62#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
63
64#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
deleted file mode 100644
index ebb5fdb565e0..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
3 *
4 * Copyright (C) 2006 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9263 datasheet revision B (Preliminary).
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9263_MATRIX_H
16#define AT91SAM9263_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
28#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
29#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
30#define AT91_MATRIX_ULBT_FOUR (2 << 0)
31#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
33
34#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
35#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
36#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
37#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
38#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
39#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
40#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
41#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
45#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
46#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
47#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
48#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
51
52#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
53#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
54#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
55#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
56#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
57#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
58#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
59#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
60#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
61#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
62#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
63#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
64#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
65#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
66#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
67#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
71#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
72#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
73#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
74#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
77
78#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
81#define AT91_MATRIX_RCB2 (1 << 2)
82#define AT91_MATRIX_RCB3 (1 << 3)
83#define AT91_MATRIX_RCB4 (1 << 4)
84#define AT91_MATRIX_RCB5 (1 << 5)
85#define AT91_MATRIX_RCB6 (1 << 6)
86#define AT91_MATRIX_RCB7 (1 << 7)
87#define AT91_MATRIX_RCB8 (1 << 8)
88
89#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
91#define AT91_MATRIX_ITCM_0 (0 << 0)
92#define AT91_MATRIX_ITCM_16 (5 << 0)
93#define AT91_MATRIX_ITCM_32 (6 << 0)
94#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
95#define AT91_MATRIX_DTCM_0 (0 << 4)
96#define AT91_MATRIX_DTCM_16 (5 << 4)
97#define AT91_MATRIX_DTCM_32 (6 << 4)
98
99#define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */
100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
103#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
104#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
105#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
106#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
107#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
108#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
109#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
110#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
111#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
112#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
113#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
116
117#define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */
118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
121#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
122#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
123#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
124#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
125#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
126#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
127#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
128
129#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
deleted file mode 100644
index b76e2ed2fbc2..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * Matrix-centric header file for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2008-2009 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9G45 preliminary datasheet.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9G45_MATRIX_H
16#define AT91SAM9G45_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
27#define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */
28#define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */
29#define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */
30#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
31#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
32#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
33#define AT91_MATRIX_ULBT_FOUR (2 << 0)
34#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
35#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
36#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
37#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
38#define AT91_MATRIX_ULBT_128 (7 << 0)
39
40#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
41#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
42#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
43#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
44#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
45#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
46#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
47#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
48#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
49#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
50#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
51#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
52#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
53#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
54
55#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
56#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
57#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
58#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
59#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
60#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
61#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
62#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
63#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
64#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
65#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
66#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
67#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
68#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
69#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
70#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
71#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
72#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
73#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
74#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
75#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
76#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
77#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
78#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
79#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
80#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
81#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
82#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
83
84#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
85#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
86#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
87#define AT91_MATRIX_RCB2 (1 << 2)
88#define AT91_MATRIX_RCB3 (1 << 3)
89#define AT91_MATRIX_RCB4 (1 << 4)
90#define AT91_MATRIX_RCB5 (1 << 5)
91#define AT91_MATRIX_RCB6 (1 << 6)
92#define AT91_MATRIX_RCB7 (1 << 7)
93#define AT91_MATRIX_RCB8 (1 << 8)
94#define AT91_MATRIX_RCB9 (1 << 9)
95#define AT91_MATRIX_RCB10 (1 << 10)
96#define AT91_MATRIX_RCB11 (1 << 11)
97
98#define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */
99#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
100#define AT91_MATRIX_ITCM_0 (0 << 0)
101#define AT91_MATRIX_ITCM_32 (6 << 0)
102#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
103#define AT91_MATRIX_DTCM_0 (0 << 4)
104#define AT91_MATRIX_DTCM_32 (6 << 4)
105#define AT91_MATRIX_DTCM_64 (7 << 4)
106#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
107#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
108#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
109
110#define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */
111#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
112#define AT91C_VDEC_SEL_OFF (0 << 0)
113#define AT91C_VDEC_SEL_ON (1 << 0)
114
115#define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */
116#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
117#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
118#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
119#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
120#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
121#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
122#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
123#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
124#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
125#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
126#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
127#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
128#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
129#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
130#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
131#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
132#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
133#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
134#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
135#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
136#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
137#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
138#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
139#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
140
141#define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */
142#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
143#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
144#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
145#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
146
147#define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */
148#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
149#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
150#define AT91_MATRIX_WPSR_WPV (1 << 0)
151#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
152
153#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
deleted file mode 100644
index 40060cd62fa9..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Matrix-centric header file for the AT91SAM9N12
3 *
4 * Copyright (C) 2012 Atmel Corporation.
5 *
6 * Only EBI related registers.
7 * Write Protect register definitions may be useful.
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#ifndef _AT91SAM9N12_MATRIX_H_
13#define _AT91SAM9N12_MATRIX_H_
14
15#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
16#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
17#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
18#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
19#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
20#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
21#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
22#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
23#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
24#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
25#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
26#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
27#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
28#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
29#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
30#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
31#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
32#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
33#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
34#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
35#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
36#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
37#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
38#define AT91_MATRIX_MP_OFF (0 << 25)
39#define AT91_MATRIX_MP_ON (1 << 25)
40
41#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
42#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
43#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
44#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
45#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
46
47#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
48#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
49#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
50#define AT91_MATRIX_WPSR_WPV (1 << 0)
51#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
52
53#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
deleted file mode 100644
index 6d160adadafc..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9RL datasheet revision A. (Preliminary)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14#ifndef AT91SAM9RL_MATRIX_H
15#define AT91SAM9RL_MATRIX_H
16
17#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
18#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
19#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
20#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
21#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
22#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
23#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
24#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
25#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
26#define AT91_MATRIX_ULBT_FOUR (2 << 0)
27#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
28#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
29
30#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
31#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
32#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
33#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
34#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
35#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
39#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
40#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
41#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
42#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45
46#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
52#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
53#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
54#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
55#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
56#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
57#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
58
59#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
60#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
61#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
62#define AT91_MATRIX_RCB2 (1 << 2)
63#define AT91_MATRIX_RCB3 (1 << 3)
64#define AT91_MATRIX_RCB4 (1 << 4)
65#define AT91_MATRIX_RCB5 (1 << 5)
66
67#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
68#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
69#define AT91_MATRIX_ITCM_0 (0 << 0)
70#define AT91_MATRIX_ITCM_16 (5 << 0)
71#define AT91_MATRIX_ITCM_32 (6 << 0)
72#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
73#define AT91_MATRIX_DTCM_0 (0 << 4)
74#define AT91_MATRIX_DTCM_16 (5 << 4)
75#define AT91_MATRIX_DTCM_32 (6 << 4)
76
77#define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */
78#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
79#define AT91_MATRIX_CS1A_SMC (0 << 1)
80#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
81#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
82#define AT91_MATRIX_CS3A_SMC (0 << 3)
83#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
84#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
85#define AT91_MATRIX_CS4A_SMC (0 << 4)
86#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
87#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
88#define AT91_MATRIX_CS5A_SMC (0 << 5)
89#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
90#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
91#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
92#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
93#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
94
95
96#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
deleted file mode 100644
index a606d3966470..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Matrix-centric header file for the AT91SAM9x5 family
3 *
4 * Copyright (C) 2009-2012 Atmel Corporation.
5 *
6 * Only EBI related registers.
7 * Write Protect register definitions may be useful.
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#ifndef AT91SAM9X5_MATRIX_H
13#define AT91SAM9X5_MATRIX_H
14
15#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
16#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
17#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
18#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
19#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
20#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
21#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
22#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
23#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
24#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
25#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
26#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
27#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
28#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
29#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
30#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
31#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
32#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
33#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
34#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
35#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
36#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
37#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
38#define AT91_MATRIX_MP_OFF (0 << 25)
39#define AT91_MATRIX_MP_ON (1 << 25)
40
41#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
42#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
43#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
44#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
45#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
46
47#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
48#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
49#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
50#define AT91_MATRIX_WPSR_WPV (1 << 0)
51#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
52
53#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-30 22:32:57 -0400