drm/i915: Allow PPGTT enable to fail

I'm really not happy that we have to support this, but this will be the
simplest way to handle cases where PPGTT init can fail, which I promise
will be coming in the future.

v2: Resolve conflicts due to patch series reordering.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

4 files changed, 15 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 70d10de73bbd..bddb9a50ea76 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -927,8 +927,11 @@ int i915_reset(struct drm_device *dev)
                         ring->init(ring);
 
                 i915_gem_context_init(dev);
-                if (dev_priv->mm.aliasing_ppgtt)
-                        dev_priv->mm.aliasing_ppgtt->enable(dev);
+                if (dev_priv->mm.aliasing_ppgtt) {
+                        ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
+                        if (ret)
+                                i915_gem_cleanup_aliasing_ppgtt(dev);
+                }
 
                 /*
                  * It would make sense to re-init all the other hw state, at
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c1213213e495..f59a388a9e8c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -449,7 +449,7 @@ struct i915_hw_ppgtt {
                                struct sg_table *st,
                                unsigned int pg_start,
                                enum i915_cache_level cache_level);
-        void (*enable)(struct drm_device *dev);
+        int (*enable)(struct drm_device *dev);
         void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
 };
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8a73a68a79ff..da6d6de0a8b9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4029,8 +4029,13 @@ i915_gem_init_hw(struct drm_device *dev)
          * contexts before PPGTT.
          */
         i915_gem_context_init(dev);
-        if (dev_priv->mm.aliasing_ppgtt)
-                dev_priv->mm.aliasing_ppgtt->enable(dev);
+        if (dev_priv->mm.aliasing_ppgtt) {
+                ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
+                if (ret) {
+                        i915_gem_cleanup_aliasing_ppgtt(dev);
+                        DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
+                }
+        }
 
         return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d32912e07bad..11143b4982fc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -75,7 +75,7 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
         return pte;
 }
 
-static void gen6_ppgtt_enable(struct drm_device *dev)
+static int gen6_ppgtt_enable(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
         uint32_t pd_offset;
@@ -128,6 +128,7 @@ static void gen6_ppgtt_enable(struct drm_device *dev)
                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
         }
+        return 0;
 }
 
 /* PPGTT support for Sandybdrige/Gen6 and later */