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authorBen Skeggs <bskeggs@redhat.com>2010-10-18 23:05:51 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-12-03 00:10:52 -0500
commitb7bc613a4cc08d867b43189c2af0bb83b1fa1dc6 (patch)
tree9f82aa99db8499a5f0eca1db4ae1b34352e92584
parent106ddad5aa8e8e03503cea05f9a64611f849952f (diff)
drm/nv50: move evo handling to nv50_evo.c
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/Makefile2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_reg.h22
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c238
-rw-r--r--drivers/gpu/drm/nouveau/nv50_evo.c295
-rw-r--r--drivers/gpu/drm/nouveau/nv50_evo.h10
5 files changed, 322 insertions, 245 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index a541f5bff75d..c8c8de0bbc77 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -20,7 +20,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
20 nv40_grctx.o nv50_grctx.o \ 20 nv40_grctx.o nv50_grctx.o \
21 nv84_crypt.o \ 21 nv84_crypt.o \
22 nv04_instmem.o nv50_instmem.o nvc0_instmem.o \ 22 nv04_instmem.o nv50_instmem.o nvc0_instmem.o \
23 nv50_crtc.o nv50_dac.o nv50_sor.o \ 23 nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
24 nv50_cursor.o nv50_display.o nv50_fbcon.o \ 24 nv50_cursor.o nv50_display.o nv50_fbcon.o \
25 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ 25 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \
26 nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ 26 nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index 5e28bc63c41e..d0ce86c24ebf 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -729,17 +729,17 @@
729#define NV50_PDISPLAY_UNK30_CTRL_PENDING 0x80000000 729#define NV50_PDISPLAY_UNK30_CTRL_PENDING 0x80000000
730#define NV50_PDISPLAY_TRAPPED_ADDR 0x00610080 730#define NV50_PDISPLAY_TRAPPED_ADDR 0x00610080
731#define NV50_PDISPLAY_TRAPPED_DATA 0x00610084 731#define NV50_PDISPLAY_TRAPPED_DATA 0x00610084
732#define NV50_PDISPLAY_CHANNEL_STAT(i) ((i) * 0x10 + 0x00610200) 732#define NV50_PDISPLAY_EVO_CTRL(i) ((i) * 0x10 + 0x00610200)
733#define NV50_PDISPLAY_CHANNEL_STAT_DMA 0x00000010 733#define NV50_PDISPLAY_EVO_CTRL_DMA 0x00000010
734#define NV50_PDISPLAY_CHANNEL_STAT_DMA_DISABLED 0x00000000 734#define NV50_PDISPLAY_EVO_CTRL_DMA_DISABLED 0x00000000
735#define NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED 0x00000010 735#define NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED 0x00000010
736#define NV50_PDISPLAY_CHANNEL_DMA_CB(i) ((i) * 0x10 + 0x00610204) 736#define NV50_PDISPLAY_EVO_DMA_CB(i) ((i) * 0x10 + 0x00610204)
737#define NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION 0x00000002 737#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION 0x00000002
738#define NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM 0x00000000 738#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM 0x00000000
739#define NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_SYSTEM 0x00000002 739#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION_SYSTEM 0x00000002
740#define NV50_PDISPLAY_CHANNEL_DMA_CB_VALID 0x00000001 740#define NV50_PDISPLAY_EVO_DMA_CB_VALID 0x00000001
741#define NV50_PDISPLAY_CHANNEL_UNK2(i) ((i) * 0x10 + 0x00610208) 741#define NV50_PDISPLAY_EVO_UNK2(i) ((i) * 0x10 + 0x00610208)
742#define NV50_PDISPLAY_CHANNEL_UNK3(i) ((i) * 0x10 + 0x0061020c) 742#define NV50_PDISPLAY_EVO_HASH_TAG(i) ((i) * 0x10 + 0x0061020c)
743 743
744#define NV50_PDISPLAY_CURSOR 0x00610270 744#define NV50_PDISPLAY_CURSOR 0x00610270
745#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i) ((i) * 0x10 + 0x00610270) 745#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i) ((i) * 0x10 + 0x00610270)
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 7c9c7c5bf22a..db100a8f231e 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -46,159 +46,6 @@ nv50_sor_nr(struct drm_device *dev)
46 return 4; 46 return 4;
47} 47}
48 48
49static void
50nv50_evo_channel_del(struct nouveau_channel **pchan)
51{
52 struct nouveau_channel *chan = *pchan;
53
54 if (!chan)
55 return;
56 *pchan = NULL;
57
58 nouveau_gpuobj_channel_takedown(chan);
59 nouveau_bo_unmap(chan->pushbuf_bo);
60 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
61
62 if (chan->user)
63 iounmap(chan->user);
64
65 kfree(chan);
66}
67
68static int
69nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
70 uint32_t tile_flags, uint32_t magic_flags,
71 uint32_t offset, uint32_t limit)
72{
73 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
74 struct drm_device *dev = evo->dev;
75 struct nouveau_gpuobj *obj = NULL;
76 int ret;
77
78 ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
79 if (ret)
80 return ret;
81 obj->engine = NVOBJ_ENGINE_DISPLAY;
82
83 nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
84 nv_wo32(obj, 4, limit);
85 nv_wo32(obj, 8, offset);
86 nv_wo32(obj, 12, 0x00000000);
87 nv_wo32(obj, 16, 0x00000000);
88 if (dev_priv->card_type < NV_C0)
89 nv_wo32(obj, 20, 0x00010000);
90 else
91 nv_wo32(obj, 20, 0x00020000);
92 dev_priv->engine.instmem.flush(dev);
93
94 ret = nouveau_ramht_insert(evo, name, obj);
95 nouveau_gpuobj_ref(NULL, &obj);
96 if (ret) {
97 return ret;
98 }
99
100 return 0;
101}
102
103static int
104nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
105{
106 struct drm_nouveau_private *dev_priv = dev->dev_private;
107 struct nouveau_gpuobj *ramht = NULL;
108 struct nouveau_channel *chan;
109 int ret;
110
111 chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
112 if (!chan)
113 return -ENOMEM;
114 *pchan = chan;
115
116 chan->id = -1;
117 chan->dev = dev;
118 chan->user_get = 4;
119 chan->user_put = 0;
120
121 ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
122 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
123 if (ret) {
124 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
125 nv50_evo_channel_del(pchan);
126 return ret;
127 }
128
129 ret = drm_mm_init(&chan->ramin_heap, 0, 32768);
130 if (ret) {
131 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
132 nv50_evo_channel_del(pchan);
133 return ret;
134 }
135
136 ret = nouveau_gpuobj_new(dev, chan, 4096, 16, 0, &ramht);
137 if (ret) {
138 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
139 nv50_evo_channel_del(pchan);
140 return ret;
141 }
142
143 ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
144 nouveau_gpuobj_ref(NULL, &ramht);
145 if (ret) {
146 nv50_evo_channel_del(pchan);
147 return ret;
148 }
149
150 if (dev_priv->chipset != 0x50) {
151 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
152 0, 0xffffffff);
153 if (ret) {
154 nv50_evo_channel_del(pchan);
155 return ret;
156 }
157
158
159 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
160 0, 0xffffffff);
161 if (ret) {
162 nv50_evo_channel_del(pchan);
163 return ret;
164 }
165 }
166
167 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
168 0, dev_priv->vram_size);
169 if (ret) {
170 nv50_evo_channel_del(pchan);
171 return ret;
172 }
173
174 ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
175 false, true, &chan->pushbuf_bo);
176 if (ret == 0)
177 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
178 if (ret) {
179 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
180 nv50_evo_channel_del(pchan);
181 return ret;
182 }
183
184 ret = nouveau_bo_map(chan->pushbuf_bo);
185 if (ret) {
186 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
187 nv50_evo_channel_del(pchan);
188 return ret;
189 }
190
191 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
192 NV50_PDISPLAY_USER(0), PAGE_SIZE);
193 if (!chan->user) {
194 NV_ERROR(dev, "Error mapping EVO control regs.\n");
195 nv50_evo_channel_del(pchan);
196 return -ENOMEM;
197 }
198
199 return 0;
200}
201
202int 49int
203nv50_display_early_init(struct drm_device *dev) 50nv50_display_early_init(struct drm_device *dev)
204{ 51{
@@ -214,12 +61,10 @@ int
214nv50_display_init(struct drm_device *dev) 61nv50_display_init(struct drm_device *dev)
215{ 62{
216 struct drm_nouveau_private *dev_priv = dev->dev_private; 63 struct drm_nouveau_private *dev_priv = dev->dev_private;
217 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
218 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; 64 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
219 struct nouveau_channel *evo = dev_priv->evo;
220 struct drm_connector *connector; 65 struct drm_connector *connector;
66 struct nouveau_channel *evo;
221 int ret, i; 67 int ret, i;
222 u64 start;
223 u32 val; 68 u32 val;
224 69
225 NV_DEBUG_KMS(dev, "\n"); 70 NV_DEBUG_KMS(dev, "\n");
@@ -303,7 +148,6 @@ nv50_display_init(struct drm_device *dev)
303 } 148 }
304 } 149 }
305 150
306 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
307 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000); 151 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
308 nv_wr32(dev, 0x610028, 0x00000000); 152 nv_wr32(dev, 0x610028, 0x00000000);
309 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000); 153 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
@@ -323,69 +167,12 @@ nv50_display_init(struct drm_device *dev)
323 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true); 167 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
324 } 168 }
325 169
326 /* taken from nv bug #12637, attempts to un-wedge the hw if it's 170 ret = nv50_evo_init(dev);
327 * stuck in some unspecified state
328 */
329 start = ptimer->read(dev);
330 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
331 while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
332 if ((val & 0x9f0000) == 0x20000)
333 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
334 val | 0x800000);
335
336 if ((val & 0x3f0000) == 0x30000)
337 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
338 val | 0x200000);
339
340 if (ptimer->read(dev) - start > 1000000000ULL) {
341 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
342 NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
343 return -EBUSY;
344 }
345 }
346
347 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
348 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
349 0x40000000, 0x40000000)) {
350 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
351 NV_ERROR(dev, "0x610200 = 0x%08x\n",
352 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
353 return -EBUSY;
354 }
355
356 /* initialise fifo */
357 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
358 ((evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT) >> 8) |
359 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
360 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
361 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
362 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
363 if (!nv_wait(dev, 0x610200, 0x80000000, 0x00000000)) {
364 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
365 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
366 return -EBUSY;
367 }
368 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
369 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
370 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
371 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
372 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
373 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
374
375 /* enable error reporting on the channel */
376 nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << 0);
377
378 evo->dma.max = (4096/4) - 2;
379 evo->dma.put = 0;
380 evo->dma.cur = evo->dma.put;
381 evo->dma.free = evo->dma.max - evo->dma.cur;
382
383 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
384 if (ret) 171 if (ret)
385 return ret; 172 return ret;
173 evo = dev_priv->evo;
386 174
387 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 175 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
388 OUT_RING(evo, 0);
389 176
390 ret = RING_SPACE(evo, 11); 177 ret = RING_SPACE(evo, 11);
391 if (ret) 178 if (ret)
@@ -449,12 +236,7 @@ static int nv50_display_disable(struct drm_device *dev)
449 } 236 }
450 } 237 }
451 238
452 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0); 239 nv50_evo_fini(dev);
453 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
454 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
455 NV_ERROR(dev, "0x610200 = 0x%08x\n",
456 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
457 }
458 240
459 for (i = 0; i < 3; i++) { 241 for (i = 0; i < 3; i++) {
460 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i), 242 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
@@ -504,13 +286,6 @@ int nv50_display_create(struct drm_device *dev)
504 286
505 dev->mode_config.fb_base = dev_priv->fb_phys; 287 dev->mode_config.fb_base = dev_priv->fb_phys;
506 288
507 /* Create EVO channel */
508 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
509 if (ret) {
510 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
511 return ret;
512 }
513
514 /* Create CRTC objects */ 289 /* Create CRTC objects */
515 for (i = 0; i < 2; i++) 290 for (i = 0; i < 2; i++)
516 nv50_crtc_create(dev, i); 291 nv50_crtc_create(dev, i);
@@ -565,14 +340,11 @@ int nv50_display_create(struct drm_device *dev)
565void 340void
566nv50_display_destroy(struct drm_device *dev) 341nv50_display_destroy(struct drm_device *dev)
567{ 342{
568 struct drm_nouveau_private *dev_priv = dev->dev_private;
569
570 NV_DEBUG_KMS(dev, "\n"); 343 NV_DEBUG_KMS(dev, "\n");
571 344
572 drm_mode_config_cleanup(dev); 345 drm_mode_config_cleanup(dev);
573 346
574 nv50_display_disable(dev); 347 nv50_display_disable(dev);
575 nv50_evo_channel_del(&dev_priv->evo);
576} 348}
577 349
578static u16 350static u16
diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c
new file mode 100644
index 000000000000..211f5fb1dc73
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_evo.c
@@ -0,0 +1,295 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28#include "nouveau_dma.h"
29#include "nouveau_ramht.h"
30
31static void
32nv50_evo_channel_del(struct nouveau_channel **pchan)
33{
34 struct nouveau_channel *chan = *pchan;
35
36 if (!chan)
37 return;
38 *pchan = NULL;
39
40 nouveau_gpuobj_channel_takedown(chan);
41 nouveau_bo_unmap(chan->pushbuf_bo);
42 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
43
44 if (chan->user)
45 iounmap(chan->user);
46
47 kfree(chan);
48}
49
50int
51nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
52 u32 tile_flags, u32 magic_flags, u32 offset, u32 limit)
53{
54 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
55 struct drm_device *dev = evo->dev;
56 struct nouveau_gpuobj *obj = NULL;
57 int ret;
58
59 ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
60 if (ret)
61 return ret;
62 obj->engine = NVOBJ_ENGINE_DISPLAY;
63
64 nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
65 nv_wo32(obj, 4, limit);
66 nv_wo32(obj, 8, offset);
67 nv_wo32(obj, 12, 0x00000000);
68 nv_wo32(obj, 16, 0x00000000);
69 if (dev_priv->card_type < NV_C0)
70 nv_wo32(obj, 20, 0x00010000);
71 else
72 nv_wo32(obj, 20, 0x00020000);
73 dev_priv->engine.instmem.flush(dev);
74
75 ret = nouveau_ramht_insert(evo, name, obj);
76 nouveau_gpuobj_ref(NULL, &obj);
77 if (ret) {
78 return ret;
79 }
80
81 return 0;
82}
83
84static int
85nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
86{
87 struct drm_nouveau_private *dev_priv = dev->dev_private;
88 struct nouveau_gpuobj *ramht = NULL;
89 struct nouveau_channel *chan;
90 int ret;
91
92 chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
93 if (!chan)
94 return -ENOMEM;
95 *pchan = chan;
96
97 chan->id = -1;
98 chan->dev = dev;
99 chan->user_get = 4;
100 chan->user_put = 0;
101
102 ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
103 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
104 if (ret) {
105 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
106 nv50_evo_channel_del(pchan);
107 return ret;
108 }
109
110 ret = drm_mm_init(&chan->ramin_heap, 0, 32768);
111 if (ret) {
112 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
113 nv50_evo_channel_del(pchan);
114 return ret;
115 }
116
117 ret = nouveau_gpuobj_new(dev, chan, 4096, 16, 0, &ramht);
118 if (ret) {
119 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
120 nv50_evo_channel_del(pchan);
121 return ret;
122 }
123
124 ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
125 nouveau_gpuobj_ref(NULL, &ramht);
126 if (ret) {
127 nv50_evo_channel_del(pchan);
128 return ret;
129 }
130
131 if (dev_priv->chipset != 0x50) {
132 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
133 0, 0xffffffff);
134 if (ret) {
135 nv50_evo_channel_del(pchan);
136 return ret;
137 }
138
139
140 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
141 0, 0xffffffff);
142 if (ret) {
143 nv50_evo_channel_del(pchan);
144 return ret;
145 }
146 }
147
148 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
149 0, dev_priv->vram_size);
150 if (ret) {
151 nv50_evo_channel_del(pchan);
152 return ret;
153 }
154
155 ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
156 false, true, &chan->pushbuf_bo);
157 if (ret == 0)
158 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
159 if (ret) {
160 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
161 nv50_evo_channel_del(pchan);
162 return ret;
163 }
164
165 ret = nouveau_bo_map(chan->pushbuf_bo);
166 if (ret) {
167 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
168 nv50_evo_channel_del(pchan);
169 return ret;
170 }
171
172 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
173 NV50_PDISPLAY_USER(0), PAGE_SIZE);
174 if (!chan->user) {
175 NV_ERROR(dev, "Error mapping EVO control regs.\n");
176 nv50_evo_channel_del(pchan);
177 return -ENOMEM;
178 }
179
180 return 0;
181}
182
183static int
184nv50_evo_channel_init(struct nouveau_channel *evo)
185{
186 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
187 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
188 struct drm_device *dev = evo->dev;
189 int ret, i;
190 u64 start;
191 u32 tmp;
192
193 /* taken from nv bug #12637, attempts to un-wedge the hw if it's
194 * stuck in some unspecified state
195 */
196 start = ptimer->read(dev);
197 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), 0x2b00);
198 while ((tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(0))) & 0x1e0000) {
199 if ((tmp & 0x9f0000) == 0x20000)
200 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), tmp | 0x800000);
201
202 if ((tmp & 0x3f0000) == 0x30000)
203 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), tmp | 0x200000);
204
205 if (ptimer->read(dev) - start > 1000000000ULL) {
206 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
207 NV_ERROR(dev, "0x610200 = 0x%08x\n", tmp);
208 return -EBUSY;
209 }
210 }
211
212 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), 0x1000b03);
213 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(0),
214 0x40000000, 0x40000000)) {
215 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
216 NV_ERROR(dev, "0x610200 = 0x%08x\n",
217 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(0)));
218 return -EBUSY;
219 }
220
221 /* initialise fifo */
222 nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(0),
223 ((evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT) >> 8) |
224 NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
225 NV50_PDISPLAY_EVO_DMA_CB_VALID);
226 nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(0), 0x00010000);
227 nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(0), 0x00000002);
228 if (!nv_wait(dev, 0x610200, 0x80000000, 0x00000000)) {
229 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
230 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
231 return -EBUSY;
232 }
233 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0),
234 (nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(0)) & ~0x00000003) |
235 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
236 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
237 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), 0x01000003 |
238 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
239
240 /* enable error reporting on the channel */
241 nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << 0);
242
243 evo->dma.max = (4096/4) - 2;
244 evo->dma.put = 0;
245 evo->dma.cur = evo->dma.put;
246 evo->dma.free = evo->dma.max - evo->dma.cur;
247
248 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
249 if (ret)
250 return ret;
251
252 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
253 OUT_RING(evo, 0);
254
255 return 0;
256}
257
258static void
259nv50_evo_channel_fini(struct nouveau_channel *evo)
260{
261 struct drm_device *dev = evo->dev;
262
263 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(0), 0);
264 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(0), 0x1e0000, 0)) {
265 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
266 NV_ERROR(dev, "0x610200 = 0x%08x\n",
267 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(0)));
268 }
269}
270
271int
272nv50_evo_init(struct drm_device *dev)
273{
274 struct drm_nouveau_private *dev_priv = dev->dev_private;
275 int ret;
276
277 if (!dev_priv->evo) {
278 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
279 if (ret)
280 return ret;
281 }
282
283 return nv50_evo_channel_init(dev_priv->evo);
284}
285
286void
287nv50_evo_fini(struct drm_device *dev)
288{
289 struct drm_nouveau_private *dev_priv = dev->dev_private;
290
291 if (dev_priv->evo) {
292 nv50_evo_channel_fini(dev_priv->evo);
293 nv50_evo_channel_del(&dev_priv->evo);
294 }
295}
diff --git a/drivers/gpu/drm/nouveau/nv50_evo.h b/drivers/gpu/drm/nouveau/nv50_evo.h
index aae13343bcec..aa4f0d3cea8e 100644
--- a/drivers/gpu/drm/nouveau/nv50_evo.h
+++ b/drivers/gpu/drm/nouveau/nv50_evo.h
@@ -24,6 +24,15 @@
24 * 24 *
25 */ 25 */
26 26
27#ifndef __NV50_EVO_H__
28#define __NV50_EVO_H__
29
30int nv50_evo_init(struct drm_device *dev);
31void nv50_evo_fini(struct drm_device *dev);
32int nv50_evo_dmaobj_new(struct nouveau_channel *, u32 class, u32 name,
33 u32 tile_flags, u32 magic_flags,
34 u32 offset, u32 limit);
35
27#define NV50_EVO_UPDATE 0x00000080 36#define NV50_EVO_UPDATE 0x00000080
28#define NV50_EVO_UNK84 0x00000084 37#define NV50_EVO_UNK84 0x00000084
29#define NV50_EVO_UNK84_NOTIFY 0x40000000 38#define NV50_EVO_UNK84_NOTIFY 0x40000000
@@ -111,3 +120,4 @@
111#define NV50_EVO_CRTC_SCALE_RES1 0x000008d8 120#define NV50_EVO_CRTC_SCALE_RES1 0x000008d8
112#define NV50_EVO_CRTC_SCALE_RES2 0x000008dc 121#define NV50_EVO_CRTC_SCALE_RES2 0x000008dc
113 122
123#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 14:16:40 -0400