diff options
author | Kishon Vijay Abraham I <kishon@ti.com> | 2014-07-14 06:42:19 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2014-07-15 03:16:11 -0400 |
commit | b700f42c863e17569ca4d864e369210d9ff00b8a (patch) | |
tree | 3ecca0c327e72a75d8bfbc26000acdf6f17dafa0 | |
parent | ba5137b27281f9016a5b2f6177f02595252305bd (diff) |
ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
There are two instances of PCIe PHY in DRA7xx. So renamed
optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to
optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk
respectively. This is needed for adding the clocks for second PCIe PHY
instance.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r-- | arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3ff6d7c3857c..fe5db55aeede 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi | |||
@@ -1165,7 +1165,7 @@ | |||
1165 | reg = <0x021c>, <0x0220>; | 1165 | reg = <0x021c>, <0x0220>; |
1166 | }; | 1166 | }; |
1167 | 1167 | ||
1168 | optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { | 1168 | optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 { |
1169 | compatible = "ti,gate-clock"; | 1169 | compatible = "ti,gate-clock"; |
1170 | clocks = <&sys_32k_ck>; | 1170 | clocks = <&sys_32k_ck>; |
1171 | #clock-cells = <0>; | 1171 | #clock-cells = <0>; |
@@ -1183,7 +1183,7 @@ | |||
1183 | ti,max-div = <2>; | 1183 | ti,max-div = <2>; |
1184 | }; | 1184 | }; |
1185 | 1185 | ||
1186 | optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { | 1186 | optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 { |
1187 | compatible = "ti,gate-clock"; | 1187 | compatible = "ti,gate-clock"; |
1188 | clocks = <&apll_pcie_ck>; | 1188 | clocks = <&apll_pcie_ck>; |
1189 | #clock-cells = <0>; | 1189 | #clock-cells = <0>; |
@@ -1191,7 +1191,7 @@ | |||
1191 | ti,bit-shift = <9>; | 1191 | ti,bit-shift = <9>; |
1192 | }; | 1192 | }; |
1193 | 1193 | ||
1194 | optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { | 1194 | optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { |
1195 | compatible = "ti,gate-clock"; | 1195 | compatible = "ti,gate-clock"; |
1196 | clocks = <&optfclk_pciephy_div>; | 1196 | clocks = <&optfclk_pciephy_div>; |
1197 | #clock-cells = <0>; | 1197 | #clock-cells = <0>; |