diff options
author | Huacai Chen <chenhc@lemote.com> | 2014-02-07 09:31:33 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-14 12:49:23 -0400 |
commit | b616365e6dafb5d7c1cf2a8b6e8cb376a3f4a387 (patch) | |
tree | 04e7d002f0b59362ac488e3c04c982d0cc5f5bce | |
parent | f5868f05dc976ecd849d2a8115fab80301c127cd (diff) |
MIPS: FPU: Fix conflict of register usage
In _restore_fp_context/_restore_fp_context32, t0 is used for both
CP0_Status and CP1_FCSR. This is a mistake and cause FP exeception on
boot, so fix it.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Tested-by: Andreas Barth <aba@ayous.org>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6507/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/kernel/r4k_fpu.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index 841ffc234464..73b0ddf910d4 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S | |||
@@ -146,7 +146,7 @@ LEAF(_save_fp_context32) | |||
146 | * - cp1 status/control register | 146 | * - cp1 status/control register |
147 | */ | 147 | */ |
148 | LEAF(_restore_fp_context) | 148 | LEAF(_restore_fp_context) |
149 | EX lw t0, SC_FPC_CSR(a0) | 149 | EX lw t1, SC_FPC_CSR(a0) |
150 | 150 | ||
151 | #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) | 151 | #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) |
152 | .set push | 152 | .set push |
@@ -191,7 +191,7 @@ LEAF(_restore_fp_context) | |||
191 | EX ldc1 $f26, SC_FPREGS+208(a0) | 191 | EX ldc1 $f26, SC_FPREGS+208(a0) |
192 | EX ldc1 $f28, SC_FPREGS+224(a0) | 192 | EX ldc1 $f28, SC_FPREGS+224(a0) |
193 | EX ldc1 $f30, SC_FPREGS+240(a0) | 193 | EX ldc1 $f30, SC_FPREGS+240(a0) |
194 | ctc1 t0, fcr31 | 194 | ctc1 t1, fcr31 |
195 | jr ra | 195 | jr ra |
196 | li v0, 0 # success | 196 | li v0, 0 # success |
197 | END(_restore_fp_context) | 197 | END(_restore_fp_context) |
@@ -199,7 +199,7 @@ LEAF(_restore_fp_context) | |||
199 | #ifdef CONFIG_MIPS32_COMPAT | 199 | #ifdef CONFIG_MIPS32_COMPAT |
200 | LEAF(_restore_fp_context32) | 200 | LEAF(_restore_fp_context32) |
201 | /* Restore an o32 sigcontext. */ | 201 | /* Restore an o32 sigcontext. */ |
202 | EX lw t0, SC32_FPC_CSR(a0) | 202 | EX lw t1, SC32_FPC_CSR(a0) |
203 | 203 | ||
204 | mfc0 t0, CP0_STATUS | 204 | mfc0 t0, CP0_STATUS |
205 | sll t0, t0, 5 | 205 | sll t0, t0, 5 |
@@ -239,7 +239,7 @@ LEAF(_restore_fp_context32) | |||
239 | EX ldc1 $f26, SC32_FPREGS+208(a0) | 239 | EX ldc1 $f26, SC32_FPREGS+208(a0) |
240 | EX ldc1 $f28, SC32_FPREGS+224(a0) | 240 | EX ldc1 $f28, SC32_FPREGS+224(a0) |
241 | EX ldc1 $f30, SC32_FPREGS+240(a0) | 241 | EX ldc1 $f30, SC32_FPREGS+240(a0) |
242 | ctc1 t0, fcr31 | 242 | ctc1 t1, fcr31 |
243 | jr ra | 243 | jr ra |
244 | li v0, 0 # success | 244 | li v0, 0 # success |
245 | END(_restore_fp_context32) | 245 | END(_restore_fp_context32) |