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authorTim Harvey <tharvey@gateworks.com>2014-09-09 02:07:30 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-09-15 22:27:20 -0400
commitb5f37b76053afe8863ce9a753903932eb542eca9 (patch)
tree1bbc5345afd12d6e3771312c7b826f10e8ffeb2e
parent73e005c111bc3f77ca3793d465539a11e7604c71 (diff)
ARM: dts: imx: ventana: cleanup pinctrl groups
Follow the conventions for pinctrl: - grouping pinctrl in logical alphabatized groups - remove any pinctrl not being used by a driver or needed by user - move iomuxc to bottom of file for readability Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/imx6q-gw5400-a.dts157
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw51xx.dtsi123
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi210
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi224
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw54xx.dtsi225
5 files changed, 491 insertions, 448 deletions
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index eb28f631279e..822ffb231c57 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -38,6 +38,8 @@
38 38
39 leds { 39 leds {
40 compatible = "gpio-leds"; 40 compatible = "gpio-leds";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_gpio_leds>;
41 43
42 led0: user1 { 44 led0: user1 {
43 label = "user1"; 45 label = "user1";
@@ -65,6 +67,8 @@
65 67
66 pps { 68 pps {
67 compatible = "pps-gpio"; 69 compatible = "pps-gpio";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_gpio_leds>;
68 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 72 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
69 status = "okay"; 73 status = "okay";
70 }; 74 };
@@ -337,27 +341,64 @@
337 }; 341 };
338}; 342};
339 343
340&iomuxc { 344&ldb {
345 status = "okay";
346};
347
348&pcie {
349 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
350 status = "okay";
351
352 eth1: sky2@8 { /* MAC/PHY on bus 8 */
353 compatible = "marvell,sky2";
354 };
355};
356
357&ssi1 {
358 status = "okay";
359};
360
361&uart1 {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_uart1>;
364 status = "okay";
365};
366
367&uart2 {
341 pinctrl-names = "default"; 368 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_hog>; 369 pinctrl-0 = <&pinctrl_uart2>;
370 status = "okay";
371};
343 372
373&uart5 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_uart5>;
376 status = "okay";
377};
378
379&usbotg {
380 vbus-supply = <&reg_usb_otg_vbus>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_usbotg>;
383 disable-over-current;
384 status = "okay";
385};
386
387&usbh1 {
388 vbus-supply = <&reg_usb_h1_vbus>;
389 status = "okay";
390};
391
392&usdhc3 {
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_usdhc3>;
395 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
396 vmmc-supply = <&reg_3p3v>;
397 status = "okay";
398};
399
400&iomuxc {
344 imx6q-gw5400-a { 401 imx6q-gw5400-a {
345 pinctrl_hog: hoggrp {
346 fsl,pins = <
347 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */
348 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0001b0b0 /* SPINOR_CS0# */
349 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */
350 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */
351 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
352 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0001b0b0 /* GPS_PPS */
353 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */
354 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */
355 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0001b0b0 /* user2 led */
356 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */
357 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x4001b0b0 /* USBHUB_RST# */
358 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x4001b0b0 /* MIPI_DIO */
359 >;
360 };
361 402
362 pinctrl_audmux: audmuxgrp { 403 pinctrl_audmux: audmuxgrp {
363 fsl,pins = < 404 fsl,pins = <
@@ -365,6 +406,7 @@
365 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 406 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
366 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 407 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
367 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 408 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
409 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
368 >; 410 >;
369 }; 411 };
370 412
@@ -373,6 +415,7 @@
373 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 415 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
374 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 416 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
375 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 417 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
418 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */
376 >; 419 >;
377 }; 420 };
378 421
@@ -397,6 +440,14 @@
397 >; 440 >;
398 }; 441 };
399 442
443 pinctrl_gpio_leds: gpioledsgrp {
444 fsl,pins = <
445 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */
446 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */
447 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */
448 >;
449 };
450
400 pinctrl_i2c1: i2c1grp { 451 pinctrl_i2c1: i2c1grp {
401 fsl,pins = < 452 fsl,pins = <
402 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 453 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
@@ -418,6 +469,19 @@
418 >; 469 >;
419 }; 470 };
420 471
472 pinctrl_pcie: pciegrp {
473 fsl,pins = <
474 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
475 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
476 >;
477 };
478
479 pinctrl_pps: ppsgrp {
480 fsl,pins = <
481 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */
482 >;
483 };
484
421 pinctrl_uart1: uart1grp { 485 pinctrl_uart1: uart1grp {
422 fsl,pins = < 486 fsl,pins = <
423 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 487 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@@ -442,6 +506,7 @@
442 pinctrl_usbotg: usbotggrp { 506 pinctrl_usbotg: usbotggrp {
443 fsl,pins = < 507 fsl,pins = <
444 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 508 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
509 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
445 >; 510 >;
446 }; 511 };
447 512
@@ -457,59 +522,3 @@
457 }; 522 };
458 }; 523 };
459}; 524};
460
461&ldb {
462 status = "okay";
463};
464
465&pcie {
466 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
467 status = "okay";
468
469 eth1: sky2@8 { /* MAC/PHY on bus 8 */
470 compatible = "marvell,sky2";
471 };
472};
473
474&ssi1 {
475 status = "okay";
476};
477
478&uart1 {
479 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_uart1>;
481 status = "okay";
482};
483
484&uart2 {
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_uart2>;
487 status = "okay";
488};
489
490&uart5 {
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_uart5>;
493 status = "okay";
494};
495
496&usbotg {
497 vbus-supply = <&reg_usb_otg_vbus>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&pinctrl_usbotg>;
500 disable-over-current;
501 status = "okay";
502};
503
504&usbh1 {
505 vbus-supply = <&reg_usb_h1_vbus>;
506 status = "okay";
507};
508
509&usdhc3 {
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_usdhc3>;
512 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
513 vmmc-supply = <&reg_3p3v>;
514 status = "okay";
515};
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 2853a1046f8d..f2867c4b34a8 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -27,6 +27,8 @@
27 27
28 leds { 28 leds {
29 compatible = "gpio-leds"; 29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_gpio_leds>;
30 32
31 led0: user1 { 33 led0: user1 {
32 label = "user1"; 34 label = "user1";
@@ -48,6 +50,8 @@
48 50
49 pps { 51 pps {
50 compatible = "pps-gpio"; 52 compatible = "pps-gpio";
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_pps>;
51 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 55 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
52 status = "okay"; 56 status = "okay";
53 }; 57 };
@@ -163,24 +167,51 @@
163 status = "okay"; 167 status = "okay";
164}; 168};
165 169
166&iomuxc { 170&pcie {
167 pinctrl-names = "default"; 171 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_hog>; 172 pinctrl-0 = <&pinctrl_pcie>;
173 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
174 status = "okay";
175};
169 176
170 imx6qdl-gw51xx { 177&uart1 {
171 pinctrl_hog: hoggrp { 178 pinctrl-names = "default";
172 fsl,pins = < 179 pinctrl-0 = <&pinctrl_uart1>;
173 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* MEZZ_DIO0 */ 180 status = "okay";
174 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* MEZZ_DIO1 */ 181};
175 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ 182
176 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ 183&uart2 {
177 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b0b0 /* PHY Reset */ 184 pinctrl-names = "default";
178 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0001b0b0 /* PCIE_RST# */ 185 pinctrl-0 = <&pinctrl_uart2>;
179 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ 186 status = "okay";
180 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ 187};
181 >; 188
182 }; 189&uart3 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_uart3>;
192 status = "okay";
193};
183 194
195&uart5 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_uart5>;
198 status = "okay";
199};
200
201&usbotg {
202 vbus-supply = <&reg_usb_otg_vbus>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_usbotg>;
205 disable-over-current;
206 status = "okay";
207};
208
209&usbh1 {
210 status = "okay";
211};
212
213&iomuxc {
214 imx6qdl-gw51xx {
184 pinctrl_enet: enetgrp { 215 pinctrl_enet: enetgrp {
185 fsl,pins = < 216 fsl,pins = <
186 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 217 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
@@ -199,6 +230,14 @@
199 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 230 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
200 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 231 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
201 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 232 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
233 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
234 >;
235 };
236
237 pinctrl_gpio_leds: gpioledsgrp {
238 fsl,pins = <
239 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
240 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
202 >; 241 >;
203 }; 242 };
204 243
@@ -244,6 +283,18 @@
244 >; 283 >;
245 }; 284 };
246 285
286 pinctrl_pcie: pciegrp {
287 fsl,pins = <
288 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
289 >;
290 };
291
292 pinctrl_pps: ppsgrp {
293 fsl,pins = <
294 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
295 >;
296 };
297
247 pinctrl_uart1: uart1grp { 298 pinctrl_uart1: uart1grp {
248 fsl,pins = < 299 fsl,pins = <
249 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 300 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@@ -275,48 +326,8 @@
275 pinctrl_usbotg: usbotggrp { 326 pinctrl_usbotg: usbotggrp {
276 fsl,pins = < 327 fsl,pins = <
277 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 328 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
329 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
278 >; 330 >;
279 }; 331 };
280 }; 332 };
281}; 333};
282
283&pcie {
284 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
285 status = "okay";
286};
287
288&uart1 {
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_uart1>;
291 status = "okay";
292};
293
294&uart2 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_uart2>;
297 status = "okay";
298};
299
300&uart3 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_uart3>;
303 status = "okay";
304};
305
306&uart5 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart5>;
309 status = "okay";
310};
311
312&usbotg {
313 vbus-supply = <&reg_usb_otg_vbus>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usbotg>;
316 disable-over-current;
317 status = "okay";
318};
319
320&usbh1 {
321 status = "okay";
322};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 26b13958f663..6d137b47068a 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -36,6 +36,8 @@
36 36
37 leds { 37 leds {
38 compatible = "gpio-leds"; 38 compatible = "gpio-leds";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpio_leds>;
39 41
40 led0: user1 { 42 led0: user1 {
41 label = "user1"; 43 label = "user1";
@@ -63,6 +65,8 @@
63 65
64 pps { 66 pps {
65 compatible = "pps-gpio"; 67 compatible = "pps-gpio";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pps>;
66 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 70 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
67 status = "okay"; 71 status = "okay";
68 }; 72 };
@@ -233,39 +237,96 @@
233 }; 237 };
234}; 238};
235 239
236&iomuxc { 240&ldb {
237 pinctrl-names = "default"; 241 status = "okay";
238 pinctrl-0 = <&pinctrl_hog>;
239 242
240 imx6qdl-gw52xx { 243 lvds-channel@0 {
241 pinctrl_hog: hoggrp { 244 fsl,data-mapping = "spwg";
242 fsl,pins = < 245 fsl,data-width = <18>;
243 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* MEZZ_DIO0 */ 246 status = "okay";
244 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* MEZZ_DIO1 */ 247
245 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ 248 display-timings {
246 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 /* VIDDEC_PDN# */ 249 native-mode = <&timing0>;
247 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b0b0 /* PHY Reset */ 250 timing0: hsd100pxn1 {
248 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE_RST# */ 251 clock-frequency = <65000000>;
249 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x4001b0b0 /* GPS_PWDN */ 252 hactive = <1024>;
250 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ 253 vactive = <768>;
251 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ 254 hback-porch = <220>;
252 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* USB_SEL_PCI */ 255 hfront-porch = <40>;
253 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ 256 vback-porch = <21>;
254 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ 257 vfront-porch = <7>;
255 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ 258 hsync-len = <60>;
256 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ 259 vsync-len = <10>;
257 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x0001b0b0 /* LVDS_TCH# */ 260 };
258 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x0001b0b0 /* SD3_CD# */
259 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 /* UART2_EN# */
260 >;
261 }; 261 };
262 };
263};
264
265&pcie {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_pcie>;
268 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
269 status = "okay";
270};
271
272&pwm4 {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_pwm4>;
275 status = "okay";
276};
277
278&ssi1 {
279 fsl,mode = "i2s-slave";
280 status = "okay";
281};
282
283&uart1 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_uart1>;
286 status = "okay";
287};
288
289&uart2 {
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_uart2>;
292 status = "okay";
293};
262 294
295&uart5 {
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_uart5>;
298 status = "okay";
299};
300
301&usbotg {
302 vbus-supply = <&reg_usb_otg_vbus>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_usbotg>;
305 disable-over-current;
306 status = "okay";
307};
308
309&usbh1 {
310 status = "okay";
311};
312
313&usdhc3 {
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usdhc3>;
316 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
317 vmmc-supply = <&reg_3p3v>;
318 status = "okay";
319};
320
321&iomuxc {
322 imx6qdl-gw52xx {
263 pinctrl_audmux: audmuxgrp { 323 pinctrl_audmux: audmuxgrp {
264 fsl,pins = < 324 fsl,pins = <
265 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 325 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
266 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 326 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
267 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 327 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
268 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 328 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
329 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
269 >; 330 >;
270 }; 331 };
271 332
@@ -287,6 +348,15 @@
287 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 348 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
288 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 349 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
289 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 350 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
351 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
352 >;
353 };
354
355 pinctrl_gpio_leds: gpioledsgrp {
356 fsl,pins = <
357 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
358 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
359 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
290 >; 360 >;
291 }; 361 };
292 362
@@ -332,6 +402,18 @@
332 >; 402 >;
333 }; 403 };
334 404
405 pinctrl_pcie: pciegrp {
406 fsl,pins = <
407 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
408 >;
409 };
410
411 pinctrl_pps: ppsgrp {
412 fsl,pins = <
413 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
414 >;
415 };
416
335 pinctrl_pwm4: pwm4grp { 417 pinctrl_pwm4: pwm4grp {
336 fsl,pins = < 418 fsl,pins = <
337 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 419 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
@@ -362,6 +444,7 @@
362 pinctrl_usbotg: usbotggrp { 444 pinctrl_usbotg: usbotggrp {
363 fsl,pins = < 445 fsl,pins = <
364 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 446 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
447 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
365 >; 448 >;
366 }; 449 };
367 450
@@ -373,85 +456,8 @@
373 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 456 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
374 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 457 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
375 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 458 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
459 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
376 >; 460 >;
377 }; 461 };
378 }; 462 };
379}; 463};
380
381&ldb {
382 status = "okay";
383
384 lvds-channel@0 {
385 fsl,data-mapping = "spwg";
386 fsl,data-width = <18>;
387 status = "okay";
388
389 display-timings {
390 native-mode = <&timing0>;
391 timing0: hsd100pxn1 {
392 clock-frequency = <65000000>;
393 hactive = <1024>;
394 vactive = <768>;
395 hback-porch = <220>;
396 hfront-porch = <40>;
397 vback-porch = <21>;
398 vfront-porch = <7>;
399 hsync-len = <60>;
400 vsync-len = <10>;
401 };
402 };
403 };
404};
405
406&pcie {
407 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
408 status = "okay";
409};
410
411&pwm4 {
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_pwm4>;
414 status = "okay";
415};
416
417&ssi1 {
418 status = "okay";
419};
420
421&uart1 {
422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_uart1>;
424 status = "okay";
425};
426
427&uart2 {
428 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_uart2>;
430 status = "okay";
431};
432
433&uart5 {
434 pinctrl-names = "default";
435 pinctrl-0 = <&pinctrl_uart5>;
436 status = "okay";
437};
438
439&usbotg {
440 vbus-supply = <&reg_usb_otg_vbus>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pinctrl_usbotg>;
443 disable-over-current;
444 status = "okay";
445};
446
447&usbh1 {
448 status = "okay";
449};
450
451&usdhc3 {
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_usdhc3>;
454 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
455 vmmc-supply = <&reg_3p3v>;
456 status = "okay";
457};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index e6e298bb7576..cade1bdc97e9 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -37,6 +37,8 @@
37 37
38 leds { 38 leds {
39 compatible = "gpio-leds"; 39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_gpio_leds>;
40 42
41 led0: user1 { 43 led0: user1 {
42 label = "user1"; 44 label = "user1";
@@ -64,6 +66,8 @@
64 66
65 pps { 67 pps {
66 compatible = "pps-gpio"; 68 compatible = "pps-gpio";
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_pps>;
67 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 71 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
68 status = "okay"; 72 status = "okay";
69 }; 73 };
@@ -240,41 +244,101 @@
240 }; 244 };
241}; 245};
242 246
243&iomuxc { 247&ldb {
244 pinctrl-names = "default"; 248 status = "okay";
245 pinctrl-0 = <&pinctrl_hog>;
246 249
247 imx6qdl-gw53xx { 250 lvds-channel@1 {
248 pinctrl_hog: hoggrp { 251 fsl,data-mapping = "spwg";
249 fsl,pins = < 252 fsl,data-width = <18>;
250 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* PCIE6EXP_DIO0 */ 253 status = "okay";
251 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* PCIE6EXP_DIO1 */ 254
252 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ 255 display-timings {
253 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x4001b0b0 /* GPS_SHDN */ 256 native-mode = <&timing0>;
254 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ 257 timing0: hsd100pxn1 {
255 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ 258 clock-frequency = <65000000>;
256 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ 259 hactive = <1024>;
257 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ 260 vactive = <768>;
258 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 261 hback-porch = <220>;
259 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 262 hfront-porch = <40>;
260 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* HUB_RST# */ 263 vback-porch = <21>;
261 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIE_WDIS# */ 264 vfront-porch = <7>;
262 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0001b0b0 /* ACCEL_IRQ# */ 265 hsync-len = <60>;
263 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ 266 vsync-len = <10>;
264 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0001b0b0 /* USBOTG_OC# */ 267 };
265 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */
266 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */
267 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x0001b0b0 /* TOUCH_IRQ# */
268 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x0001b0b0 /* SD3_DET# */
269 >;
270 }; 268 };
269 };
270};
271
272&pcie {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_pcie>;
275 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
276 status = "okay";
277
278 eth1: sky2@8 { /* MAC/PHY on bus 8 */
279 compatible = "marvell,sky2";
280 };
281};
282
283&pwm4 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_pwm4>;
286 status = "okay";
287};
288
289&ssi1 {
290 fsl,mode = "i2s-slave";
291 status = "okay";
292};
271 293
294&uart1 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_uart1>;
297 status = "okay";
298};
299
300&uart2 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_uart2>;
303 status = "okay";
304};
305
306&uart5 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart5>;
309 status = "okay";
310};
311
312&usbotg {
313 vbus-supply = <&reg_usb_otg_vbus>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usbotg>;
316 disable-over-current;
317 status = "okay";
318};
319
320&usbh1 {
321 vbus-supply = <&reg_usb_h1_vbus>;
322 status = "okay";
323};
324
325&usdhc3 {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_usdhc3>;
328 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
329 vmmc-supply = <&reg_3p3v>;
330 status = "okay";
331};
332
333&iomuxc {
334 imx6qdl-gw53xx {
272 pinctrl_audmux: audmuxgrp { 335 pinctrl_audmux: audmuxgrp {
273 fsl,pins = < 336 fsl,pins = <
274 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 337 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
275 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 338 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
276 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 339 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
277 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 340 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
341 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
278 >; 342 >;
279 }; 343 };
280 344
@@ -303,6 +367,15 @@
303 fsl,pins = < 367 fsl,pins = <
304 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 368 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
305 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 369 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
370 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
371 >;
372 };
373
374 pinctrl_gpio_leds: gpioledsgrp {
375 fsl,pins = <
376 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
377 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
378 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
306 >; 379 >;
307 }; 380 };
308 381
@@ -348,6 +421,19 @@
348 >; 421 >;
349 }; 422 };
350 423
424 pinctrl_pcie: pciegrp {
425 fsl,pins = <
426 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
427 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
428 >;
429 };
430
431 pinctrl_pps: ppsgrp {
432 fsl,pins = <
433 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
434 >;
435 };
436
351 pinctrl_pwm4: pwm4grp { 437 pinctrl_pwm4: pwm4grp {
352 fsl,pins = < 438 fsl,pins = <
353 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 439 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
@@ -378,6 +464,8 @@
378 pinctrl_usbotg: usbotggrp { 464 pinctrl_usbotg: usbotggrp {
379 fsl,pins = < 465 fsl,pins = <
380 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 466 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
467 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
468 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
381 >; 469 >;
382 }; 470 };
383 471
@@ -389,90 +477,8 @@
389 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 477 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
390 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 478 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
391 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 479 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
480 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
392 >; 481 >;
393 }; 482 };
394 }; 483 };
395}; 484};
396
397&ldb {
398 status = "okay";
399
400 lvds-channel@1 {
401 fsl,data-mapping = "spwg";
402 fsl,data-width = <18>;
403 status = "okay";
404
405 display-timings {
406 native-mode = <&timing0>;
407 timing0: hsd100pxn1 {
408 clock-frequency = <65000000>;
409 hactive = <1024>;
410 vactive = <768>;
411 hback-porch = <220>;
412 hfront-porch = <40>;
413 vback-porch = <21>;
414 vfront-porch = <7>;
415 hsync-len = <60>;
416 vsync-len = <10>;
417 };
418 };
419 };
420};
421
422&pcie {
423 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
424 status = "okay";
425
426 eth1: sky2@8 { /* MAC/PHY on bus 8 */
427 compatible = "marvell,sky2";
428 };
429};
430
431&pwm4 {
432 pinctrl-names = "default";
433 pinctrl-0 = <&pinctrl_pwm4>;
434 status = "okay";
435};
436
437&ssi1 {
438 status = "okay";
439};
440
441&uart1 {
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_uart1>;
444 status = "okay";
445};
446
447&uart2 {
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_uart2>;
450 status = "okay";
451};
452
453&uart5 {
454 pinctrl-names = "default";
455 pinctrl-0 = <&pinctrl_uart5>;
456 status = "okay";
457};
458
459&usbotg {
460 vbus-supply = <&reg_usb_otg_vbus>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_usbotg>;
463 disable-over-current;
464 status = "okay";
465};
466
467&usbh1 {
468 vbus-supply = <&reg_usb_h1_vbus>;
469 status = "okay";
470};
471
472&usdhc3 {
473 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_usdhc3>;
475 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
476 vmmc-supply = <&reg_3p3v>;
477 status = "okay";
478};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index a366a9332509..cf13239a1619 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -37,6 +37,8 @@
37 37
38 leds { 38 leds {
39 compatible = "gpio-leds"; 39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_gpio_leds>;
40 42
41 led0: user1 { 43 led0: user1 {
42 label = "user1"; 44 label = "user1";
@@ -64,6 +66,8 @@
64 66
65 pps { 67 pps {
66 compatible = "pps-gpio"; 68 compatible = "pps-gpio";
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_pps>;
67 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 71 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
68 status = "okay"; 72 status = "okay";
69 }; 73 };
@@ -329,35 +333,106 @@
329 }; 333 };
330}; 334};
331 335
332&iomuxc { 336&ldb {
333 pinctrl-names = "default"; 337 status = "okay";
334 pinctrl-0 = <&pinctrl_hog>;
335 338
336 imx6qdl-gw54xx { 339 lvds-channel@1 {
337 pinctrl_hog: hoggrp { 340 fsl,data-mapping = "spwg";
338 fsl,pins = < 341 fsl,data-width = <18>;
339 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ 342 status = "okay";
340 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0001b0b0 /* SPINOR_CS0# */ 343
341 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ 344 display-timings {
342 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ 345 native-mode = <&timing0>;
343 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ 346 timing0: hsd100pxn1 {
344 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ 347 clock-frequency = <65000000>;
345 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 348 hactive = <1024>;
346 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ 349 vactive = <768>;
347 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ 350 hback-porch = <220>;
348 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ 351 hfront-porch = <40>;
349 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ 352 vback-porch = <21>;
350 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x4001b0b0 /* USBHUB_RST# */ 353 vfront-porch = <7>;
351 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x4001b0b0 /* MIPI_DIO */ 354 hsync-len = <60>;
352 >; 355 vsync-len = <10>;
356 };
353 }; 357 };
358 };
359};
360
361&pcie {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_pcie>;
364 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
365 status = "okay";
366
367 eth1: sky2@8 { /* MAC/PHY on bus 8 */
368 compatible = "marvell,sky2";
369 };
370};
354 371
372&pwm4 {
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_pwm4>;
375 status = "okay";
376};
377
378&ssi1 {
379 fsl,mode = "i2s-slave";
380 status = "okay";
381};
382
383&ssi2 {
384 fsl,mode = "i2s-slave";
385 status = "okay";
386};
387
388&uart1 {
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_uart1>;
391 status = "okay";
392};
393
394&uart2 {
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_uart2>;
397 status = "okay";
398};
399
400&uart5 {
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_uart5>;
403 status = "okay";
404};
405
406&usbotg {
407 vbus-supply = <&reg_usb_otg_vbus>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_usbotg>;
410 disable-over-current;
411 status = "okay";
412};
413
414&usbh1 {
415 vbus-supply = <&reg_usb_h1_vbus>;
416 status = "okay";
417};
418
419&usdhc3 {
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_usdhc3>;
422 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
423 vmmc-supply = <&reg_3p3v>;
424 status = "okay";
425};
426
427&iomuxc {
428 imx6qdl-gw54xx {
355 pinctrl_audmux: audmuxgrp { 429 pinctrl_audmux: audmuxgrp {
356 fsl,pins = < 430 fsl,pins = <
357 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 431 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
358 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 432 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
359 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 433 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
360 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 434 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
435 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
361 >; 436 >;
362 }; 437 };
363 438
@@ -386,6 +461,15 @@
386 fsl,pins = < 461 fsl,pins = <
387 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 462 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
388 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 463 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
464 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
465 >;
466 };
467
468 pinctrl_gpio_leds: gpioledsgrp {
469 fsl,pins = <
470 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
471 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
472 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
389 >; 473 >;
390 }; 474 };
391 475
@@ -431,6 +515,19 @@
431 >; 515 >;
432 }; 516 };
433 517
518 pinctrl_pcie: pciegrp {
519 fsl,pins = <
520 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
521 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
522 >;
523 };
524
525 pinctrl_pps: ppsgrp {
526 fsl,pins = <
527 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
528 >;
529 };
530
434 pinctrl_pwm4: pwm4grp { 531 pinctrl_pwm4: pwm4grp {
435 fsl,pins = < 532 fsl,pins = <
436 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 533 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
@@ -461,6 +558,7 @@
461 pinctrl_usbotg: usbotggrp { 558 pinctrl_usbotg: usbotggrp {
462 fsl,pins = < 559 fsl,pins = <
463 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 560 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
561 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
464 >; 562 >;
465 }; 563 };
466 564
@@ -476,90 +574,3 @@
476 }; 574 };
477 }; 575 };
478}; 576};
479
480&ldb {
481 status = "okay";
482
483 lvds-channel@1 {
484 fsl,data-mapping = "spwg";
485 fsl,data-width = <18>;
486 status = "okay";
487
488 display-timings {
489 native-mode = <&timing0>;
490 timing0: hsd100pxn1 {
491 clock-frequency = <65000000>;
492 hactive = <1024>;
493 vactive = <768>;
494 hback-porch = <220>;
495 hfront-porch = <40>;
496 vback-porch = <21>;
497 vfront-porch = <7>;
498 hsync-len = <60>;
499 vsync-len = <10>;
500 };
501 };
502 };
503};
504
505&pcie {
506 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
507 status = "okay";
508
509 eth1: sky2@8 { /* MAC/PHY on bus 8 */
510 compatible = "marvell,sky2";
511 };
512};
513
514&pwm4 {
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_pwm4>;
517 status = "okay";
518};
519
520&ssi1 {
521 status = "okay";
522};
523
524&ssi2 {
525 status = "okay";
526};
527
528&uart1 {
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_uart1>;
531 status = "okay";
532};
533
534&uart2 {
535 pinctrl-names = "default";
536 pinctrl-0 = <&pinctrl_uart2>;
537 status = "okay";
538};
539
540&uart5 {
541 pinctrl-names = "default";
542 pinctrl-0 = <&pinctrl_uart5>;
543 status = "okay";
544};
545
546&usbotg {
547 vbus-supply = <&reg_usb_otg_vbus>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_usbotg>;
550 disable-over-current;
551 status = "okay";
552};
553
554&usbh1 {
555 vbus-supply = <&reg_usb_h1_vbus>;
556 status = "okay";
557};
558
559&usdhc3 {
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_usdhc3>;
562 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
563 vmmc-supply = <&reg_3p3v>;
564 status = "okay";
565};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 16:18:04 -0400