diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-12 06:56:00 -0500 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-16 10:33:42 -0500 |
| commit | b5af6b100c9fb4498051f831c90f69adebd82b88 (patch) | |
| tree | f8513c5d3bd39cc7a0ff33465f20561844f8ce9e | |
| parent | abed9a6bf2bb79e94ac6d6127f70be2f9718bb33 (diff) | |
ARM i.MX51: Add IPU support
This adds the IPU device to the devicetree along with the necessary pinctrl
settings for the parallel display outputs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/imx51.dtsi | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 54aea74769a1..44c7af791fa5 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi | |||
| @@ -62,6 +62,13 @@ | |||
| 62 | interrupt-parent = <&tzic>; | 62 | interrupt-parent = <&tzic>; |
| 63 | ranges; | 63 | ranges; |
| 64 | 64 | ||
| 65 | ipu: ipu@40000000 { | ||
| 66 | #crtc-cells = <1>; | ||
| 67 | compatible = "fsl,imx51-ipu"; | ||
| 68 | reg = <0x40000000 0x20000000>; | ||
| 69 | interrupts = <11 10>; | ||
| 70 | }; | ||
| 71 | |||
| 65 | aips@70000000 { /* AIPS1 */ | 72 | aips@70000000 { /* AIPS1 */ |
| 66 | compatible = "fsl,aips-bus", "simple-bus"; | 73 | compatible = "fsl,aips-bus", "simple-bus"; |
| 67 | #address-cells = <1>; | 74 | #address-cells = <1>; |
| @@ -295,6 +302,66 @@ | |||
| 295 | }; | 302 | }; |
| 296 | }; | 303 | }; |
| 297 | 304 | ||
| 305 | ipu_disp1 { | ||
| 306 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | ||
| 307 | fsl,pins = < | ||
| 308 | 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */ | ||
| 309 | 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */ | ||
| 310 | 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */ | ||
| 311 | 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */ | ||
| 312 | 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */ | ||
| 313 | 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */ | ||
| 314 | 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */ | ||
| 315 | 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */ | ||
| 316 | 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */ | ||
| 317 | 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */ | ||
| 318 | 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */ | ||
| 319 | 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */ | ||
| 320 | 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */ | ||
| 321 | 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */ | ||
| 322 | 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */ | ||
| 323 | 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */ | ||
| 324 | 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */ | ||
| 325 | 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */ | ||
| 326 | 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */ | ||
| 327 | 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */ | ||
| 328 | 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */ | ||
| 329 | 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */ | ||
| 330 | 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */ | ||
| 331 | 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */ | ||
| 332 | 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */ | ||
| 333 | 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */ | ||
| 334 | >; | ||
| 335 | }; | ||
| 336 | }; | ||
| 337 | |||
| 338 | ipu_disp2 { | ||
| 339 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | ||
| 340 | fsl,pins = < | ||
| 341 | 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */ | ||
| 342 | 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */ | ||
| 343 | 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */ | ||
| 344 | 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */ | ||
| 345 | 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */ | ||
| 346 | 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */ | ||
| 347 | 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */ | ||
| 348 | 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */ | ||
| 349 | 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */ | ||
| 350 | 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */ | ||
| 351 | 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */ | ||
| 352 | 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */ | ||
| 353 | 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */ | ||
| 354 | 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */ | ||
| 355 | 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */ | ||
| 356 | 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */ | ||
| 357 | 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */ | ||
| 358 | 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */ | ||
| 359 | 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */ | ||
| 360 | 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */ | ||
| 361 | >; | ||
| 362 | }; | ||
| 363 | }; | ||
| 364 | |||
| 298 | uart1 { | 365 | uart1 { |
| 299 | pinctrl_uart1_1: uart1grp-1 { | 366 | pinctrl_uart1_1: uart1grp-1 { |
| 300 | fsl,pins = < | 367 | fsl,pins = < |