i2c: rk3x: fix divisor calculation for SCL frequency

I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.

The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)

It will be updated to the latest version of chip manual.

Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org

1 files changed, 5 insertions, 6 deletions

diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32ae517..93cfc837200b 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,12 +433,11 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
         unsigned long i2c_rate = clk_get_rate(i2c->clk);
         unsigned int div;
 
-        /* SCL rate = (clk rate) / (8 * DIV) */
-        div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
-
-        /* The lower and upper half of the CLKDIV reg describe the length of
-         * SCL low & high periods. */
-        div = DIV_ROUND_UP(div, 2);
+        /* set DIV = DIVH = DIVL
+         * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
+         *          = (clk rate) / (16 * (DIV + 1))
+         */
+        div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
 
         i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
 }