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authorRalf Baechle <ralf@linux-mips.org>2005-12-08 09:04:24 -0500
committer <ralf@denk.linux-mips.net>2006-01-10 08:39:06 -0500
commitb4672d37293cb045ec4d57e8b76a62810c96da71 (patch)
tree21ba827850d7bc7c36d7009575b979d12b35227c
parente7958bb90d57f0da073cbd031a1808de51d1de15 (diff)
MIPS: Introduce machinery for testing for MIPSxxR1/2.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/kernel/cpu-probe.c35
-rw-r--r--arch/mips/kernel/time.c6
-rw-r--r--include/asm-mips/cpu-features.h24
-rw-r--r--include/asm-mips/cpu.h4
-rw-r--r--include/asm-mips/mach-ip22/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-ip27/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-ip32/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-ja/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-ocelot3/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-rm200/cpu-feature-overrides.h5
-rw-r--r--include/asm-mips/mach-yosemite/cpu-feature-overrides.h5
11 files changed, 95 insertions, 9 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index d00f8768e2a0..fac48ad27b34 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -435,6 +435,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
435 } 435 }
436} 436}
437 437
438static char unknown_isa[] __initdata = KERN_ERR \
439 "Unsupported ISA type, c0.config0: %d.";
440
438static inline unsigned int decode_config0(struct cpuinfo_mips *c) 441static inline unsigned int decode_config0(struct cpuinfo_mips *c)
439{ 442{
440 unsigned int config0; 443 unsigned int config0;
@@ -447,16 +450,37 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
447 isa = (config0 & MIPS_CONF_AT) >> 13; 450 isa = (config0 & MIPS_CONF_AT) >> 13;
448 switch (isa) { 451 switch (isa) {
449 case 0: 452 case 0:
450 c->isa_level = MIPS_CPU_ISA_M32R1; 453 switch ((config0 >> 10) & 7) {
454 case 0:
455 c->isa_level = MIPS_CPU_ISA_M32R1;
456 break;
457 case 1:
458 c->isa_level = MIPS_CPU_ISA_M32R2;
459 break;
460 default:
461 goto unknown;
462 }
451 break; 463 break;
452 case 2: 464 case 2:
453 c->isa_level = MIPS_CPU_ISA_M64R1; 465 switch ((config0 >> 10) & 7) {
466 case 0:
467 c->isa_level = MIPS_CPU_ISA_M64R1;
468 break;
469 case 1:
470 c->isa_level = MIPS_CPU_ISA_M64R2;
471 break;
472 default:
473 goto unknown;
474 }
454 break; 475 break;
455 default: 476 default:
456 panic("Unsupported ISA type, cp0.config0.at: %d.", isa); 477 goto unknown;
457 } 478 }
458 479
459 return config0 & MIPS_CONF_M; 480 return config0 & MIPS_CONF_M;
481
482unknown:
483 panic(unknown_isa, config0);
460} 484}
461 485
462static inline unsigned int decode_config1(struct cpuinfo_mips *c) 486static inline unsigned int decode_config1(struct cpuinfo_mips *c)
@@ -568,7 +592,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
568 break; 592 break;
569 case PRID_IMP_34K: 593 case PRID_IMP_34K:
570 c->cputype = CPU_34K; 594 c->cputype = CPU_34K;
571 c->isa_level = MIPS_CPU_ISA_M32R1;
572 break; 595 break;
573 } 596 }
574} 597}
@@ -691,7 +714,9 @@ __init void cpu_probe(void)
691 c->fpu_id = cpu_get_fpu_id(); 714 c->fpu_id = cpu_get_fpu_id();
692 715
693 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 716 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
694 c->isa_level == MIPS_CPU_ISA_M64R1) { 717 c->isa_level == MIPS_CPU_ISA_M32R2 ||
718 c->isa_level == MIPS_CPU_ISA_M64R1 ||
719 c->isa_level == MIPS_CPU_ISA_M64R2) {
695 if (c->fpu_id & MIPS_FPIR_3D) 720 if (c->fpu_id & MIPS_FPIR_3D)
696 c->ases |= MIPS_ASE_MIPS3D; 721 c->ases |= MIPS_ASE_MIPS3D;
697 } 722 }
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 174959bf1d59..07e125c027b2 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -628,9 +628,9 @@ void __init time_init(void)
628 mips_hpt_init = c0_hpt_init; 628 mips_hpt_init = c0_hpt_init;
629 } 629 }
630 630
631 if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32R1) || 631 if (cpu_has_mips32r1 || cpu_has_mips32r2 ||
632 (current_cpu_data.isa_level == MIPS_CPU_ISA_I) || 632 (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
633 (current_cpu_data.isa_level == MIPS_CPU_ISA_II)) 633 (current_cpu_data.isa_level == MIPS_CPU_ISA_II))
634 /* 634 /*
635 * We need to calibrate the counter but we don't have 635 * We need to calibrate the counter but we don't have
636 * 64-bit division. 636 * 64-bit division.
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 03627cfb3e45..f8be4a470754 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -144,6 +144,18 @@
144# ifndef cpu_has_64bit_addresses 144# ifndef cpu_has_64bit_addresses
145# define cpu_has_64bit_addresses 0 145# define cpu_has_64bit_addresses 0
146# endif 146# endif
147# ifndef cpu_has_mips32r1
148# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
149# endif
150# ifndef cpu_has_mips32r2
151# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
152# endif
153# ifndef cpu_has_mips64r1
154# define cpu_has_mips64r1 0
155# endif
156# ifndef cpu_has_mips64r2
157# define cpu_has_mips64r2 0
158# endif
147#endif 159#endif
148 160
149#ifdef CONFIG_64BIT 161#ifdef CONFIG_64BIT
@@ -162,6 +174,18 @@
162# ifndef cpu_has_64bit_addresses 174# ifndef cpu_has_64bit_addresses
163# define cpu_has_64bit_addresses 1 175# define cpu_has_64bit_addresses 1
164# endif 176# endif
177# ifndef cpu_has_mips32r1
178# define cpu_has_mips32r1 0
179# endif
180# ifndef cpu_has_mips32r2
181# define cpu_has_mips32r2 0
182# endif
183# ifndef cpu_has_mips64r1
184# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
185# endif
186# ifndef cpu_has_mips64r2
187# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
188# endif
165#endif 189#endif
166 190
167#ifdef CONFIG_CPU_MIPSR2 191#ifdef CONFIG_CPU_MIPSR2
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 256fe130eae8..48c37c46053a 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -210,7 +210,9 @@
210#define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT) 210#define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT)
211#define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT) 211#define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT)
212#define MIPS_CPU_ISA_M32R1 0x00000020 212#define MIPS_CPU_ISA_M32R1 0x00000020
213#define MIPS_CPU_ISA_M64R1 (0x00000040 | MIPS_CPU_ISA_64BIT) 213#define MIPS_CPU_ISA_M32R2 0x00000040
214#define MIPS_CPU_ISA_M64R1 (0x00000080 | MIPS_CPU_ISA_64BIT)
215#define MIPS_CPU_ISA_M64R2 (0x00000100 | MIPS_CPU_ISA_64BIT)
214 216
215/* 217/*
216 * CPU Option encodings 218 * CPU Option encodings
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
index ab9714668177..2a37bedb4053 100644
--- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
@@ -34,4 +34,9 @@
34#define cpu_has_nofpuex 0 34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1 35#define cpu_has_64bits 1
36 36
37#define cpu_has_mips32r1 0
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 0
40#define cpu_has_mips64r2 0
41
37#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */ 42#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
index 4c8a90051fd0..2d2f5b91e47f 100644
--- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
@@ -37,4 +37,9 @@
37#define cpu_icache_line_size() 64 37#define cpu_icache_line_size() 64
38#define cpu_scache_line_size() 128 38#define cpu_scache_line_size() 128
39 39
40#define cpu_has_mips32r1 0
41#define cpu_has_mips32r2 0
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
40#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */ 45#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
index ab37fc1842ba..b80c30725cf6 100644
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
@@ -39,4 +39,9 @@
39#define cpu_has_ic_fills_f_dc 0 39#define cpu_has_ic_fills_f_dc 0
40#define cpu_has_dsp 0 40#define cpu_has_dsp 0
41 41
42#define cpu_has_mips32r1 0
43#define cpu_has_mips32r2 0
44#define cpu_has_mips64r1 0
45#define cpu_has_mips64r2 0
46
42#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */ 47#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h
index a0fde405d4c4..90ff087083b9 100644
--- a/include/asm-mips/mach-ja/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h
@@ -37,4 +37,9 @@
37#define cpu_icache_line_size() 32 37#define cpu_icache_line_size() 32
38#define cpu_scache_line_size() 32 38#define cpu_scache_line_size() 32
39 39
40#define cpu_has_mips32r1 0
41#define cpu_has_mips32r2 0
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
40#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ 45#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
index 825c5f674dfc..782b986241dd 100644
--- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
@@ -40,4 +40,9 @@
40#define cpu_icache_line_size() 32 40#define cpu_icache_line_size() 32
41#define cpu_scache_line_size() 32 41#define cpu_scache_line_size() 32
42 42
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 0
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47
43#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ 48#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
index 79f9b064c864..91e7cf5f2bfe 100644
--- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
@@ -40,4 +40,9 @@
40#define cpu_icache_line_size() 32 40#define cpu_icache_line_size() 32
41#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */ 41#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */
42 42
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 0
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47
43#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */ 48#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
index 463d051f4683..3073542c93c7 100644
--- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
@@ -37,4 +37,9 @@
37#define cpu_icache_line_size() 32 37#define cpu_icache_line_size() 32
38#define cpu_scache_line_size() 32 38#define cpu_scache_line_size() 32
39 39
40#define cpu_has_mips32r1 0
41#define cpu_has_mips32r2 0
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
40#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */ 45#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */