diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-16 16:55:54 -0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-21 12:32:43 -0400 |
| commit | b4437a4139f455d1d6557d81789dcbbe849b0496 (patch) | |
| tree | 357f4d06e3341c9ae73b0b671877b9a8e951f7a7 | |
| parent | 0b5c5ed072b8e0de8dc4e085dbd855e440c58bf4 (diff) | |
drm/i915: CRC source selection #defines for gmch/vlv chips
A bit a mess, since with DP/TV outputs we can't use the pipe CRC.
Also, no plane CRCs, so we need to update the basic testcases.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a45fbae59e68..08061fc83e5c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -1843,15 +1843,37 @@ | |||
| 1843 | /* Pipe A CRC regs */ | 1843 | /* Pipe A CRC regs */ |
| 1844 | #define _PIPE_CRC_CTL_A (dev_priv->info->display_mmio_offset + 0x60050) | 1844 | #define _PIPE_CRC_CTL_A (dev_priv->info->display_mmio_offset + 0x60050) |
| 1845 | #define PIPE_CRC_ENABLE (1 << 31) | 1845 | #define PIPE_CRC_ENABLE (1 << 31) |
| 1846 | /* ivb+ source selection */ | ||
| 1846 | #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) | 1847 | #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) |
| 1847 | #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) | 1848 | #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) |
| 1848 | #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) | 1849 | #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) |
| 1850 | /* ilk+ source selection */ | ||
| 1849 | #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) | 1851 | #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) |
| 1850 | #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) | 1852 | #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) |
| 1851 | #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) | 1853 | #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) |
| 1852 | /* embedded DP port on the north display block, reserved on ivb */ | 1854 | /* embedded DP port on the north display block, reserved on ivb */ |
| 1853 | #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) | 1855 | #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) |
| 1854 | #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ | 1856 | #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ |
| 1857 | /* vlv source selection */ | ||
| 1858 | #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) | ||
| 1859 | #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) | ||
| 1860 | #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) | ||
| 1861 | /* with DP port the pipe source is invalid */ | ||
| 1862 | #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) | ||
| 1863 | #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) | ||
| 1864 | #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) | ||
| 1865 | /* gen3+ source selection */ | ||
| 1866 | #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) | ||
| 1867 | #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) | ||
| 1868 | #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) | ||
| 1869 | /* with DP/TV port the pipe source is invalid */ | ||
| 1870 | #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) | ||
| 1871 | #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) | ||
| 1872 | #define PIPE_CRC_SOURCE_TV_POST (5 << 28) | ||
| 1873 | #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) | ||
| 1874 | #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) | ||
| 1875 | /* gen2 doesn't have source selection bits */ | ||
| 1876 | |||
| 1855 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 | 1877 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 |
| 1856 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 | 1878 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 |
| 1857 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c | 1879 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c |