diff options
| author | Olof Johansson <olof@lixom.net> | 2014-07-19 14:56:39 -0400 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2014-07-19 14:56:39 -0400 |
| commit | b40abaf07fa19c5aa3e649369ed8e0f9df1d2eda (patch) | |
| tree | 6a3196ae1613619c0b85fafede012c7b78d0344c | |
| parent | 9b03c6041c4e47a5d2c2eca3c2dd2239e7ae6ce6 (diff) | |
| parent | 4349c4298f676815bf7ad146cf37e76843054783 (diff) | |
Merge tag 'imx-soc-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "ARM: imx: SoC changes for 3.17" from Shawn Guo:
The i.MX SoC changes for 3.17:
- Add devicetree support for i.MX1 and i.MX21 clock driver
- Use CLOCKSOURCE_OF_DECLARE() to initialize timer for DT targets
- Use of_clk_init() to initialize i.MX25 and i.MX27 clock driver in
device tree boot
- Remove i.MX1 camera support
- Remove i.MX27 IP Camera and Lite-Kit board support
- Add suspend and cpuidle support for i.mx6sx
- Clean up unused clk_register_clkdev() lookups
- Update imx-weim bus driver to support populating devices on a simple
bus
- Switch i.MX27 and i.MX6QDL clock driver to use macro for clock IDs
- Make i.MX51 a DT only platform and clean up the non-DT support code
- Support disabling supervisor protect via DT
- Random defconfig updates
* tag 'imx-soc-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (69 commits)
ARM: imx: clk-vf610: fix FlexCAN clock gating
ARM: i.MX: Use CLOCKSOURCE_OF_DECLARE() for DT targets
ARM: i.MX53: globally disable supervisor protect
ARM: i.MX: allow disabling supervisor protect via DT
ARM: i.MX27 clk: Add 26 MHz oscillator circuit clock gate
ARM: i.MX27 clk: Remove unused definitions
ARM: i.MX27 clk: Introduce DT include for clock provider
ARM: i.MX: Remove Freescale Logic Product Development i.MX27 Lite-Kit board support
ARM: i.MX: Remove excess symbols ARCH_MX1, ARCH_MX25 and MACH_MX27
ARM: i.MX: Remove i.MX1 camera support
ARM: imx: use PTR_ERR_OR_ZERO
bus: imx-weim: populate devices on a simple bus
ARM: imx: build cpu_is_imx6sl function conditionally
ARM: imx: imx6sx uses imx6q cpuidle code
ARM: imx: drop PL310 errata 588369 and 727915
ARM: imx_v6_v7_defconfig: add FSL_EDMA and PRINTK_TIME
ARM: imx: clk-imx6sx: register SSI/SSI_IPG as shared gate clocks
ARM: imx_v6_v7_defconfig: Enable flexcan driver for can support
ARM: imx_v6_v7_defconfig: Enable STMPE gpio support
ARM: imx: mark .dt_compat as const
...
Signed-off-by: Olof Johansson <olof@lixom.net>
109 files changed, 1806 insertions, 4664 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx1-clock.txt b/Documentation/devicetree/bindings/clock/imx1-clock.txt new file mode 100644 index 000000000000..b7adf4e3ea98 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx1-clock.txt | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | * Clock bindings for Freescale i.MX1 CPUs | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: Should be "fsl,imx1-ccm". | ||
| 5 | - reg: Address and length of the register set. | ||
| 6 | - #clock-cells: Should be <1>. | ||
| 7 | |||
| 8 | The clock consumer should specify the desired clock by having the clock | ||
| 9 | ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h | ||
| 10 | for the full list of i.MX1 clock IDs. | ||
| 11 | |||
| 12 | Examples: | ||
| 13 | clks: ccm@0021b000 { | ||
| 14 | #clock-cells = <1>; | ||
| 15 | compatible = "fsl,imx1-ccm"; | ||
| 16 | reg = <0x0021b000 0x1000>; | ||
| 17 | }; | ||
| 18 | |||
| 19 | pwm: pwm@00208000 { | ||
| 20 | #pwm-cells = <2>; | ||
| 21 | compatible = "fsl,imx1-pwm"; | ||
| 22 | reg = <0x00208000 0x1000>; | ||
| 23 | interrupts = <34>; | ||
| 24 | clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>; | ||
| 25 | clock-names = "ipg", "per"; | ||
| 26 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/imx21-clock.txt b/Documentation/devicetree/bindings/clock/imx21-clock.txt new file mode 100644 index 000000000000..c3b0db437c48 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx21-clock.txt | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | * Clock bindings for Freescale i.MX21 | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible : Should be "fsl,imx21-ccm". | ||
| 5 | - reg : Address and length of the register set. | ||
| 6 | - interrupts : Should contain CCM interrupt. | ||
| 7 | - #clock-cells: Should be <1>. | ||
| 8 | |||
| 9 | The clock consumer should specify the desired clock by having the clock | ||
| 10 | ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h | ||
| 11 | for the full list of i.MX21 clock IDs. | ||
| 12 | |||
| 13 | Examples: | ||
| 14 | clks: ccm@10027000{ | ||
| 15 | compatible = "fsl,imx21-ccm"; | ||
| 16 | reg = <0x10027000 0x800>; | ||
| 17 | #clock-cells = <1>; | ||
| 18 | }; | ||
| 19 | |||
| 20 | uart1: serial@1000a000 { | ||
| 21 | compatible = "fsl,imx21-uart"; | ||
| 22 | reg = <0x1000a000 0x1000>; | ||
| 23 | interrupts = <20>; | ||
| 24 | clocks = <&clks IMX21_CLK_UART1_IPG_GATE>, | ||
| 25 | <&clks IMX21_CLK_PER1>; | ||
| 26 | clock-names = "ipg", "per"; | ||
| 27 | status = "disabled"; | ||
| 28 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/imx27-clock.txt b/Documentation/devicetree/bindings/clock/imx27-clock.txt index 6bc9fd2c6631..cc05de9ec393 100644 --- a/Documentation/devicetree/bindings/clock/imx27-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx27-clock.txt | |||
| @@ -7,117 +7,22 @@ Required properties: | |||
| 7 | - #clock-cells: Should be <1> | 7 | - #clock-cells: Should be <1> |
| 8 | 8 | ||
| 9 | The clock consumer should specify the desired clock by having the clock | 9 | The clock consumer should specify the desired clock by having the clock |
| 10 | ID in its "clocks" phandle cell. The following is a full list of i.MX27 | 10 | ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h |
| 11 | clocks and IDs. | 11 | for the full list of i.MX27 clock IDs. |
| 12 | |||
| 13 | Clock ID | ||
| 14 | ----------------------- | ||
| 15 | dummy 0 | ||
| 16 | ckih 1 | ||
| 17 | ckil 2 | ||
| 18 | mpll 3 | ||
| 19 | spll 4 | ||
| 20 | mpll_main2 5 | ||
| 21 | ahb 6 | ||
| 22 | ipg 7 | ||
| 23 | nfc_div 8 | ||
| 24 | per1_div 9 | ||
| 25 | per2_div 10 | ||
| 26 | per3_div 11 | ||
| 27 | per4_div 12 | ||
| 28 | vpu_sel 13 | ||
| 29 | vpu_div 14 | ||
| 30 | usb_div 15 | ||
| 31 | cpu_sel 16 | ||
| 32 | clko_sel 17 | ||
| 33 | cpu_div 18 | ||
| 34 | clko_div 19 | ||
| 35 | ssi1_sel 20 | ||
| 36 | ssi2_sel 21 | ||
| 37 | ssi1_div 22 | ||
| 38 | ssi2_div 23 | ||
| 39 | clko_en 24 | ||
| 40 | ssi2_ipg_gate 25 | ||
| 41 | ssi1_ipg_gate 26 | ||
| 42 | slcdc_ipg_gate 27 | ||
| 43 | sdhc3_ipg_gate 28 | ||
| 44 | sdhc2_ipg_gate 29 | ||
| 45 | sdhc1_ipg_gate 30 | ||
| 46 | scc_ipg_gate 31 | ||
| 47 | sahara_ipg_gate 32 | ||
| 48 | rtc_ipg_gate 33 | ||
| 49 | pwm_ipg_gate 34 | ||
| 50 | owire_ipg_gate 35 | ||
| 51 | lcdc_ipg_gate 36 | ||
| 52 | kpp_ipg_gate 37 | ||
| 53 | iim_ipg_gate 38 | ||
| 54 | i2c2_ipg_gate 39 | ||
| 55 | i2c1_ipg_gate 40 | ||
| 56 | gpt6_ipg_gate 41 | ||
| 57 | gpt5_ipg_gate 42 | ||
| 58 | gpt4_ipg_gate 43 | ||
| 59 | gpt3_ipg_gate 44 | ||
| 60 | gpt2_ipg_gate 45 | ||
| 61 | gpt1_ipg_gate 46 | ||
| 62 | gpio_ipg_gate 47 | ||
| 63 | fec_ipg_gate 48 | ||
| 64 | emma_ipg_gate 49 | ||
| 65 | dma_ipg_gate 50 | ||
| 66 | cspi3_ipg_gate 51 | ||
| 67 | cspi2_ipg_gate 52 | ||
| 68 | cspi1_ipg_gate 53 | ||
| 69 | nfc_baud_gate 54 | ||
| 70 | ssi2_baud_gate 55 | ||
| 71 | ssi1_baud_gate 56 | ||
| 72 | vpu_baud_gate 57 | ||
| 73 | per4_gate 58 | ||
| 74 | per3_gate 59 | ||
| 75 | per2_gate 60 | ||
| 76 | per1_gate 61 | ||
| 77 | usb_ahb_gate 62 | ||
| 78 | slcdc_ahb_gate 63 | ||
| 79 | sahara_ahb_gate 64 | ||
| 80 | lcdc_ahb_gate 65 | ||
| 81 | vpu_ahb_gate 66 | ||
| 82 | fec_ahb_gate 67 | ||
| 83 | emma_ahb_gate 68 | ||
| 84 | emi_ahb_gate 69 | ||
| 85 | dma_ahb_gate 70 | ||
| 86 | csi_ahb_gate 71 | ||
| 87 | brom_ahb_gate 72 | ||
| 88 | ata_ahb_gate 73 | ||
| 89 | wdog_ipg_gate 74 | ||
| 90 | usb_ipg_gate 75 | ||
| 91 | uart6_ipg_gate 76 | ||
| 92 | uart5_ipg_gate 77 | ||
| 93 | uart4_ipg_gate 78 | ||
| 94 | uart3_ipg_gate 79 | ||
| 95 | uart2_ipg_gate 80 | ||
| 96 | uart1_ipg_gate 81 | ||
| 97 | ckih_div1p5 82 | ||
| 98 | fpm 83 | ||
| 99 | mpll_osc_sel 84 | ||
| 100 | mpll_sel 85 | ||
| 101 | spll_gate 86 | ||
| 102 | mshc_div 87 | ||
| 103 | rtic_ipg_gate 88 | ||
| 104 | mshc_ipg_gate 89 | ||
| 105 | rtic_ahb_gate 90 | ||
| 106 | mshc_baud_gate 91 | ||
| 107 | 12 | ||
| 108 | Examples: | 13 | Examples: |
| 14 | clks: ccm@10027000{ | ||
| 15 | compatible = "fsl,imx27-ccm"; | ||
| 16 | reg = <0x10027000 0x1000>; | ||
| 17 | #clock-cells = <1>; | ||
| 18 | }; | ||
| 109 | 19 | ||
| 110 | clks: ccm@10027000{ | 20 | uart1: serial@1000a000 { |
| 111 | compatible = "fsl,imx27-ccm"; | 21 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 112 | reg = <0x10027000 0x1000>; | 22 | reg = <0x1000a000 0x1000>; |
| 113 | #clock-cells = <1>; | 23 | interrupts = <20>; |
| 114 | }; | 24 | clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, |
| 115 | 25 | <&clks IMX27_CLK_PER1_GATE>; | |
| 116 | uart1: serial@1000a000 { | 26 | clock-names = "ipg", "per"; |
| 117 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | 27 | status = "disabled"; |
| 118 | reg = <0x1000a000 0x1000>; | 28 | }; |
| 119 | interrupts = <20>; | ||
| 120 | clocks = <&clks 81>, <&clks 61>; | ||
| 121 | clock-names = "ipg", "per"; | ||
| 122 | status = "disabled"; | ||
| 123 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index 90ec91fe5ce0..9252912a5b0e 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt | |||
| @@ -7,223 +7,13 @@ Required properties: | |||
| 7 | - #clock-cells: Should be <1> | 7 | - #clock-cells: Should be <1> |
| 8 | 8 | ||
| 9 | The clock consumer should specify the desired clock by having the clock | 9 | The clock consumer should specify the desired clock by having the clock |
| 10 | ID in its "clocks" phandle cell. The following is a full list of i.MX6Q | 10 | ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h |
| 11 | clocks and IDs. | 11 | for the full list of i.MX6 Quad and DualLite clock IDs. |
| 12 | |||
| 13 | Clock ID | ||
| 14 | --------------------------- | ||
| 15 | dummy 0 | ||
| 16 | ckil 1 | ||
| 17 | ckih 2 | ||
| 18 | osc 3 | ||
| 19 | pll2_pfd0_352m 4 | ||
| 20 | pll2_pfd1_594m 5 | ||
| 21 | pll2_pfd2_396m 6 | ||
| 22 | pll3_pfd0_720m 7 | ||
| 23 | pll3_pfd1_540m 8 | ||
| 24 | pll3_pfd2_508m 9 | ||
| 25 | pll3_pfd3_454m 10 | ||
| 26 | pll2_198m 11 | ||
| 27 | pll3_120m 12 | ||
| 28 | pll3_80m 13 | ||
| 29 | pll3_60m 14 | ||
| 30 | twd 15 | ||
| 31 | step 16 | ||
| 32 | pll1_sw 17 | ||
| 33 | periph_pre 18 | ||
| 34 | periph2_pre 19 | ||
| 35 | periph_clk2_sel 20 | ||
| 36 | periph2_clk2_sel 21 | ||
| 37 | axi_sel 22 | ||
| 38 | esai_sel 23 | ||
| 39 | asrc_sel 24 | ||
| 40 | spdif_sel 25 | ||
| 41 | gpu2d_axi 26 | ||
| 42 | gpu3d_axi 27 | ||
| 43 | gpu2d_core_sel 28 | ||
| 44 | gpu3d_core_sel 29 | ||
| 45 | gpu3d_shader_sel 30 | ||
| 46 | ipu1_sel 31 | ||
| 47 | ipu2_sel 32 | ||
| 48 | ldb_di0_sel 33 | ||
| 49 | ldb_di1_sel 34 | ||
| 50 | ipu1_di0_pre_sel 35 | ||
| 51 | ipu1_di1_pre_sel 36 | ||
| 52 | ipu2_di0_pre_sel 37 | ||
| 53 | ipu2_di1_pre_sel 38 | ||
| 54 | ipu1_di0_sel 39 | ||
| 55 | ipu1_di1_sel 40 | ||
| 56 | ipu2_di0_sel 41 | ||
| 57 | ipu2_di1_sel 42 | ||
| 58 | hsi_tx_sel 43 | ||
| 59 | pcie_axi_sel 44 | ||
| 60 | ssi1_sel 45 | ||
| 61 | ssi2_sel 46 | ||
| 62 | ssi3_sel 47 | ||
| 63 | usdhc1_sel 48 | ||
| 64 | usdhc2_sel 49 | ||
| 65 | usdhc3_sel 50 | ||
| 66 | usdhc4_sel 51 | ||
| 67 | enfc_sel 52 | ||
| 68 | emi_sel 53 | ||
| 69 | emi_slow_sel 54 | ||
| 70 | vdo_axi_sel 55 | ||
| 71 | vpu_axi_sel 56 | ||
| 72 | cko1_sel 57 | ||
| 73 | periph 58 | ||
| 74 | periph2 59 | ||
| 75 | periph_clk2 60 | ||
| 76 | periph2_clk2 61 | ||
| 77 | ipg 62 | ||
| 78 | ipg_per 63 | ||
| 79 | esai_pred 64 | ||
| 80 | esai_podf 65 | ||
| 81 | asrc_pred 66 | ||
| 82 | asrc_podf 67 | ||
| 83 | spdif_pred 68 | ||
| 84 | spdif_podf 69 | ||
| 85 | can_root 70 | ||
| 86 | ecspi_root 71 | ||
| 87 | gpu2d_core_podf 72 | ||
| 88 | gpu3d_core_podf 73 | ||
| 89 | gpu3d_shader 74 | ||
| 90 | ipu1_podf 75 | ||
| 91 | ipu2_podf 76 | ||
| 92 | ldb_di0_podf 77 | ||
| 93 | ldb_di1_podf 78 | ||
| 94 | ipu1_di0_pre 79 | ||
| 95 | ipu1_di1_pre 80 | ||
| 96 | ipu2_di0_pre 81 | ||
| 97 | ipu2_di1_pre 82 | ||
| 98 | hsi_tx_podf 83 | ||
| 99 | ssi1_pred 84 | ||
| 100 | ssi1_podf 85 | ||
| 101 | ssi2_pred 86 | ||
| 102 | ssi2_podf 87 | ||
| 103 | ssi3_pred 88 | ||
| 104 | ssi3_podf 89 | ||
| 105 | uart_serial_podf 90 | ||
| 106 | usdhc1_podf 91 | ||
| 107 | usdhc2_podf 92 | ||
| 108 | usdhc3_podf 93 | ||
| 109 | usdhc4_podf 94 | ||
| 110 | enfc_pred 95 | ||
| 111 | enfc_podf 96 | ||
| 112 | emi_podf 97 | ||
| 113 | emi_slow_podf 98 | ||
| 114 | vpu_axi_podf 99 | ||
| 115 | cko1_podf 100 | ||
| 116 | axi 101 | ||
| 117 | mmdc_ch0_axi_podf 102 | ||
| 118 | mmdc_ch1_axi_podf 103 | ||
| 119 | arm 104 | ||
| 120 | ahb 105 | ||
| 121 | apbh_dma 106 | ||
| 122 | asrc 107 | ||
| 123 | can1_ipg 108 | ||
| 124 | can1_serial 109 | ||
| 125 | can2_ipg 110 | ||
| 126 | can2_serial 111 | ||
| 127 | ecspi1 112 | ||
| 128 | ecspi2 113 | ||
| 129 | ecspi3 114 | ||
| 130 | ecspi4 115 | ||
| 131 | ecspi5 116 | ||
| 132 | enet 117 | ||
| 133 | esai 118 | ||
| 134 | gpt_ipg 119 | ||
| 135 | gpt_ipg_per 120 | ||
| 136 | gpu2d_core 121 | ||
| 137 | gpu3d_core 122 | ||
| 138 | hdmi_iahb 123 | ||
| 139 | hdmi_isfr 124 | ||
| 140 | i2c1 125 | ||
| 141 | i2c2 126 | ||
| 142 | i2c3 127 | ||
| 143 | iim 128 | ||
| 144 | enfc 129 | ||
| 145 | ipu1 130 | ||
| 146 | ipu1_di0 131 | ||
| 147 | ipu1_di1 132 | ||
| 148 | ipu2 133 | ||
| 149 | ipu2_di0 134 | ||
| 150 | ldb_di0 135 | ||
| 151 | ldb_di1 136 | ||
| 152 | ipu2_di1 137 | ||
| 153 | hsi_tx 138 | ||
| 154 | mlb 139 | ||
| 155 | mmdc_ch0_axi 140 | ||
| 156 | mmdc_ch1_axi 141 | ||
| 157 | ocram 142 | ||
| 158 | openvg_axi 143 | ||
| 159 | pcie_axi 144 | ||
| 160 | pwm1 145 | ||
| 161 | pwm2 146 | ||
| 162 | pwm3 147 | ||
| 163 | pwm4 148 | ||
| 164 | per1_bch 149 | ||
| 165 | gpmi_bch_apb 150 | ||
| 166 | gpmi_bch 151 | ||
| 167 | gpmi_io 152 | ||
| 168 | gpmi_apb 153 | ||
| 169 | sata 154 | ||
| 170 | sdma 155 | ||
| 171 | spba 156 | ||
| 172 | ssi1 157 | ||
| 173 | ssi2 158 | ||
| 174 | ssi3 159 | ||
| 175 | uart_ipg 160 | ||
| 176 | uart_serial 161 | ||
| 177 | usboh3 162 | ||
| 178 | usdhc1 163 | ||
| 179 | usdhc2 164 | ||
| 180 | usdhc3 165 | ||
| 181 | usdhc4 166 | ||
| 182 | vdo_axi 167 | ||
| 183 | vpu_axi 168 | ||
| 184 | cko1 169 | ||
| 185 | pll1_sys 170 | ||
| 186 | pll2_bus 171 | ||
| 187 | pll3_usb_otg 172 | ||
| 188 | pll4_audio 173 | ||
| 189 | pll5_video 174 | ||
| 190 | pll8_mlb 175 | ||
| 191 | pll7_usb_host 176 | ||
| 192 | pll6_enet 177 | ||
| 193 | ssi1_ipg 178 | ||
| 194 | ssi2_ipg 179 | ||
| 195 | ssi3_ipg 180 | ||
| 196 | rom 181 | ||
| 197 | usbphy1 182 | ||
| 198 | usbphy2 183 | ||
| 199 | ldb_di0_div_3_5 184 | ||
| 200 | ldb_di1_div_3_5 185 | ||
| 201 | sata_ref 186 | ||
| 202 | sata_ref_100m 187 | ||
| 203 | pcie_ref 188 | ||
| 204 | pcie_ref_125m 189 | ||
| 205 | enet_ref 190 | ||
| 206 | usbphy1_gate 191 | ||
| 207 | usbphy2_gate 192 | ||
| 208 | pll4_post_div 193 | ||
| 209 | pll5_post_div 194 | ||
| 210 | pll5_video_div 195 | ||
| 211 | eim_slow 196 | ||
| 212 | spdif 197 | ||
| 213 | cko2_sel 198 | ||
| 214 | cko2_podf 199 | ||
| 215 | cko2 200 | ||
| 216 | cko 201 | ||
| 217 | vdoa 202 | ||
| 218 | pll4_audio_div 203 | ||
| 219 | lvds1_sel 204 | ||
| 220 | lvds2_sel 205 | ||
| 221 | lvds1_gate 206 | ||
| 222 | lvds2_gate 207 | ||
| 223 | esai_ahb 208 | ||
| 224 | 12 | ||
| 225 | Examples: | 13 | Examples: |
| 226 | 14 | ||
| 15 | #include <dt-bindings/clock/imx6qdl-clock.h> | ||
| 16 | |||
| 227 | clks: ccm@020c4000 { | 17 | clks: ccm@020c4000 { |
| 228 | compatible = "fsl,imx6q-ccm"; | 18 | compatible = "fsl,imx6q-ccm"; |
| 229 | reg = <0x020c4000 0x4000>; | 19 | reg = <0x020c4000 0x4000>; |
| @@ -235,7 +25,7 @@ uart1: serial@02020000 { | |||
| 235 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | 25 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 236 | reg = <0x02020000 0x4000>; | 26 | reg = <0x02020000 0x4000>; |
| 237 | interrupts = <0 26 0x04>; | 27 | interrupts = <0 26 0x04>; |
| 238 | clocks = <&clks 160>, <&clks 161>; | 28 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>; |
| 239 | clock-names = "ipg", "per"; | 29 | clock-names = "ipg", "per"; |
| 240 | status = "disabled"; | 30 | status = "disabled"; |
| 241 | }; | 31 | }; |
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index bada59d93b67..63bde0efc041 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # CONFIG_SWAP is not set | 1 | # CONFIG_SWAP is not set |
| 2 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_POSIX_MQUEUE=y | 3 | CONFIG_POSIX_MQUEUE=y |
| 4 | CONFIG_FHANDLE=y | ||
| 4 | CONFIG_NO_HZ=y | 5 | CONFIG_NO_HZ=y |
| 5 | CONFIG_HIGH_RES_TIMERS=y | 6 | CONFIG_HIGH_RES_TIMERS=y |
| 6 | CONFIG_LOG_BUF_SHIFT=14 | 7 | CONFIG_LOG_BUF_SHIFT=14 |
| @@ -35,10 +36,8 @@ CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y | |||
| 35 | CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y | 36 | CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y |
| 36 | CONFIG_MACH_MX27_3DS=y | 37 | CONFIG_MACH_MX27_3DS=y |
| 37 | CONFIG_MACH_IMX27_VISSTRIM_M10=y | 38 | CONFIG_MACH_IMX27_VISSTRIM_M10=y |
| 38 | CONFIG_MACH_IMX27LITE=y | ||
| 39 | CONFIG_MACH_PCA100=y | 39 | CONFIG_MACH_PCA100=y |
| 40 | CONFIG_MACH_MXT_TD60=y | 40 | CONFIG_MACH_MXT_TD60=y |
| 41 | CONFIG_MACH_IMX27IPCAM=y | ||
| 42 | CONFIG_MACH_IMX27_DT=y | 41 | CONFIG_MACH_IMX27_DT=y |
| 43 | CONFIG_PREEMPT=y | 42 | CONFIG_PREEMPT=y |
| 44 | CONFIG_AEABI=y | 43 | CONFIG_AEABI=y |
| @@ -159,6 +158,8 @@ CONFIG_USB_CHIPIDEA=y | |||
| 159 | CONFIG_USB_CHIPIDEA_UDC=y | 158 | CONFIG_USB_CHIPIDEA_UDC=y |
| 160 | CONFIG_USB_CHIPIDEA_HOST=y | 159 | CONFIG_USB_CHIPIDEA_HOST=y |
| 161 | CONFIG_NOP_USB_XCEIV=y | 160 | CONFIG_NOP_USB_XCEIV=y |
| 161 | CONFIG_USB_GADGET=y | ||
| 162 | CONFIG_USB_ETH=m | ||
| 162 | CONFIG_MMC=y | 163 | CONFIG_MMC=y |
| 163 | CONFIG_MMC_SDHCI=y | 164 | CONFIG_MMC_SDHCI=y |
| 164 | CONFIG_MMC_SDHCI_PLTFM=y | 165 | CONFIG_MMC_SDHCI_PLTFM=y |
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 59b7e45142d8..16cfec4385c8 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig | |||
| @@ -1,5 +1,6 @@ | |||
| 1 | CONFIG_KERNEL_LZO=y | 1 | CONFIG_KERNEL_LZO=y |
| 2 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_FHANDLE=y | ||
| 3 | CONFIG_NO_HZ=y | 4 | CONFIG_NO_HZ=y |
| 4 | CONFIG_HIGH_RES_TIMERS=y | 5 | CONFIG_HIGH_RES_TIMERS=y |
| 5 | CONFIG_LOG_BUF_SHIFT=18 | 6 | CONFIG_LOG_BUF_SHIFT=18 |
| @@ -31,11 +32,12 @@ CONFIG_MACH_IMX35_DT=y | |||
| 31 | CONFIG_MACH_PCM043=y | 32 | CONFIG_MACH_PCM043=y |
| 32 | CONFIG_MACH_MX35_3DS=y | 33 | CONFIG_MACH_MX35_3DS=y |
| 33 | CONFIG_MACH_VPR200=y | 34 | CONFIG_MACH_VPR200=y |
| 34 | CONFIG_MACH_IMX51_DT=y | 35 | CONFIG_SOC_IMX51=y |
| 35 | CONFIG_SOC_IMX50=y | 36 | CONFIG_SOC_IMX50=y |
| 36 | CONFIG_SOC_IMX53=y | 37 | CONFIG_SOC_IMX53=y |
| 37 | CONFIG_SOC_IMX6Q=y | 38 | CONFIG_SOC_IMX6Q=y |
| 38 | CONFIG_SOC_IMX6SL=y | 39 | CONFIG_SOC_IMX6SL=y |
| 40 | CONFIG_SOC_IMX6SX=y | ||
| 39 | CONFIG_SOC_VF610=y | 41 | CONFIG_SOC_VF610=y |
| 40 | CONFIG_PCI=y | 42 | CONFIG_PCI=y |
| 41 | CONFIG_PCI_IMX6=y | 43 | CONFIG_PCI_IMX6=y |
| @@ -67,6 +69,8 @@ CONFIG_IP_PNP_DHCP=y | |||
| 67 | # CONFIG_INET_LRO is not set | 69 | # CONFIG_INET_LRO is not set |
| 68 | CONFIG_IPV6=y | 70 | CONFIG_IPV6=y |
| 69 | CONFIG_NETFILTER=y | 71 | CONFIG_NETFILTER=y |
| 72 | CONFIG_CAN=y | ||
| 73 | CONFIG_CAN_FLEXCAN=y | ||
| 70 | CONFIG_CFG80211=y | 74 | CONFIG_CFG80211=y |
| 71 | CONFIG_MAC80211=y | 75 | CONFIG_MAC80211=y |
| 72 | CONFIG_RFKILL=y | 76 | CONFIG_RFKILL=y |
| @@ -160,6 +164,7 @@ CONFIG_SPI=y | |||
| 160 | CONFIG_SPI_IMX=y | 164 | CONFIG_SPI_IMX=y |
| 161 | CONFIG_GPIO_SYSFS=y | 165 | CONFIG_GPIO_SYSFS=y |
| 162 | CONFIG_GPIO_MC9S08DZ60=y | 166 | CONFIG_GPIO_MC9S08DZ60=y |
| 167 | CONFIG_GPIO_STMPE=y | ||
| 163 | # CONFIG_HWMON is not set | 168 | # CONFIG_HWMON is not set |
| 164 | CONFIG_WATCHDOG=y | 169 | CONFIG_WATCHDOG=y |
| 165 | CONFIG_IMX2_WDT=y | 170 | CONFIG_IMX2_WDT=y |
| @@ -242,6 +247,7 @@ CONFIG_RTC_DRV_SNVS=y | |||
| 242 | CONFIG_DMADEVICES=y | 247 | CONFIG_DMADEVICES=y |
| 243 | CONFIG_IMX_SDMA=y | 248 | CONFIG_IMX_SDMA=y |
| 244 | CONFIG_MXS_DMA=y | 249 | CONFIG_MXS_DMA=y |
| 250 | CONFIG_FSL_EDMA=y | ||
| 245 | CONFIG_STAGING=y | 251 | CONFIG_STAGING=y |
| 246 | CONFIG_DRM_IMX=y | 252 | CONFIG_DRM_IMX=y |
| 247 | CONFIG_DRM_IMX_FB_HELPER=y | 253 | CONFIG_DRM_IMX_FB_HELPER=y |
| @@ -288,6 +294,7 @@ CONFIG_NLS_ASCII=y | |||
| 288 | CONFIG_NLS_ISO8859_1=y | 294 | CONFIG_NLS_ISO8859_1=y |
| 289 | CONFIG_NLS_ISO8859_15=m | 295 | CONFIG_NLS_ISO8859_15=m |
| 290 | CONFIG_NLS_UTF8=y | 296 | CONFIG_NLS_UTF8=y |
| 297 | CONFIG_PRINTK_TIME=y | ||
| 291 | CONFIG_DEBUG_FS=y | 298 | CONFIG_DEBUG_FS=y |
| 292 | CONFIG_MAGIC_SYSRQ=y | 299 | CONFIG_MAGIC_SYSRQ=y |
| 293 | # CONFIG_SCHED_DEBUG is not set | 300 | # CONFIG_SCHED_DEBUG is not set |
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index be1a3455a9fe..9a1e7b0c3bea 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig | |||
| @@ -27,7 +27,7 @@ CONFIG_ARCH_HIGHBANK=y | |||
| 27 | CONFIG_ARCH_HI3xxx=y | 27 | CONFIG_ARCH_HI3xxx=y |
| 28 | CONFIG_ARCH_KEYSTONE=y | 28 | CONFIG_ARCH_KEYSTONE=y |
| 29 | CONFIG_ARCH_MXC=y | 29 | CONFIG_ARCH_MXC=y |
| 30 | CONFIG_MACH_IMX51_DT=y | 30 | CONFIG_SOC_IMX51=y |
| 31 | CONFIG_SOC_IMX53=y | 31 | CONFIG_SOC_IMX53=y |
| 32 | CONFIG_SOC_IMX6Q=y | 32 | CONFIG_SOC_IMX6Q=y |
| 33 | CONFIG_SOC_IMX6SL=y | 33 | CONFIG_SOC_IMX6SL=y |
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index a9f992335eb2..c7906c2fd645 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig | |||
| @@ -1,4 +1,5 @@ | |||
| 1 | CONFIG_SYSVIPC=y | 1 | CONFIG_SYSVIPC=y |
| 2 | CONFIG_FHANDLE=y | ||
| 2 | CONFIG_NO_HZ=y | 3 | CONFIG_NO_HZ=y |
| 3 | CONFIG_HIGH_RES_TIMERS=y | 4 | CONFIG_HIGH_RES_TIMERS=y |
| 4 | CONFIG_TASKSTATS=y | 5 | CONFIG_TASKSTATS=y |
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 4b5185748f74..2bc7b97861b4 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
| @@ -65,18 +65,8 @@ config IMX_HAVE_IOMUX_V1 | |||
| 65 | config ARCH_MXC_IOMUX_V3 | 65 | config ARCH_MXC_IOMUX_V3 |
| 66 | bool | 66 | bool |
| 67 | 67 | ||
| 68 | config ARCH_MX1 | ||
| 69 | bool | ||
| 70 | |||
| 71 | config ARCH_MX25 | ||
| 72 | bool | ||
| 73 | |||
| 74 | config MACH_MX27 | ||
| 75 | bool | ||
| 76 | |||
| 77 | config SOC_IMX1 | 68 | config SOC_IMX1 |
| 78 | bool | 69 | bool |
| 79 | select ARCH_MX1 | ||
| 80 | select CPU_ARM920T | 70 | select CPU_ARM920T |
| 81 | select IMX_HAVE_IOMUX_V1 | 71 | select IMX_HAVE_IOMUX_V1 |
| 82 | select MXC_AVIC | 72 | select MXC_AVIC |
| @@ -89,7 +79,6 @@ config SOC_IMX21 | |||
| 89 | 79 | ||
| 90 | config SOC_IMX25 | 80 | config SOC_IMX25 |
| 91 | bool | 81 | bool |
| 92 | select ARCH_MX25 | ||
| 93 | select ARCH_MXC_IOMUX_V3 | 82 | select ARCH_MXC_IOMUX_V3 |
| 94 | select CPU_ARM926T | 83 | select CPU_ARM926T |
| 95 | select MXC_AVIC | 84 | select MXC_AVIC |
| @@ -100,7 +89,6 @@ config SOC_IMX27 | |||
| 100 | select ARCH_HAS_OPP | 89 | select ARCH_HAS_OPP |
| 101 | select CPU_ARM926T | 90 | select CPU_ARM926T |
| 102 | select IMX_HAVE_IOMUX_V1 | 91 | select IMX_HAVE_IOMUX_V1 |
| 103 | select MACH_MX27 | ||
| 104 | select MXC_AVIC | 92 | select MXC_AVIC |
| 105 | select PINCTRL_IMX27 | 93 | select PINCTRL_IMX27 |
| 106 | 94 | ||
| @@ -119,18 +107,6 @@ config SOC_IMX35 | |||
| 119 | select PINCTRL_IMX35 | 107 | select PINCTRL_IMX35 |
| 120 | select SMP_ON_UP if SMP | 108 | select SMP_ON_UP if SMP |
| 121 | 109 | ||
| 122 | config SOC_IMX5 | ||
| 123 | bool | ||
| 124 | select ARCH_HAS_OPP | ||
| 125 | select ARCH_MXC_IOMUX_V3 | ||
| 126 | select MXC_TZIC | ||
| 127 | |||
| 128 | config SOC_IMX51 | ||
| 129 | bool | ||
| 130 | select HAVE_IMX_SRC | ||
| 131 | select PINCTRL_IMX51 | ||
| 132 | select SOC_IMX5 | ||
| 133 | |||
| 134 | if ARCH_MULTI_V4T | 110 | if ARCH_MULTI_V4T |
| 135 | 111 | ||
| 136 | comment "MX1 platforms:" | 112 | comment "MX1 platforms:" |
| @@ -366,15 +342,6 @@ config MACH_IMX27_VISSTRIM_M10 | |||
| 366 | This includes specific configurations for the board and its | 342 | This includes specific configurations for the board and its |
| 367 | peripherals. | 343 | peripherals. |
| 368 | 344 | ||
| 369 | config MACH_IMX27LITE | ||
| 370 | bool "LogicPD MX27 LITEKIT platform" | ||
| 371 | select IMX_HAVE_PLATFORM_IMX_SSI | ||
| 372 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 373 | select SOC_IMX27 | ||
| 374 | help | ||
| 375 | Include support for MX27 LITEKIT platform. This includes specific | ||
| 376 | configurations for the board and its peripherals. | ||
| 377 | |||
| 378 | config MACH_PCA100 | 345 | config MACH_PCA100 |
| 379 | bool "Phytec phyCARD-s (pca100)" | 346 | bool "Phytec phyCARD-s (pca100)" |
| 380 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | 347 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC |
| @@ -406,15 +373,6 @@ config MACH_MXT_TD60 | |||
| 406 | Include support for i-MXT (aka td60) platform. This | 373 | Include support for i-MXT (aka td60) platform. This |
| 407 | includes specific configurations for the module and its peripherals. | 374 | includes specific configurations for the module and its peripherals. |
| 408 | 375 | ||
| 409 | config MACH_IMX27IPCAM | ||
| 410 | bool "IMX27 IPCAM platform" | ||
| 411 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 412 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 413 | select SOC_IMX27 | ||
| 414 | help | ||
| 415 | Include support for IMX27 IPCAM platform. This includes specific | ||
| 416 | configurations for the board and its peripherals. | ||
| 417 | |||
| 418 | config MACH_IMX27_DT | 376 | config MACH_IMX27_DT |
| 419 | bool "Support i.MX27 platforms from device tree" | 377 | bool "Support i.MX27 platforms from device tree" |
| 420 | select SOC_IMX27 | 378 | select SOC_IMX27 |
| @@ -700,24 +658,29 @@ if ARCH_MULTI_V7 | |||
| 700 | 658 | ||
| 701 | comment "Device tree only" | 659 | comment "Device tree only" |
| 702 | 660 | ||
| 661 | config SOC_IMX5 | ||
| 662 | bool | ||
| 663 | select ARCH_HAS_OPP | ||
| 664 | select HAVE_IMX_SRC | ||
| 665 | select MXC_TZIC | ||
| 666 | |||
| 703 | config SOC_IMX50 | 667 | config SOC_IMX50 |
| 704 | bool "i.MX50 support" | 668 | bool "i.MX50 support" |
| 705 | select HAVE_IMX_SRC | ||
| 706 | select PINCTRL_IMX50 | 669 | select PINCTRL_IMX50 |
| 707 | select SOC_IMX5 | 670 | select SOC_IMX5 |
| 708 | 671 | ||
| 709 | help | 672 | help |
| 710 | This enables support for Freescale i.MX50 processor. | 673 | This enables support for Freescale i.MX50 processor. |
| 711 | 674 | ||
| 712 | config MACH_IMX51_DT | 675 | config SOC_IMX51 |
| 713 | bool "i.MX51 support" | 676 | bool "i.MX51 support" |
| 714 | select SOC_IMX51 | 677 | select PINCTRL_IMX51 |
| 678 | select SOC_IMX5 | ||
| 715 | help | 679 | help |
| 716 | This enables support for Freescale i.MX51 processor | 680 | This enables support for Freescale i.MX51 processor |
| 717 | 681 | ||
| 718 | config SOC_IMX53 | 682 | config SOC_IMX53 |
| 719 | bool "i.MX53 support" | 683 | bool "i.MX53 support" |
| 720 | select HAVE_IMX_SRC | ||
| 721 | select PINCTRL_IMX53 | 684 | select PINCTRL_IMX53 |
| 722 | select SOC_IMX5 | 685 | select SOC_IMX5 |
| 723 | 686 | ||
| @@ -734,8 +697,6 @@ config SOC_IMX6 | |||
| 734 | select HAVE_IMX_MMDC | 697 | select HAVE_IMX_MMDC |
| 735 | select HAVE_IMX_SRC | 698 | select HAVE_IMX_SRC |
| 736 | select MFD_SYSCON | 699 | select MFD_SYSCON |
| 737 | select PL310_ERRATA_588369 if CACHE_L2X0 | ||
| 738 | select PL310_ERRATA_727915 if CACHE_L2X0 | ||
| 739 | select PL310_ERRATA_769419 if CACHE_L2X0 | 700 | select PL310_ERRATA_769419 if CACHE_L2X0 |
| 740 | 701 | ||
| 741 | config SOC_IMX6Q | 702 | config SOC_IMX6Q |
| @@ -771,8 +732,6 @@ config SOC_VF610 | |||
| 771 | select ARM_GIC | 732 | select ARM_GIC |
| 772 | select PINCTRL_VF610 | 733 | select PINCTRL_VF610 |
| 773 | select VF_PIT_TIMER | 734 | select VF_PIT_TIMER |
| 774 | select PL310_ERRATA_588369 if CACHE_L2X0 | ||
| 775 | select PL310_ERRATA_727915 if CACHE_L2X0 | ||
| 776 | select PL310_ERRATA_769419 if CACHE_L2X0 | 735 | select PL310_ERRATA_769419 if CACHE_L2X0 |
| 777 | 736 | ||
| 778 | help | 737 | help |
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index bbe93bbfd003..ac88599ca080 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
| @@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci- | |||
| 12 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o | 12 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o |
| 13 | 13 | ||
| 14 | imx5-pm-$(CONFIG_PM) += pm-imx5.o | 14 | imx5-pm-$(CONFIG_PM) += pm-imx5.o |
| 15 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) | 15 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y) |
| 16 | 16 | ||
| 17 | obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ | 17 | obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ |
| 18 | clk-pfd.o clk-busy.o clk.o \ | 18 | clk-pfd.o clk-busy.o clk.o \ |
| @@ -31,6 +31,8 @@ ifeq ($(CONFIG_CPU_IDLE),y) | |||
| 31 | obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o | 31 | obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o |
| 32 | obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o | 32 | obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o |
| 33 | obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o | 33 | obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o |
| 34 | # i.MX6SX reuses i.MX6Q cpuidle driver | ||
| 35 | obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o | ||
| 34 | endif | 36 | endif |
| 35 | 37 | ||
| 36 | ifdef CONFIG_SND_IMX_SOC | 38 | ifdef CONFIG_SND_IMX_SOC |
| @@ -38,9 +40,6 @@ obj-y += ssi-fiq.o | |||
| 38 | obj-y += ssi-fiq-ksym.o | 40 | obj-y += ssi-fiq-ksym.o |
| 39 | endif | 41 | endif |
| 40 | 42 | ||
| 41 | # Support for CMOS sensor interface | ||
| 42 | obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o | ||
| 43 | |||
| 44 | # i.MX1 based machines | 43 | # i.MX1 based machines |
| 45 | obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o | 44 | obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o |
| 46 | obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o | 45 | obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o |
| @@ -60,13 +59,11 @@ obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o | |||
| 60 | obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o | 59 | obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o |
| 61 | obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o | 60 | obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o |
| 62 | obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o | 61 | obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o |
| 63 | obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o | ||
| 64 | obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o | 62 | obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o |
| 65 | obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o | 63 | obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o |
| 66 | obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o | 64 | obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o |
| 67 | obj-$(CONFIG_MACH_PCA100) += mach-pca100.o | 65 | obj-$(CONFIG_MACH_PCA100) += mach-pca100.o |
| 68 | obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o | 66 | obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o |
| 69 | obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o | ||
| 70 | obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o | 67 | obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o |
| 71 | 68 | ||
| 72 | # i.MX31 based machines | 69 | # i.MX31 based machines |
| @@ -109,8 +106,8 @@ obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o | |||
| 109 | endif | 106 | endif |
| 110 | obj-$(CONFIG_SOC_IMX6) += pm-imx6.o | 107 | obj-$(CONFIG_SOC_IMX6) += pm-imx6.o |
| 111 | 108 | ||
| 112 | obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o | ||
| 113 | obj-$(CONFIG_SOC_IMX50) += mach-imx50.o | 109 | obj-$(CONFIG_SOC_IMX50) += mach-imx50.o |
| 110 | obj-$(CONFIG_SOC_IMX51) += mach-imx51.o | ||
| 114 | obj-$(CONFIG_SOC_IMX53) += mach-imx53.o | 111 | obj-$(CONFIG_SOC_IMX53) += mach-imx53.o |
| 115 | 112 | ||
| 116 | obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o | 113 | obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o |
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c index 7f739be3de2c..37c307a8d896 100644 --- a/arch/arm/mach-imx/clk-imx1.c +++ b/arch/arm/mach-imx/clk-imx1.c | |||
| @@ -15,100 +15,103 @@ | |||
| 15 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | 15 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | #include <linux/kernel.h> | ||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
| 21 | #include <linux/io.h> | ||
| 22 | #include <linux/clkdev.h> | 19 | #include <linux/clkdev.h> |
| 20 | #include <linux/clk-provider.h> | ||
| 23 | #include <linux/err.h> | 21 | #include <linux/err.h> |
| 22 | #include <linux/init.h> | ||
| 23 | #include <linux/of.h> | ||
| 24 | #include <linux/of_address.h> | ||
| 25 | #include <dt-bindings/clock/imx1-clock.h> | ||
| 24 | 26 | ||
| 25 | #include "clk.h" | 27 | #include "clk.h" |
| 26 | #include "common.h" | 28 | #include "common.h" |
| 27 | #include "hardware.h" | 29 | #include "hardware.h" |
| 28 | 30 | ||
| 29 | /* CCM register addresses */ | ||
| 30 | #define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off))) | ||
| 31 | |||
| 32 | #define CCM_CSCR IO_ADDR_CCM(0x0) | ||
| 33 | #define CCM_MPCTL0 IO_ADDR_CCM(0x4) | ||
| 34 | #define CCM_SPCTL0 IO_ADDR_CCM(0xc) | ||
| 35 | #define CCM_PCDR IO_ADDR_CCM(0x20) | ||
| 36 | |||
| 37 | /* SCM register addresses */ | ||
| 38 | #define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off))) | ||
| 39 | |||
| 40 | #define SCM_GCCR IO_ADDR_SCM(0xc) | ||
| 41 | |||
| 42 | static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", }; | 31 | static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", }; |
| 43 | static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", | 32 | static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", |
| 44 | "prem", "fclk", }; | 33 | "prem", "fclk", }; |
| 45 | 34 | ||
| 46 | enum imx1_clks { | 35 | static struct clk *clk[IMX1_CLK_MAX]; |
| 47 | dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate, | 36 | static struct clk_onecell_data clk_data; |
| 48 | spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko, | ||
| 49 | uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate, | ||
| 50 | usbd_gate, clk_max | ||
| 51 | }; | ||
| 52 | 37 | ||
| 53 | static struct clk *clk[clk_max]; | 38 | static void __iomem *ccm __initdata; |
| 39 | #define CCM_CSCR (ccm + 0x0000) | ||
| 40 | #define CCM_MPCTL0 (ccm + 0x0004) | ||
| 41 | #define CCM_SPCTL0 (ccm + 0x000c) | ||
| 42 | #define CCM_PCDR (ccm + 0x0020) | ||
| 43 | #define SCM_GCCR (ccm + 0x0810) | ||
| 54 | 44 | ||
| 55 | int __init mx1_clocks_init(unsigned long fref) | 45 | static void __init _mx1_clocks_init(unsigned long fref) |
| 56 | { | 46 | { |
| 57 | int i; | 47 | clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
| 48 | clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref); | ||
| 49 | clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000); | ||
| 50 | clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); | ||
| 51 | clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); | ||
| 52 | clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks)); | ||
| 53 | clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0); | ||
| 54 | clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); | ||
| 55 | clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0); | ||
| 56 | clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); | ||
| 57 | clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1); | ||
| 58 | clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1); | ||
| 59 | clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4); | ||
| 60 | clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3); | ||
| 61 | clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4); | ||
| 62 | clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4); | ||
| 63 | clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7); | ||
| 64 | clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); | ||
| 65 | clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); | ||
| 66 | clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5); | ||
| 67 | clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4); | ||
| 68 | clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3); | ||
| 69 | clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); | ||
| 70 | clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); | ||
| 71 | clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); | ||
| 72 | |||
| 73 | imx_check_clocks(clk, ARRAY_SIZE(clk)); | ||
| 74 | } | ||
| 58 | 75 | ||
| 59 | clk[dummy] = imx_clk_fixed("dummy", 0); | 76 | int __init mx1_clocks_init(unsigned long fref) |
| 60 | clk[clk32] = imx_clk_fixed("clk32", fref); | 77 | { |
| 61 | clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000); | 78 | ccm = MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR); |
| 62 | clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); | ||
| 63 | clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); | ||
| 64 | clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, | ||
| 65 | ARRAY_SIZE(prem_sel_clks)); | ||
| 66 | clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0); | ||
| 67 | clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); | ||
| 68 | clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0); | ||
| 69 | clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); | ||
| 70 | clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1); | ||
| 71 | clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1); | ||
| 72 | clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4); | ||
| 73 | clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3); | ||
| 74 | clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4); | ||
| 75 | clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4); | ||
| 76 | clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7); | ||
| 77 | clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, | ||
| 78 | ARRAY_SIZE(clko_sel_clks)); | ||
| 79 | clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); | ||
| 80 | clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5); | ||
| 81 | clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4); | ||
| 82 | clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3); | ||
| 83 | clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); | ||
| 84 | clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); | ||
| 85 | clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); | ||
| 86 | 79 | ||
| 87 | for (i = 0; i < ARRAY_SIZE(clk); i++) | 80 | _mx1_clocks_init(fref); |
| 88 | if (IS_ERR(clk[i])) | ||
| 89 | pr_err("imx1 clk %d: register failed with %ld\n", | ||
| 90 | i, PTR_ERR(clk[i])); | ||
| 91 | 81 | ||
| 92 | clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma"); | 82 | clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0"); |
| 93 | clk_register_clkdev(clk[hclk], "ipg", "imx1-dma"); | 83 | clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0"); |
| 94 | clk_register_clkdev(clk[per1], "per", "imx-gpt.0"); | 84 | clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma"); |
| 95 | clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0"); | 85 | clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma"); |
| 96 | clk_register_clkdev(clk[per1], "per", "imx1-uart.0"); | 86 | clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0"); |
| 97 | clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0"); | 87 | clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0"); |
| 98 | clk_register_clkdev(clk[per1], "per", "imx1-uart.1"); | 88 | clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1"); |
| 99 | clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1"); | 89 | clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1"); |
| 100 | clk_register_clkdev(clk[per1], "per", "imx1-uart.2"); | 90 | clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2"); |
| 101 | clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2"); | 91 | clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2"); |
| 102 | clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0"); | 92 | clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0"); |
| 103 | clk_register_clkdev(clk[per2], "per", "imx1-cspi.0"); | 93 | clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0"); |
| 104 | clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0"); | 94 | clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0"); |
| 105 | clk_register_clkdev(clk[per2], "per", "imx1-cspi.1"); | 95 | clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1"); |
| 106 | clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1"); | 96 | clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1"); |
| 107 | clk_register_clkdev(clk[per2], "per", "imx1-fb.0"); | 97 | clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0"); |
| 108 | clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0"); | 98 | clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0"); |
| 109 | clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0"); | 99 | clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0"); |
| 110 | 100 | ||
| 111 | mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT); | 101 | mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT); |
| 112 | 102 | ||
| 113 | return 0; | 103 | return 0; |
| 114 | } | 104 | } |
| 105 | |||
| 106 | static void __init mx1_clocks_init_dt(struct device_node *np) | ||
| 107 | { | ||
| 108 | ccm = of_iomap(np, 0); | ||
| 109 | BUG_ON(!ccm); | ||
| 110 | |||
| 111 | _mx1_clocks_init(32768); | ||
| 112 | |||
| 113 | clk_data.clks = clk; | ||
| 114 | clk_data.clk_num = ARRAY_SIZE(clk); | ||
| 115 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
| 116 | } | ||
| 117 | CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt); | ||
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index bdc2e4630a08..4b4c75339aa6 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c | |||
| @@ -7,178 +7,165 @@ | |||
| 7 | * modify it under the terms of the GNU General Public License | 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 | 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. | 9 | * of the License, or (at your option) any later version. |
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | 10 | */ |
| 20 | 11 | ||
| 21 | #include <linux/clk.h> | 12 | #include <linux/clk.h> |
| 22 | #include <linux/clkdev.h> | ||
| 23 | #include <linux/clk-provider.h> | 13 | #include <linux/clk-provider.h> |
| 24 | #include <linux/io.h> | 14 | #include <linux/clkdev.h> |
| 25 | #include <linux/module.h> | 15 | #include <linux/of.h> |
| 26 | #include <linux/err.h> | 16 | #include <linux/of_address.h> |
| 17 | #include <dt-bindings/clock/imx21-clock.h> | ||
| 27 | 18 | ||
| 28 | #include "clk.h" | 19 | #include "clk.h" |
| 29 | #include "common.h" | 20 | #include "common.h" |
| 30 | #include "hardware.h" | 21 | #include "hardware.h" |
| 31 | 22 | ||
| 32 | #define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off))) | 23 | static void __iomem *ccm __initdata; |
| 33 | 24 | ||
| 34 | /* Register offsets */ | 25 | /* Register offsets */ |
| 35 | #define CCM_CSCR IO_ADDR_CCM(0x0) | 26 | #define CCM_CSCR (ccm + 0x00) |
| 36 | #define CCM_MPCTL0 IO_ADDR_CCM(0x4) | 27 | #define CCM_MPCTL0 (ccm + 0x04) |
| 37 | #define CCM_MPCTL1 IO_ADDR_CCM(0x8) | 28 | #define CCM_SPCTL0 (ccm + 0x0c) |
| 38 | #define CCM_SPCTL0 IO_ADDR_CCM(0xc) | 29 | #define CCM_PCDR0 (ccm + 0x18) |
| 39 | #define CCM_SPCTL1 IO_ADDR_CCM(0x10) | 30 | #define CCM_PCDR1 (ccm + 0x1c) |
| 40 | #define CCM_OSC26MCTL IO_ADDR_CCM(0x14) | 31 | #define CCM_PCCR0 (ccm + 0x20) |
| 41 | #define CCM_PCDR0 IO_ADDR_CCM(0x18) | 32 | #define CCM_PCCR1 (ccm + 0x24) |
| 42 | #define CCM_PCDR1 IO_ADDR_CCM(0x1c) | 33 | |
| 43 | #define CCM_PCCR0 IO_ADDR_CCM(0x20) | 34 | static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", }; |
| 44 | #define CCM_PCCR1 IO_ADDR_CCM(0x24) | 35 | static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", }; |
| 45 | #define CCM_CCSR IO_ADDR_CCM(0x28) | 36 | static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", }; |
| 46 | #define CCM_PMCTL IO_ADDR_CCM(0x2c) | 37 | static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", }; |
| 47 | #define CCM_PMCOUNT IO_ADDR_CCM(0x30) | 38 | |
| 48 | #define CCM_WKGDCTL IO_ADDR_CCM(0x34) | 39 | static struct clk *clk[IMX21_CLK_MAX]; |
| 49 | 40 | static struct clk_onecell_data clk_data; | |
| 50 | static const char *mpll_sel_clks[] = { "fpm", "ckih", }; | 41 | |
| 51 | static const char *spll_sel_clks[] = { "fpm", "ckih", }; | 42 | static void __init _mx21_clocks_init(unsigned long lref, unsigned long href) |
| 52 | 43 | { | |
| 53 | enum imx21_clks { | 44 | BUG_ON(!ccm); |
| 54 | ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1, | 45 | |
| 55 | per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate, | 46 | clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
| 56 | uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate, | 47 | clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref); |
| 57 | pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate, | 48 | clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href); |
| 58 | lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate, | 49 | clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); |
| 59 | per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate, | 50 | clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); |
| 60 | ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate, | 51 | |
| 61 | emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate, | 52 | clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); |
| 62 | gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max | 53 | clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); |
| 63 | }; | 54 | clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2); |
| 64 | 55 | clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); | |
| 65 | static struct clk *clk[clk_max]; | 56 | clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); |
| 57 | clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1); | ||
| 58 | clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4); | ||
| 59 | clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); | ||
| 60 | clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks)); | ||
| 61 | clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | ||
| 62 | clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | ||
| 63 | clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3); | ||
| 64 | clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3); | ||
| 65 | |||
| 66 | clk[IMX21_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); | ||
| 67 | |||
| 68 | clk[IMX21_CLK_SPLL] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0); | ||
| 69 | |||
| 70 | clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4); | ||
| 71 | clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); | ||
| 72 | clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); | ||
| 73 | |||
| 74 | clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6); | ||
| 75 | clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6); | ||
| 76 | clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6); | ||
| 77 | clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6); | ||
| 78 | |||
| 79 | clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0); | ||
| 80 | clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1); | ||
| 81 | clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2); | ||
| 82 | clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3); | ||
| 83 | clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4); | ||
| 84 | clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5); | ||
| 85 | clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6); | ||
| 86 | clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7); | ||
| 87 | clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9); | ||
| 88 | clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10); | ||
| 89 | clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11); | ||
| 90 | clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12); | ||
| 91 | clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13); | ||
| 92 | clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14); | ||
| 93 | clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15); | ||
| 94 | clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16); | ||
| 95 | clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17); | ||
| 96 | clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18); | ||
| 97 | clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19); | ||
| 98 | clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21); | ||
| 99 | clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22); | ||
| 100 | clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23); | ||
| 101 | clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24); | ||
| 102 | clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25); | ||
| 103 | clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26); | ||
| 104 | clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27); | ||
| 105 | clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28); | ||
| 106 | clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30); | ||
| 107 | clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31); | ||
| 108 | |||
| 109 | clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23); | ||
| 110 | clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24); | ||
| 111 | clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25); | ||
| 112 | clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26); | ||
| 113 | clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27); | ||
| 114 | clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28); | ||
| 115 | clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29); | ||
| 116 | clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30); | ||
| 117 | clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31); | ||
| 118 | |||
| 119 | imx_check_clocks(clk, ARRAY_SIZE(clk)); | ||
| 120 | } | ||
| 66 | 121 | ||
| 67 | /* | ||
| 68 | * must be called very early to get information about the | ||
| 69 | * available clock rate when the timer framework starts | ||
| 70 | */ | ||
| 71 | int __init mx21_clocks_init(unsigned long lref, unsigned long href) | 122 | int __init mx21_clocks_init(unsigned long lref, unsigned long href) |
| 72 | { | 123 | { |
| 73 | int i; | 124 | ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K); |
| 74 | 125 | ||
| 75 | clk[ckil] = imx_clk_fixed("ckil", lref); | 126 | _mx21_clocks_init(lref, href); |
| 76 | clk[ckih] = imx_clk_fixed("ckih", href); | 127 | |
| 77 | clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); | 128 | clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0"); |
| 78 | clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, | 129 | clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); |
| 79 | ARRAY_SIZE(mpll_sel_clks)); | 130 | clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1"); |
| 80 | clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, | 131 | clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); |
| 81 | ARRAY_SIZE(spll_sel_clks)); | 132 | clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2"); |
| 82 | clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); | 133 | clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); |
| 83 | clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0); | 134 | clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3"); |
| 84 | clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3); | 135 | clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); |
| 85 | clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4); | 136 | clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); |
| 86 | clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1); | 137 | clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0"); |
| 87 | clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6); | 138 | clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0"); |
| 88 | clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6); | 139 | clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0"); |
| 89 | clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6); | 140 | clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1"); |
| 90 | clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6); | 141 | clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1"); |
| 91 | clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0); | 142 | clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2"); |
| 92 | clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1); | 143 | clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2"); |
| 93 | clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2); | 144 | clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0"); |
| 94 | clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3); | 145 | clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); |
| 95 | clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25); | 146 | clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0"); |
| 96 | clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26); | 147 | clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0"); |
| 97 | clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27); | 148 | clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0"); |
| 98 | clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28); | 149 | clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0"); |
| 99 | clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9); | 150 | clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma"); |
| 100 | clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10); | 151 | clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma"); |
| 101 | clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18); | 152 | clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0"); |
| 102 | clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26); | 153 | clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0"); |
| 103 | clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23); | 154 | clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0"); |
| 104 | clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5); | ||
| 105 | clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4); | ||
| 106 | clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22); | ||
| 107 | clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31); | ||
| 108 | clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3); | ||
| 109 | clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14); | ||
| 110 | clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24); | ||
| 111 | clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6); | ||
| 112 | clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7); | ||
| 113 | clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4); | ||
| 114 | clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19); | ||
| 115 | clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13); | ||
| 116 | clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30); | ||
| 117 | clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28); | ||
| 118 | clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15); | ||
| 119 | clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27); | ||
| 120 | clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25); | ||
| 121 | clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21); | ||
| 122 | clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24); | ||
| 123 | clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11); | ||
| 124 | clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12); | ||
| 125 | clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30); | ||
| 126 | clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31); | ||
| 127 | clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29); | ||
| 128 | |||
| 129 | for (i = 0; i < ARRAY_SIZE(clk); i++) | ||
| 130 | if (IS_ERR(clk[i])) | ||
| 131 | pr_err("i.MX21 clk %d: register failed with %ld\n", | ||
| 132 | i, PTR_ERR(clk[i])); | ||
| 133 | |||
| 134 | clk_register_clkdev(clk[per1], "per1", NULL); | ||
| 135 | clk_register_clkdev(clk[per2], "per2", NULL); | ||
| 136 | clk_register_clkdev(clk[per3], "per3", NULL); | ||
| 137 | clk_register_clkdev(clk[per4], "per4", NULL); | ||
| 138 | clk_register_clkdev(clk[per1], "per", "imx21-uart.0"); | ||
| 139 | clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); | ||
| 140 | clk_register_clkdev(clk[per1], "per", "imx21-uart.1"); | ||
| 141 | clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); | ||
| 142 | clk_register_clkdev(clk[per1], "per", "imx21-uart.2"); | ||
| 143 | clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); | ||
| 144 | clk_register_clkdev(clk[per1], "per", "imx21-uart.3"); | ||
| 145 | clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); | ||
| 146 | clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0"); | ||
| 147 | clk_register_clkdev(clk[per1], "per", "imx-gpt.0"); | ||
| 148 | clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1"); | ||
| 149 | clk_register_clkdev(clk[per1], "per", "imx-gpt.1"); | ||
| 150 | clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2"); | ||
| 151 | clk_register_clkdev(clk[per1], "per", "imx-gpt.2"); | ||
| 152 | clk_register_clkdev(clk[per2], "per", "imx21-cspi.0"); | ||
| 153 | clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0"); | ||
| 154 | clk_register_clkdev(clk[per2], "per", "imx21-cspi.1"); | ||
| 155 | clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1"); | ||
| 156 | clk_register_clkdev(clk[per2], "per", "imx21-cspi.2"); | ||
| 157 | clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2"); | ||
| 158 | clk_register_clkdev(clk[per3], "per", "imx21-fb.0"); | ||
| 159 | clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0"); | ||
| 160 | clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0"); | ||
| 161 | clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0"); | ||
| 162 | clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0"); | ||
| 163 | clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0"); | ||
| 164 | clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma"); | ||
| 165 | clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma"); | ||
| 166 | clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); | ||
| 167 | clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0"); | ||
| 168 | clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad"); | ||
| 169 | clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0"); | ||
| 170 | clk_register_clkdev(clk[brom_gate], "brom", NULL); | ||
| 171 | clk_register_clkdev(clk[emma_gate], "emma", NULL); | ||
| 172 | clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL); | ||
| 173 | clk_register_clkdev(clk[gpio_gate], "gpio", NULL); | ||
| 174 | clk_register_clkdev(clk[rtc_gate], "rtc", NULL); | ||
| 175 | clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL); | ||
| 176 | clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL); | ||
| 177 | clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL); | ||
| 178 | clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL); | ||
| 179 | clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL); | ||
| 180 | 155 | ||
| 181 | mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1); | 156 | mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1); |
| 182 | 157 | ||
| 183 | return 0; | 158 | return 0; |
| 184 | } | 159 | } |
| 160 | |||
| 161 | static void __init mx21_clocks_init_dt(struct device_node *np) | ||
| 162 | { | ||
| 163 | ccm = of_iomap(np, 0); | ||
| 164 | |||
| 165 | _mx21_clocks_init(32768, 26000000); | ||
| 166 | |||
| 167 | clk_data.clks = clk; | ||
| 168 | clk_data.clk_num = ARRAY_SIZE(clk); | ||
| 169 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
| 170 | } | ||
| 171 | CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt); | ||
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index ae578c096ad8..59c0c8558c6b 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c | |||
| @@ -32,8 +32,6 @@ | |||
| 32 | #include "hardware.h" | 32 | #include "hardware.h" |
| 33 | #include "mx25.h" | 33 | #include "mx25.h" |
| 34 | 34 | ||
| 35 | #define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR) | ||
| 36 | |||
| 37 | #define CCM_MPCTL 0x00 | 35 | #define CCM_MPCTL 0x00 |
| 38 | #define CCM_UPCTL 0x04 | 36 | #define CCM_UPCTL 0x04 |
| 39 | #define CCM_CCTL 0x08 | 37 | #define CCM_CCTL 0x08 |
| @@ -56,7 +54,7 @@ | |||
| 56 | #define CCM_LTR3 0x4c | 54 | #define CCM_LTR3 0x4c |
| 57 | #define CCM_MCR 0x64 | 55 | #define CCM_MCR 0x64 |
| 58 | 56 | ||
| 59 | #define ccm(x) (CRM_BASE + (x)) | 57 | #define ccm(x) (ccm_base + (x)) |
| 60 | 58 | ||
| 61 | static struct clk_onecell_data clk_data; | 59 | static struct clk_onecell_data clk_data; |
| 62 | 60 | ||
| @@ -91,9 +89,10 @@ enum mx25_clks { | |||
| 91 | 89 | ||
| 92 | static struct clk *clk[clk_max]; | 90 | static struct clk *clk[clk_max]; |
| 93 | 91 | ||
| 94 | static int __init __mx25_clocks_init(unsigned long osc_rate) | 92 | static int __init __mx25_clocks_init(unsigned long osc_rate, |
| 93 | void __iomem *ccm_base) | ||
| 95 | { | 94 | { |
| 96 | int i; | 95 | BUG_ON(!ccm_base); |
| 97 | 96 | ||
| 98 | clk[dummy] = imx_clk_fixed("dummy", 0); | 97 | clk[dummy] = imx_clk_fixed("dummy", 0); |
| 99 | clk[osc] = imx_clk_fixed("osc", osc_rate); | 98 | clk[osc] = imx_clk_fixed("osc", osc_rate); |
| @@ -224,19 +223,13 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) | |||
| 224 | /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */ | 223 | /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */ |
| 225 | clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19); | 224 | clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19); |
| 226 | 225 | ||
| 227 | for (i = 0; i < ARRAY_SIZE(clk); i++) | 226 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
| 228 | if (IS_ERR(clk[i])) | ||
| 229 | pr_err("i.MX25 clk %d: register failed with %ld\n", | ||
| 230 | i, PTR_ERR(clk[i])); | ||
| 231 | 227 | ||
| 232 | clk_prepare_enable(clk[emi_ahb]); | 228 | clk_prepare_enable(clk[emi_ahb]); |
| 233 | 229 | ||
| 234 | /* Clock source for gpt must be derived from AHB */ | 230 | /* Clock source for gpt must be derived from AHB */ |
| 235 | clk_set_parent(clk[per5_sel], clk[ahb]); | 231 | clk_set_parent(clk[per5_sel], clk[ahb]); |
| 236 | 232 | ||
| 237 | clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); | ||
| 238 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); | ||
| 239 | |||
| 240 | /* | 233 | /* |
| 241 | * Let's initially set up CLKO parent as ipg, since this configuration | 234 | * Let's initially set up CLKO parent as ipg, since this configuration |
| 242 | * is used on some imx25 board designs to clock the audio codec. | 235 | * is used on some imx25 board designs to clock the audio codec. |
| @@ -248,8 +241,14 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) | |||
| 248 | 241 | ||
| 249 | int __init mx25_clocks_init(void) | 242 | int __init mx25_clocks_init(void) |
| 250 | { | 243 | { |
| 251 | __mx25_clocks_init(24000000); | 244 | void __iomem *ccm; |
| 252 | 245 | ||
| 246 | ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K); | ||
| 247 | |||
| 248 | __mx25_clocks_init(24000000, ccm); | ||
| 249 | |||
| 250 | clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0"); | ||
| 251 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); | ||
| 253 | /* i.mx25 has the i.mx21 type uart */ | 252 | /* i.mx25 has the i.mx21 type uart */ |
| 254 | clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0"); | 253 | clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0"); |
| 255 | clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0"); | 254 | clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0"); |
| @@ -314,29 +313,27 @@ int __init mx25_clocks_init(void) | |||
| 314 | return 0; | 313 | return 0; |
| 315 | } | 314 | } |
| 316 | 315 | ||
| 317 | int __init mx25_clocks_init_dt(void) | 316 | static void __init mx25_clocks_init_dt(struct device_node *np) |
| 318 | { | 317 | { |
| 319 | struct device_node *np; | 318 | struct device_node *refnp; |
| 320 | unsigned long osc_rate = 24000000; | 319 | unsigned long osc_rate = 24000000; |
| 320 | void __iomem *ccm; | ||
| 321 | 321 | ||
| 322 | /* retrieve the freqency of fixed clocks from device tree */ | 322 | /* retrieve the freqency of fixed clocks from device tree */ |
| 323 | for_each_compatible_node(np, NULL, "fixed-clock") { | 323 | for_each_compatible_node(refnp, NULL, "fixed-clock") { |
| 324 | u32 rate; | 324 | u32 rate; |
| 325 | if (of_property_read_u32(np, "clock-frequency", &rate)) | 325 | if (of_property_read_u32(refnp, "clock-frequency", &rate)) |
| 326 | continue; | 326 | continue; |
| 327 | 327 | ||
| 328 | if (of_device_is_compatible(np, "fsl,imx-osc")) | 328 | if (of_device_is_compatible(refnp, "fsl,imx-osc")) |
| 329 | osc_rate = rate; | 329 | osc_rate = rate; |
| 330 | } | 330 | } |
| 331 | 331 | ||
| 332 | np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm"); | 332 | ccm = of_iomap(np, 0); |
| 333 | __mx25_clocks_init(osc_rate, ccm); | ||
| 334 | |||
| 333 | clk_data.clks = clk; | 335 | clk_data.clks = clk; |
| 334 | clk_data.clk_num = ARRAY_SIZE(clk); | 336 | clk_data.clk_num = ARRAY_SIZE(clk); |
| 335 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | 337 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
| 336 | |||
| 337 | __mx25_clocks_init(osc_rate); | ||
| 338 | |||
| 339 | mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt")); | ||
| 340 | |||
| 341 | return 0; | ||
| 342 | } | 338 | } |
| 339 | CLK_OF_DECLARE(imx25_ccm, "fsl,imx25-ccm", mx25_clocks_init_dt); | ||
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index 317a662626d6..ab6349ec23b9 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c | |||
| @@ -1,61 +1,36 @@ | |||
| 1 | #include <linux/clk.h> | 1 | #include <linux/clk.h> |
| 2 | #include <linux/io.h> | 2 | #include <linux/clk-provider.h> |
| 3 | #include <linux/module.h> | ||
| 4 | #include <linux/clkdev.h> | 3 | #include <linux/clkdev.h> |
| 5 | #include <linux/err.h> | 4 | #include <linux/err.h> |
| 6 | #include <linux/clk-provider.h> | ||
| 7 | #include <linux/of.h> | 5 | #include <linux/of.h> |
| 6 | #include <linux/of_address.h> | ||
| 7 | #include <dt-bindings/clock/imx27-clock.h> | ||
| 8 | 8 | ||
| 9 | #include "clk.h" | 9 | #include "clk.h" |
| 10 | #include "common.h" | 10 | #include "common.h" |
| 11 | #include "hardware.h" | 11 | #include "hardware.h" |
| 12 | 12 | ||
| 13 | #define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) | 13 | static void __iomem *ccm __initdata; |
| 14 | 14 | ||
| 15 | /* Register offsets */ | 15 | /* Register offsets */ |
| 16 | #define CCM_CSCR IO_ADDR_CCM(0x0) | 16 | #define CCM_CSCR (ccm + 0x00) |
| 17 | #define CCM_MPCTL0 IO_ADDR_CCM(0x4) | 17 | #define CCM_MPCTL0 (ccm + 0x04) |
| 18 | #define CCM_MPCTL1 IO_ADDR_CCM(0x8) | 18 | #define CCM_MPCTL1 (ccm + 0x08) |
| 19 | #define CCM_SPCTL0 IO_ADDR_CCM(0xc) | 19 | #define CCM_SPCTL0 (ccm + 0x0c) |
| 20 | #define CCM_SPCTL1 IO_ADDR_CCM(0x10) | 20 | #define CCM_SPCTL1 (ccm + 0x10) |
| 21 | #define CCM_OSC26MCTL IO_ADDR_CCM(0x14) | 21 | #define CCM_PCDR0 (ccm + 0x18) |
| 22 | #define CCM_PCDR0 IO_ADDR_CCM(0x18) | 22 | #define CCM_PCDR1 (ccm + 0x1c) |
| 23 | #define CCM_PCDR1 IO_ADDR_CCM(0x1c) | 23 | #define CCM_PCCR0 (ccm + 0x20) |
| 24 | #define CCM_PCCR0 IO_ADDR_CCM(0x20) | 24 | #define CCM_PCCR1 (ccm + 0x24) |
| 25 | #define CCM_PCCR1 IO_ADDR_CCM(0x24) | 25 | #define CCM_CCSR (ccm + 0x28) |
| 26 | #define CCM_CCSR IO_ADDR_CCM(0x28) | ||
| 27 | #define CCM_PMCTL IO_ADDR_CCM(0x2c) | ||
| 28 | #define CCM_PMCOUNT IO_ADDR_CCM(0x30) | ||
| 29 | #define CCM_WKGDCTL IO_ADDR_CCM(0x34) | ||
| 30 | |||
| 31 | #define CCM_CSCR_UPDATE_DIS (1 << 31) | ||
| 32 | #define CCM_CSCR_SSI2 (1 << 23) | ||
| 33 | #define CCM_CSCR_SSI1 (1 << 22) | ||
| 34 | #define CCM_CSCR_VPU (1 << 21) | ||
| 35 | #define CCM_CSCR_MSHC (1 << 20) | ||
| 36 | #define CCM_CSCR_SPLLRES (1 << 19) | ||
| 37 | #define CCM_CSCR_MPLLRES (1 << 18) | ||
| 38 | #define CCM_CSCR_SP (1 << 17) | ||
| 39 | #define CCM_CSCR_MCU (1 << 16) | ||
| 40 | #define CCM_CSCR_OSC26MDIV (1 << 4) | ||
| 41 | #define CCM_CSCR_OSC26M (1 << 3) | ||
| 42 | #define CCM_CSCR_FPM (1 << 2) | ||
| 43 | #define CCM_CSCR_SPEN (1 << 1) | ||
| 44 | #define CCM_CSCR_MPEN (1 << 0) | ||
| 45 | |||
| 46 | /* i.MX27 TO 2+ */ | ||
| 47 | #define CCM_CSCR_ARM_SRC (1 << 15) | ||
| 48 | |||
| 49 | #define CCM_SPCTL1_LF (1 << 15) | ||
| 50 | #define CCM_SPCTL1_BRMO (1 << 6) | ||
| 51 | 26 | ||
| 52 | static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; | 27 | static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; |
| 53 | static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; | 28 | static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; |
| 54 | static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", }; | 29 | static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", }; |
| 55 | static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", }; | 30 | static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", }; |
| 56 | static const char *clko_sel_clks[] = { | 31 | static const char *clko_sel_clks[] = { |
| 57 | "ckil", "fpm", "ckih", "ckih", | 32 | "ckil", "fpm", "ckih_gate", "ckih_gate", |
| 58 | "ckih", "mpll", "spll", "cpu_div", | 33 | "ckih_gate", "mpll", "spll", "cpu_div", |
| 59 | "ahb", "ipg", "per1_div", "per2_div", | 34 | "ahb", "ipg", "per1_div", "per2_div", |
| 60 | "per3_div", "per4_div", "ssi1_div", "ssi2_div", | 35 | "per3_div", "per4_div", "ssi1_div", "ssi2_div", |
| 61 | "nfc_div", "mshc_div", "vpu_div", "60m", | 36 | "nfc_div", "mshc_div", "vpu_div", "60m", |
| @@ -64,239 +39,220 @@ static const char *clko_sel_clks[] = { | |||
| 64 | 39 | ||
| 65 | static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; | 40 | static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; |
| 66 | 41 | ||
| 67 | enum mx27_clks { | 42 | static struct clk *clk[IMX27_CLK_MAX]; |
| 68 | dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, | ||
| 69 | per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel, | ||
| 70 | clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div, | ||
| 71 | clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate, | ||
| 72 | sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate, | ||
| 73 | rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate, | ||
| 74 | kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate, | ||
| 75 | gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate, | ||
| 76 | gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate, | ||
| 77 | emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate, | ||
| 78 | cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate, | ||
| 79 | vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate, | ||
| 80 | usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate, | ||
| 81 | vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate, | ||
| 82 | csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate, | ||
| 83 | uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate, | ||
| 84 | uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel, | ||
| 85 | mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate, | ||
| 86 | rtic_ahb_gate, mshc_baud_gate, clk_max | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct clk *clk[clk_max]; | ||
| 90 | static struct clk_onecell_data clk_data; | 43 | static struct clk_onecell_data clk_data; |
| 91 | 44 | ||
| 92 | int __init mx27_clocks_init(unsigned long fref) | 45 | static void __init _mx27_clocks_init(unsigned long fref) |
| 93 | { | 46 | { |
| 94 | int i; | 47 | BUG_ON(!ccm); |
| 95 | struct device_node *np; | ||
| 96 | |||
| 97 | clk[dummy] = imx_clk_fixed("dummy", 0); | ||
| 98 | clk[ckih] = imx_clk_fixed("ckih", fref); | ||
| 99 | clk[ckil] = imx_clk_fixed("ckil", 32768); | ||
| 100 | clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); | ||
| 101 | clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3); | ||
| 102 | 48 | ||
| 103 | clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, | 49 | clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
| 104 | mpll_osc_sel_clks, | 50 | clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); |
| 105 | ARRAY_SIZE(mpll_osc_sel_clks)); | 51 | clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); |
| 106 | clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, | 52 | clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); |
| 107 | ARRAY_SIZE(mpll_sel_clks)); | 53 | clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); |
| 108 | clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); | 54 | clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); |
| 109 | clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0); | 55 | clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); |
| 110 | clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); | 56 | clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); |
| 111 | clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); | 57 | clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); |
| 58 | clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih_gate", CCM_SPCTL0); | ||
| 59 | clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); | ||
| 60 | clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); | ||
| 112 | 61 | ||
| 113 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { | 62 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { |
| 114 | clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); | 63 | clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); |
| 115 | clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); | 64 | clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); |
| 116 | } else { | 65 | } else { |
| 117 | clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); | 66 | clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); |
| 118 | clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); | 67 | clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); |
| 119 | } | 68 | } |
| 120 | 69 | ||
| 121 | clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); | 70 | clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); |
| 122 | clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); | 71 | clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); |
| 123 | clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); | 72 | clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); |
| 124 | clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); | 73 | clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); |
| 125 | clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); | 74 | clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); |
| 126 | clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); | 75 | clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); |
| 127 | clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); | 76 | clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); |
| 128 | clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); | 77 | clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); |
| 129 | clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); | 78 | clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); |
| 130 | clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); | 79 | clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); |
| 131 | clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); | 80 | clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); |
| 81 | |||
| 132 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) | 82 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
| 133 | clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2); | 83 | clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2); |
| 134 | else | 84 | else |
| 135 | clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3); | 85 | clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3); |
| 136 | clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3); | ||
| 137 | clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | ||
| 138 | clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | ||
| 139 | clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); | ||
| 140 | clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); | ||
| 141 | clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0); | ||
| 142 | clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); | ||
| 143 | clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); | ||
| 144 | clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); | ||
| 145 | clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); | ||
| 146 | clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); | ||
| 147 | clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); | ||
| 148 | clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); | ||
| 149 | clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); | ||
| 150 | clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8); | ||
| 151 | clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); | ||
| 152 | clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); | ||
| 153 | clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); | ||
| 154 | clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13); | ||
| 155 | clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); | ||
| 156 | clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); | ||
| 157 | clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); | ||
| 158 | clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17); | ||
| 159 | clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18); | ||
| 160 | clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19); | ||
| 161 | clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20); | ||
| 162 | clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21); | ||
| 163 | clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22); | ||
| 164 | clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23); | ||
| 165 | clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24); | ||
| 166 | clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25); | ||
| 167 | clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26); | ||
| 168 | clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27); | ||
| 169 | clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28); | ||
| 170 | clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); | ||
| 171 | clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); | ||
| 172 | clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); | ||
| 173 | clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2); | ||
| 174 | clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3); | ||
| 175 | clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4); | ||
| 176 | clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5); | ||
| 177 | clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6); | ||
| 178 | clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7); | ||
| 179 | clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8); | ||
| 180 | clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9); | ||
| 181 | clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10); | ||
| 182 | clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); | ||
| 183 | clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); | ||
| 184 | clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); | ||
| 185 | clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14); | ||
| 186 | clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15); | ||
| 187 | clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16); | ||
| 188 | clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17); | ||
| 189 | clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18); | ||
| 190 | clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19); | ||
| 191 | clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20); | ||
| 192 | clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21); | ||
| 193 | clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22); | ||
| 194 | clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23); | ||
| 195 | clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24); | ||
| 196 | clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25); | ||
| 197 | clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26); | ||
| 198 | clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27); | ||
| 199 | clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28); | ||
| 200 | clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29); | ||
| 201 | clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); | ||
| 202 | clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); | ||
| 203 | 86 | ||
| 204 | for (i = 0; i < ARRAY_SIZE(clk); i++) | 87 | clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3); |
| 205 | if (IS_ERR(clk[i])) | 88 | clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); |
| 206 | pr_err("i.MX27 clk %d: register failed with %ld\n", | 89 | clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); |
| 207 | i, PTR_ERR(clk[i])); | 90 | clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); |
| 91 | clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); | ||
| 92 | clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0); | ||
| 93 | clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); | ||
| 94 | clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); | ||
| 95 | clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); | ||
| 96 | clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); | ||
| 97 | clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); | ||
| 98 | clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); | ||
| 99 | clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); | ||
| 100 | clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); | ||
| 101 | clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8); | ||
| 102 | clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); | ||
| 103 | clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); | ||
| 104 | clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); | ||
| 105 | clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13); | ||
| 106 | clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); | ||
| 107 | clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); | ||
| 108 | clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); | ||
| 109 | clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17); | ||
| 110 | clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18); | ||
| 111 | clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19); | ||
| 112 | clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20); | ||
| 113 | clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21); | ||
| 114 | clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22); | ||
| 115 | clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23); | ||
| 116 | clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24); | ||
| 117 | clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25); | ||
| 118 | clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26); | ||
| 119 | clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27); | ||
| 120 | clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28); | ||
| 121 | clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); | ||
| 122 | clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); | ||
| 123 | clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); | ||
| 124 | clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2); | ||
| 125 | clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3); | ||
| 126 | clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4); | ||
| 127 | clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5); | ||
| 128 | clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6); | ||
| 129 | clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7); | ||
| 130 | clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8); | ||
| 131 | clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9); | ||
| 132 | clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10); | ||
| 133 | clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); | ||
| 134 | clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); | ||
| 135 | clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); | ||
| 136 | clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14); | ||
| 137 | clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15); | ||
| 138 | clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16); | ||
| 139 | clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17); | ||
| 140 | clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18); | ||
| 141 | clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19); | ||
| 142 | clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20); | ||
| 143 | clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21); | ||
| 144 | clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22); | ||
| 145 | clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23); | ||
| 146 | clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24); | ||
| 147 | clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25); | ||
| 148 | clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26); | ||
| 149 | clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27); | ||
| 150 | clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28); | ||
| 151 | clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29); | ||
| 152 | clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); | ||
| 153 | clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); | ||
| 208 | 154 | ||
| 209 | np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); | 155 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
| 210 | if (np) { | ||
| 211 | clk_data.clks = clk; | ||
| 212 | clk_data.clk_num = ARRAY_SIZE(clk); | ||
| 213 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
| 214 | } | ||
| 215 | 156 | ||
| 216 | clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); | 157 | clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0"); |
| 217 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0"); | ||
| 218 | clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); | ||
| 219 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1"); | ||
| 220 | clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); | ||
| 221 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2"); | ||
| 222 | clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); | ||
| 223 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3"); | ||
| 224 | clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4"); | ||
| 225 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4"); | ||
| 226 | clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5"); | ||
| 227 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5"); | ||
| 228 | clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0"); | ||
| 229 | clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0"); | ||
| 230 | clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0"); | ||
| 231 | clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0"); | ||
| 232 | clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1"); | ||
| 233 | clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1"); | ||
| 234 | clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2"); | ||
| 235 | clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2"); | ||
| 236 | clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0"); | ||
| 237 | clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0"); | ||
| 238 | clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1"); | ||
| 239 | clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1"); | ||
| 240 | clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2"); | ||
| 241 | clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2"); | ||
| 242 | clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0"); | ||
| 243 | clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0"); | ||
| 244 | clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0"); | ||
| 245 | clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0"); | ||
| 246 | clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0"); | ||
| 247 | clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); | ||
| 248 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27"); | ||
| 249 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27"); | ||
| 250 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); | ||
| 251 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0"); | ||
| 252 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0"); | ||
| 253 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); | ||
| 254 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1"); | ||
| 255 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1"); | ||
| 256 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); | ||
| 257 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2"); | ||
| 258 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2"); | ||
| 259 | clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); | ||
| 260 | clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); | ||
| 261 | clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0"); | ||
| 262 | clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0"); | ||
| 263 | clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0"); | ||
| 264 | clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma"); | ||
| 265 | clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma"); | ||
| 266 | clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0"); | ||
| 267 | clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0"); | ||
| 268 | clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0"); | ||
| 269 | clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0"); | ||
| 270 | clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1"); | ||
| 271 | clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0"); | ||
| 272 | clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad"); | ||
| 273 | clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0"); | ||
| 274 | clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0"); | ||
| 275 | clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0"); | ||
| 276 | clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0"); | ||
| 277 | clk_register_clkdev(clk[cpu_div], NULL, "cpu0"); | ||
| 278 | 158 | ||
| 279 | mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); | 159 | clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); |
| 280 | |||
| 281 | clk_prepare_enable(clk[emi_ahb_gate]); | ||
| 282 | 160 | ||
| 283 | imx_print_silicon_rev("i.MX27", mx27_revision()); | 161 | imx_print_silicon_rev("i.MX27", mx27_revision()); |
| 162 | } | ||
| 163 | |||
| 164 | int __init mx27_clocks_init(unsigned long fref) | ||
| 165 | { | ||
| 166 | ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K); | ||
| 167 | |||
| 168 | _mx27_clocks_init(fref); | ||
| 169 | |||
| 170 | clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); | ||
| 171 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0"); | ||
| 172 | clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); | ||
| 173 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1"); | ||
| 174 | clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); | ||
| 175 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2"); | ||
| 176 | clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); | ||
| 177 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3"); | ||
| 178 | clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); | ||
| 179 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4"); | ||
| 180 | clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5"); | ||
| 181 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5"); | ||
| 182 | clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); | ||
| 183 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0"); | ||
| 184 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0"); | ||
| 185 | clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0"); | ||
| 186 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1"); | ||
| 187 | clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1"); | ||
| 188 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2"); | ||
| 189 | clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2"); | ||
| 190 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0"); | ||
| 191 | clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0"); | ||
| 192 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1"); | ||
| 193 | clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1"); | ||
| 194 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2"); | ||
| 195 | clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2"); | ||
| 196 | clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0"); | ||
| 197 | clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); | ||
| 198 | clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0"); | ||
| 199 | clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0"); | ||
| 200 | clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0"); | ||
| 201 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27"); | ||
| 202 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27"); | ||
| 203 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27"); | ||
| 204 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0"); | ||
| 205 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0"); | ||
| 206 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0"); | ||
| 207 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1"); | ||
| 208 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1"); | ||
| 209 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1"); | ||
| 210 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2"); | ||
| 211 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2"); | ||
| 212 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2"); | ||
| 213 | clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0"); | ||
| 214 | clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1"); | ||
| 215 | clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0"); | ||
| 216 | clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0"); | ||
| 217 | clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0"); | ||
| 218 | clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma"); | ||
| 219 | clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma"); | ||
| 220 | clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0"); | ||
| 221 | clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0"); | ||
| 222 | clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0"); | ||
| 223 | clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0"); | ||
| 224 | clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1"); | ||
| 225 | clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0"); | ||
| 226 | clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad"); | ||
| 227 | clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0"); | ||
| 228 | clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0"); | ||
| 229 | clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0"); | ||
| 230 | clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); | ||
| 231 | |||
| 232 | mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); | ||
| 284 | 233 | ||
| 285 | return 0; | 234 | return 0; |
| 286 | } | 235 | } |
| 287 | 236 | ||
| 288 | int __init mx27_clocks_init_dt(void) | 237 | static void __init mx27_clocks_init_dt(struct device_node *np) |
| 289 | { | 238 | { |
| 290 | struct device_node *np; | 239 | struct device_node *refnp; |
| 291 | u32 fref = 26000000; /* default */ | 240 | u32 fref = 26000000; /* default */ |
| 292 | 241 | ||
| 293 | for_each_compatible_node(np, NULL, "fixed-clock") { | 242 | for_each_compatible_node(refnp, NULL, "fixed-clock") { |
| 294 | if (!of_device_is_compatible(np, "fsl,imx-osc26m")) | 243 | if (!of_device_is_compatible(refnp, "fsl,imx-osc26m")) |
| 295 | continue; | 244 | continue; |
| 296 | 245 | ||
| 297 | if (!of_property_read_u32(np, "clock-frequency", &fref)) | 246 | if (!of_property_read_u32(refnp, "clock-frequency", &fref)) |
| 298 | break; | 247 | break; |
| 299 | } | 248 | } |
| 300 | 249 | ||
| 301 | return mx27_clocks_init(fref); | 250 | ccm = of_iomap(np, 0); |
| 251 | |||
| 252 | _mx27_clocks_init(fref); | ||
| 253 | |||
| 254 | clk_data.clks = clk; | ||
| 255 | clk_data.clk_num = ARRAY_SIZE(clk); | ||
| 256 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
| 302 | } | 257 | } |
| 258 | CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt); | ||
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index 4a9de0835eb1..286ef422cebc 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c | |||
| @@ -51,7 +51,6 @@ static struct clk_onecell_data clk_data; | |||
| 51 | int __init mx31_clocks_init(unsigned long fref) | 51 | int __init mx31_clocks_init(unsigned long fref) |
| 52 | { | 52 | { |
| 53 | void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); | 53 | void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); |
| 54 | int i; | ||
| 55 | struct device_node *np; | 54 | struct device_node *np; |
| 56 | 55 | ||
| 57 | clk[dummy] = imx_clk_fixed("dummy", 0); | 56 | clk[dummy] = imx_clk_fixed("dummy", 0); |
| @@ -114,10 +113,7 @@ int __init mx31_clocks_init(unsigned long fref) | |||
| 114 | clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); | 113 | clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); |
| 115 | clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); | 114 | clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); |
| 116 | 115 | ||
| 117 | for (i = 0; i < ARRAY_SIZE(clk); i++) | 116 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
| 118 | if (IS_ERR(clk[i])) | ||
| 119 | pr_err("imx31 clk %d: register failed with %ld\n", | ||
| 120 | i, PTR_ERR(clk[i])); | ||
| 121 | 117 | ||
| 122 | np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm"); | 118 | np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm"); |
| 123 | 119 | ||
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index 71c86a2f856d..a0d2b57fd376 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c | |||
| @@ -75,7 +75,6 @@ int __init mx35_clocks_init(void) | |||
| 75 | u32 pdr0, consumer_sel, hsp_sel; | 75 | u32 pdr0, consumer_sel, hsp_sel; |
| 76 | struct arm_ahb_div *aad; | 76 | struct arm_ahb_div *aad; |
| 77 | unsigned char *hsp_div; | 77 | unsigned char *hsp_div; |
| 78 | u32 i; | ||
| 79 | 78 | ||
| 80 | pdr0 = __raw_readl(base + MXC_CCM_PDR0); | 79 | pdr0 = __raw_readl(base + MXC_CCM_PDR0); |
| 81 | consumer_sel = (pdr0 >> 16) & 0xf; | 80 | consumer_sel = (pdr0 >> 16) & 0xf; |
| @@ -200,10 +199,7 @@ int __init mx35_clocks_init(void) | |||
| 200 | clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); | 199 | clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); |
| 201 | clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); | 200 | clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); |
| 202 | 201 | ||
| 203 | for (i = 0; i < ARRAY_SIZE(clk); i++) | 202 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
| 204 | if (IS_ERR(clk[i])) | ||
| 205 | pr_err("i.MX35 clk %d: register failed with %ld\n", | ||
| 206 | i, PTR_ERR(clk[i])); | ||
| 207 | 203 | ||
| 208 | clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); | 204 | clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); |
| 209 | clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); | 205 | clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); |
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 21d2b111c83d..72d65214223e 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c | |||
| @@ -18,11 +18,54 @@ | |||
| 18 | #include <linux/of_irq.h> | 18 | #include <linux/of_irq.h> |
| 19 | #include <dt-bindings/clock/imx5-clock.h> | 19 | #include <dt-bindings/clock/imx5-clock.h> |
| 20 | 20 | ||
| 21 | #include "crm-regs-imx5.h" | ||
| 22 | #include "clk.h" | 21 | #include "clk.h" |
| 23 | #include "common.h" | 22 | #include "common.h" |
| 24 | #include "hardware.h" | 23 | #include "hardware.h" |
| 25 | 24 | ||
| 25 | #define MX51_DPLL1_BASE 0x83f80000 | ||
| 26 | #define MX51_DPLL2_BASE 0x83f84000 | ||
| 27 | #define MX51_DPLL3_BASE 0x83f88000 | ||
| 28 | |||
| 29 | #define MX53_DPLL1_BASE 0x63f80000 | ||
| 30 | #define MX53_DPLL2_BASE 0x63f84000 | ||
| 31 | #define MX53_DPLL3_BASE 0x63f88000 | ||
| 32 | #define MX53_DPLL4_BASE 0x63f8c000 | ||
| 33 | |||
| 34 | #define MXC_CCM_CCR (ccm_base + 0x00) | ||
| 35 | #define MXC_CCM_CCDR (ccm_base + 0x04) | ||
| 36 | #define MXC_CCM_CSR (ccm_base + 0x08) | ||
| 37 | #define MXC_CCM_CCSR (ccm_base + 0x0c) | ||
| 38 | #define MXC_CCM_CACRR (ccm_base + 0x10) | ||
| 39 | #define MXC_CCM_CBCDR (ccm_base + 0x14) | ||
| 40 | #define MXC_CCM_CBCMR (ccm_base + 0x18) | ||
| 41 | #define MXC_CCM_CSCMR1 (ccm_base + 0x1c) | ||
| 42 | #define MXC_CCM_CSCMR2 (ccm_base + 0x20) | ||
| 43 | #define MXC_CCM_CSCDR1 (ccm_base + 0x24) | ||
| 44 | #define MXC_CCM_CS1CDR (ccm_base + 0x28) | ||
| 45 | #define MXC_CCM_CS2CDR (ccm_base + 0x2c) | ||
| 46 | #define MXC_CCM_CDCDR (ccm_base + 0x30) | ||
| 47 | #define MXC_CCM_CHSCDR (ccm_base + 0x34) | ||
| 48 | #define MXC_CCM_CSCDR2 (ccm_base + 0x38) | ||
| 49 | #define MXC_CCM_CSCDR3 (ccm_base + 0x3c) | ||
| 50 | #define MXC_CCM_CSCDR4 (ccm_base + 0x40) | ||
| 51 | #define MXC_CCM_CWDR (ccm_base + 0x44) | ||
| 52 | #define MXC_CCM_CDHIPR (ccm_base + 0x48) | ||
| 53 | #define MXC_CCM_CDCR (ccm_base + 0x4c) | ||
| 54 | #define MXC_CCM_CTOR (ccm_base + 0x50) | ||
| 55 | #define MXC_CCM_CLPCR (ccm_base + 0x54) | ||
| 56 | #define MXC_CCM_CISR (ccm_base + 0x58) | ||
| 57 | #define MXC_CCM_CIMR (ccm_base + 0x5c) | ||
| 58 | #define MXC_CCM_CCOSR (ccm_base + 0x60) | ||
| 59 | #define MXC_CCM_CGPR (ccm_base + 0x64) | ||
| 60 | #define MXC_CCM_CCGR0 (ccm_base + 0x68) | ||
| 61 | #define MXC_CCM_CCGR1 (ccm_base + 0x6c) | ||
| 62 | #define MXC_CCM_CCGR2 (ccm_base + 0x70) | ||
| 63 | #define MXC_CCM_CCGR3 (ccm_base + 0x74) | ||
| 64 | #define MXC_CCM_CCGR4 (ccm_base + 0x78) | ||
| 65 | #define MXC_CCM_CCGR5 (ccm_base + 0x7c) | ||
| 66 | #define MXC_CCM_CCGR6 (ccm_base + 0x80) | ||
| 67 | #define MXC_CCM_CCGR7 (ccm_base + 0x84) | ||
| 68 | |||
| 26 | /* Low-power Audio Playback Mode clock */ | 69 | /* Low-power Audio Playback Mode clock */ |
| 27 | static const char *lp_apm_sel[] = { "osc", }; | 70 | static const char *lp_apm_sel[] = { "osc", }; |
| 28 | 71 | ||
| @@ -86,17 +129,15 @@ static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; | |||
| 86 | static struct clk *clk[IMX5_CLK_END]; | 129 | static struct clk *clk[IMX5_CLK_END]; |
| 87 | static struct clk_onecell_data clk_data; | 130 | static struct clk_onecell_data clk_data; |
| 88 | 131 | ||
| 89 | static void __init mx5_clocks_common_init(unsigned long rate_ckil, | 132 | static void __init mx5_clocks_common_init(void __iomem *ccm_base) |
| 90 | unsigned long rate_osc, unsigned long rate_ckih1, | ||
| 91 | unsigned long rate_ckih2) | ||
| 92 | { | 133 | { |
| 93 | int i; | 134 | imx5_pm_set_ccm_base(ccm_base); |
| 94 | 135 | ||
| 95 | clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); | 136 | clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
| 96 | clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil); | 137 | clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); |
| 97 | clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc); | 138 | clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); |
| 98 | clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); | 139 | clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0); |
| 99 | clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); | 140 | clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0); |
| 100 | 141 | ||
| 101 | clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, | 142 | clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, |
| 102 | periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); | 143 | periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); |
| @@ -244,58 +285,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, | |||
| 244 | clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); | 285 | clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); |
| 245 | clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1); | 286 | clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1); |
| 246 | 287 | ||
| 247 | for (i = 0; i < ARRAY_SIZE(clk); i++) | ||
| 248 | if (IS_ERR(clk[i])) | ||
| 249 | pr_err("i.MX5 clk %d: register failed with %ld\n", | ||
| 250 | i, PTR_ERR(clk[i])); | ||
| 251 | |||
| 252 | clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0"); | ||
| 253 | clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0"); | ||
| 254 | clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0"); | ||
| 255 | clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); | ||
| 256 | clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1"); | ||
| 257 | clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); | ||
| 258 | clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2"); | ||
| 259 | clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); | ||
| 260 | clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3"); | ||
| 261 | clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); | ||
| 262 | clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4"); | ||
| 263 | clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); | ||
| 264 | clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0"); | ||
| 265 | clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0"); | ||
| 266 | clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1"); | ||
| 267 | clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1"); | ||
| 268 | clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2"); | ||
| 269 | clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0"); | ||
| 270 | clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1"); | ||
| 271 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0"); | ||
| 272 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0"); | ||
| 273 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0"); | ||
| 274 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1"); | ||
| 275 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1"); | ||
| 276 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1"); | ||
| 277 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2"); | ||
| 278 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2"); | ||
| 279 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2"); | ||
| 280 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51"); | ||
| 281 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51"); | ||
| 282 | clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51"); | ||
| 283 | clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand"); | ||
| 284 | clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0"); | ||
| 285 | clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1"); | ||
| 286 | clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2"); | ||
| 287 | clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma"); | ||
| 288 | clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0"); | 288 | clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0"); |
| 289 | clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL); | ||
| 290 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0"); | ||
| 291 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1"); | ||
| 292 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad"); | ||
| 293 | clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0"); | ||
| 294 | clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL); | 289 | clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL); |
| 295 | clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0"); | ||
| 296 | clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0"); | ||
| 297 | clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1"); | ||
| 298 | clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1"); | ||
| 299 | 290 | ||
| 300 | /* Set SDHC parents to be PLL2 */ | 291 | /* Set SDHC parents to be PLL2 */ |
| 301 | clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); | 292 | clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); |
| @@ -322,12 +313,26 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, | |||
| 322 | 313 | ||
| 323 | static void __init mx50_clocks_init(struct device_node *np) | 314 | static void __init mx50_clocks_init(struct device_node *np) |
| 324 | { | 315 | { |
| 316 | void __iomem *ccm_base; | ||
| 317 | void __iomem *pll_base; | ||
| 325 | unsigned long r; | 318 | unsigned long r; |
| 326 | int i; | ||
| 327 | 319 | ||
| 328 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); | 320 | pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); |
| 329 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); | 321 | WARN_ON(!pll_base); |
| 330 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); | 322 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); |
| 323 | |||
| 324 | pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K); | ||
| 325 | WARN_ON(!pll_base); | ||
| 326 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); | ||
| 327 | |||
| 328 | pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K); | ||
| 329 | WARN_ON(!pll_base); | ||
| 330 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); | ||
| 331 | |||
| 332 | ccm_base = of_iomap(np, 0); | ||
| 333 | WARN_ON(!ccm_base); | ||
| 334 | |||
| 335 | mx5_clocks_common_init(ccm_base); | ||
| 331 | 336 | ||
| 332 | clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, | 337 | clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, |
| 333 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); | 338 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); |
| @@ -349,17 +354,12 @@ static void __init mx50_clocks_init(struct device_node *np) | |||
| 349 | clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); | 354 | clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); |
| 350 | clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); | 355 | clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); |
| 351 | 356 | ||
| 352 | for (i = 0; i < ARRAY_SIZE(clk); i++) | 357 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
| 353 | if (IS_ERR(clk[i])) | ||
| 354 | pr_err("i.MX50 clk %d: register failed with %ld\n", | ||
| 355 | i, PTR_ERR(clk[i])); | ||
| 356 | 358 | ||
| 357 | clk_data.clks = clk; | 359 | clk_data.clks = clk; |
| 358 | clk_data.clk_num = ARRAY_SIZE(clk); | 360 | clk_data.clk_num = ARRAY_SIZE(clk); |
| 359 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | 361 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
| 360 | 362 | ||
| 361 | mx5_clocks_common_init(0, 0, 0, 0); | ||
| 362 | |||
| 363 | /* set SDHC root clock to 200MHZ*/ | 363 | /* set SDHC root clock to 200MHZ*/ |
| 364 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); | 364 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); |
| 365 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); | 365 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); |
| @@ -370,21 +370,32 @@ static void __init mx50_clocks_init(struct device_node *np) | |||
| 370 | 370 | ||
| 371 | r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); | 371 | r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); |
| 372 | clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); | 372 | clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); |
| 373 | |||
| 374 | mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt")); | ||
| 375 | } | 373 | } |
| 376 | CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); | 374 | CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); |
| 377 | 375 | ||
| 378 | int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, | 376 | static void __init mx51_clocks_init(struct device_node *np) |
| 379 | unsigned long rate_ckih1, unsigned long rate_ckih2) | ||
| 380 | { | 377 | { |
| 381 | int i; | 378 | void __iomem *ccm_base; |
| 379 | void __iomem *pll_base; | ||
| 382 | u32 val; | 380 | u32 val; |
| 383 | struct device_node *np; | ||
| 384 | 381 | ||
| 385 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); | 382 | pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K); |
| 386 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); | 383 | WARN_ON(!pll_base); |
| 387 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE); | 384 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); |
| 385 | |||
| 386 | pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K); | ||
| 387 | WARN_ON(!pll_base); | ||
| 388 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); | ||
| 389 | |||
| 390 | pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K); | ||
| 391 | WARN_ON(!pll_base); | ||
| 392 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); | ||
| 393 | |||
| 394 | ccm_base = of_iomap(np, 0); | ||
| 395 | WARN_ON(!ccm_base); | ||
| 396 | |||
| 397 | mx5_clocks_common_init(ccm_base); | ||
| 398 | |||
| 388 | clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, | 399 | clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, |
| 389 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); | 400 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); |
| 390 | clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, | 401 | clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, |
| @@ -417,35 +428,12 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, | |||
| 417 | mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); | 428 | mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); |
| 418 | clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); | 429 | clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); |
| 419 | 430 | ||
| 420 | for (i = 0; i < ARRAY_SIZE(clk); i++) | 431 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
| 421 | if (IS_ERR(clk[i])) | ||
| 422 | pr_err("i.MX51 clk %d: register failed with %ld\n", | ||
| 423 | i, PTR_ERR(clk[i])); | ||
| 424 | 432 | ||
| 425 | np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm"); | ||
| 426 | clk_data.clks = clk; | 433 | clk_data.clks = clk; |
| 427 | clk_data.clk_num = ARRAY_SIZE(clk); | 434 | clk_data.clk_num = ARRAY_SIZE(clk); |
| 428 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | 435 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
| 429 | 436 | ||
| 430 | mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); | ||
| 431 | |||
| 432 | clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2"); | ||
| 433 | clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL); | ||
| 434 | clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0"); | ||
| 435 | clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0"); | ||
| 436 | clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0"); | ||
| 437 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0"); | ||
| 438 | clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0"); | ||
| 439 | clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1"); | ||
| 440 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1"); | ||
| 441 | clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1"); | ||
| 442 | clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2"); | ||
| 443 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2"); | ||
| 444 | clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2"); | ||
| 445 | clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3"); | ||
| 446 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3"); | ||
| 447 | clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3"); | ||
| 448 | |||
| 449 | /* set the usboh3 parent to pll2_sw */ | 437 | /* set the usboh3 parent to pll2_sw */ |
| 450 | clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); | 438 | clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); |
| 451 | 439 | ||
| @@ -453,9 +441,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, | |||
| 453 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); | 441 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); |
| 454 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); | 442 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); |
| 455 | 443 | ||
| 456 | /* System timer */ | ||
| 457 | mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT); | ||
| 458 | |||
| 459 | clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); | 444 | clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); |
| 460 | imx_print_silicon_rev("i.MX51", mx51_revision()); | 445 | imx_print_silicon_rev("i.MX51", mx51_revision()); |
| 461 | clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); | 446 | clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); |
| @@ -474,25 +459,35 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, | |||
| 474 | val = readl(MXC_CCM_CLPCR); | 459 | val = readl(MXC_CCM_CLPCR); |
| 475 | val |= 1 << 23; | 460 | val |= 1 << 23; |
| 476 | writel(val, MXC_CCM_CLPCR); | 461 | writel(val, MXC_CCM_CLPCR); |
| 477 | |||
| 478 | return 0; | ||
| 479 | } | ||
| 480 | |||
| 481 | static void __init mx51_clocks_init_dt(struct device_node *np) | ||
| 482 | { | ||
| 483 | mx51_clocks_init(0, 0, 0, 0); | ||
| 484 | } | 462 | } |
| 485 | CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); | 463 | CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init); |
| 486 | 464 | ||
| 487 | static void __init mx53_clocks_init(struct device_node *np) | 465 | static void __init mx53_clocks_init(struct device_node *np) |
| 488 | { | 466 | { |
| 489 | int i; | 467 | void __iomem *ccm_base; |
| 468 | void __iomem *pll_base; | ||
| 490 | unsigned long r; | 469 | unsigned long r; |
| 491 | 470 | ||
| 492 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); | 471 | pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); |
| 493 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); | 472 | WARN_ON(!pll_base); |
| 494 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); | 473 | clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); |
| 495 | clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE); | 474 | |
| 475 | pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K); | ||
| 476 | WARN_ON(!pll_base); | ||
| 477 | clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); | ||
| 478 | |||
| 479 | pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K); | ||
| 480 | WARN_ON(!pll_base); | ||
| 481 | clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); | ||
| 482 | |||
| 483 | pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K); | ||
| 484 | WARN_ON(!pll_base); | ||
| 485 | clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base); | ||
| 486 | |||
| 487 | ccm_base = of_iomap(np, 0); | ||
| 488 | WARN_ON(!ccm_base); | ||
| 489 | |||
| 490 | mx5_clocks_common_init(ccm_base); | ||
| 496 | 491 | ||
| 497 | clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, | 492 | clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, |
| 498 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); | 493 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); |
| @@ -543,33 +538,12 @@ static void __init mx53_clocks_init(struct device_node *np) | |||
| 543 | clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, | 538 | clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, |
| 544 | mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); | 539 | mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); |
| 545 | 540 | ||
| 546 | for (i = 0; i < ARRAY_SIZE(clk); i++) | 541 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
| 547 | if (IS_ERR(clk[i])) | ||
| 548 | pr_err("i.MX53 clk %d: register failed with %ld\n", | ||
| 549 | i, PTR_ERR(clk[i])); | ||
| 550 | 542 | ||
| 551 | clk_data.clks = clk; | 543 | clk_data.clks = clk; |
| 552 | clk_data.clk_num = ARRAY_SIZE(clk); | 544 | clk_data.clk_num = ARRAY_SIZE(clk); |
| 553 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | 545 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
| 554 | 546 | ||
| 555 | mx5_clocks_common_init(0, 0, 0, 0); | ||
| 556 | |||
| 557 | clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2"); | ||
| 558 | clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0"); | ||
| 559 | clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0"); | ||
| 560 | clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0"); | ||
| 561 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0"); | ||
| 562 | clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0"); | ||
| 563 | clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1"); | ||
| 564 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1"); | ||
| 565 | clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1"); | ||
| 566 | clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2"); | ||
| 567 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2"); | ||
| 568 | clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2"); | ||
| 569 | clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3"); | ||
| 570 | clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3"); | ||
| 571 | clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3"); | ||
| 572 | |||
| 573 | /* set SDHC root clock to 200MHZ*/ | 547 | /* set SDHC root clock to 200MHZ*/ |
| 574 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); | 548 | clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); |
| 575 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); | 549 | clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); |
| @@ -583,7 +557,5 @@ static void __init mx53_clocks_init(struct device_node *np) | |||
| 583 | 557 | ||
| 584 | r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); | 558 | r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); |
| 585 | clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); | 559 | clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); |
| 586 | |||
| 587 | mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt")); | ||
| 588 | } | 560 | } |
| 589 | CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); | 561 | CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); |
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 8e795dea02ec..6cceb7765c14 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/of.h> | 19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> | 20 | #include <linux/of_address.h> |
| 21 | #include <linux/of_irq.h> | 21 | #include <linux/of_irq.h> |
| 22 | #include <dt-bindings/clock/imx6qdl-clock.h> | ||
| 22 | 23 | ||
| 23 | #include "clk.h" | 24 | #include "clk.h" |
| 24 | #include "common.h" | 25 | #include "common.h" |
| @@ -70,51 +71,16 @@ static const char *cko_sels[] = { "cko1", "cko2", }; | |||
| 70 | static const char *lvds_sels[] = { | 71 | static const char *lvds_sels[] = { |
| 71 | "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", | 72 | "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", |
| 72 | "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", | 73 | "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", |
| 73 | "pcie_ref", "sata_ref", | 74 | "pcie_ref_125m", "sata_ref_100m", |
| 74 | }; | 75 | }; |
| 75 | 76 | ||
| 76 | enum mx6q_clks { | 77 | static struct clk *clk[IMX6QDL_CLK_END]; |
| 77 | dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, | ||
| 78 | pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m, | ||
| 79 | pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw, | ||
| 80 | periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel, | ||
| 81 | esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel, | ||
| 82 | gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel, | ||
| 83 | ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel, | ||
| 84 | ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, | ||
| 85 | ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel, | ||
| 86 | usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel, | ||
| 87 | emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2, | ||
| 88 | periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf, | ||
| 89 | asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root, | ||
| 90 | gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf, | ||
| 91 | ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre, | ||
| 92 | ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf, | ||
| 93 | ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf, | ||
| 94 | usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf, | ||
| 95 | emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf, | ||
| 96 | mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial, | ||
| 97 | can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet, | ||
| 98 | esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, | ||
| 99 | hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, | ||
| 100 | ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, | ||
| 101 | mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, | ||
| 102 | gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, | ||
| 103 | ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, | ||
| 104 | usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, | ||
| 105 | pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, | ||
| 106 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, | ||
| 107 | sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, | ||
| 108 | usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, | ||
| 109 | spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, | ||
| 110 | lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max | ||
| 111 | }; | ||
| 112 | |||
| 113 | static struct clk *clk[clk_max]; | ||
| 114 | static struct clk_onecell_data clk_data; | 78 | static struct clk_onecell_data clk_data; |
| 115 | 79 | ||
| 116 | static enum mx6q_clks const clks_init_on[] __initconst = { | 80 | static unsigned int const clks_init_on[] __initconst = { |
| 117 | mmdc_ch0_axi, rom, arm, | 81 | IMX6QDL_CLK_MMDC_CH0_AXI, |
| 82 | IMX6QDL_CLK_ROM, | ||
| 83 | IMX6QDL_CLK_ARM, | ||
| 118 | }; | 84 | }; |
| 119 | 85 | ||
| 120 | static struct clk_div_table clk_enet_ref_table[] = { | 86 | static struct clk_div_table clk_enet_ref_table[] = { |
| @@ -149,10 +115,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 149 | int i; | 115 | int i; |
| 150 | int ret; | 116 | int ret; |
| 151 | 117 | ||
| 152 | clk[dummy] = imx_clk_fixed("dummy", 0); | 118 | clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
| 153 | clk[ckil] = imx_obtain_fixed_clock("ckil", 0); | 119 | clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); |
| 154 | clk[ckih] = imx_obtain_fixed_clock("ckih1", 0); | 120 | clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); |
| 155 | clk[osc] = imx_obtain_fixed_clock("osc", 0); | 121 | clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); |
| 156 | 122 | ||
| 157 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); | 123 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); |
| 158 | base = of_iomap(np, 0); | 124 | base = of_iomap(np, 0); |
| @@ -166,14 +132,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 166 | video_div_table[2].div = 1; | 132 | video_div_table[2].div = 1; |
| 167 | }; | 133 | }; |
| 168 | 134 | ||
| 169 | /* type name parent_name base div_mask */ | 135 | /* type name parent_name base div_mask */ |
| 170 | clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); | 136 | clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); |
| 171 | clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); | 137 | clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); |
| 172 | clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); | 138 | clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); |
| 173 | clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); | 139 | clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); |
| 174 | clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); | 140 | clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); |
| 175 | clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); | 141 | clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); |
| 176 | clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); | 142 | clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); |
| 177 | 143 | ||
| 178 | /* | 144 | /* |
| 179 | * Bit 20 is the reserved and read-only bit, we do this only for: | 145 | * Bit 20 is the reserved and read-only bit, we do this only for: |
| @@ -181,28 +147,28 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 181 | * - Keep refcount when do usbphy clk_enable/disable, in that case, | 147 | * - Keep refcount when do usbphy clk_enable/disable, in that case, |
| 182 | * the clk framework may need to enable/disable usbphy's parent | 148 | * the clk framework may need to enable/disable usbphy's parent |
| 183 | */ | 149 | */ |
| 184 | clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); | 150 | clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); |
| 185 | clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); | 151 | clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); |
| 186 | 152 | ||
| 187 | /* | 153 | /* |
| 188 | * usbphy*_gate needs to be on after system boots up, and software | 154 | * usbphy*_gate needs to be on after system boots up, and software |
| 189 | * never needs to control it anymore. | 155 | * never needs to control it anymore. |
| 190 | */ | 156 | */ |
| 191 | clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); | 157 | clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); |
| 192 | clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); | 158 | clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); |
| 193 | 159 | ||
| 194 | clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); | 160 | clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); |
| 195 | clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); | 161 | clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); |
| 196 | 162 | ||
| 197 | clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); | 163 | clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); |
| 198 | clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); | 164 | clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); |
| 199 | 165 | ||
| 200 | clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, | 166 | clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, |
| 201 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, | 167 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, |
| 202 | &imx_ccm_lock); | 168 | &imx_ccm_lock); |
| 203 | 169 | ||
| 204 | clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); | 170 | clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); |
| 205 | clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); | 171 | clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); |
| 206 | 172 | ||
| 207 | /* | 173 | /* |
| 208 | * lvds1_gate and lvds2_gate are pseudo-gates. Both can be | 174 | * lvds1_gate and lvds2_gate are pseudo-gates. Both can be |
| @@ -210,29 +176,29 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 210 | * the "output_enable" bit as a gate, even though it's really just | 176 | * the "output_enable" bit as a gate, even though it's really just |
| 211 | * enabling clock output. | 177 | * enabling clock output. |
| 212 | */ | 178 | */ |
| 213 | clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10); | 179 | clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10); |
| 214 | clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11); | 180 | clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11); |
| 215 | 181 | ||
| 216 | /* name parent_name reg idx */ | 182 | /* name parent_name reg idx */ |
| 217 | clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); | 183 | clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); |
| 218 | clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); | 184 | clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); |
| 219 | clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); | 185 | clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); |
| 220 | clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); | 186 | clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); |
| 221 | clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); | 187 | clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); |
| 222 | clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); | 188 | clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); |
| 223 | clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); | 189 | clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); |
| 224 | 190 | ||
| 225 | /* name parent_name mult div */ | 191 | /* name parent_name mult div */ |
| 226 | clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); | 192 | clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); |
| 227 | clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); | 193 | clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); |
| 228 | clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); | 194 | clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); |
| 229 | clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); | 195 | clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); |
| 230 | clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); | 196 | clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); |
| 231 | 197 | ||
| 232 | clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); | 198 | clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); |
| 233 | clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); | 199 | clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); |
| 234 | clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); | 200 | clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); |
| 235 | clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); | 201 | clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); |
| 236 | 202 | ||
| 237 | np = ccm_node; | 203 | np = ccm_node; |
| 238 | base = of_iomap(np, 0); | 204 | base = of_iomap(np, 0); |
| @@ -240,262 +206,254 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 240 | 206 | ||
| 241 | imx6q_pm_set_ccm_base(base); | 207 | imx6q_pm_set_ccm_base(base); |
| 242 | 208 | ||
| 243 | /* name reg shift width parent_names num_parents */ | 209 | /* name reg shift width parent_names num_parents */ |
| 244 | clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); | 210 | clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); |
| 245 | clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); | 211 | clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); |
| 246 | clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); | 212 | clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); |
| 247 | clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); | 213 | clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); |
| 248 | clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); | 214 | clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); |
| 249 | clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); | 215 | clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); |
| 250 | clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); | 216 | clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); |
| 251 | clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); | 217 | clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); |
| 252 | clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); | 218 | clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); |
| 253 | clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); | 219 | clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); |
| 254 | clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); | 220 | clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); |
| 255 | clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); | 221 | clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); |
| 256 | clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); | 222 | clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); |
| 257 | clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); | 223 | clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); |
| 258 | clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); | 224 | clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); |
| 259 | clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | 225 | clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); |
| 260 | clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | 226 | clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); |
| 261 | clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); | 227 | clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); |
| 262 | clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); | 228 | clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); |
| 263 | clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | 229 | clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
| 264 | clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | 230 | clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
| 265 | clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | 231 | clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
| 266 | clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | 232 | clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
| 267 | clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); | 233 | clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); |
| 268 | clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); | 234 | clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); |
| 269 | clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); | 235 | clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); |
| 270 | clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); | 236 | clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); |
| 271 | clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); | 237 | clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); |
| 272 | clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); | 238 | clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); |
| 273 | clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | 239 | clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 274 | clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | 240 | clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 275 | clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | 241 | clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 276 | clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | 242 | clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 277 | clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | 243 | clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 278 | clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | 244 | clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 279 | clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | 245 | clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 280 | clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); | 246 | clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); |
| 281 | clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); | 247 | clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); |
| 282 | clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); | 248 | clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); |
| 283 | clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); | 249 | clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); |
| 284 | clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); | 250 | clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); |
| 285 | clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); | 251 | clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); |
| 286 | clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); | 252 | clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); |
| 287 | clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); | 253 | clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); |
| 288 | 254 | ||
| 289 | /* name reg shift width busy: reg, shift parent_names num_parents */ | 255 | /* name reg shift width busy: reg, shift parent_names num_parents */ |
| 290 | clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); | 256 | clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); |
| 291 | clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); | 257 | clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); |
| 292 | 258 | ||
| 293 | /* name parent_name reg shift width */ | 259 | /* name parent_name reg shift width */ |
| 294 | clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); | 260 | clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); |
| 295 | clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); | 261 | clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); |
| 296 | clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); | 262 | clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); |
| 297 | clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); | 263 | clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); |
| 298 | clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); | 264 | clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); |
| 299 | clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); | 265 | clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); |
| 300 | clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); | 266 | clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); |
| 301 | clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); | 267 | clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); |
| 302 | clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); | 268 | clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); |
| 303 | clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); | 269 | clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); |
| 304 | clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); | 270 | clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); |
| 305 | clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); | 271 | clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); |
| 306 | clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); | 272 | clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); |
| 307 | clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); | 273 | clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); |
| 308 | clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); | 274 | clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); |
| 309 | clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); | 275 | clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); |
| 310 | clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); | 276 | clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); |
| 311 | clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); | 277 | clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); |
| 312 | clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); | 278 | clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); |
| 313 | clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); | 279 | clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); |
| 314 | clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); | 280 | clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); |
| 315 | clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); | 281 | clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); |
| 316 | clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); | 282 | clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); |
| 317 | clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); | 283 | clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); |
| 318 | clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); | 284 | clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); |
| 319 | clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); | 285 | clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); |
| 320 | clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); | 286 | clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); |
| 321 | clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); | 287 | clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); |
| 322 | clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); | 288 | clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); |
| 323 | clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); | 289 | clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); |
| 324 | clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); | 290 | clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); |
| 325 | clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); | 291 | clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); |
| 326 | clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); | 292 | clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); |
| 327 | clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); | 293 | clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); |
| 328 | clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); | 294 | clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); |
| 329 | clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); | 295 | clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); |
| 330 | clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); | 296 | clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); |
| 331 | clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); | 297 | clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); |
| 332 | clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); | 298 | clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); |
| 333 | clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); | 299 | clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); |
| 334 | clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); | 300 | clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); |
| 335 | clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); | 301 | clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); |
| 336 | clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); | 302 | clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); |
| 337 | clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); | 303 | clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); |
| 338 | 304 | ||
| 339 | /* name parent_name reg shift width busy: reg, shift */ | 305 | /* name parent_name reg shift width busy: reg, shift */ |
| 340 | clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); | 306 | clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); |
| 341 | clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); | 307 | clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); |
| 342 | clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); | 308 | clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); |
| 343 | clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); | 309 | clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); |
| 344 | clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); | 310 | clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); |
| 345 | 311 | ||
| 346 | /* name parent_name reg shift */ | 312 | /* name parent_name reg shift */ |
| 347 | clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); | 313 | clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); |
| 348 | clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); | 314 | clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); |
| 349 | clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); | 315 | clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); |
| 350 | clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); | 316 | clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); |
| 351 | clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); | 317 | clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); |
| 352 | clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); | 318 | clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); |
| 353 | clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); | 319 | clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); |
| 354 | clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); | 320 | clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); |
| 355 | clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); | 321 | clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); |
| 356 | clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); | 322 | clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); |
| 357 | if (cpu_is_imx6dl()) | 323 | if (cpu_is_imx6dl()) |
| 358 | /* ecspi5 is replaced with i2c4 on imx6dl & imx6s */ | 324 | clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); |
| 359 | clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); | ||
| 360 | else | 325 | else |
| 361 | clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); | 326 | clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); |
| 362 | clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); | 327 | clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); |
| 363 | clk[esai] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai); | 328 | clk[IMX6QDL_CLK_ESAI] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai); |
| 364 | clk[esai_ahb] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai); | 329 | clk[IMX6QDL_CLK_ESAI_AHB] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai); |
| 365 | clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); | 330 | clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); |
| 366 | clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); | 331 | clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); |
| 367 | if (cpu_is_imx6dl()) | 332 | if (cpu_is_imx6dl()) |
| 368 | /* | 333 | /* |
| 369 | * The multiplexer and divider of imx6q clock gpu3d_shader get | 334 | * The multiplexer and divider of imx6q clock gpu3d_shader get |
| 370 | * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. | 335 | * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. |
| 371 | */ | 336 | */ |
| 372 | clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); | 337 | clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); |
| 373 | else | 338 | else |
| 374 | clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); | 339 | clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); |
| 375 | clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); | 340 | clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); |
| 376 | clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); | 341 | clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); |
| 377 | clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); | 342 | clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); |
| 378 | clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); | 343 | clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); |
| 379 | clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); | 344 | clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); |
| 380 | clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); | 345 | clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); |
| 381 | clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); | 346 | clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); |
| 382 | clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); | 347 | clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); |
| 383 | clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); | 348 | clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); |
| 384 | clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); | 349 | clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); |
| 385 | clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); | 350 | clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); |
| 386 | clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); | 351 | clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); |
| 387 | clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); | 352 | clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); |
| 388 | clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); | 353 | clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); |
| 389 | clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); | 354 | clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); |
| 390 | clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); | 355 | clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); |
| 391 | clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); | 356 | clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); |
| 392 | clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); | 357 | clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); |
| 393 | if (cpu_is_imx6dl()) | 358 | if (cpu_is_imx6dl()) |
| 394 | /* | 359 | /* |
| 395 | * The multiplexer and divider of the imx6q clock gpu2d get | 360 | * The multiplexer and divider of the imx6q clock gpu2d get |
| 396 | * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. | 361 | * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. |
| 397 | */ | 362 | */ |
| 398 | clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); | 363 | clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); |
| 399 | else | 364 | else |
| 400 | clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); | 365 | clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); |
| 401 | clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); | 366 | clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); |
| 402 | clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); | 367 | clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); |
| 403 | clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); | 368 | clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); |
| 404 | clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); | 369 | clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); |
| 405 | clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); | 370 | clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); |
| 406 | clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); | 371 | clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); |
| 407 | clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); | 372 | clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); |
| 408 | clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); | 373 | clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); |
| 409 | clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); | 374 | clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); |
| 410 | clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); | 375 | clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); |
| 411 | clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); | 376 | clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); |
| 412 | clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); | 377 | clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); |
| 413 | clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); | 378 | clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); |
| 414 | clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); | 379 | clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); |
| 415 | clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); | 380 | clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); |
| 416 | clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); | 381 | clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); |
| 417 | clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); | 382 | clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); |
| 418 | clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); | 383 | clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); |
| 419 | clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); | 384 | clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); |
| 420 | clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); | 385 | clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); |
| 421 | clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); | 386 | clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); |
| 422 | clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); | 387 | clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); |
| 423 | clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); | 388 | clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); |
| 424 | clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); | 389 | clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); |
| 425 | clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); | 390 | clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); |
| 426 | clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); | 391 | clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); |
| 427 | clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); | 392 | clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); |
| 428 | clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); | 393 | clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); |
| 429 | clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); | 394 | clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); |
| 430 | clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); | 395 | clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); |
| 431 | clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); | 396 | clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); |
| 432 | clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); | 397 | clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); |
| 433 | clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); | 398 | clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); |
| 434 | clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); | 399 | clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); |
| 435 | 400 | ||
| 436 | for (i = 0; i < ARRAY_SIZE(clk); i++) | 401 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
| 437 | if (IS_ERR(clk[i])) | ||
| 438 | pr_err("i.MX6q clk %d: register failed with %ld\n", | ||
| 439 | i, PTR_ERR(clk[i])); | ||
| 440 | 402 | ||
| 441 | clk_data.clks = clk; | 403 | clk_data.clks = clk; |
| 442 | clk_data.clk_num = ARRAY_SIZE(clk); | 404 | clk_data.clk_num = ARRAY_SIZE(clk); |
| 443 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | 405 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
| 444 | 406 | ||
| 445 | clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); | 407 | clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); |
| 446 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); | ||
| 447 | clk_register_clkdev(clk[enet_ref], "enet_ref", NULL); | ||
| 448 | 408 | ||
| 449 | if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || | 409 | if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || |
| 450 | cpu_is_imx6dl()) { | 410 | cpu_is_imx6dl()) { |
| 451 | clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); | 411 | clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); |
| 452 | clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); | 412 | clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); |
| 453 | } | 413 | } |
| 454 | 414 | ||
| 455 | clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); | 415 | clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); |
| 456 | clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); | 416 | clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); |
| 457 | clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); | 417 | clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); |
| 458 | clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]); | 418 | clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); |
| 459 | clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]); | 419 | clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]); |
| 460 | clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]); | 420 | clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]); |
| 461 | clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]); | 421 | clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]); |
| 462 | clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]); | 422 | clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); |
| 463 | 423 | ||
| 464 | /* | 424 | /* |
| 465 | * The gpmi needs 100MHz frequency in the EDO/Sync mode, | 425 | * The gpmi needs 100MHz frequency in the EDO/Sync mode, |
| 466 | * We can not get the 100MHz from the pll2_pfd0_352m. | 426 | * We can not get the 100MHz from the pll2_pfd0_352m. |
| 467 | * So choose pll2_pfd2_396m as enfc_sel's parent. | 427 | * So choose pll2_pfd2_396m as enfc_sel's parent. |
| 468 | */ | 428 | */ |
| 469 | clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); | 429 | clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); |
| 470 | 430 | ||
| 471 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | 431 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
| 472 | clk_prepare_enable(clk[clks_init_on[i]]); | 432 | clk_prepare_enable(clk[clks_init_on[i]]); |
| 473 | 433 | ||
| 474 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { | 434 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { |
| 475 | clk_prepare_enable(clk[usbphy1_gate]); | 435 | clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); |
| 476 | clk_prepare_enable(clk[usbphy2_gate]); | 436 | clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); |
| 477 | } | 437 | } |
| 478 | 438 | ||
| 479 | /* | 439 | /* |
| 480 | * Let's initially set up CLKO with OSC24M, since this configuration | 440 | * Let's initially set up CLKO with OSC24M, since this configuration |
| 481 | * is widely used by imx6q board designs to clock audio codec. | 441 | * is widely used by imx6q board designs to clock audio codec. |
| 482 | */ | 442 | */ |
| 483 | ret = clk_set_parent(clk[cko2_sel], clk[osc]); | 443 | ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); |
| 484 | if (!ret) | 444 | if (!ret) |
| 485 | ret = clk_set_parent(clk[cko], clk[cko2]); | 445 | ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); |
| 486 | if (ret) | 446 | if (ret) |
| 487 | pr_warn("failed to set up CLKO: %d\n", ret); | 447 | pr_warn("failed to set up CLKO: %d\n", ret); |
| 488 | 448 | ||
| 489 | /* Audio-related clocks configuration */ | 449 | /* Audio-related clocks configuration */ |
| 490 | clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); | 450 | clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); |
| 491 | 451 | ||
| 492 | /* All existing boards with PCIe use LVDS1 */ | 452 | /* All existing boards with PCIe use LVDS1 */ |
| 493 | if (IS_ENABLED(CONFIG_PCI_IMX6)) | 453 | if (IS_ENABLED(CONFIG_PCI_IMX6)) |
| 494 | clk_set_parent(clk[lvds1_sel], clk[sata_ref]); | 454 | clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); |
| 495 | 455 | ||
| 496 | /* Set initial power mode */ | 456 | /* Set initial power mode */ |
| 497 | imx6q_set_lpm(WAIT_CLOCKED); | 457 | imx6q_set_lpm(WAIT_CLOCKED); |
| 498 | |||
| 499 | mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt")); | ||
| 500 | } | 458 | } |
| 501 | CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); | 459 | CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); |
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index 5408ca70c8d6..fef46faf692f 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c | |||
| @@ -348,18 +348,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) | |||
| 348 | clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); | 348 | clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); |
| 349 | clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); | 349 | clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); |
| 350 | 350 | ||
| 351 | for (i = 0; i < ARRAY_SIZE(clks); i++) | 351 | imx_check_clocks(clks, ARRAY_SIZE(clks)); |
| 352 | if (IS_ERR(clks[i])) | ||
| 353 | pr_err("i.MX6SL clk %d: register failed with %ld\n", | ||
| 354 | i, PTR_ERR(clks[i])); | ||
| 355 | 352 | ||
| 356 | clk_data.clks = clks; | 353 | clk_data.clks = clks; |
| 357 | clk_data.clk_num = ARRAY_SIZE(clks); | 354 | clk_data.clk_num = ARRAY_SIZE(clks); |
| 358 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | 355 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
| 359 | 356 | ||
| 360 | clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0"); | ||
| 361 | clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0"); | ||
| 362 | |||
| 363 | /* Ensure the AHB clk is at 132MHz. */ | 357 | /* Ensure the AHB clk is at 132MHz. */ |
| 364 | ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); | 358 | ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); |
| 365 | if (ret) | 359 | if (ret) |
| @@ -383,8 +377,5 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) | |||
| 383 | 377 | ||
| 384 | /* Set initial power mode */ | 378 | /* Set initial power mode */ |
| 385 | imx6q_set_lpm(WAIT_CLOCKED); | 379 | imx6q_set_lpm(WAIT_CLOCKED); |
| 386 | |||
| 387 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt"); | ||
| 388 | mxc_timer_init_dt(np); | ||
| 389 | } | 380 | } |
| 390 | CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); | 381 | CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); |
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 72f8902235d1..ecde72bdfe88 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c | |||
| @@ -124,6 +124,9 @@ static struct clk_div_table video_div_table[] = { | |||
| 124 | static u32 share_count_asrc; | 124 | static u32 share_count_asrc; |
| 125 | static u32 share_count_audio; | 125 | static u32 share_count_audio; |
| 126 | static u32 share_count_esai; | 126 | static u32 share_count_esai; |
| 127 | static u32 share_count_ssi1; | ||
| 128 | static u32 share_count_ssi2; | ||
| 129 | static u32 share_count_ssi3; | ||
| 127 | 130 | ||
| 128 | static void __init imx6sx_clocks_init(struct device_node *ccm_node) | 131 | static void __init imx6sx_clocks_init(struct device_node *ccm_node) |
| 129 | { | 132 | { |
| @@ -409,12 +412,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) | |||
| 409 | clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); | 412 | clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); |
| 410 | clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio); | 413 | clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio); |
| 411 | clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); | 414 | clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); |
| 412 | clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); | 415 | clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); |
| 413 | clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); | 416 | clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); |
| 414 | clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); | 417 | clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); |
| 415 | clks[IMX6SX_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); | 418 | clks[IMX6SX_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); |
| 416 | clks[IMX6SX_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); | 419 | clks[IMX6SX_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); |
| 417 | clks[IMX6SX_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22); | 420 | clks[IMX6SX_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); |
| 418 | clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); | 421 | clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); |
| 419 | clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26); | 422 | clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26); |
| 420 | clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2("sai1_ipg", "ipg", base + 0x7c, 28); | 423 | clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2("sai1_ipg", "ipg", base + 0x7c, 28); |
| @@ -443,17 +446,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) | |||
| 443 | /* mask handshake of mmdc */ | 446 | /* mask handshake of mmdc */ |
| 444 | writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); | 447 | writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); |
| 445 | 448 | ||
| 446 | for (i = 0; i < ARRAY_SIZE(clks); i++) | 449 | imx_check_clocks(clks, ARRAY_SIZE(clks)); |
| 447 | if (IS_ERR(clks[i])) | ||
| 448 | pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); | ||
| 449 | 450 | ||
| 450 | clk_data.clks = clks; | 451 | clk_data.clks = clks; |
| 451 | clk_data.clk_num = ARRAY_SIZE(clks); | 452 | clk_data.clk_num = ARRAY_SIZE(clks); |
| 452 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | 453 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
| 453 | 454 | ||
| 454 | clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0"); | ||
| 455 | clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0"); | ||
| 456 | |||
| 457 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | 455 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
| 458 | clk_prepare_enable(clks[clks_init_on[i]]); | 456 | clk_prepare_enable(clks[clks_init_on[i]]); |
| 459 | 457 | ||
| @@ -517,8 +515,5 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) | |||
| 517 | 515 | ||
| 518 | /* Set initial power mode */ | 516 | /* Set initial power mode */ |
| 519 | imx6q_set_lpm(WAIT_CLOCKED); | 517 | imx6q_set_lpm(WAIT_CLOCKED); |
| 520 | |||
| 521 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt"); | ||
| 522 | mxc_timer_init_dt(np); | ||
| 523 | } | 518 | } |
| 524 | CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init); | 519 | CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init); |
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index 22dc3ee21fd4..f60d6d569ce3 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c | |||
| @@ -295,14 +295,18 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) | |||
| 295 | 295 | ||
| 296 | clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); | 296 | clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); |
| 297 | 297 | ||
| 298 | clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); | 298 | clk[VF610_CLK_FLEXCAN0_EN] = imx_clk_gate("flexcan0_en", "ipg_bus", CCM_CSCDR2, 11); |
| 299 | clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); | 299 | clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "flexcan0_en", CCM_CCGR0, CCM_CCGRx_CGn(0)); |
| 300 | clk[VF610_CLK_FLEXCAN1_EN] = imx_clk_gate("flexcan1_en", "ipg_bus", CCM_CSCDR2, 12); | ||
| 301 | clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "flexcan1_en", CCM_CCGR9, CCM_CCGRx_CGn(4)); | ||
| 300 | 302 | ||
| 301 | clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4)); | 303 | clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4)); |
| 302 | clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5)); | 304 | clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5)); |
| 303 | clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); | 305 | clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); |
| 304 | clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); | 306 | clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); |
| 305 | 307 | ||
| 308 | imx_check_clocks(clk, ARRAY_SIZE(clk)); | ||
| 309 | |||
| 306 | clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); | 310 | clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); |
| 307 | clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); | 311 | clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); |
| 308 | clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); | 312 | clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); |
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c index edc35df7bed4..df12b5307175 100644 --- a/arch/arm/mach-imx/clk.c +++ b/arch/arm/mach-imx/clk.c | |||
| @@ -7,6 +7,16 @@ | |||
| 7 | 7 | ||
| 8 | DEFINE_SPINLOCK(imx_ccm_lock); | 8 | DEFINE_SPINLOCK(imx_ccm_lock); |
| 9 | 9 | ||
| 10 | void __init imx_check_clocks(struct clk *clks[], unsigned int count) | ||
| 11 | { | ||
| 12 | unsigned i; | ||
| 13 | |||
| 14 | for (i = 0; i < count; i++) | ||
| 15 | if (IS_ERR(clks[i])) | ||
| 16 | pr_err("i.MX clk %u: register failed with %ld\n", | ||
| 17 | i, PTR_ERR(clks[i])); | ||
| 18 | } | ||
| 19 | |||
| 10 | static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) | 20 | static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) |
| 11 | { | 21 | { |
| 12 | struct of_phandle_args phandle; | 22 | struct of_phandle_args phandle; |
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index e29f6ebe9f39..d5ba76fee115 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h | |||
| @@ -6,6 +6,8 @@ | |||
| 6 | 6 | ||
| 7 | extern spinlock_t imx_ccm_lock; | 7 | extern spinlock_t imx_ccm_lock; |
| 8 | 8 | ||
| 9 | void imx_check_clocks(struct clk *clks[], unsigned int count); | ||
| 10 | |||
| 9 | extern void imx_cscmr1_fixup(u32 *val); | 11 | extern void imx_cscmr1_fixup(u32 *val); |
| 10 | 12 | ||
| 11 | struct clk *imx_clk_pllv1(const char *name, const char *parent, | 13 | struct clk *imx_clk_pllv1(const char *name, const char *parent, |
| @@ -95,6 +97,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent, | |||
| 95 | shift, 0, &imx_ccm_lock); | 97 | shift, 0, &imx_ccm_lock); |
| 96 | } | 98 | } |
| 97 | 99 | ||
| 100 | static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, | ||
| 101 | void __iomem *reg, u8 shift) | ||
| 102 | { | ||
| 103 | return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, | ||
| 104 | shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); | ||
| 105 | } | ||
| 106 | |||
| 98 | static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, | 107 | static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, |
| 99 | u8 shift, u8 width, const char **parents, int num_parents) | 108 | u8 shift, u8 width, const char **parents, int num_parents) |
| 100 | { | 109 | { |
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 9ab785ce13e8..22ba8973bcb9 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h | |||
| @@ -19,6 +19,7 @@ struct pt_regs; | |||
| 19 | struct clk; | 19 | struct clk; |
| 20 | struct device_node; | 20 | struct device_node; |
| 21 | enum mxc_cpu_pwr_mode; | 21 | enum mxc_cpu_pwr_mode; |
| 22 | struct of_device_id; | ||
| 22 | 23 | ||
| 23 | void mx1_map_io(void); | 24 | void mx1_map_io(void); |
| 24 | void mx21_map_io(void); | 25 | void mx21_map_io(void); |
| @@ -26,48 +27,34 @@ void mx25_map_io(void); | |||
| 26 | void mx27_map_io(void); | 27 | void mx27_map_io(void); |
| 27 | void mx31_map_io(void); | 28 | void mx31_map_io(void); |
| 28 | void mx35_map_io(void); | 29 | void mx35_map_io(void); |
| 29 | void mx51_map_io(void); | ||
| 30 | void mx53_map_io(void); | ||
| 31 | void imx1_init_early(void); | 30 | void imx1_init_early(void); |
| 32 | void imx21_init_early(void); | 31 | void imx21_init_early(void); |
| 33 | void imx25_init_early(void); | 32 | void imx25_init_early(void); |
| 34 | void imx27_init_early(void); | 33 | void imx27_init_early(void); |
| 35 | void imx31_init_early(void); | 34 | void imx31_init_early(void); |
| 36 | void imx35_init_early(void); | 35 | void imx35_init_early(void); |
| 37 | void imx51_init_early(void); | ||
| 38 | void imx53_init_early(void); | ||
| 39 | void mxc_init_irq(void __iomem *); | 36 | void mxc_init_irq(void __iomem *); |
| 40 | void tzic_init_irq(void __iomem *); | 37 | void tzic_init_irq(void); |
| 41 | void mx1_init_irq(void); | 38 | void mx1_init_irq(void); |
| 42 | void mx21_init_irq(void); | 39 | void mx21_init_irq(void); |
| 43 | void mx25_init_irq(void); | 40 | void mx25_init_irq(void); |
| 44 | void mx27_init_irq(void); | 41 | void mx27_init_irq(void); |
| 45 | void mx31_init_irq(void); | 42 | void mx31_init_irq(void); |
| 46 | void mx35_init_irq(void); | 43 | void mx35_init_irq(void); |
| 47 | void mx51_init_irq(void); | ||
| 48 | void mx53_init_irq(void); | ||
| 49 | void imx1_soc_init(void); | 44 | void imx1_soc_init(void); |
| 50 | void imx21_soc_init(void); | 45 | void imx21_soc_init(void); |
| 51 | void imx25_soc_init(void); | 46 | void imx25_soc_init(void); |
| 52 | void imx27_soc_init(void); | 47 | void imx27_soc_init(void); |
| 53 | void imx31_soc_init(void); | 48 | void imx31_soc_init(void); |
| 54 | void imx35_soc_init(void); | 49 | void imx35_soc_init(void); |
| 55 | void imx51_soc_init(void); | ||
| 56 | void imx51_init_late(void); | ||
| 57 | void imx53_init_late(void); | ||
| 58 | void epit_timer_init(void __iomem *base, int irq); | 50 | void epit_timer_init(void __iomem *base, int irq); |
| 59 | void mxc_timer_init(void __iomem *, int); | 51 | void mxc_timer_init(void __iomem *, int); |
| 60 | void mxc_timer_init_dt(struct device_node *); | ||
| 61 | int mx1_clocks_init(unsigned long fref); | 52 | int mx1_clocks_init(unsigned long fref); |
| 62 | int mx21_clocks_init(unsigned long lref, unsigned long fref); | 53 | int mx21_clocks_init(unsigned long lref, unsigned long fref); |
| 63 | int mx25_clocks_init(void); | 54 | int mx25_clocks_init(void); |
| 64 | int mx27_clocks_init(unsigned long fref); | 55 | int mx27_clocks_init(unsigned long fref); |
| 65 | int mx31_clocks_init(unsigned long fref); | 56 | int mx31_clocks_init(unsigned long fref); |
| 66 | int mx35_clocks_init(void); | 57 | int mx35_clocks_init(void); |
| 67 | int mx51_clocks_init(unsigned long ckil, unsigned long osc, | ||
| 68 | unsigned long ckih1, unsigned long ckih2); | ||
| 69 | int mx25_clocks_init_dt(void); | ||
| 70 | int mx27_clocks_init_dt(void); | ||
| 71 | int mx31_clocks_init_dt(void); | 58 | int mx31_clocks_init_dt(void); |
| 72 | struct platform_device *mxc_register_gpio(char *name, int id, | 59 | struct platform_device *mxc_register_gpio(char *name, int id, |
| 73 | resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); | 60 | resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); |
| @@ -75,8 +62,10 @@ void mxc_set_cpu_type(unsigned int type); | |||
| 75 | void mxc_restart(enum reboot_mode, const char *); | 62 | void mxc_restart(enum reboot_mode, const char *); |
| 76 | void mxc_arch_reset_init(void __iomem *); | 63 | void mxc_arch_reset_init(void __iomem *); |
| 77 | void mxc_arch_reset_init_dt(void); | 64 | void mxc_arch_reset_init_dt(void); |
| 65 | int mx51_revision(void); | ||
| 78 | int mx53_revision(void); | 66 | int mx53_revision(void); |
| 79 | void imx_set_aips(void __iomem *); | 67 | void imx_set_aips(void __iomem *); |
| 68 | void imx_aips_allow_unprivileged_access(const char *compat); | ||
| 80 | int mxc_device_init(void); | 69 | int mxc_device_init(void); |
| 81 | void imx_set_soc_revision(unsigned int rev); | 70 | void imx_set_soc_revision(unsigned int rev); |
| 82 | unsigned int imx_get_soc_revision(void); | 71 | unsigned int imx_get_soc_revision(void); |
| @@ -117,7 +106,7 @@ static inline void imx_scu_standby_enable(void) {} | |||
| 117 | #endif | 106 | #endif |
| 118 | void imx_src_init(void); | 107 | void imx_src_init(void); |
| 119 | void imx_gpc_init(void); | 108 | void imx_gpc_init(void); |
| 120 | void imx_gpc_pre_suspend(void); | 109 | void imx_gpc_pre_suspend(bool arm_power_off); |
| 121 | void imx_gpc_post_resume(void); | 110 | void imx_gpc_post_resume(void); |
| 122 | void imx_gpc_mask_all(void); | 111 | void imx_gpc_mask_all(void); |
| 123 | void imx_gpc_restore_all(void); | 112 | void imx_gpc_restore_all(void); |
| @@ -127,7 +116,7 @@ void imx_anatop_init(void); | |||
| 127 | void imx_anatop_pre_suspend(void); | 116 | void imx_anatop_pre_suspend(void); |
| 128 | void imx_anatop_post_resume(void); | 117 | void imx_anatop_post_resume(void); |
| 129 | int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); | 118 | int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); |
| 130 | void imx6q_set_int_mem_clk_lpm(void); | 119 | void imx6q_set_int_mem_clk_lpm(bool enable); |
| 131 | void imx6sl_set_wait_clk(bool enter); | 120 | void imx6sl_set_wait_clk(bool enter); |
| 132 | 121 | ||
| 133 | void imx_cpu_die(unsigned int cpu); | 122 | void imx_cpu_die(unsigned int cpu); |
| @@ -144,12 +133,17 @@ static inline void imx6_suspend(void __iomem *ocram_vbase) {} | |||
| 144 | void imx6q_pm_init(void); | 133 | void imx6q_pm_init(void); |
| 145 | void imx6dl_pm_init(void); | 134 | void imx6dl_pm_init(void); |
| 146 | void imx6sl_pm_init(void); | 135 | void imx6sl_pm_init(void); |
| 136 | void imx6sx_pm_init(void); | ||
| 147 | void imx6q_pm_set_ccm_base(void __iomem *base); | 137 | void imx6q_pm_set_ccm_base(void __iomem *base); |
| 148 | 138 | ||
| 149 | #ifdef CONFIG_PM | 139 | #ifdef CONFIG_PM |
| 150 | void imx5_pm_init(void); | 140 | void imx51_pm_init(void); |
| 141 | void imx53_pm_init(void); | ||
| 142 | void imx5_pm_set_ccm_base(void __iomem *base); | ||
| 151 | #else | 143 | #else |
| 152 | static inline void imx5_pm_init(void) {} | 144 | static inline void imx51_pm_init(void) {} |
| 145 | static inline void imx53_pm_init(void) {} | ||
| 146 | static inline void imx5_pm_set_ccm_base(void __iomem *base) {} | ||
| 153 | #endif | 147 | #endif |
| 154 | 148 | ||
| 155 | #ifdef CONFIG_NEON | 149 | #ifdef CONFIG_NEON |
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c index c1c99a72c6a1..3403bac94a31 100644 --- a/arch/arm/mach-imx/cpu-imx5.c +++ b/arch/arm/mach-imx/cpu-imx5.c | |||
| @@ -16,6 +16,8 @@ | |||
| 16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 17 | #include <linux/module.h> | 17 | #include <linux/module.h> |
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | #include <linux/of.h> | ||
| 20 | #include <linux/of_address.h> | ||
| 19 | 21 | ||
| 20 | #include "hardware.h" | 22 | #include "hardware.h" |
| 21 | #include "common.h" | 23 | #include "common.h" |
| @@ -24,10 +26,26 @@ static int mx5_cpu_rev = -1; | |||
| 24 | 26 | ||
| 25 | #define IIM_SREV 0x24 | 27 | #define IIM_SREV 0x24 |
| 26 | 28 | ||
| 29 | static u32 imx5_read_srev_reg(const char *compat) | ||
| 30 | { | ||
| 31 | void __iomem *iim_base; | ||
| 32 | struct device_node *np; | ||
| 33 | u32 srev; | ||
| 34 | |||
| 35 | np = of_find_compatible_node(NULL, NULL, compat); | ||
| 36 | iim_base = of_iomap(np, 0); | ||
| 37 | WARN_ON(!iim_base); | ||
| 38 | |||
| 39 | srev = readl(iim_base + IIM_SREV) & 0xff; | ||
| 40 | |||
| 41 | iounmap(iim_base); | ||
| 42 | |||
| 43 | return srev; | ||
| 44 | } | ||
| 45 | |||
| 27 | static int get_mx51_srev(void) | 46 | static int get_mx51_srev(void) |
| 28 | { | 47 | { |
| 29 | void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); | 48 | u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); |
| 30 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; | ||
| 31 | 49 | ||
| 32 | switch (rev) { | 50 | switch (rev) { |
| 33 | case 0x0: | 51 | case 0x0: |
| @@ -77,8 +95,7 @@ int __init mx51_neon_fixup(void) | |||
| 77 | 95 | ||
| 78 | static int get_mx53_srev(void) | 96 | static int get_mx53_srev(void) |
| 79 | { | 97 | { |
| 80 | void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); | 98 | u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); |
| 81 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; | ||
| 82 | 99 | ||
| 83 | switch (rev) { | 100 | switch (rev) { |
| 84 | case 0x0: | 101 | case 0x0: |
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index bbe8ff1f0412..df42c14ff749 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | #include <linux/module.h> | 2 | #include <linux/module.h> |
| 3 | #include <linux/io.h> | 3 | #include <linux/io.h> |
| 4 | #include <linux/of.h> | 4 | #include <linux/of.h> |
| 5 | #include <linux/of_address.h> | ||
| 5 | #include <linux/slab.h> | 6 | #include <linux/slab.h> |
| 6 | #include <linux/sys_soc.h> | 7 | #include <linux/sys_soc.h> |
| 7 | 8 | ||
| @@ -60,6 +61,18 @@ void __init imx_set_aips(void __iomem *base) | |||
| 60 | __raw_writel(reg, base + 0x50); | 61 | __raw_writel(reg, base + 0x50); |
| 61 | } | 62 | } |
| 62 | 63 | ||
| 64 | void __init imx_aips_allow_unprivileged_access( | ||
| 65 | const char *compat) | ||
| 66 | { | ||
| 67 | void __iomem *aips_base_addr; | ||
| 68 | struct device_node *np; | ||
| 69 | |||
| 70 | for_each_compatible_node(np, NULL, compat) { | ||
| 71 | aips_base_addr = of_iomap(np, 0); | ||
| 72 | imx_set_aips(aips_base_addr); | ||
| 73 | } | ||
| 74 | } | ||
| 75 | |||
| 63 | struct device * __init imx_soc_device_init(void) | 76 | struct device * __init imx_soc_device_init(void) |
| 64 | { | 77 | { |
| 65 | struct soc_device_attribute *soc_dev_attr; | 78 | struct soc_device_attribute *soc_dev_attr; |
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index 6bcae0479049..10844d3bb926 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | #include "common.h" | 14 | #include "common.h" |
| 15 | #include "cpuidle.h" | 15 | #include "cpuidle.h" |
| 16 | #include "hardware.h" | ||
| 16 | 17 | ||
| 17 | static atomic_t master = ATOMIC_INIT(0); | 18 | static atomic_t master = ATOMIC_INIT(0); |
| 18 | static DEFINE_SPINLOCK(master_lock); | 19 | static DEFINE_SPINLOCK(master_lock); |
| @@ -66,10 +67,11 @@ static struct cpuidle_driver imx6q_cpuidle_driver = { | |||
| 66 | int __init imx6q_cpuidle_init(void) | 67 | int __init imx6q_cpuidle_init(void) |
| 67 | { | 68 | { |
| 68 | /* Need to enable SCU standby for entering WAIT modes */ | 69 | /* Need to enable SCU standby for entering WAIT modes */ |
| 69 | imx_scu_standby_enable(); | 70 | if (!cpu_is_imx6sx()) |
| 71 | imx_scu_standby_enable(); | ||
| 70 | 72 | ||
| 71 | /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ | 73 | /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ |
| 72 | imx6q_set_int_mem_clk_lpm(); | 74 | imx6q_set_int_mem_clk_lpm(true); |
| 73 | 75 | ||
| 74 | return cpuidle_register(&imx6q_cpuidle_driver, NULL); | 76 | return cpuidle_register(&imx6q_cpuidle_driver, NULL); |
| 75 | } | 77 | } |
diff --git a/arch/arm/mach-imx/crm-regs-imx5.h b/arch/arm/mach-imx/crm-regs-imx5.h deleted file mode 100644 index 5e3f1f0f4cab..000000000000 --- a/arch/arm/mach-imx/crm-regs-imx5.h +++ /dev/null | |||
| @@ -1,600 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ | ||
| 12 | #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ | ||
| 13 | |||
| 14 | #define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) | ||
| 15 | #define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) | ||
| 16 | #define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) | ||
| 17 | #define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR) | ||
| 18 | #define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) | ||
| 19 | #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) | ||
| 20 | |||
| 21 | /*MX53*/ | ||
| 22 | #define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR) | ||
| 23 | #define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR) | ||
| 24 | #define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) | ||
| 25 | #define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) | ||
| 26 | #define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR) | ||
| 27 | |||
| 28 | /* PLL Register Offsets */ | ||
| 29 | #define MXC_PLL_DP_CTL 0x00 | ||
| 30 | #define MXC_PLL_DP_CONFIG 0x04 | ||
| 31 | #define MXC_PLL_DP_OP 0x08 | ||
| 32 | #define MXC_PLL_DP_MFD 0x0C | ||
| 33 | #define MXC_PLL_DP_MFN 0x10 | ||
| 34 | #define MXC_PLL_DP_MFNMINUS 0x14 | ||
| 35 | #define MXC_PLL_DP_MFNPLUS 0x18 | ||
| 36 | #define MXC_PLL_DP_HFS_OP 0x1C | ||
| 37 | #define MXC_PLL_DP_HFS_MFD 0x20 | ||
| 38 | #define MXC_PLL_DP_HFS_MFN 0x24 | ||
| 39 | #define MXC_PLL_DP_MFN_TOGC 0x28 | ||
| 40 | #define MXC_PLL_DP_DESTAT 0x2c | ||
| 41 | |||
| 42 | /* PLL Register Bit definitions */ | ||
| 43 | #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 | ||
| 44 | #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 | ||
| 45 | #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 | ||
| 46 | #define MXC_PLL_DP_CTL_ADE 0x800 | ||
| 47 | #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 | ||
| 48 | #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) | ||
| 49 | #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 | ||
| 50 | #define MXC_PLL_DP_CTL_HFSM 0x80 | ||
| 51 | #define MXC_PLL_DP_CTL_PRE 0x40 | ||
| 52 | #define MXC_PLL_DP_CTL_UPEN 0x20 | ||
| 53 | #define MXC_PLL_DP_CTL_RST 0x10 | ||
| 54 | #define MXC_PLL_DP_CTL_RCP 0x8 | ||
| 55 | #define MXC_PLL_DP_CTL_PLM 0x4 | ||
| 56 | #define MXC_PLL_DP_CTL_BRM0 0x2 | ||
| 57 | #define MXC_PLL_DP_CTL_LRF 0x1 | ||
| 58 | |||
| 59 | #define MXC_PLL_DP_CONFIG_BIST 0x8 | ||
| 60 | #define MXC_PLL_DP_CONFIG_SJC_CE 0x4 | ||
| 61 | #define MXC_PLL_DP_CONFIG_AREN 0x2 | ||
| 62 | #define MXC_PLL_DP_CONFIG_LDREQ 0x1 | ||
| 63 | |||
| 64 | #define MXC_PLL_DP_OP_MFI_OFFSET 4 | ||
| 65 | #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) | ||
| 66 | #define MXC_PLL_DP_OP_PDF_OFFSET 0 | ||
| 67 | #define MXC_PLL_DP_OP_PDF_MASK 0xF | ||
| 68 | |||
| 69 | #define MXC_PLL_DP_MFD_OFFSET 0 | ||
| 70 | #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF | ||
| 71 | |||
| 72 | #define MXC_PLL_DP_MFN_OFFSET 0x0 | ||
| 73 | #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF | ||
| 74 | |||
| 75 | #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) | ||
| 76 | #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) | ||
| 77 | #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 | ||
| 78 | #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF | ||
| 79 | |||
| 80 | #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) | ||
| 81 | #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF | ||
| 82 | |||
| 83 | /* Register addresses of CCM*/ | ||
| 84 | #define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) | ||
| 85 | #define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) | ||
| 86 | #define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) | ||
| 87 | #define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) | ||
| 88 | #define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) | ||
| 89 | #define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) | ||
| 90 | #define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) | ||
| 91 | #define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) | ||
| 92 | #define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) | ||
| 93 | #define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) | ||
| 94 | #define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) | ||
| 95 | #define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) | ||
| 96 | #define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) | ||
| 97 | #define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) | ||
| 98 | #define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) | ||
| 99 | #define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) | ||
| 100 | #define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) | ||
| 101 | #define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) | ||
| 102 | #define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) | ||
| 103 | #define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) | ||
| 104 | #define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) | ||
| 105 | #define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) | ||
| 106 | #define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) | ||
| 107 | #define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) | ||
| 108 | #define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) | ||
| 109 | #define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) | ||
| 110 | #define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) | ||
| 111 | #define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) | ||
| 112 | #define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) | ||
| 113 | #define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) | ||
| 114 | #define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) | ||
| 115 | #define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) | ||
| 116 | #define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) | ||
| 117 | #define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84) | ||
| 118 | |||
| 119 | #define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) | ||
| 120 | |||
| 121 | /* Define the bits in register CCR */ | ||
| 122 | #define MXC_CCM_CCR_COSC_EN (1 << 12) | ||
| 123 | #define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) | ||
| 124 | #define MXC_CCM_CCR_CAMP2_EN (1 << 10) | ||
| 125 | #define MXC_CCM_CCR_CAMP1_EN (1 << 9) | ||
| 126 | #define MXC_CCM_CCR_FPM_EN (1 << 8) | ||
| 127 | #define MXC_CCM_CCR_OSCNT_OFFSET (0) | ||
| 128 | #define MXC_CCM_CCR_OSCNT_MASK (0xFF) | ||
| 129 | |||
| 130 | /* Define the bits in register CCDR */ | ||
| 131 | #define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) | ||
| 132 | #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) | ||
| 133 | #define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) | ||
| 134 | |||
| 135 | /* Define the bits in register CSR */ | ||
| 136 | #define MXC_CCM_CSR_COSR_READY (1 << 5) | ||
| 137 | #define MXC_CCM_CSR_LVS_VALUE (1 << 4) | ||
| 138 | #define MXC_CCM_CSR_CAMP2_READY (1 << 3) | ||
| 139 | #define MXC_CCM_CSR_CAMP1_READY (1 << 2) | ||
| 140 | #define MXC_CCM_CSR_FPM_READY (1 << 1) | ||
| 141 | #define MXC_CCM_CSR_REF_EN_B (1 << 0) | ||
| 142 | |||
| 143 | /* Define the bits in register CCSR */ | ||
| 144 | #define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) | ||
| 145 | #define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) | ||
| 146 | #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) | ||
| 147 | #define MXC_CCM_CCSR_STEP_SEL_LP_APM 0 | ||
| 148 | #define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */ | ||
| 149 | #define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2 | ||
| 150 | #define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3 | ||
| 151 | #define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) | ||
| 152 | #define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) | ||
| 153 | #define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) | ||
| 154 | #define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) | ||
| 155 | #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk, | ||
| 156 | 1: step_clk */ | ||
| 157 | #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) | ||
| 158 | #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) | ||
| 159 | |||
| 160 | /* Define the bits in register CACRR */ | ||
| 161 | #define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) | ||
| 162 | #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) | ||
| 163 | |||
| 164 | /* Define the bits in register CBCDR */ | ||
| 165 | #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) | ||
| 166 | #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) | ||
| 167 | #define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) | ||
| 168 | #define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) | ||
| 169 | #define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) | ||
| 170 | #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) | ||
| 171 | #define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) | ||
| 172 | #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) | ||
| 173 | #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) | ||
| 174 | #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) | ||
| 175 | #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) | ||
| 176 | #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) | ||
| 177 | #define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) | ||
| 178 | #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) | ||
| 179 | #define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) | ||
| 180 | #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) | ||
| 181 | #define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) | ||
| 182 | #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) | ||
| 183 | #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) | ||
| 184 | #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) | ||
| 185 | #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) | ||
| 186 | #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) | ||
| 187 | #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) | ||
| 188 | #define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) | ||
| 189 | |||
| 190 | /* Define the bits in register CBCMR */ | ||
| 191 | #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) | ||
| 192 | #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) | ||
| 193 | #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) | ||
| 194 | #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) | ||
| 195 | #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) | ||
| 196 | #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) | ||
| 197 | #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) | ||
| 198 | #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) | ||
| 199 | #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) | ||
| 200 | #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) | ||
| 201 | #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) | ||
| 202 | #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) | ||
| 203 | #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) | ||
| 204 | #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) | ||
| 205 | #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) | ||
| 206 | #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) | ||
| 207 | |||
| 208 | /* Define the bits in register CSCMR1 */ | ||
| 209 | #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) | ||
| 210 | #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) | ||
| 211 | #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) | ||
| 212 | #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) | ||
| 213 | #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) | ||
| 214 | #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) | ||
| 215 | #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) | ||
| 216 | #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) | ||
| 217 | #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) | ||
| 218 | #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) | ||
| 219 | #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) | ||
| 220 | #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) | ||
| 221 | #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) | ||
| 222 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19) | ||
| 223 | #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) | ||
| 224 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) | ||
| 225 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) | ||
| 226 | #define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16) | ||
| 227 | #define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16) | ||
| 228 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) | ||
| 229 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) | ||
| 230 | #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) | ||
| 231 | #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) | ||
| 232 | #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) | ||
| 233 | #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) | ||
| 234 | #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) | ||
| 235 | #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) | ||
| 236 | #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) | ||
| 237 | #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) | ||
| 238 | #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) | ||
| 239 | #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) | ||
| 240 | #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) | ||
| 241 | #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) | ||
| 242 | #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) | ||
| 243 | #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) | ||
| 244 | |||
| 245 | /* Define the bits in register CSCMR2 */ | ||
| 246 | #define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) | ||
| 247 | #define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) | ||
| 248 | #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) | ||
| 249 | #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) | ||
| 250 | #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) | ||
| 251 | #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) | ||
| 252 | #define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) | ||
| 253 | #define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) | ||
| 254 | #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) | ||
| 255 | #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) | ||
| 256 | #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) | ||
| 257 | #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) | ||
| 258 | #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) | ||
| 259 | #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) | ||
| 260 | #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) | ||
| 261 | #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) | ||
| 262 | #define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) | ||
| 263 | #define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) | ||
| 264 | #define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) | ||
| 265 | #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) | ||
| 266 | #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) | ||
| 267 | #define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) | ||
| 268 | #define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) | ||
| 269 | #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) | ||
| 270 | #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) | ||
| 271 | #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) | ||
| 272 | #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) | ||
| 273 | |||
| 274 | /* Define the bits in register CSCDR1 */ | ||
| 275 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) | ||
| 276 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) | ||
| 277 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) | ||
| 278 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) | ||
| 279 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22) | ||
| 280 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22) | ||
| 281 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19) | ||
| 282 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19) | ||
| 283 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) | ||
| 284 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) | ||
| 285 | #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) | ||
| 286 | #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) | ||
| 287 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) | ||
| 288 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) | ||
| 289 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) | ||
| 290 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) | ||
| 291 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) | ||
| 292 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) | ||
| 293 | #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) | ||
| 294 | #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) | ||
| 295 | #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) | ||
| 296 | #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) | ||
| 297 | |||
| 298 | /* Define the bits in register CS1CDR and CS2CDR */ | ||
| 299 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) | ||
| 300 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) | ||
| 301 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) | ||
| 302 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) | ||
| 303 | #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) | ||
| 304 | #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) | ||
| 305 | #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) | ||
| 306 | #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) | ||
| 307 | |||
| 308 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) | ||
| 309 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) | ||
| 310 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) | ||
| 311 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) | ||
| 312 | #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) | ||
| 313 | #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) | ||
| 314 | #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) | ||
| 315 | #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) | ||
| 316 | |||
| 317 | /* Define the bits in register CDCDR */ | ||
| 318 | #define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) | ||
| 319 | #define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) | ||
| 320 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) | ||
| 321 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) | ||
| 322 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) | ||
| 323 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) | ||
| 324 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) | ||
| 325 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) | ||
| 326 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) | ||
| 327 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) | ||
| 328 | #define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) | ||
| 329 | #define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) | ||
| 330 | #define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) | ||
| 331 | #define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) | ||
| 332 | #define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) | ||
| 333 | #define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) | ||
| 334 | |||
| 335 | /* Define the bits in register CHSCCDR */ | ||
| 336 | #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) | ||
| 337 | #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) | ||
| 338 | #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) | ||
| 339 | #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) | ||
| 340 | #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) | ||
| 341 | #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) | ||
| 342 | #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) | ||
| 343 | #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) | ||
| 344 | |||
| 345 | /* Define the bits in register CSCDR2 */ | ||
| 346 | #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) | ||
| 347 | #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) | ||
| 348 | #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) | ||
| 349 | #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) | ||
| 350 | #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) | ||
| 351 | #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) | ||
| 352 | #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) | ||
| 353 | #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) | ||
| 354 | #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) | ||
| 355 | #define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) | ||
| 356 | #define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) | ||
| 357 | #define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) | ||
| 358 | |||
| 359 | /* Define the bits in register CSCDR3 */ | ||
| 360 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) | ||
| 361 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) | ||
| 362 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) | ||
| 363 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) | ||
| 364 | #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) | ||
| 365 | #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) | ||
| 366 | #define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) | ||
| 367 | #define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) | ||
| 368 | |||
| 369 | /* Define the bits in register CSCDR4 */ | ||
| 370 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) | ||
| 371 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) | ||
| 372 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) | ||
| 373 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) | ||
| 374 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) | ||
| 375 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) | ||
| 376 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) | ||
| 377 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) | ||
| 378 | |||
| 379 | /* Define the bits in register CDHIPR */ | ||
| 380 | #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) | ||
| 381 | #define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) | ||
| 382 | #define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) | ||
| 383 | #define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) | ||
| 384 | #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) | ||
| 385 | #define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) | ||
| 386 | #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) | ||
| 387 | #define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) | ||
| 388 | #define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) | ||
| 389 | #define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) | ||
| 390 | |||
| 391 | /* Define the bits in register CDCR */ | ||
| 392 | #define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) | ||
| 393 | #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) | ||
| 394 | #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) | ||
| 395 | |||
| 396 | /* Define the bits in register CLPCR */ | ||
| 397 | #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) | ||
| 398 | #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) | ||
| 399 | #define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) | ||
| 400 | #define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) | ||
| 401 | #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) | ||
| 402 | #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) | ||
| 403 | #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) | ||
| 404 | #define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) | ||
| 405 | #define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) | ||
| 406 | #define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) | ||
| 407 | #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) | ||
| 408 | #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) | ||
| 409 | #define MXC_CCM_CLPCR_VSTBY (0x1 << 8) | ||
| 410 | #define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) | ||
| 411 | #define MXC_CCM_CLPCR_SBYOS (0x1 << 6) | ||
| 412 | #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) | ||
| 413 | #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) | ||
| 414 | #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) | ||
| 415 | #define MXC_CCM_CLPCR_LPM_OFFSET (0) | ||
| 416 | #define MXC_CCM_CLPCR_LPM_MASK (0x3) | ||
| 417 | |||
| 418 | /* Define the bits in register CISR */ | ||
| 419 | #define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) | ||
| 420 | #define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) | ||
| 421 | #define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) | ||
| 422 | #define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) | ||
| 423 | #define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) | ||
| 424 | #define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) | ||
| 425 | #define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) | ||
| 426 | #define MXC_CCM_CISR_COSC_READY (0x1 << 6) | ||
| 427 | #define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) | ||
| 428 | #define MXC_CCM_CISR_CKIH_READY (0x1 << 4) | ||
| 429 | #define MXC_CCM_CISR_FPM_READY (0x1 << 3) | ||
| 430 | #define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) | ||
| 431 | #define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) | ||
| 432 | #define MXC_CCM_CISR_LRF_PLL1 (0x1) | ||
| 433 | |||
| 434 | /* Define the bits in register CIMR */ | ||
| 435 | #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) | ||
| 436 | #define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) | ||
| 437 | #define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) | ||
| 438 | #define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) | ||
| 439 | #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) | ||
| 440 | #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) | ||
| 441 | #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) | ||
| 442 | #define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) | ||
| 443 | #define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) | ||
| 444 | #define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) | ||
| 445 | #define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) | ||
| 446 | #define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) | ||
| 447 | #define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) | ||
| 448 | |||
| 449 | /* Define the bits in register CCOSR */ | ||
| 450 | #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) | ||
| 451 | #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) | ||
| 452 | #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) | ||
| 453 | #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) | ||
| 454 | #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) | ||
| 455 | #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) | ||
| 456 | #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) | ||
| 457 | #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) | ||
| 458 | #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) | ||
| 459 | #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) | ||
| 460 | |||
| 461 | /* Define the bits in registers CGPR */ | ||
| 462 | #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) | ||
| 463 | #define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) | ||
| 464 | #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) | ||
| 465 | #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) | ||
| 466 | |||
| 467 | /* Define the bits in registers CCGRx */ | ||
| 468 | #define MXC_CCM_CCGRx_CG_MASK 0x3 | ||
| 469 | #define MXC_CCM_CCGRx_MOD_OFF 0x0 | ||
| 470 | #define MXC_CCM_CCGRx_MOD_ON 0x3 | ||
| 471 | #define MXC_CCM_CCGRx_MOD_IDLE 0x1 | ||
| 472 | |||
| 473 | #define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) | ||
| 474 | #define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) | ||
| 475 | #define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) | ||
| 476 | #define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) | ||
| 477 | #define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) | ||
| 478 | #define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) | ||
| 479 | #define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) | ||
| 480 | #define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) | ||
| 481 | #define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) | ||
| 482 | #define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) | ||
| 483 | #define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) | ||
| 484 | #define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) | ||
| 485 | #define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) | ||
| 486 | #define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) | ||
| 487 | |||
| 488 | #define MXC_CCM_CCGRx_CG15_OFFSET 30 | ||
| 489 | #define MXC_CCM_CCGRx_CG14_OFFSET 28 | ||
| 490 | #define MXC_CCM_CCGRx_CG13_OFFSET 26 | ||
| 491 | #define MXC_CCM_CCGRx_CG12_OFFSET 24 | ||
| 492 | #define MXC_CCM_CCGRx_CG11_OFFSET 22 | ||
| 493 | #define MXC_CCM_CCGRx_CG10_OFFSET 20 | ||
| 494 | #define MXC_CCM_CCGRx_CG9_OFFSET 18 | ||
| 495 | #define MXC_CCM_CCGRx_CG8_OFFSET 16 | ||
| 496 | #define MXC_CCM_CCGRx_CG7_OFFSET 14 | ||
| 497 | #define MXC_CCM_CCGRx_CG6_OFFSET 12 | ||
| 498 | #define MXC_CCM_CCGRx_CG5_OFFSET 10 | ||
| 499 | #define MXC_CCM_CCGRx_CG4_OFFSET 8 | ||
| 500 | #define MXC_CCM_CCGRx_CG3_OFFSET 6 | ||
| 501 | #define MXC_CCM_CCGRx_CG2_OFFSET 4 | ||
| 502 | #define MXC_CCM_CCGRx_CG1_OFFSET 2 | ||
| 503 | #define MXC_CCM_CCGRx_CG0_OFFSET 0 | ||
| 504 | |||
| 505 | #define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) | ||
| 506 | #define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) | ||
| 507 | #define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) | ||
| 508 | #define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) | ||
| 509 | #define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) | ||
| 510 | #define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) | ||
| 511 | #define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) | ||
| 512 | #define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) | ||
| 513 | #define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) | ||
| 514 | #define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) | ||
| 515 | #define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) | ||
| 516 | #define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) | ||
| 517 | #define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) | ||
| 518 | |||
| 519 | /* CORTEXA8 platform */ | ||
| 520 | #define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) | ||
| 521 | #define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) | ||
| 522 | #define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) | ||
| 523 | #define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) | ||
| 524 | #define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) | ||
| 525 | #define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) | ||
| 526 | #define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) | ||
| 527 | #define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) | ||
| 528 | #define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) | ||
| 529 | |||
| 530 | /* DVFS CORE */ | ||
| 531 | #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) | ||
| 532 | #define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) | ||
| 533 | #define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) | ||
| 534 | #define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) | ||
| 535 | #define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) | ||
| 536 | #define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) | ||
| 537 | #define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) | ||
| 538 | #define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) | ||
| 539 | #define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) | ||
| 540 | #define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) | ||
| 541 | #define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) | ||
| 542 | #define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) | ||
| 543 | #define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) | ||
| 544 | #define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) | ||
| 545 | #define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) | ||
| 546 | #define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) | ||
| 547 | #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) | ||
| 548 | |||
| 549 | /* GPC */ | ||
| 550 | #define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) | ||
| 551 | #define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) | ||
| 552 | #define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) | ||
| 553 | #define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) | ||
| 554 | #define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) | ||
| 555 | #define MXC_GPC_PGR_ARMPG_OFFSET 8 | ||
| 556 | #define MXC_GPC_PGR_ARMPG_MASK (3 << 8) | ||
| 557 | |||
| 558 | /* PGC */ | ||
| 559 | #define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) | ||
| 560 | #define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) | ||
| 561 | #define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) | ||
| 562 | #define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) | ||
| 563 | #define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) | ||
| 564 | #define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) | ||
| 565 | |||
| 566 | #define MXC_PGCR_PCR 1 | ||
| 567 | #define MXC_SRPGCR_PCR 1 | ||
| 568 | #define MXC_EMPGCR_PCR 1 | ||
| 569 | #define MXC_PGSR_PSR 1 | ||
| 570 | |||
| 571 | |||
| 572 | #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) | ||
| 573 | #define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) | ||
| 574 | |||
| 575 | /* SRPG */ | ||
| 576 | #define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) | ||
| 577 | #define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) | ||
| 578 | #define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) | ||
| 579 | |||
| 580 | #define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) | ||
| 581 | #define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) | ||
| 582 | #define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) | ||
| 583 | |||
| 584 | #define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) | ||
| 585 | #define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) | ||
| 586 | #define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) | ||
| 587 | |||
| 588 | #define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) | ||
| 589 | #define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) | ||
| 590 | #define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) | ||
| 591 | |||
| 592 | #define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) | ||
| 593 | #define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) | ||
| 594 | #define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) | ||
| 595 | |||
| 596 | #define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) | ||
| 597 | #define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) | ||
| 598 | #define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) | ||
| 599 | |||
| 600 | #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ | ||
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h deleted file mode 100644 index 26389f35a2b2..000000000000 --- a/arch/arm/mach-imx/devices-imx51.h +++ /dev/null | |||
| @@ -1,66 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include "devices/devices-common.h" | ||
| 10 | |||
| 11 | extern const struct imx_fec_data imx51_fec_data; | ||
| 12 | #define imx51_add_fec(pdata) \ | ||
| 13 | imx_add_fec(&imx51_fec_data, pdata) | ||
| 14 | |||
| 15 | extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data; | ||
| 16 | #define imx51_add_fsl_usb2_udc(pdata) \ | ||
| 17 | imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata) | ||
| 18 | |||
| 19 | extern const struct imx_imx_i2c_data imx51_imx_i2c_data[]; | ||
| 20 | #define imx51_add_imx_i2c(id, pdata) \ | ||
| 21 | imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) | ||
| 22 | #define imx51_add_hsi2c(pdata) \ | ||
| 23 | imx51_add_imx_i2c(2, pdata) | ||
| 24 | |||
| 25 | extern const struct imx_imx_ssi_data imx51_imx_ssi_data[]; | ||
| 26 | #define imx51_add_imx_ssi(id, pdata) \ | ||
| 27 | imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata) | ||
| 28 | |||
| 29 | extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[]; | ||
| 30 | #define imx51_add_imx_uart(id, pdata) \ | ||
| 31 | imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) | ||
| 32 | |||
| 33 | extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data; | ||
| 34 | #define imx51_add_mxc_ehci_otg(pdata) \ | ||
| 35 | imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata) | ||
| 36 | extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[]; | ||
| 37 | #define imx51_add_mxc_ehci_hs(id, pdata) \ | ||
| 38 | imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata) | ||
| 39 | |||
| 40 | extern const struct imx_mxc_nand_data imx51_mxc_nand_data; | ||
| 41 | #define imx51_add_mxc_nand(pdata) \ | ||
| 42 | imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) | ||
| 43 | |||
| 44 | extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[]; | ||
| 45 | #define imx51_add_sdhci_esdhc_imx(id, pdata) \ | ||
| 46 | imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata) | ||
| 47 | |||
| 48 | extern const struct imx_spi_imx_data imx51_cspi_data; | ||
| 49 | #define imx51_add_cspi(pdata) \ | ||
| 50 | imx_add_spi_imx(&imx51_cspi_data, pdata) | ||
| 51 | |||
| 52 | extern const struct imx_spi_imx_data imx51_ecspi_data[]; | ||
| 53 | #define imx51_add_ecspi(id, pdata) \ | ||
| 54 | imx_add_spi_imx(&imx51_ecspi_data[id], pdata) | ||
| 55 | |||
| 56 | extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[]; | ||
| 57 | #define imx51_add_imx2_wdt(id) \ | ||
| 58 | imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) | ||
| 59 | |||
| 60 | extern const struct imx_imx_keypad_data imx51_imx_keypad_data; | ||
| 61 | #define imx51_add_imx_keypad(pdata) \ | ||
| 62 | imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) | ||
| 63 | |||
| 64 | extern const struct imx_pata_imx_data imx51_pata_imx_data; | ||
| 65 | #define imx51_add_pata_imx() \ | ||
| 66 | imx_add_pata_imx(&imx51_pata_imx_data) | ||
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig index 2d260a5a307c..1d2cc1805f3e 100644 --- a/arch/arm/mach-imx/devices/Kconfig +++ b/arch/arm/mach-imx/devices/Kconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | config IMX_HAVE_PLATFORM_FEC | 1 | config IMX_HAVE_PLATFORM_FEC |
| 2 | bool | 2 | bool |
| 3 | default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 | 3 | default y if SOC_IMX25 || SOC_IMX27 || SOC_IMX35 |
| 4 | 4 | ||
| 5 | config IMX_HAVE_PLATFORM_FLEXCAN | 5 | config IMX_HAVE_PLATFORM_FLEXCAN |
| 6 | bool | 6 | bool |
| @@ -10,7 +10,6 @@ config IMX_HAVE_PLATFORM_FSL_USB2_UDC | |||
| 10 | 10 | ||
| 11 | config IMX_HAVE_PLATFORM_GPIO_KEYS | 11 | config IMX_HAVE_PLATFORM_GPIO_KEYS |
| 12 | bool | 12 | bool |
| 13 | default y if SOC_IMX51 | ||
| 14 | 13 | ||
| 15 | config IMX_HAVE_PLATFORM_IMX21_HCD | 14 | config IMX_HAVE_PLATFORM_IMX21_HCD |
| 16 | bool | 15 | bool |
| @@ -43,15 +42,9 @@ config IMX_HAVE_PLATFORM_IMX_SSI | |||
| 43 | config IMX_HAVE_PLATFORM_IMX_UART | 42 | config IMX_HAVE_PLATFORM_IMX_UART |
| 44 | bool | 43 | bool |
| 45 | 44 | ||
| 46 | config IMX_HAVE_PLATFORM_IMX_UDC | ||
| 47 | bool | ||
| 48 | |||
| 49 | config IMX_HAVE_PLATFORM_IPU_CORE | 45 | config IMX_HAVE_PLATFORM_IPU_CORE |
| 50 | bool | 46 | bool |
| 51 | 47 | ||
| 52 | config IMX_HAVE_PLATFORM_MX1_CAMERA | ||
| 53 | bool | ||
| 54 | |||
| 55 | config IMX_HAVE_PLATFORM_MX2_CAMERA | 48 | config IMX_HAVE_PLATFORM_MX2_CAMERA |
| 56 | bool | 49 | bool |
| 57 | 50 | ||
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile index 1cbc14cd80d1..8fdb12b4ca7e 100644 --- a/arch/arm/mach-imx/devices/Makefile +++ b/arch/arm/mach-imx/devices/Makefile | |||
| @@ -16,9 +16,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o | |||
| 16 | obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o | 16 | obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o |
| 17 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o | 17 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o |
| 18 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o | 18 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o |
| 19 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o | ||
| 20 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o | 19 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o |
| 21 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o | ||
| 22 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o | 20 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o |
| 23 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o | 21 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o |
| 24 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o | 22 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o |
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h index 61352a80bb59..67f7fb13050d 100644 --- a/arch/arm/mach-imx/devices/devices-common.h +++ b/arch/arm/mach-imx/devices/devices-common.h | |||
| @@ -176,22 +176,6 @@ struct platform_device *__init imx_add_imx_uart_1irq( | |||
| 176 | const struct imx_imx_uart_1irq_data *data, | 176 | const struct imx_imx_uart_1irq_data *data, |
| 177 | const struct imxuart_platform_data *pdata); | 177 | const struct imxuart_platform_data *pdata); |
| 178 | 178 | ||
| 179 | #include <linux/platform_data/usb-imx_udc.h> | ||
| 180 | struct imx_imx_udc_data { | ||
| 181 | resource_size_t iobase; | ||
| 182 | resource_size_t iosize; | ||
| 183 | resource_size_t irq0; | ||
| 184 | resource_size_t irq1; | ||
| 185 | resource_size_t irq2; | ||
| 186 | resource_size_t irq3; | ||
| 187 | resource_size_t irq4; | ||
| 188 | resource_size_t irq5; | ||
| 189 | resource_size_t irq6; | ||
| 190 | }; | ||
| 191 | struct platform_device *__init imx_add_imx_udc( | ||
| 192 | const struct imx_imx_udc_data *data, | ||
| 193 | const struct imxusb_platform_data *pdata); | ||
| 194 | |||
| 195 | #include <linux/platform_data/video-mx3fb.h> | 179 | #include <linux/platform_data/video-mx3fb.h> |
| 196 | #include <linux/platform_data/camera-mx3.h> | 180 | #include <linux/platform_data/camera-mx3.h> |
| 197 | struct imx_ipu_core_data { | 181 | struct imx_ipu_core_data { |
| @@ -208,16 +192,6 @@ struct platform_device *__init imx_add_mx3_sdc_fb( | |||
| 208 | const struct imx_ipu_core_data *data, | 192 | const struct imx_ipu_core_data *data, |
| 209 | struct mx3fb_platform_data *pdata); | 193 | struct mx3fb_platform_data *pdata); |
| 210 | 194 | ||
| 211 | #include <linux/platform_data/camera-mx1.h> | ||
| 212 | struct imx_mx1_camera_data { | ||
| 213 | resource_size_t iobase; | ||
| 214 | resource_size_t iosize; | ||
| 215 | resource_size_t irq; | ||
| 216 | }; | ||
| 217 | struct platform_device *__init imx_add_mx1_camera( | ||
| 218 | const struct imx_mx1_camera_data *data, | ||
| 219 | const struct mx1_camera_pdata *pdata); | ||
| 220 | |||
| 221 | #include <linux/platform_data/camera-mx2.h> | 195 | #include <linux/platform_data/camera-mx2.h> |
| 222 | struct imx_mx2_camera_data { | 196 | struct imx_mx2_camera_data { |
| 223 | const char *devid; | 197 | const char *devid; |
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c index 63eba08f87b1..d86f9250b4ee 100644 --- a/arch/arm/mach-imx/devices/platform-fec.c +++ b/arch/arm/mach-imx/devices/platform-fec.c | |||
| @@ -35,18 +35,6 @@ const struct imx_fec_data imx35_fec_data __initconst = | |||
| 35 | imx_fec_data_entry_single(MX35, "imx27-fec"); | 35 | imx_fec_data_entry_single(MX35, "imx27-fec"); |
| 36 | #endif | 36 | #endif |
| 37 | 37 | ||
| 38 | #ifdef CONFIG_SOC_IMX51 | ||
| 39 | /* i.mx51 has the i.mx27 type fec */ | ||
| 40 | const struct imx_fec_data imx51_fec_data __initconst = | ||
| 41 | imx_fec_data_entry_single(MX51, "imx27-fec"); | ||
| 42 | #endif | ||
| 43 | |||
| 44 | #ifdef CONFIG_SOC_IMX53 | ||
| 45 | /* i.mx53 has the i.mx25 type fec */ | ||
| 46 | const struct imx_fec_data imx53_fec_data __initconst = | ||
| 47 | imx_fec_data_entry_single(MX53, "imx25-fec"); | ||
| 48 | #endif | ||
| 49 | |||
| 50 | struct platform_device *__init imx_add_fec( | 38 | struct platform_device *__init imx_add_fec( |
| 51 | const struct imx_fec_data *data, | 39 | const struct imx_fec_data *data, |
| 52 | const struct fec_platform_data *pdata) | 40 | const struct fec_platform_data *pdata) |
diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c index 3c06bd96e9cc..23b0061347cb 100644 --- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c +++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c | |||
| @@ -38,11 +38,6 @@ const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = | |||
| 38 | imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27"); | 38 | imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27"); |
| 39 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 39 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 40 | 40 | ||
| 41 | #ifdef CONFIG_SOC_IMX51 | ||
| 42 | const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst = | ||
| 43 | imx_fsl_usb2_udc_data_entry_single(MX51, "imx-udc-mx51"); | ||
| 44 | #endif | ||
| 45 | |||
| 46 | struct platform_device *__init imx_add_fsl_usb2_udc( | 41 | struct platform_device *__init imx_add_fsl_usb2_udc( |
| 47 | const struct imx_fsl_usb2_udc_data *data, | 42 | const struct imx_fsl_usb2_udc_data *data, |
| 48 | const struct fsl_usb2_platform_data *pdata) | 43 | const struct fsl_usb2_platform_data *pdata) |
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c index 57d342e85c2f..644ac2689882 100644 --- a/arch/arm/mach-imx/devices/platform-imx-i2c.c +++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c | |||
| @@ -70,32 +70,6 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { | |||
| 70 | }; | 70 | }; |
| 71 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 71 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 72 | 72 | ||
| 73 | #ifdef CONFIG_SOC_IMX51 | ||
| 74 | const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { | ||
| 75 | #define imx51_imx_i2c_data_entry(_id, _hwid) \ | ||
| 76 | imx_imx_i2c_data_entry(MX51, "imx21-i2c", _id, _hwid, SZ_4K) | ||
| 77 | imx51_imx_i2c_data_entry(0, 1), | ||
| 78 | imx51_imx_i2c_data_entry(1, 2), | ||
| 79 | { | ||
| 80 | .devid = "imx21-i2c", | ||
| 81 | .id = 2, | ||
| 82 | .iobase = MX51_HSI2C_DMA_BASE_ADDR, | ||
| 83 | .iosize = SZ_16K, | ||
| 84 | .irq = MX51_INT_HS_I2C, | ||
| 85 | }, | ||
| 86 | }; | ||
| 87 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 88 | |||
| 89 | #ifdef CONFIG_SOC_IMX53 | ||
| 90 | const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = { | ||
| 91 | #define imx53_imx_i2c_data_entry(_id, _hwid) \ | ||
| 92 | imx_imx_i2c_data_entry(MX53, "imx21-i2c", _id, _hwid, SZ_4K) | ||
| 93 | imx53_imx_i2c_data_entry(0, 1), | ||
| 94 | imx53_imx_i2c_data_entry(1, 2), | ||
| 95 | imx53_imx_i2c_data_entry(2, 3), | ||
| 96 | }; | ||
| 97 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
| 98 | |||
| 99 | struct platform_device *__init imx_add_imx_i2c( | 73 | struct platform_device *__init imx_add_imx_i2c( |
| 100 | const struct imx_imx_i2c_data *data, | 74 | const struct imx_imx_i2c_data *data, |
| 101 | const struct imxi2c_platform_data *pdata) | 75 | const struct imxi2c_platform_data *pdata) |
diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c index 8f22a4c98a4c..f42200b7aca9 100644 --- a/arch/arm/mach-imx/devices/platform-imx-keypad.c +++ b/arch/arm/mach-imx/devices/platform-imx-keypad.c | |||
| @@ -41,16 +41,6 @@ const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = | |||
| 41 | imx_imx_keypad_data_entry_single(MX35, SZ_16); | 41 | imx_imx_keypad_data_entry_single(MX35, SZ_16); |
| 42 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 42 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 43 | 43 | ||
| 44 | #ifdef CONFIG_SOC_IMX51 | ||
| 45 | const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst = | ||
| 46 | imx_imx_keypad_data_entry_single(MX51, SZ_16); | ||
| 47 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 48 | |||
| 49 | #ifdef CONFIG_SOC_IMX53 | ||
| 50 | const struct imx_imx_keypad_data imx53_imx_keypad_data __initconst = | ||
| 51 | imx_imx_keypad_data_entry_single(MX53, SZ_16); | ||
| 52 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
| 53 | |||
| 54 | struct platform_device *__init imx_add_imx_keypad( | 44 | struct platform_device *__init imx_add_imx_keypad( |
| 55 | const struct imx_imx_keypad_data *data, | 45 | const struct imx_imx_keypad_data *data, |
| 56 | const struct matrix_keymap_data *pdata) | 46 | const struct matrix_keymap_data *pdata) |
diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c index bfcb8f3dfa8d..1c7c721ebff1 100644 --- a/arch/arm/mach-imx/devices/platform-imx-ssi.c +++ b/arch/arm/mach-imx/devices/platform-imx-ssi.c | |||
| @@ -66,26 +66,6 @@ const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { | |||
| 66 | }; | 66 | }; |
| 67 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 67 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 68 | 68 | ||
| 69 | #ifdef CONFIG_SOC_IMX51 | ||
| 70 | const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { | ||
| 71 | #define imx51_imx_ssi_data_entry(_id, _hwid) \ | ||
| 72 | imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_16K) | ||
| 73 | imx51_imx_ssi_data_entry(0, 1), | ||
| 74 | imx51_imx_ssi_data_entry(1, 2), | ||
| 75 | imx51_imx_ssi_data_entry(2, 3), | ||
| 76 | }; | ||
| 77 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 78 | |||
| 79 | #ifdef CONFIG_SOC_IMX53 | ||
| 80 | const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = { | ||
| 81 | #define imx53_imx_ssi_data_entry(_id, _hwid) \ | ||
| 82 | imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_16K) | ||
| 83 | imx53_imx_ssi_data_entry(0, 1), | ||
| 84 | imx53_imx_ssi_data_entry(1, 2), | ||
| 85 | imx53_imx_ssi_data_entry(2, 3), | ||
| 86 | }; | ||
| 87 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
| 88 | |||
| 89 | struct platform_device *__init imx_add_imx_ssi( | 69 | struct platform_device *__init imx_add_imx_ssi( |
| 90 | const struct imx_imx_ssi_data *data, | 70 | const struct imx_imx_ssi_data *data, |
| 91 | const struct imx_ssi_platform_data *pdata) | 71 | const struct imx_ssi_platform_data *pdata) |
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c index faac4aa6ca6d..8c01836bc1d4 100644 --- a/arch/arm/mach-imx/devices/platform-imx-uart.c +++ b/arch/arm/mach-imx/devices/platform-imx-uart.c | |||
| @@ -94,28 +94,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { | |||
| 94 | }; | 94 | }; |
| 95 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 95 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 96 | 96 | ||
| 97 | #ifdef CONFIG_SOC_IMX51 | ||
| 98 | const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { | ||
| 99 | #define imx51_imx_uart_data_entry(_id, _hwid) \ | ||
| 100 | imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) | ||
| 101 | imx51_imx_uart_data_entry(0, 1), | ||
| 102 | imx51_imx_uart_data_entry(1, 2), | ||
| 103 | imx51_imx_uart_data_entry(2, 3), | ||
| 104 | }; | ||
| 105 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 106 | |||
| 107 | #ifdef CONFIG_SOC_IMX53 | ||
| 108 | const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = { | ||
| 109 | #define imx53_imx_uart_data_entry(_id, _hwid) \ | ||
| 110 | imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K) | ||
| 111 | imx53_imx_uart_data_entry(0, 1), | ||
| 112 | imx53_imx_uart_data_entry(1, 2), | ||
| 113 | imx53_imx_uart_data_entry(2, 3), | ||
| 114 | imx53_imx_uart_data_entry(3, 4), | ||
| 115 | imx53_imx_uart_data_entry(4, 5), | ||
| 116 | }; | ||
| 117 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
| 118 | |||
| 119 | struct platform_device *__init imx_add_imx_uart_3irq( | 97 | struct platform_device *__init imx_add_imx_uart_3irq( |
| 120 | const struct imx_imx_uart_3irq_data *data, | 98 | const struct imx_imx_uart_3irq_data *data, |
| 121 | const struct imxuart_platform_data *pdata) | 99 | const struct imxuart_platform_data *pdata) |
diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c index ec75d6413686..54f63bc25ca4 100644 --- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c +++ b/arch/arm/mach-imx/devices/platform-imx2-wdt.c | |||
| @@ -45,24 +45,6 @@ const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = | |||
| 45 | imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K); | 45 | imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K); |
| 46 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 46 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 47 | 47 | ||
| 48 | #ifdef CONFIG_SOC_IMX51 | ||
| 49 | const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = { | ||
| 50 | #define imx51_imx2_wdt_data_entry(_id, _hwid) \ | ||
| 51 | imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K) | ||
| 52 | imx51_imx2_wdt_data_entry(0, 1), | ||
| 53 | imx51_imx2_wdt_data_entry(1, 2), | ||
| 54 | }; | ||
| 55 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 56 | |||
| 57 | #ifdef CONFIG_SOC_IMX53 | ||
| 58 | const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = { | ||
| 59 | #define imx53_imx2_wdt_data_entry(_id, _hwid) \ | ||
| 60 | imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K) | ||
| 61 | imx53_imx2_wdt_data_entry(0, 1), | ||
| 62 | imx53_imx2_wdt_data_entry(1, 2), | ||
| 63 | }; | ||
| 64 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
| 65 | |||
| 66 | struct platform_device *__init imx_add_imx2_wdt( | 48 | struct platform_device *__init imx_add_imx2_wdt( |
| 67 | const struct imx_imx2_wdt_data *data) | 49 | const struct imx_imx2_wdt_data *data) |
| 68 | { | 50 | { |
diff --git a/arch/arm/mach-imx/devices/platform-imx_udc.c b/arch/arm/mach-imx/devices/platform-imx_udc.c deleted file mode 100644 index 5ced7e4e2c71..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx_udc.c +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include "../hardware.h" | ||
| 10 | #include "devices-common.h" | ||
| 11 | |||
| 12 | #define imx_imx_udc_data_entry_single(soc, _size) \ | ||
| 13 | { \ | ||
| 14 | .iobase = soc ## _USBD_BASE_ADDR, \ | ||
| 15 | .iosize = _size, \ | ||
| 16 | .irq0 = soc ## _INT_USBD0, \ | ||
| 17 | .irq1 = soc ## _INT_USBD1, \ | ||
| 18 | .irq2 = soc ## _INT_USBD2, \ | ||
| 19 | .irq3 = soc ## _INT_USBD3, \ | ||
| 20 | .irq4 = soc ## _INT_USBD4, \ | ||
| 21 | .irq5 = soc ## _INT_USBD5, \ | ||
| 22 | .irq6 = soc ## _INT_USBD6, \ | ||
| 23 | } | ||
| 24 | |||
| 25 | #define imx_imx_udc_data_entry(soc, _size) \ | ||
| 26 | [_id] = imx_imx_udc_data_entry_single(soc, _size) | ||
| 27 | |||
| 28 | #ifdef CONFIG_SOC_IMX1 | ||
| 29 | const struct imx_imx_udc_data imx1_imx_udc_data __initconst = | ||
| 30 | imx_imx_udc_data_entry_single(MX1, SZ_4K); | ||
| 31 | #endif /* ifdef CONFIG_SOC_IMX1 */ | ||
| 32 | |||
| 33 | struct platform_device *__init imx_add_imx_udc( | ||
| 34 | const struct imx_imx_udc_data *data, | ||
| 35 | const struct imxusb_platform_data *pdata) | ||
| 36 | { | ||
| 37 | struct resource res[] = { | ||
| 38 | { | ||
| 39 | .start = data->iobase, | ||
| 40 | .end = data->iobase + data->iosize - 1, | ||
| 41 | .flags = IORESOURCE_MEM, | ||
| 42 | }, { | ||
| 43 | .start = data->irq0, | ||
| 44 | .end = data->irq0, | ||
| 45 | .flags = IORESOURCE_IRQ, | ||
| 46 | }, { | ||
| 47 | .start = data->irq1, | ||
| 48 | .end = data->irq1, | ||
| 49 | .flags = IORESOURCE_IRQ, | ||
| 50 | }, { | ||
| 51 | .start = data->irq2, | ||
| 52 | .end = data->irq2, | ||
| 53 | .flags = IORESOURCE_IRQ, | ||
| 54 | }, { | ||
| 55 | .start = data->irq3, | ||
| 56 | .end = data->irq3, | ||
| 57 | .flags = IORESOURCE_IRQ, | ||
| 58 | }, { | ||
| 59 | .start = data->irq4, | ||
| 60 | .end = data->irq4, | ||
| 61 | .flags = IORESOURCE_IRQ, | ||
| 62 | }, { | ||
| 63 | .start = data->irq5, | ||
| 64 | .end = data->irq5, | ||
| 65 | .flags = IORESOURCE_IRQ, | ||
| 66 | }, { | ||
| 67 | .start = data->irq6, | ||
| 68 | .end = data->irq6, | ||
| 69 | .flags = IORESOURCE_IRQ, | ||
| 70 | }, | ||
| 71 | }; | ||
| 72 | |||
| 73 | return imx_add_platform_device("imx_udc", 0, | ||
| 74 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 75 | } | ||
diff --git a/arch/arm/mach-imx/devices/platform-mx1-camera.c b/arch/arm/mach-imx/devices/platform-mx1-camera.c deleted file mode 100644 index 2c6788131080..000000000000 --- a/arch/arm/mach-imx/devices/platform-mx1-camera.c +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include "../hardware.h" | ||
| 10 | #include "devices-common.h" | ||
| 11 | |||
| 12 | #define imx_mx1_camera_data_entry_single(soc, _size) \ | ||
| 13 | { \ | ||
| 14 | .iobase = soc ## _CSI ## _BASE_ADDR, \ | ||
| 15 | .iosize = _size, \ | ||
| 16 | .irq = soc ## _INT_CSI, \ | ||
| 17 | } | ||
| 18 | |||
| 19 | #ifdef CONFIG_SOC_IMX1 | ||
| 20 | const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst = | ||
| 21 | imx_mx1_camera_data_entry_single(MX1, 10); | ||
| 22 | #endif /* ifdef CONFIG_SOC_IMX1 */ | ||
| 23 | |||
| 24 | struct platform_device *__init imx_add_mx1_camera( | ||
| 25 | const struct imx_mx1_camera_data *data, | ||
| 26 | const struct mx1_camera_pdata *pdata) | ||
| 27 | { | ||
| 28 | struct resource res[] = { | ||
| 29 | { | ||
| 30 | .start = data->iobase, | ||
| 31 | .end = data->iobase + data->iosize - 1, | ||
| 32 | .flags = IORESOURCE_MEM, | ||
| 33 | }, { | ||
| 34 | .start = data->irq, | ||
| 35 | .end = data->irq, | ||
| 36 | .flags = IORESOURCE_IRQ, | ||
| 37 | }, | ||
| 38 | }; | ||
| 39 | return imx_add_platform_device_dmamask("mx1-camera", 0, | ||
| 40 | res, ARRAY_SIZE(res), | ||
| 41 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 42 | } | ||
diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c index 5d4bbbfde641..296353662ff0 100644 --- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c +++ b/arch/arm/mach-imx/devices/platform-mxc-ehci.c | |||
| @@ -50,15 +50,6 @@ const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = | |||
| 50 | imx_mxc_ehci_data_entry_single(MX35, 1, HS); | 50 | imx_mxc_ehci_data_entry_single(MX35, 1, HS); |
| 51 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 51 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 52 | 52 | ||
| 53 | #ifdef CONFIG_SOC_IMX51 | ||
| 54 | const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst = | ||
| 55 | imx_mxc_ehci_data_entry_single(MX51, 0, OTG); | ||
| 56 | const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = { | ||
| 57 | imx_mxc_ehci_data_entry_single(MX51, 1, HS1), | ||
| 58 | imx_mxc_ehci_data_entry_single(MX51, 2, HS2), | ||
| 59 | }; | ||
| 60 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 61 | |||
| 62 | struct platform_device *__init imx_add_mxc_ehci( | 53 | struct platform_device *__init imx_add_mxc_ehci( |
| 63 | const struct imx_mxc_ehci_data *data, | 54 | const struct imx_mxc_ehci_data *data, |
| 64 | const struct mxc_usbh_platform_data *pdata) | 55 | const struct mxc_usbh_platform_data *pdata) |
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c index 7af1c53e42b5..fa618a34f462 100644 --- a/arch/arm/mach-imx/devices/platform-mxc_nand.c +++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c | |||
| @@ -54,11 +54,6 @@ const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = | |||
| 54 | imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K); | 54 | imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K); |
| 55 | #endif | 55 | #endif |
| 56 | 56 | ||
| 57 | #ifdef CONFIG_SOC_IMX51 | ||
| 58 | const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = | ||
| 59 | imx_mxc_nandv3_data_entry_single(MX51, "imx51-nand", SZ_16K); | ||
| 60 | #endif | ||
| 61 | |||
| 62 | struct platform_device *__init imx_add_mxc_nand( | 57 | struct platform_device *__init imx_add_mxc_nand( |
| 63 | const struct imx_mxc_nand_data *data, | 58 | const struct imx_mxc_nand_data *data, |
| 64 | const struct mxc_nand_platform_data *pdata) | 59 | const struct mxc_nand_platform_data *pdata) |
diff --git a/arch/arm/mach-imx/devices/platform-mxc_rnga.c b/arch/arm/mach-imx/devices/platform-mxc_rnga.c index c58404badb59..851fbc8af7a9 100644 --- a/arch/arm/mach-imx/devices/platform-mxc_rnga.c +++ b/arch/arm/mach-imx/devices/platform-mxc_rnga.c | |||
| @@ -48,9 +48,6 @@ static int __init imxXX_add_mxc_rnga(void) | |||
| 48 | #endif /* if defined(CONFIG_SOC_IMX31) */ | 48 | #endif /* if defined(CONFIG_SOC_IMX31) */ |
| 49 | ret = ERR_PTR(-ENODEV); | 49 | ret = ERR_PTR(-ENODEV); |
| 50 | 50 | ||
| 51 | if (IS_ERR(ret)) | 51 | return PTR_ERR_OR_ZERO(ret); |
| 52 | return PTR_ERR(ret); | ||
| 53 | |||
| 54 | return 0; | ||
| 55 | } | 52 | } |
| 56 | arch_initcall(imxXX_add_mxc_rnga); | 53 | arch_initcall(imxXX_add_mxc_rnga); |
diff --git a/arch/arm/mach-imx/devices/platform-pata_imx.c b/arch/arm/mach-imx/devices/platform-pata_imx.c index e4ec11c8ce55..1c7f895a69d2 100644 --- a/arch/arm/mach-imx/devices/platform-pata_imx.c +++ b/arch/arm/mach-imx/devices/platform-pata_imx.c | |||
| @@ -28,16 +28,6 @@ const struct imx_pata_imx_data imx35_pata_imx_data __initconst = | |||
| 28 | imx_pata_imx_data_entry_single(MX35, SZ_16K); | 28 | imx_pata_imx_data_entry_single(MX35, SZ_16K); |
| 29 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 29 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 30 | 30 | ||
| 31 | #ifdef CONFIG_SOC_IMX51 | ||
| 32 | const struct imx_pata_imx_data imx51_pata_imx_data __initconst = | ||
| 33 | imx_pata_imx_data_entry_single(MX51, SZ_16K); | ||
| 34 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 35 | |||
| 36 | #ifdef CONFIG_SOC_IMX53 | ||
| 37 | const struct imx_pata_imx_data imx53_pata_imx_data __initconst = | ||
| 38 | imx_pata_imx_data_entry_single(MX53, SZ_16K); | ||
| 39 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
| 40 | |||
| 41 | struct platform_device *__init imx_add_pata_imx( | 31 | struct platform_device *__init imx_add_pata_imx( |
| 42 | const struct imx_pata_imx_data *data) | 32 | const struct imx_pata_imx_data *data) |
| 43 | { | 33 | { |
diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c index e66a4e316311..fb8d4a2ad48c 100644 --- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c +++ b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c | |||
| @@ -43,30 +43,6 @@ imx35_sdhci_esdhc_imx_data[] __initconst = { | |||
| 43 | }; | 43 | }; |
| 44 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 44 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 45 | 45 | ||
| 46 | #ifdef CONFIG_SOC_IMX51 | ||
| 47 | const struct imx_sdhci_esdhc_imx_data | ||
| 48 | imx51_sdhci_esdhc_imx_data[] __initconst = { | ||
| 49 | #define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \ | ||
| 50 | imx_sdhci_esdhc_imx_data_entry(MX51, "sdhci-esdhc-imx51", _id, _hwid) | ||
| 51 | imx51_sdhci_esdhc_imx_data_entry(0, 1), | ||
| 52 | imx51_sdhci_esdhc_imx_data_entry(1, 2), | ||
| 53 | imx51_sdhci_esdhc_imx_data_entry(2, 3), | ||
| 54 | imx51_sdhci_esdhc_imx_data_entry(3, 4), | ||
| 55 | }; | ||
| 56 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 57 | |||
| 58 | #ifdef CONFIG_SOC_IMX53 | ||
| 59 | const struct imx_sdhci_esdhc_imx_data | ||
| 60 | imx53_sdhci_esdhc_imx_data[] __initconst = { | ||
| 61 | #define imx53_sdhci_esdhc_imx_data_entry(_id, _hwid) \ | ||
| 62 | imx_sdhci_esdhc_imx_data_entry(MX53, "sdhci-esdhc-imx53", _id, _hwid) | ||
| 63 | imx53_sdhci_esdhc_imx_data_entry(0, 1), | ||
| 64 | imx53_sdhci_esdhc_imx_data_entry(1, 2), | ||
| 65 | imx53_sdhci_esdhc_imx_data_entry(2, 3), | ||
| 66 | imx53_sdhci_esdhc_imx_data_entry(3, 4), | ||
| 67 | }; | ||
| 68 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
| 69 | |||
| 70 | static const struct esdhc_platform_data default_esdhc_pdata __initconst = { | 46 | static const struct esdhc_platform_data default_esdhc_pdata __initconst = { |
| 71 | .wp_type = ESDHC_WP_NONE, | 47 | .wp_type = ESDHC_WP_NONE, |
| 72 | .cd_type = ESDHC_CD_NONE, | 48 | .cd_type = ESDHC_CD_NONE, |
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c index 8880bcb11e05..aca825d74c48 100644 --- a/arch/arm/mach-imx/devices/platform-spi_imx.c +++ b/arch/arm/mach-imx/devices/platform-spi_imx.c | |||
| @@ -79,33 +79,6 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { | |||
| 79 | }; | 79 | }; |
| 80 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 80 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 81 | 81 | ||
| 82 | #ifdef CONFIG_SOC_IMX51 | ||
| 83 | /* i.mx51 has the i.mx35 type cspi */ | ||
| 84 | const struct imx_spi_imx_data imx51_cspi_data __initconst = | ||
| 85 | imx_spi_imx_data_entry_single(MX51, CSPI, "imx35-cspi", 2, , SZ_4K); | ||
| 86 | |||
| 87 | const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { | ||
| 88 | #define imx51_ecspi_data_entry(_id, _hwid) \ | ||
| 89 | imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K) | ||
| 90 | imx51_ecspi_data_entry(0, 1), | ||
| 91 | imx51_ecspi_data_entry(1, 2), | ||
| 92 | }; | ||
| 93 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 94 | |||
| 95 | #ifdef CONFIG_SOC_IMX53 | ||
| 96 | /* i.mx53 has the i.mx35 type cspi */ | ||
| 97 | const struct imx_spi_imx_data imx53_cspi_data __initconst = | ||
| 98 | imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 2, , SZ_4K); | ||
| 99 | |||
| 100 | /* i.mx53 has the i.mx51 type ecspi */ | ||
| 101 | const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = { | ||
| 102 | #define imx53_ecspi_data_entry(_id, _hwid) \ | ||
| 103 | imx_spi_imx_data_entry(MX53, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K) | ||
| 104 | imx53_ecspi_data_entry(0, 1), | ||
| 105 | imx53_ecspi_data_entry(1, 2), | ||
| 106 | }; | ||
| 107 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
| 108 | |||
| 109 | struct platform_device *__init imx_add_spi_imx( | 82 | struct platform_device *__init imx_add_spi_imx( |
| 110 | const struct imx_spi_imx_data *data, | 83 | const struct imx_spi_imx_data *data, |
| 111 | const struct spi_imx_master *pdata) | 84 | const struct spi_imx_master *pdata) |
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c index 134c190e3003..42a5a3d14c5f 100644 --- a/arch/arm/mach-imx/ehci-imx25.c +++ b/arch/arm/mach-imx/ehci-imx25.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/platform_data/usb-ehci-mxc.h> | 18 | #include <linux/platform_data/usb-ehci-mxc.h> |
| 19 | 19 | ||
| 20 | #include "ehci.h" | ||
| 20 | #include "hardware.h" | 21 | #include "hardware.h" |
| 21 | 22 | ||
| 22 | #define USBCTRL_OTGBASE_OFFSET 0x600 | 23 | #define USBCTRL_OTGBASE_OFFSET 0x600 |
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c index 448d9115539d..c56974346c16 100644 --- a/arch/arm/mach-imx/ehci-imx27.c +++ b/arch/arm/mach-imx/ehci-imx27.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/platform_data/usb-ehci-mxc.h> | 18 | #include <linux/platform_data/usb-ehci-mxc.h> |
| 19 | 19 | ||
| 20 | #include "ehci.h" | ||
| 20 | #include "hardware.h" | 21 | #include "hardware.h" |
| 21 | 22 | ||
| 22 | #define USBCTRL_OTGBASE_OFFSET 0x600 | 23 | #define USBCTRL_OTGBASE_OFFSET 0x600 |
diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c index 05de4e1e39d7..bede21d9b981 100644 --- a/arch/arm/mach-imx/ehci-imx31.c +++ b/arch/arm/mach-imx/ehci-imx31.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/platform_data/usb-ehci-mxc.h> | 18 | #include <linux/platform_data/usb-ehci-mxc.h> |
| 19 | 19 | ||
| 20 | #include "ehci.h" | ||
| 20 | #include "hardware.h" | 21 | #include "hardware.h" |
| 21 | 22 | ||
| 22 | #define USBCTRL_OTGBASE_OFFSET 0x600 | 23 | #define USBCTRL_OTGBASE_OFFSET 0x600 |
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c index 554e7cccff53..f424a543755c 100644 --- a/arch/arm/mach-imx/ehci-imx35.c +++ b/arch/arm/mach-imx/ehci-imx35.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/platform_data/usb-ehci-mxc.h> | 18 | #include <linux/platform_data/usb-ehci-mxc.h> |
| 19 | 19 | ||
| 20 | #include "ehci.h" | ||
| 20 | #include "hardware.h" | 21 | #include "hardware.h" |
| 21 | 22 | ||
| 22 | #define USBCTRL_OTGBASE_OFFSET 0x600 | 23 | #define USBCTRL_OTGBASE_OFFSET 0x600 |
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c deleted file mode 100644 index e49710b10c68..000000000000 --- a/arch/arm/mach-imx/ehci-imx5.c +++ /dev/null | |||
| @@ -1,171 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> | ||
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of the GNU General Public License as published by the | ||
| 7 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 8 | * option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, but | ||
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
| 12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
| 13 | * for more details. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/platform_data/usb-ehci-mxc.h> | ||
| 19 | |||
| 20 | #include "hardware.h" | ||
| 21 | |||
| 22 | #define MXC_OTG_OFFSET 0 | ||
| 23 | #define MXC_H1_OFFSET 0x200 | ||
| 24 | #define MXC_H2_OFFSET 0x400 | ||
| 25 | |||
| 26 | /* USB_CTRL */ | ||
| 27 | #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ | ||
| 28 | #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ | ||
| 29 | #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ | ||
| 30 | #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ | ||
| 31 | #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ | ||
| 32 | |||
| 33 | /* USB_PHY_CTRL_FUNC */ | ||
| 34 | #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */ | ||
| 35 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ | ||
| 36 | #define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */ | ||
| 37 | #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ | ||
| 38 | #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */ | ||
| 39 | |||
| 40 | /* USBH2CTRL */ | ||
| 41 | #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) | ||
| 42 | #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) | ||
| 43 | #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) | ||
| 44 | |||
| 45 | #define MXC_USBCMD_OFFSET 0x140 | ||
| 46 | |||
| 47 | /* USBCMD */ | ||
| 48 | #define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */ | ||
| 49 | |||
| 50 | int mx51_initialize_usb_hw(int port, unsigned int flags) | ||
| 51 | { | ||
| 52 | unsigned int v; | ||
| 53 | void __iomem *usb_base; | ||
| 54 | void __iomem *usbotg_base; | ||
| 55 | void __iomem *usbother_base; | ||
| 56 | int ret = 0; | ||
| 57 | |||
| 58 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); | ||
| 59 | if (!usb_base) { | ||
| 60 | printk(KERN_ERR "%s(): ioremap failed\n", __func__); | ||
| 61 | return -ENOMEM; | ||
| 62 | } | ||
| 63 | |||
| 64 | switch (port) { | ||
| 65 | case 0: /* OTG port */ | ||
| 66 | usbotg_base = usb_base + MXC_OTG_OFFSET; | ||
| 67 | break; | ||
| 68 | case 1: /* Host 1 port */ | ||
| 69 | usbotg_base = usb_base + MXC_H1_OFFSET; | ||
| 70 | break; | ||
| 71 | case 2: /* Host 2 port */ | ||
| 72 | usbotg_base = usb_base + MXC_H2_OFFSET; | ||
| 73 | break; | ||
| 74 | default: | ||
| 75 | printk(KERN_ERR"%s no such port %d\n", __func__, port); | ||
| 76 | ret = -ENOENT; | ||
| 77 | goto error; | ||
| 78 | } | ||
| 79 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | ||
| 80 | |||
| 81 | switch (port) { | ||
| 82 | case 0: /*OTG port */ | ||
| 83 | if (flags & MXC_EHCI_INTERNAL_PHY) { | ||
| 84 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | ||
| 85 | |||
| 86 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) | ||
| 87 | v |= MXC_OTG_PHYCTRL_OC_POL_BIT; | ||
| 88 | else | ||
| 89 | v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; | ||
| 90 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) { | ||
| 91 | /* OC/USBPWR is used */ | ||
| 92 | v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; | ||
| 93 | } else { | ||
| 94 | /* OC/USBPWR is not used */ | ||
| 95 | v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; | ||
| 96 | } | ||
| 97 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
| 98 | v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; | ||
| 99 | else | ||
| 100 | v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; | ||
| 101 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | ||
| 102 | |||
| 103 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | ||
| 104 | if (flags & MXC_EHCI_WAKEUP_ENABLED) | ||
| 105 | v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ | ||
| 106 | else | ||
| 107 | v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ | ||
| 108 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | ||
| 109 | v &= ~MXC_OTG_UCTRL_OPM_BIT; | ||
| 110 | else | ||
| 111 | v |= MXC_OTG_UCTRL_OPM_BIT; | ||
| 112 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); | ||
| 113 | } | ||
| 114 | break; | ||
| 115 | case 1: /* Host 1 */ | ||
| 116 | /*Host ULPI */ | ||
| 117 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | ||
| 118 | if (flags & MXC_EHCI_WAKEUP_ENABLED) { | ||
| 119 | /* HOST1 wakeup/ULPI intr enable */ | ||
| 120 | v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); | ||
| 121 | } else { | ||
| 122 | /* HOST1 wakeup/ULPI intr disable */ | ||
| 123 | v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); | ||
| 124 | } | ||
| 125 | |||
| 126 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | ||
| 127 | v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/ | ||
| 128 | else | ||
| 129 | v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ | ||
| 130 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); | ||
| 131 | |||
| 132 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | ||
| 133 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) | ||
| 134 | v |= MXC_H1_OC_POL_BIT; | ||
| 135 | else | ||
| 136 | v &= ~MXC_H1_OC_POL_BIT; | ||
| 137 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | ||
| 138 | v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ | ||
| 139 | else | ||
| 140 | v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ | ||
| 141 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | ||
| 142 | |||
| 143 | v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET); | ||
| 144 | if (flags & MXC_EHCI_ITC_NO_THRESHOLD) | ||
| 145 | /* Interrupt Threshold Control:Immediate (no threshold) */ | ||
| 146 | v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; | ||
| 147 | __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); | ||
| 148 | break; | ||
| 149 | case 2: /* Host 2 ULPI */ | ||
| 150 | v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); | ||
| 151 | if (flags & MXC_EHCI_WAKEUP_ENABLED) { | ||
| 152 | /* HOST1 wakeup/ULPI intr enable */ | ||
| 153 | v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); | ||
| 154 | } else { | ||
| 155 | /* HOST1 wakeup/ULPI intr disable */ | ||
| 156 | v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); | ||
| 157 | } | ||
| 158 | |||
| 159 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | ||
| 160 | v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/ | ||
| 161 | else | ||
| 162 | v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ | ||
| 163 | __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); | ||
| 164 | break; | ||
| 165 | } | ||
| 166 | |||
| 167 | error: | ||
| 168 | iounmap(usb_base); | ||
| 169 | return ret; | ||
| 170 | } | ||
| 171 | |||
diff --git a/arch/arm/mach-imx/ehci.h b/arch/arm/mach-imx/ehci.h new file mode 100644 index 000000000000..0e060023db8b --- /dev/null +++ b/arch/arm/mach-imx/ehci.h | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | #ifndef __MACH_IMX_EHCI_H | ||
| 2 | #define __MACH_IMX_EHCI_H | ||
| 3 | |||
| 4 | /* values for portsc field */ | ||
| 5 | #define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) | ||
| 6 | #define MXC_EHCI_FORCE_FS (1 << 24) | ||
| 7 | #define MXC_EHCI_UTMI_8BIT (0 << 28) | ||
| 8 | #define MXC_EHCI_UTMI_16BIT (1 << 28) | ||
| 9 | #define MXC_EHCI_SERIAL (1 << 29) | ||
| 10 | #define MXC_EHCI_MODE_UTMI (0 << 30) | ||
| 11 | #define MXC_EHCI_MODE_PHILIPS (1 << 30) | ||
| 12 | #define MXC_EHCI_MODE_ULPI (2 << 30) | ||
| 13 | #define MXC_EHCI_MODE_SERIAL (3 << 30) | ||
| 14 | |||
| 15 | /* values for flags field */ | ||
| 16 | #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) | ||
| 17 | #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) | ||
| 18 | #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) | ||
| 19 | #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) | ||
| 20 | #define MXC_EHCI_INTERFACE_MASK (0xf) | ||
| 21 | |||
| 22 | #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) | ||
| 23 | #define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) | ||
| 24 | #define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) | ||
| 25 | #define MXC_EHCI_TTL_ENABLED (1 << 8) | ||
| 26 | |||
| 27 | #define MXC_EHCI_INTERNAL_PHY (1 << 9) | ||
| 28 | #define MXC_EHCI_IPPUE_DOWN (1 << 10) | ||
| 29 | #define MXC_EHCI_IPPUE_UP (1 << 11) | ||
| 30 | #define MXC_EHCI_WAKEUP_ENABLED (1 << 12) | ||
| 31 | #define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13) | ||
| 32 | |||
| 33 | #define MXC_USBCTRL_OFFSET 0 | ||
| 34 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 | ||
| 35 | #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc | ||
| 36 | #define MXC_USBH2CTRL_OFFSET 0x14 | ||
| 37 | |||
| 38 | int mx25_initialize_usb_hw(int port, unsigned int flags); | ||
| 39 | int mx31_initialize_usb_hw(int port, unsigned int flags); | ||
| 40 | int mx35_initialize_usb_hw(int port, unsigned int flags); | ||
| 41 | int mx27_initialize_usb_hw(int port, unsigned int flags); | ||
| 42 | |||
| 43 | #endif /* __MACH_IMX_EHCI_H */ | ||
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index 586e0171a652..82ea74e68482 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c | |||
| @@ -27,13 +27,14 @@ static void __iomem *gpc_base; | |||
| 27 | static u32 gpc_wake_irqs[IMR_NUM]; | 27 | static u32 gpc_wake_irqs[IMR_NUM]; |
| 28 | static u32 gpc_saved_imrs[IMR_NUM]; | 28 | static u32 gpc_saved_imrs[IMR_NUM]; |
| 29 | 29 | ||
| 30 | void imx_gpc_pre_suspend(void) | 30 | void imx_gpc_pre_suspend(bool arm_power_off) |
| 31 | { | 31 | { |
| 32 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; | 32 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; |
| 33 | int i; | 33 | int i; |
| 34 | 34 | ||
| 35 | /* Tell GPC to power off ARM core when suspend */ | 35 | /* Tell GPC to power off ARM core when suspend */ |
| 36 | writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN); | 36 | if (arm_power_off) |
| 37 | writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN); | ||
| 37 | 38 | ||
| 38 | for (i = 0; i < IMR_NUM; i++) { | 39 | for (i = 0; i < IMR_NUM; i++) { |
| 39 | gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); | 40 | gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); |
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index abf43bb47eca..66b2b564c463 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h | |||
| @@ -105,8 +105,6 @@ | |||
| 105 | 105 | ||
| 106 | #include "mxc.h" | 106 | #include "mxc.h" |
| 107 | 107 | ||
| 108 | #include "mx51.h" | ||
| 109 | #include "mx53.h" | ||
| 110 | #include "mx3x.h" | 108 | #include "mx3x.h" |
| 111 | #include "mx31.h" | 109 | #include "mx31.h" |
| 112 | #include "mx35.h" | 110 | #include "mx35.h" |
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c index 42a65e067443..cf8032bae277 100644 --- a/arch/arm/mach-imx/imx25-dt.c +++ b/arch/arm/mach-imx/imx25-dt.c | |||
| @@ -29,16 +29,10 @@ static const char * const imx25_dt_board_compat[] __initconst = { | |||
| 29 | NULL | 29 | NULL |
| 30 | }; | 30 | }; |
| 31 | 31 | ||
| 32 | static void __init imx25_timer_init(void) | ||
| 33 | { | ||
| 34 | mx25_clocks_init_dt(); | ||
| 35 | } | ||
| 36 | |||
| 37 | DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") | 32 | DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") |
| 38 | .map_io = mx25_map_io, | 33 | .map_io = mx25_map_io, |
| 39 | .init_early = imx25_init_early, | 34 | .init_early = imx25_init_early, |
| 40 | .init_irq = mx25_init_irq, | 35 | .init_irq = mx25_init_irq, |
| 41 | .init_time = imx25_timer_init, | ||
| 42 | .init_machine = imx25_dt_init, | 36 | .init_machine = imx25_dt_init, |
| 43 | .dt_compat = imx25_dt_board_compat, | 37 | .dt_compat = imx25_dt_board_compat, |
| 44 | .restart = mxc_restart, | 38 | .restart = mxc_restart, |
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c index 17bd4058133d..080e66c6a1d0 100644 --- a/arch/arm/mach-imx/imx27-dt.c +++ b/arch/arm/mach-imx/imx27-dt.c | |||
| @@ -34,16 +34,10 @@ static const char * const imx27_dt_board_compat[] __initconst = { | |||
| 34 | NULL | 34 | NULL |
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | static void __init imx27_timer_init(void) | ||
| 38 | { | ||
| 39 | mx27_clocks_init_dt(); | ||
| 40 | } | ||
| 41 | |||
| 42 | DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)") | 37 | DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)") |
| 43 | .map_io = mx27_map_io, | 38 | .map_io = mx27_map_io, |
| 44 | .init_early = imx27_init_early, | 39 | .init_early = imx27_init_early, |
| 45 | .init_irq = mx27_init_irq, | 40 | .init_irq = mx27_init_irq, |
| 46 | .init_time = imx27_timer_init, | ||
| 47 | .init_machine = imx27_dt_init, | 41 | .init_machine = imx27_dt_init, |
| 48 | .dt_compat = imx27_dt_board_compat, | 42 | .dt_compat = imx27_dt_board_compat, |
| 49 | .restart = mxc_restart, | 43 | .restart = mxc_restart, |
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c index 581f4d6c9b8a..418dbc82adc4 100644 --- a/arch/arm/mach-imx/imx31-dt.c +++ b/arch/arm/mach-imx/imx31-dt.c | |||
| @@ -25,7 +25,7 @@ static void __init imx31_dt_init(void) | |||
| 25 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 25 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 26 | } | 26 | } |
| 27 | 27 | ||
| 28 | static const char *imx31_dt_board_compat[] __initconst = { | 28 | static const char * const imx31_dt_board_compat[] __initconst = { |
| 29 | "fsl,imx31", | 29 | "fsl,imx31", |
| 30 | NULL | 30 | NULL |
| 31 | }; | 31 | }; |
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c index a62854c59240..584fbe105579 100644 --- a/arch/arm/mach-imx/imx35-dt.c +++ b/arch/arm/mach-imx/imx35-dt.c | |||
| @@ -34,7 +34,7 @@ static void __init imx35_irq_init(void) | |||
| 34 | mx35_init_irq(); | 34 | mx35_init_irq(); |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | static const char *imx35_dt_board_compat[] __initconst = { | 37 | static const char * const imx35_dt_board_compat[] __initconst = { |
| 38 | "fsl,imx35", | 38 | "fsl,imx35", |
| 39 | NULL | 39 | NULL |
| 40 | }; | 40 | }; |
diff --git a/arch/arm/mach-imx/iomux-mx51.h b/arch/arm/mach-imx/iomux-mx51.h deleted file mode 100644 index 75bbcc4aa2d2..000000000000 --- a/arch/arm/mach-imx/iomux-mx51.h +++ /dev/null | |||
| @@ -1,827 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> | ||
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_IOMUX_MX51_H__ | ||
| 14 | #define __MACH_IOMUX_MX51_H__ | ||
| 15 | |||
| 16 | #include "iomux-v3.h" | ||
| 17 | #define __NA_ 0x000 | ||
| 18 | |||
| 19 | |||
| 20 | /* Pad control groupings */ | ||
| 21 | #define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ | ||
| 22 | PAD_CTL_HYS | PAD_CTL_SRE_FAST) | ||
| 23 | #define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ | ||
| 24 | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ | ||
| 25 | PAD_CTL_HYS) | ||
| 26 | #define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ | ||
| 27 | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ | ||
| 28 | PAD_CTL_HYS) | ||
| 29 | #define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ | ||
| 30 | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ | ||
| 31 | PAD_CTL_HYS | PAD_CTL_PUE) | ||
| 32 | #define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ | ||
| 33 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) | ||
| 34 | #define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ | ||
| 35 | PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \ | ||
| 36 | PAD_CTL_SRE_FAST | PAD_CTL_DVS) | ||
| 37 | #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) | ||
| 38 | |||
| 39 | #define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) | ||
| 40 | #define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) | ||
| 41 | #define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) | ||
| 42 | #define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) | ||
| 43 | |||
| 44 | /* | ||
| 45 | * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> | ||
| 46 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num> | ||
| 47 | * See also iomux-v3.h | ||
| 48 | */ | ||
| 49 | |||
| 50 | /* Raw pin modes without pad control */ | ||
| 51 | /* PAD MUX ALT INPSE PATH PADCTRL */ | ||
| 52 | |||
| 53 | /* The same pins as above but with the default pad control values applied */ | ||
| 54 | #define MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 55 | #define MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL) | ||
| 56 | #define MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 57 | #define MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 58 | #define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL) | ||
| 59 | #define MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 60 | #define MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 61 | #define MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL) | ||
| 62 | #define MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 63 | #define MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 64 | #define MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL) | ||
| 65 | #define MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 66 | #define MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 67 | #define MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL) | ||
| 68 | #define MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 69 | #define MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 70 | #define MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 71 | #define MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL) | ||
| 72 | #define MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 73 | #define MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 74 | #define MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL) | ||
| 75 | #define MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 76 | #define MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 77 | #define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL) | ||
| 78 | #define MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL) | ||
| 79 | #define MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 80 | #define MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL) | ||
| 81 | #define MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 82 | #define MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 83 | #define MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 84 | #define MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 85 | #define MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL) | ||
| 86 | #define MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 87 | #define MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 88 | #define MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 89 | #define MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 90 | #define MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL) | ||
| 91 | #define MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 92 | #define MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 93 | #define MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 94 | #define MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL) | ||
| 95 | #define MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 96 | #define MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 97 | #define MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 98 | #define MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 99 | #define MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL) | ||
| 100 | #define MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 101 | #define MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 102 | #define MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL) | ||
| 103 | #define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 104 | #define MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 105 | #define MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 106 | #define MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL) | ||
| 107 | #define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 108 | #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) | ||
| 109 | #define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 110 | #define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 111 | #define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 112 | #define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) | ||
| 113 | #define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) | ||
| 114 | #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 115 | #define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 116 | #define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 117 | #define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) | ||
| 118 | #define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 119 | #define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 120 | #define MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL) | ||
| 121 | #define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL) | ||
| 122 | #define MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 123 | #define MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL) | ||
| 124 | #define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 125 | #define MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL) | ||
| 126 | #define MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 127 | #define MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL) | ||
| 128 | #define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 129 | #define MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL) | ||
| 130 | #define MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 131 | #define MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL) | ||
| 132 | #define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 133 | #define MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL) | ||
| 134 | #define MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 135 | #define MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL) | ||
| 136 | #define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 137 | #define MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL) | ||
| 138 | #define MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 139 | #define MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 140 | #define MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 141 | #define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 142 | #define MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 143 | #define MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 144 | #define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 145 | #define MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 146 | #define MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 147 | #define MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 148 | #define MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 149 | #define MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 150 | #define MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 151 | #define MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 152 | #define MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 153 | #define MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 154 | #define MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 155 | #define MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 156 | #define MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 157 | #define MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 158 | #define MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 159 | #define MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 160 | #define MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 161 | #define MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 162 | #define MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 163 | #define MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 164 | #define MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 165 | #define MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 166 | #define MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 167 | #define MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 168 | #define MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 169 | #define MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL) | ||
| 170 | #define MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL) | ||
| 171 | #define MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 172 | #define MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 173 | #define MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 174 | #define MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL) | ||
| 175 | #define MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL) | ||
| 176 | #define MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 177 | #define MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 178 | #define MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 179 | #define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 180 | #define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 181 | #define MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL) | ||
| 182 | #define MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 183 | #define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 184 | #define MX51_PAD_EIM_EB2__FEC_MDIO (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \ | ||
| 185 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ | ||
| 186 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) | ||
| 187 | #define MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 188 | #define MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 189 | #define MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL) | ||
| 190 | #define MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 191 | #define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 192 | #define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL) | ||
| 193 | #define MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 194 | #define MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 195 | #define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 196 | #define MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 197 | #define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 198 | #define MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 199 | #define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 200 | #define MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 201 | #define MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL) | ||
| 202 | #define MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 203 | #define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 204 | #define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL) | ||
| 205 | #define MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 206 | #define MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 207 | #define MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL) | ||
| 208 | #define MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 209 | #define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 210 | #define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL) | ||
| 211 | #define MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 212 | #define MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 213 | #define MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL) | ||
| 214 | #define MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 215 | #define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 216 | #define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2) | ||
| 217 | #define MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 218 | #define MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 219 | #define MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL) | ||
| 220 | #define MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 221 | #define MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL) | ||
| 222 | #define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 223 | #define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2) | ||
| 224 | #define MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 225 | #define MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 226 | #define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 227 | #define MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 228 | #define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 229 | #define MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL) | ||
| 230 | #define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 231 | #define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) | ||
| 232 | #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 233 | #define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 234 | #define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) | ||
| 235 | #define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 236 | #define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 237 | #define MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL) | ||
| 238 | #define MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL) | ||
| 239 | #define MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 240 | #define MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 241 | #define MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL) | ||
| 242 | #define MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL) | ||
| 243 | #define MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 244 | #define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 245 | #define MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL) | ||
| 246 | #define MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 247 | #define MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 248 | #define MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL) | ||
| 249 | #define MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 250 | #define MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 251 | #define MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL) | ||
| 252 | #define MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL) | ||
| 253 | #define MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL) | ||
| 254 | #define MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 255 | #define MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 256 | #define MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL) | ||
| 257 | #define MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL) | ||
| 258 | #define MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 259 | #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 260 | #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 261 | #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 262 | #define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 263 | #define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 264 | #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) | ||
| 265 | #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 266 | #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) | ||
| 267 | #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 268 | #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 269 | #define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 270 | #define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) | ||
| 271 | #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) | ||
| 272 | #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 273 | #define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 274 | #define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2) | ||
| 275 | #define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 276 | #define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 277 | #define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL) | ||
| 278 | #define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL) | ||
| 279 | #define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL) | ||
| 280 | #define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 281 | #define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 282 | #define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 283 | #define MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 284 | #define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 285 | #define MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL) | ||
| 286 | #define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 287 | #define MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 288 | #define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 289 | #define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 290 | #define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) | ||
| 291 | #define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL) | ||
| 292 | #define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 293 | #define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 294 | #define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 295 | #define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 296 | #define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 297 | #define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL) | ||
| 298 | #define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 299 | #define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 300 | #define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 301 | #define MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 302 | #define MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 303 | #define MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL) | ||
| 304 | #define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 305 | #define MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 306 | #define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 307 | #define MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 308 | #define MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 309 | #define MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL) | ||
| 310 | #define MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL) | ||
| 311 | #define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 312 | #define MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 313 | #define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 314 | #define MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 315 | #define MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 316 | #define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 317 | #define MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 318 | #define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 319 | #define MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) | ||
| 320 | #define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 321 | #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4) | ||
| 322 | #define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 323 | #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL) | ||
| 324 | #define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 325 | #define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 326 | #define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 327 | #define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 328 | #define MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 329 | #define MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 330 | #define MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL) | ||
| 331 | #define MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 332 | #define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 333 | #define MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 334 | #define MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 335 | #define MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 336 | #define MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 337 | #define MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 338 | #define MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 339 | #define MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 340 | #define MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL) | ||
| 341 | #define MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 342 | #define MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 343 | #define MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 344 | #define MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 345 | #define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL) | ||
| 346 | #define MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 347 | #define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 348 | #define MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 349 | #define MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL) | ||
| 350 | #define MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 351 | #define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 352 | #define MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 353 | #define MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL) | ||
| 354 | #define MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4) | ||
| 355 | #define MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 356 | #define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 357 | #define MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 358 | #define MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL) | ||
| 359 | #define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 360 | #define MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 361 | #define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 362 | #define MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 363 | #define MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL) | ||
| 364 | #define MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 365 | #define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 366 | #define MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 367 | #define MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL) | ||
| 368 | #define MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 369 | #define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 370 | #define MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 371 | #define MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 372 | #define MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL) | ||
| 373 | #define MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 374 | #define MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 375 | #define MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 376 | #define MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 377 | #define MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL) | ||
| 378 | #define MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 379 | #define MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 380 | #define MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 381 | #define MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 382 | #define MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL) | ||
| 383 | #define MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 384 | #define MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 385 | #define MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 386 | #define MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 387 | #define MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL) | ||
| 388 | #define MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 389 | #define MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 390 | #define MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 391 | #define MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 392 | #define MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL) | ||
| 393 | #define MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 394 | #define MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 395 | #define MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 396 | #define MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 397 | #define MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL) | ||
| 398 | #define MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 399 | #define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 400 | #define MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 401 | #define MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 402 | #define MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL) | ||
| 403 | #define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 404 | #define MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL) | ||
| 405 | #define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 406 | #define MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 407 | #define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 408 | #define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 409 | #define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 410 | #define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 411 | #define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 412 | #define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 413 | #define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 414 | #define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 415 | #define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 416 | #define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 417 | #define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 418 | #define MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 419 | #define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 420 | #define MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 421 | #define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 422 | #define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 423 | #define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 424 | #define MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 425 | #define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 426 | #define MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 427 | #define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 428 | #define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 429 | #define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 430 | #define MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 431 | #define MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 432 | #define MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 433 | #define MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 434 | #define MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 435 | #define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 436 | #define MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 437 | #define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 438 | #define MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 439 | #define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 440 | #define MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 441 | #define MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 442 | #define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) | ||
| 443 | #define MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 444 | #define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) | ||
| 445 | #define MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 446 | #define MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 447 | #define MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 448 | #define MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 449 | #define MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL) | ||
| 450 | #define MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 451 | #define MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 452 | #define MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 453 | #define MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 454 | #define MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 455 | #define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 456 | #define MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 457 | #define MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL) | ||
| 458 | #define MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL) | ||
| 459 | #define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 460 | #define MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 461 | #define MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL) | ||
| 462 | #define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 463 | #define MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 464 | #define MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL) | ||
| 465 | #define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 466 | #define MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 467 | #define MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL) | ||
| 468 | #define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 469 | #define MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 470 | #define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 471 | #define MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 472 | #define MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL) | ||
| 473 | #define MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 474 | #define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL) | ||
| 475 | #define MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 476 | #define MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 477 | #define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 478 | #define MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 479 | #define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL) | ||
| 480 | #define MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 481 | #define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 482 | #define MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 483 | #define MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 484 | #define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL) | ||
| 485 | #define MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 486 | #define MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 487 | #define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 488 | #define MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 489 | #define MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 490 | #define MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 491 | #define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL) | ||
| 492 | #define MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 493 | #define MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 494 | #define MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 495 | #define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 496 | #define MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 497 | #define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 498 | #define MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 499 | #define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 500 | #define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 501 | #define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 502 | #define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 503 | #define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 504 | #define MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL) | ||
| 505 | #define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 506 | #define MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL) | ||
| 507 | #define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 508 | #define MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 509 | #define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 510 | #define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL) | ||
| 511 | #define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 512 | #define MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 513 | #define MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 514 | #define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL) | ||
| 515 | #define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL) | ||
| 516 | #define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 517 | #define MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 518 | #define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 519 | #define MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL) | ||
| 520 | #define MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 521 | #define MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL) | ||
| 522 | #define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 523 | #define MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL) | ||
| 524 | #define MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 525 | #define MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL) | ||
| 526 | #define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 527 | #define MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 528 | #define MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 529 | #define MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL) | ||
| 530 | #define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 531 | #define MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL) | ||
| 532 | #define MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 533 | #define MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 534 | #define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 535 | #define MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 536 | #define MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 537 | #define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 538 | #define MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 539 | #define MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL) | ||
| 540 | #define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 541 | #define MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 542 | #define MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 543 | #define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 544 | #define MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 545 | #define MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL) | ||
| 546 | #define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 547 | #define MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 548 | #define MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 549 | #define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 550 | #define MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL) | ||
| 551 | #define MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 552 | #define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 553 | #define MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL) | ||
| 554 | #define MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 555 | #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 556 | #define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 557 | #define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL) | ||
| 558 | #define MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 559 | #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) | ||
| 560 | #define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 561 | #define MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL) | ||
| 562 | #define MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 563 | #define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 564 | #define MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL) | ||
| 565 | #define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 566 | #define MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL) | ||
| 567 | #define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 568 | #define MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL) | ||
| 569 | #define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 570 | #define MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 571 | #define MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 572 | #define MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL) | ||
| 573 | #define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL) | ||
| 574 | #define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL) | ||
| 575 | #define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL) | ||
| 576 | #define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 577 | #define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL) | ||
| 578 | #define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL) | ||
| 579 | #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 580 | #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 581 | #define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 582 | #define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL) | ||
| 583 | #define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 584 | #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 585 | #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 586 | #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 587 | #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 588 | #define MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL) | ||
| 589 | #define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 590 | #define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 591 | #define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 592 | #define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 593 | #define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 594 | #define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 595 | #define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 596 | #define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 597 | #define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 598 | #define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 599 | #define MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 600 | #define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 601 | #define MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 602 | #define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 603 | #define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 604 | #define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 605 | #define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 606 | #define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 607 | #define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 608 | #define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 609 | #define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 610 | #define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 611 | #define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 612 | #define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 613 | #define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 614 | #define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 615 | #define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 616 | #define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 617 | #define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 618 | #define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 619 | #define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 620 | #define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 621 | #define MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 622 | #define MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 623 | #define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 624 | #define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 625 | #define MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 626 | #define MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 627 | #define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 628 | #define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 629 | #define MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 630 | #define MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 631 | #define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 632 | #define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 633 | #define MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 634 | #define MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 635 | #define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 636 | #define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 637 | #define MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 638 | #define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 639 | #define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 640 | #define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 641 | #define MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 642 | #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 643 | #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 644 | #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 645 | #define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 646 | #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 647 | #define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 648 | #define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 649 | #define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) | ||
| 650 | #define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) | ||
| 651 | #define MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL) | ||
| 652 | #define MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 653 | #define MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL) | ||
| 654 | #define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 655 | #define MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL) | ||
| 656 | #define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 657 | #define MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 658 | #define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 659 | #define MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL) | ||
| 660 | #define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 661 | #define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL) | ||
| 662 | #define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 663 | #define MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL) | ||
| 664 | #define MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 665 | #define MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL) | ||
| 666 | #define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 667 | #define MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL) | ||
| 668 | #define MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL) | ||
| 669 | #define MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL) | ||
| 670 | #define MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL) | ||
| 671 | #define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 672 | #define MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL) | ||
| 673 | #define MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL) | ||
| 674 | #define MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL) | ||
| 675 | #define MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL) | ||
| 676 | #define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 677 | #define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 678 | #define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 679 | #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 680 | #define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 681 | #define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 682 | #define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 683 | #define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL) | ||
| 684 | #define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL) | ||
| 685 | #define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 686 | #define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 687 | #define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 688 | #define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL) | ||
| 689 | #define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL) | ||
| 690 | #define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 691 | #define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 692 | #define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 693 | #define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL) | ||
| 694 | #define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL) | ||
| 695 | #define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL) | ||
| 696 | #define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 697 | #define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 698 | #define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 699 | #define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL) | ||
| 700 | #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 701 | #define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 702 | #define MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL) | ||
| 703 | #define MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL) | ||
| 704 | #define MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL) | ||
| 705 | #define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL) | ||
| 706 | #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 707 | #define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL) | ||
| 708 | #define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 709 | #define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL) | ||
| 710 | #define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL) | ||
| 711 | #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 712 | #define MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL) | ||
| 713 | #define MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL) | ||
| 714 | #define MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL) | ||
| 715 | #define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 716 | #define MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4) | ||
| 717 | #define MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL) | ||
| 718 | #define MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL) | ||
| 719 | #define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 720 | #define MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4) | ||
| 721 | #define MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL) | ||
| 722 | #define MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL) | ||
| 723 | #define MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 724 | #define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 725 | #define MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5) | ||
| 726 | #define MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL) | ||
| 727 | #define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) | ||
| 728 | #define MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL) | ||
| 729 | #define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 730 | #define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) | ||
| 731 | #define MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL) | ||
| 732 | #define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) | ||
| 733 | #define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL) | ||
| 734 | #define MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL) | ||
| 735 | #define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 736 | #define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 737 | #define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 738 | #define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 739 | #define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 740 | #define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL) | ||
| 741 | #define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 742 | #define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 743 | #define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 744 | #define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 745 | #define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 746 | #define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL) | ||
| 747 | #define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 748 | #define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 749 | #define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 750 | #define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 751 | #define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 752 | #define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL) | ||
| 753 | #define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL) | ||
| 754 | #define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 755 | #define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL) | ||
| 756 | #define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 757 | #define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) | ||
| 758 | #define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL) | ||
| 759 | #define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 760 | #define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) | ||
| 761 | #define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 762 | #define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 763 | #define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 764 | #define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL) | ||
| 765 | #define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) | ||
| 766 | #define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL) | ||
| 767 | #define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 768 | #define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL) | ||
| 769 | #define MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL) | ||
| 770 | #define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) | ||
| 771 | #define MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL) | ||
| 772 | #define MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 773 | #define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 774 | #define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 775 | #define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 776 | #define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL) | ||
| 777 | #define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 778 | #define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 779 | #define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL) | ||
| 780 | #define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL) | ||
| 781 | #define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 782 | #define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) | ||
| 783 | #define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 784 | #define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 785 | #define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL) | ||
| 786 | #define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL) | ||
| 787 | #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 788 | #define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 789 | #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) | ||
| 790 | #define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 791 | #define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 792 | #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) | ||
| 793 | #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 794 | #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 795 | #define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 796 | #define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL) | ||
| 797 | #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) | ||
| 798 | #define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 799 | #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 800 | #define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 801 | #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 802 | #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 803 | #define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 804 | #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 805 | #define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 806 | #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 807 | #define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 808 | #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 809 | #define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 810 | #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 811 | #define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 812 | #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) | ||
| 813 | #define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 814 | #define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL) | ||
| 815 | #define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 816 | #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) | ||
| 817 | #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 818 | #define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 819 | #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) | ||
| 820 | #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) | ||
| 821 | #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 822 | #define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | ||
| 823 | #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 824 | #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 825 | #define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 826 | |||
| 827 | #endif /* __MACH_IOMUX_MX51_H__ */ | ||
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index 39406b7e3228..a7e9bd26a552 100644 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c | |||
| @@ -50,6 +50,7 @@ | |||
| 50 | #include "common.h" | 50 | #include "common.h" |
| 51 | #include "devices-imx31.h" | 51 | #include "devices-imx31.h" |
| 52 | #include "crmregs-imx3.h" | 52 | #include "crmregs-imx3.h" |
| 53 | #include "ehci.h" | ||
| 53 | #include "hardware.h" | 54 | #include "hardware.h" |
| 54 | #include "iomux-mx3.h" | 55 | #include "iomux-mx3.h" |
| 55 | #include "ulpi.h" | 56 | #include "ulpi.h" |
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 75b7b6aa2720..e6d4b9929571 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | 36 | ||
| 37 | #include "common.h" | 37 | #include "common.h" |
| 38 | #include "devices-imx27.h" | 38 | #include "devices-imx27.h" |
| 39 | #include "ehci.h" | ||
| 39 | #include "eukrea-baseboards.h" | 40 | #include "eukrea-baseboards.h" |
| 40 | #include "hardware.h" | 41 | #include "hardware.h" |
| 41 | #include "iomux-mx27.h" | 42 | #include "iomux-mx27.h" |
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c index 1ffa27169045..62a6e02f4763 100644 --- a/arch/arm/mach-imx/mach-cpuimx35.c +++ b/arch/arm/mach-imx/mach-cpuimx35.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | 39 | ||
| 40 | #include "common.h" | 40 | #include "common.h" |
| 41 | #include "devices-imx35.h" | 41 | #include "devices-imx35.h" |
| 42 | #include "ehci.h" | ||
| 42 | #include "eukrea-baseboards.h" | 43 | #include "eukrea-baseboards.h" |
| 43 | #include "hardware.h" | 44 | #include "hardware.h" |
| 44 | #include "iomux-mx35.h" | 45 | #include "iomux-mx35.h" |
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index e978dda1434c..b2ee6e009fe4 100644 --- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c | |||
| @@ -35,6 +35,7 @@ | |||
| 35 | 35 | ||
| 36 | #include "common.h" | 36 | #include "common.h" |
| 37 | #include "devices-imx25.h" | 37 | #include "devices-imx25.h" |
| 38 | #include "ehci.h" | ||
| 38 | #include "eukrea-baseboards.h" | 39 | #include "eukrea-baseboards.h" |
| 39 | #include "hardware.h" | 40 | #include "hardware.h" |
| 40 | #include "iomux-mx25.h" | 41 | #include "iomux-mx25.h" |
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index b61bd8ed5568..ede2bdbb5dd5 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c | |||
| @@ -43,6 +43,7 @@ | |||
| 43 | 43 | ||
| 44 | #include "common.h" | 44 | #include "common.h" |
| 45 | #include "devices-imx27.h" | 45 | #include "devices-imx27.h" |
| 46 | #include "ehci.h" | ||
| 46 | #include "hardware.h" | 47 | #include "hardware.h" |
| 47 | #include "iomux-mx27.h" | 48 | #include "iomux-mx27.h" |
| 48 | 49 | ||
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c deleted file mode 100644 index bb3ca0429680..000000000000 --- a/arch/arm/mach-imx/mach-imx27ipcam.c +++ /dev/null | |||
| @@ -1,77 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <asm/mach-types.h> | ||
| 18 | #include <asm/mach/arch.h> | ||
| 19 | #include <asm/mach/time.h> | ||
| 20 | |||
| 21 | #include "hardware.h" | ||
| 22 | #include "common.h" | ||
| 23 | #include "devices-imx27.h" | ||
| 24 | #include "iomux-mx27.h" | ||
| 25 | |||
| 26 | static const int mx27ipcam_pins[] __initconst = { | ||
| 27 | /* UART1 */ | ||
| 28 | PE12_PF_UART1_TXD, | ||
| 29 | PE13_PF_UART1_RXD, | ||
| 30 | /* FEC */ | ||
| 31 | PD0_AIN_FEC_TXD0, | ||
| 32 | PD1_AIN_FEC_TXD1, | ||
| 33 | PD2_AIN_FEC_TXD2, | ||
| 34 | PD3_AIN_FEC_TXD3, | ||
| 35 | PD4_AOUT_FEC_RX_ER, | ||
| 36 | PD5_AOUT_FEC_RXD1, | ||
| 37 | PD6_AOUT_FEC_RXD2, | ||
| 38 | PD7_AOUT_FEC_RXD3, | ||
| 39 | PD8_AF_FEC_MDIO, | ||
| 40 | PD9_AIN_FEC_MDC, | ||
| 41 | PD10_AOUT_FEC_CRS, | ||
| 42 | PD11_AOUT_FEC_TX_CLK, | ||
| 43 | PD12_AOUT_FEC_RXD0, | ||
| 44 | PD13_AOUT_FEC_RX_DV, | ||
| 45 | PD14_AOUT_FEC_RX_CLK, | ||
| 46 | PD15_AOUT_FEC_COL, | ||
| 47 | PD16_AIN_FEC_TX_ER, | ||
| 48 | PF23_AIN_FEC_TX_EN, | ||
| 49 | }; | ||
| 50 | |||
| 51 | static void __init mx27ipcam_init(void) | ||
| 52 | { | ||
| 53 | imx27_soc_init(); | ||
| 54 | |||
| 55 | mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins), | ||
| 56 | "mx27ipcam"); | ||
| 57 | |||
| 58 | imx27_add_imx_uart0(NULL); | ||
| 59 | imx27_add_fec(NULL); | ||
| 60 | imx27_add_imx2_wdt(); | ||
| 61 | } | ||
| 62 | |||
| 63 | static void __init mx27ipcam_timer_init(void) | ||
| 64 | { | ||
| 65 | mx27_clocks_init(25000000); | ||
| 66 | } | ||
| 67 | |||
| 68 | MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM") | ||
| 69 | /* maintainer: Freescale Semiconductor, Inc. */ | ||
| 70 | .atag_offset = 0x100, | ||
| 71 | .map_io = mx27_map_io, | ||
| 72 | .init_early = imx27_init_early, | ||
| 73 | .init_irq = mx27_init_irq, | ||
| 74 | .init_time = mx27ipcam_timer_init, | ||
| 75 | .init_machine = mx27ipcam_init, | ||
| 76 | .restart = mxc_restart, | ||
| 77 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c deleted file mode 100644 index 9992089d3ad1..000000000000 --- a/arch/arm/mach-imx/mach-imx27lite.c +++ /dev/null | |||
| @@ -1,83 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix | ||
| 3 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) | ||
| 4 | * Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/gpio.h> | ||
| 19 | #include <asm/mach-types.h> | ||
| 20 | #include <asm/mach/arch.h> | ||
| 21 | #include <asm/mach/time.h> | ||
| 22 | #include <asm/mach/map.h> | ||
| 23 | |||
| 24 | #include "common.h" | ||
| 25 | #include "devices-imx27.h" | ||
| 26 | #include "hardware.h" | ||
| 27 | #include "iomux-mx27.h" | ||
| 28 | |||
| 29 | static const int mx27lite_pins[] __initconst = { | ||
| 30 | /* UART1 */ | ||
| 31 | PE12_PF_UART1_TXD, | ||
| 32 | PE13_PF_UART1_RXD, | ||
| 33 | PE14_PF_UART1_CTS, | ||
| 34 | PE15_PF_UART1_RTS, | ||
| 35 | /* FEC */ | ||
| 36 | PD0_AIN_FEC_TXD0, | ||
| 37 | PD1_AIN_FEC_TXD1, | ||
| 38 | PD2_AIN_FEC_TXD2, | ||
| 39 | PD3_AIN_FEC_TXD3, | ||
| 40 | PD4_AOUT_FEC_RX_ER, | ||
| 41 | PD5_AOUT_FEC_RXD1, | ||
| 42 | PD6_AOUT_FEC_RXD2, | ||
| 43 | PD7_AOUT_FEC_RXD3, | ||
| 44 | PD8_AF_FEC_MDIO, | ||
| 45 | PD9_AIN_FEC_MDC, | ||
| 46 | PD10_AOUT_FEC_CRS, | ||
| 47 | PD11_AOUT_FEC_TX_CLK, | ||
| 48 | PD12_AOUT_FEC_RXD0, | ||
| 49 | PD13_AOUT_FEC_RX_DV, | ||
| 50 | PD14_AOUT_FEC_RX_CLK, | ||
| 51 | PD15_AOUT_FEC_COL, | ||
| 52 | PD16_AIN_FEC_TX_ER, | ||
| 53 | PF23_AIN_FEC_TX_EN, | ||
| 54 | }; | ||
| 55 | |||
| 56 | static const struct imxuart_platform_data uart_pdata __initconst = { | ||
| 57 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static void __init mx27lite_init(void) | ||
| 61 | { | ||
| 62 | imx27_soc_init(); | ||
| 63 | |||
| 64 | mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins), | ||
| 65 | "imx27lite"); | ||
| 66 | imx27_add_imx_uart0(&uart_pdata); | ||
| 67 | imx27_add_fec(NULL); | ||
| 68 | } | ||
| 69 | |||
| 70 | static void __init mx27lite_timer_init(void) | ||
| 71 | { | ||
| 72 | mx27_clocks_init(26000000); | ||
| 73 | } | ||
| 74 | |||
| 75 | MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") | ||
| 76 | .atag_offset = 0x100, | ||
| 77 | .map_io = mx27_map_io, | ||
| 78 | .init_early = imx27_init_early, | ||
| 79 | .init_irq = mx27_init_irq, | ||
| 80 | .init_time = mx27lite_timer_init, | ||
| 81 | .init_machine = mx27lite_init, | ||
| 82 | .restart = mxc_restart, | ||
| 83 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c index b899c0b59afd..b1e56a94a382 100644 --- a/arch/arm/mach-imx/mach-imx50.c +++ b/arch/arm/mach-imx/mach-imx50.c | |||
| @@ -23,14 +23,13 @@ static void __init imx50_dt_init(void) | |||
| 23 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 23 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 24 | } | 24 | } |
| 25 | 25 | ||
| 26 | static const char *imx50_dt_board_compat[] __initconst = { | 26 | static const char * const imx50_dt_board_compat[] __initconst = { |
| 27 | "fsl,imx50", | 27 | "fsl,imx50", |
| 28 | NULL | 28 | NULL |
| 29 | }; | 29 | }; |
| 30 | 30 | ||
| 31 | DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)") | 31 | DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)") |
| 32 | .map_io = mx53_map_io, | 32 | .init_irq = tzic_init_irq, |
| 33 | .init_irq = mx53_init_irq, | ||
| 34 | .init_machine = imx50_dt_init, | 33 | .init_machine = imx50_dt_init, |
| 35 | .dt_compat = imx50_dt_board_compat, | 34 | .dt_compat = imx50_dt_board_compat, |
| 36 | .restart = mxc_restart, | 35 | .restart = mxc_restart, |
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/mach-imx51.c index b8cd968faa52..c77deb3f0893 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/mach-imx51.c | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | * http://www.gnu.org/copyleft/gpl.html | 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/io.h> | ||
| 13 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
| 14 | #include <linux/of_irq.h> | 15 | #include <linux/of_irq.h> |
| 15 | #include <linux/of_platform.h> | 16 | #include <linux/of_platform.h> |
| @@ -17,27 +18,63 @@ | |||
| 17 | #include <asm/mach/time.h> | 18 | #include <asm/mach/time.h> |
| 18 | 19 | ||
| 19 | #include "common.h" | 20 | #include "common.h" |
| 20 | #include "mx51.h" | 21 | #include "hardware.h" |
| 22 | |||
| 23 | static void __init imx51_init_early(void) | ||
| 24 | { | ||
| 25 | mxc_set_cpu_type(MXC_CPU_MX51); | ||
| 26 | } | ||
| 27 | |||
| 28 | /* | ||
| 29 | * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by | ||
| 30 | * the Freescale marketing division. However this did not remove the | ||
| 31 | * hardware from the chip which still needs to be configured for proper | ||
| 32 | * IPU support. | ||
| 33 | */ | ||
| 34 | #define MX51_MIPI_HSC_BASE 0x83fdc000 | ||
| 35 | static void __init imx51_ipu_mipi_setup(void) | ||
| 36 | { | ||
| 37 | void __iomem *hsc_addr; | ||
| 38 | |||
| 39 | hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K); | ||
| 40 | WARN_ON(!hsc_addr); | ||
| 41 | |||
| 42 | /* setup MIPI module to legacy mode */ | ||
| 43 | __raw_writel(0xf00, hsc_addr); | ||
| 44 | |||
| 45 | /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ | ||
| 46 | __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff, | ||
| 47 | hsc_addr + 0x800); | ||
| 48 | |||
| 49 | iounmap(hsc_addr); | ||
| 50 | } | ||
| 21 | 51 | ||
| 22 | static void __init imx51_dt_init(void) | 52 | static void __init imx51_dt_init(void) |
| 23 | { | 53 | { |
| 24 | struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; | 54 | struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; |
| 25 | 55 | ||
| 26 | mxc_arch_reset_init_dt(); | 56 | mxc_arch_reset_init_dt(); |
| 57 | imx51_ipu_mipi_setup(); | ||
| 58 | imx_src_init(); | ||
| 27 | 59 | ||
| 28 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 60 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 29 | platform_device_register_full(&devinfo); | 61 | platform_device_register_full(&devinfo); |
| 30 | } | 62 | } |
| 31 | 63 | ||
| 32 | static const char *imx51_dt_board_compat[] __initconst = { | 64 | static void __init imx51_init_late(void) |
| 65 | { | ||
| 66 | mx51_neon_fixup(); | ||
| 67 | imx51_pm_init(); | ||
| 68 | } | ||
| 69 | |||
| 70 | static const char * const imx51_dt_board_compat[] __initconst = { | ||
| 33 | "fsl,imx51", | 71 | "fsl,imx51", |
| 34 | NULL | 72 | NULL |
| 35 | }; | 73 | }; |
| 36 | 74 | ||
| 37 | DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") | 75 | DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") |
| 38 | .map_io = mx51_map_io, | ||
| 39 | .init_early = imx51_init_early, | 76 | .init_early = imx51_init_early, |
| 40 | .init_irq = mx51_init_irq, | 77 | .init_irq = tzic_init_irq, |
| 41 | .init_machine = imx51_dt_init, | 78 | .init_machine = imx51_dt_init, |
| 42 | .init_late = imx51_init_late, | 79 | .init_late = imx51_init_late, |
| 43 | .dt_compat = imx51_dt_board_compat, | 80 | .dt_compat = imx51_dt_board_compat, |
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 2bad387956c0..03dd6ea13acc 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c | |||
| @@ -22,24 +22,35 @@ | |||
| 22 | 22 | ||
| 23 | #include "common.h" | 23 | #include "common.h" |
| 24 | #include "hardware.h" | 24 | #include "hardware.h" |
| 25 | #include "mx53.h" | 25 | |
| 26 | static void __init imx53_init_early(void) | ||
| 27 | { | ||
| 28 | mxc_set_cpu_type(MXC_CPU_MX53); | ||
| 29 | } | ||
| 26 | 30 | ||
| 27 | static void __init imx53_dt_init(void) | 31 | static void __init imx53_dt_init(void) |
| 28 | { | 32 | { |
| 29 | mxc_arch_reset_init_dt(); | 33 | mxc_arch_reset_init_dt(); |
| 34 | imx_src_init(); | ||
| 30 | 35 | ||
| 31 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 36 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 37 | |||
| 38 | imx_aips_allow_unprivileged_access("fsl,imx53-aipstz"); | ||
| 39 | } | ||
| 40 | |||
| 41 | static void __init imx53_init_late(void) | ||
| 42 | { | ||
| 43 | imx53_pm_init(); | ||
| 32 | } | 44 | } |
| 33 | 45 | ||
| 34 | static const char *imx53_dt_board_compat[] __initconst = { | 46 | static const char * const imx53_dt_board_compat[] __initconst = { |
| 35 | "fsl,imx53", | 47 | "fsl,imx53", |
| 36 | NULL | 48 | NULL |
| 37 | }; | 49 | }; |
| 38 | 50 | ||
| 39 | DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)") | 51 | DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)") |
| 40 | .map_io = mx53_map_io, | ||
| 41 | .init_early = imx53_init_early, | 52 | .init_early = imx53_init_early, |
| 42 | .init_irq = mx53_init_irq, | 53 | .init_irq = tzic_init_irq, |
| 43 | .init_machine = imx53_dt_init, | 54 | .init_machine = imx53_dt_init, |
| 44 | .init_late = imx53_init_late, | 55 | .init_late = imx53_init_late, |
| 45 | .dt_compat = imx53_dt_board_compat, | 56 | .dt_compat = imx53_dt_board_compat, |
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index e60456d85c9d..d51c6e99a2e9 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c | |||
| @@ -320,7 +320,7 @@ static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev) | |||
| 320 | val >>= OCOTP_CFG3_SPEED_SHIFT; | 320 | val >>= OCOTP_CFG3_SPEED_SHIFT; |
| 321 | val &= 0x3; | 321 | val &= 0x3; |
| 322 | 322 | ||
| 323 | if (val != OCOTP_CFG3_SPEED_1P2GHZ) | 323 | if ((val != OCOTP_CFG3_SPEED_1P2GHZ) && cpu_is_imx6q()) |
| 324 | if (dev_pm_opp_disable(cpu_dev, 1200000000)) | 324 | if (dev_pm_opp_disable(cpu_dev, 1200000000)) |
| 325 | pr_warn("failed to disable 1.2 GHz OPP\n"); | 325 | pr_warn("failed to disable 1.2 GHz OPP\n"); |
| 326 | if (val < OCOTP_CFG3_SPEED_996MHZ) | 326 | if (val < OCOTP_CFG3_SPEED_996MHZ) |
| @@ -396,7 +396,7 @@ static void __init imx6q_init_irq(void) | |||
| 396 | irqchip_init(); | 396 | irqchip_init(); |
| 397 | } | 397 | } |
| 398 | 398 | ||
| 399 | static const char *imx6q_dt_compat[] __initconst = { | 399 | static const char * const imx6q_dt_compat[] __initconst = { |
| 400 | "fsl,imx6dl", | 400 | "fsl,imx6dl", |
| 401 | "fsl,imx6q", | 401 | "fsl,imx6q", |
| 402 | NULL, | 402 | NULL, |
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index ad323385115c..ed263a21d928 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c | |||
| @@ -70,7 +70,7 @@ static void __init imx6sl_init_irq(void) | |||
| 70 | irqchip_init(); | 70 | irqchip_init(); |
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | static const char *imx6sl_dt_compat[] __initconst = { | 73 | static const char * const imx6sl_dt_compat[] __initconst = { |
| 74 | "fsl,imx6sl", | 74 | "fsl,imx6sl", |
| 75 | NULL, | 75 | NULL, |
| 76 | }; | 76 | }; |
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c index 02fccf6033ac..673a734165ba 100644 --- a/arch/arm/mach-imx/mach-imx6sx.c +++ b/arch/arm/mach-imx/mach-imx6sx.c | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | #include <asm/mach/map.h> | 12 | #include <asm/mach/map.h> |
| 13 | 13 | ||
| 14 | #include "common.h" | 14 | #include "common.h" |
| 15 | #include "cpuidle.h" | ||
| 15 | 16 | ||
| 16 | static void __init imx6sx_init_machine(void) | 17 | static void __init imx6sx_init_machine(void) |
| 17 | { | 18 | { |
| @@ -26,6 +27,7 @@ static void __init imx6sx_init_machine(void) | |||
| 26 | of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); | 27 | of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); |
| 27 | 28 | ||
| 28 | imx_anatop_init(); | 29 | imx_anatop_init(); |
| 30 | imx6sx_pm_init(); | ||
| 29 | } | 31 | } |
| 30 | 32 | ||
| 31 | static void __init imx6sx_init_irq(void) | 33 | static void __init imx6sx_init_irq(void) |
| @@ -37,7 +39,12 @@ static void __init imx6sx_init_irq(void) | |||
| 37 | irqchip_init(); | 39 | irqchip_init(); |
| 38 | } | 40 | } |
| 39 | 41 | ||
| 40 | static const char *imx6sx_dt_compat[] __initconst = { | 42 | static void __init imx6sx_init_late(void) |
| 43 | { | ||
| 44 | imx6q_cpuidle_init(); | ||
| 45 | } | ||
| 46 | |||
| 47 | static const char * const imx6sx_dt_compat[] __initconst = { | ||
| 41 | "fsl,imx6sx", | 48 | "fsl,imx6sx", |
| 42 | NULL, | 49 | NULL, |
| 43 | }; | 50 | }; |
| @@ -47,5 +54,6 @@ DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)") | |||
| 47 | .init_irq = imx6sx_init_irq, | 54 | .init_irq = imx6sx_init_irq, |
| 48 | .init_machine = imx6sx_init_machine, | 55 | .init_machine = imx6sx_init_machine, |
| 49 | .dt_compat = imx6sx_dt_compat, | 56 | .dt_compat = imx6sx_dt_compat, |
| 57 | .init_late = imx6sx_init_late, | ||
| 50 | .restart = mxc_restart, | 58 | .restart = mxc_restart, |
| 51 | MACHINE_END | 59 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index ea1fa199c148..0d01e367b062 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | 39 | ||
| 40 | #include "common.h" | 40 | #include "common.h" |
| 41 | #include "devices-imx25.h" | 41 | #include "devices-imx25.h" |
| 42 | #include "ehci.h" | ||
| 42 | #include "hardware.h" | 43 | #include "hardware.h" |
| 43 | #include "iomux-mx25.h" | 44 | #include "iomux-mx25.h" |
| 44 | #include "mx25.h" | 45 | #include "mx25.h" |
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 435a5428a678..9ef4640f3660 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | #include "3ds_debugboard.h" | 40 | #include "3ds_debugboard.h" |
| 41 | #include "common.h" | 41 | #include "common.h" |
| 42 | #include "devices-imx27.h" | 42 | #include "devices-imx27.h" |
| 43 | #include "ehci.h" | ||
| 43 | #include "hardware.h" | 44 | #include "hardware.h" |
| 44 | #include "iomux-mx27.h" | 45 | #include "iomux-mx27.h" |
| 45 | #include "ulpi.h" | 46 | #include "ulpi.h" |
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 4217871a9653..453f41a2c5a9 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | #include "3ds_debugboard.h" | 40 | #include "3ds_debugboard.h" |
| 41 | #include "common.h" | 41 | #include "common.h" |
| 42 | #include "devices-imx31.h" | 42 | #include "devices-imx31.h" |
| 43 | #include "ehci.h" | ||
| 43 | #include "hardware.h" | 44 | #include "hardware.h" |
| 44 | #include "iomux-mx3.h" | 45 | #include "iomux-mx3.h" |
| 45 | #include "ulpi.h" | 46 | #include "ulpi.h" |
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c index eee042fa2768..e9549a3c0223 100644 --- a/arch/arm/mach-imx/mach-mx31lilly.c +++ b/arch/arm/mach-imx/mach-mx31lilly.c | |||
| @@ -45,6 +45,7 @@ | |||
| 45 | #include "board-mx31lilly.h" | 45 | #include "board-mx31lilly.h" |
| 46 | #include "common.h" | 46 | #include "common.h" |
| 47 | #include "devices-imx31.h" | 47 | #include "devices-imx31.h" |
| 48 | #include "ehci.h" | ||
| 48 | #include "hardware.h" | 49 | #include "hardware.h" |
| 49 | #include "iomux-mx3.h" | 50 | #include "iomux-mx3.h" |
| 50 | #include "ulpi.h" | 51 | #include "ulpi.h" |
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c index fa15d0b6118d..57eac6f45fab 100644 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ b/arch/arm/mach-imx/mach-mx31lite.c | |||
| @@ -42,6 +42,7 @@ | |||
| 42 | #include "board-mx31lite.h" | 42 | #include "board-mx31lite.h" |
| 43 | #include "common.h" | 43 | #include "common.h" |
| 44 | #include "devices-imx31.h" | 44 | #include "devices-imx31.h" |
| 45 | #include "ehci.h" | ||
| 45 | #include "hardware.h" | 46 | #include "hardware.h" |
| 46 | #include "iomux-mx3.h" | 47 | #include "iomux-mx3.h" |
| 47 | #include "ulpi.h" | 48 | #include "ulpi.h" |
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index 08730f238449..bb6f8a52a6b8 100644 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c | |||
| @@ -47,6 +47,7 @@ | |||
| 47 | #include "board-mx31moboard.h" | 47 | #include "board-mx31moboard.h" |
| 48 | #include "common.h" | 48 | #include "common.h" |
| 49 | #include "devices-imx31.h" | 49 | #include "devices-imx31.h" |
| 50 | #include "ehci.h" | ||
| 50 | #include "hardware.h" | 51 | #include "hardware.h" |
| 51 | #include "iomux-mx3.h" | 52 | #include "iomux-mx3.h" |
| 52 | #include "ulpi.h" | 53 | #include "ulpi.h" |
| @@ -434,10 +435,8 @@ static int __init moboard_usbh2_init(void) | |||
| 434 | return -ENODEV; | 435 | return -ENODEV; |
| 435 | 436 | ||
| 436 | pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); | 437 | pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); |
| 437 | if (IS_ERR(pdev)) | ||
| 438 | return PTR_ERR(pdev); | ||
| 439 | 438 | ||
| 440 | return 0; | 439 | return PTR_ERR_OR_ZERO(pdev); |
| 441 | } | 440 | } |
| 442 | 441 | ||
| 443 | static const struct gpio_led mx31moboard_leds[] __initconst = { | 442 | static const struct gpio_led mx31moboard_leds[] __initconst = { |
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c index 4e8b184d773b..72cd77d21f63 100644 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ b/arch/arm/mach-imx/mach-mx35_3ds.c | |||
| @@ -50,6 +50,7 @@ | |||
| 50 | #include "3ds_debugboard.h" | 50 | #include "3ds_debugboard.h" |
| 51 | #include "common.h" | 51 | #include "common.h" |
| 52 | #include "devices-imx35.h" | 52 | #include "devices-imx35.h" |
| 53 | #include "ehci.h" | ||
| 53 | #include "hardware.h" | 54 | #include "hardware.h" |
| 54 | #include "iomux-mx35.h" | 55 | #include "iomux-mx35.h" |
| 55 | 56 | ||
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 12212378c672..2d1c50bd8bdf 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | 36 | ||
| 37 | #include "common.h" | 37 | #include "common.h" |
| 38 | #include "devices-imx27.h" | 38 | #include "devices-imx27.h" |
| 39 | #include "ehci.h" | ||
| 39 | #include "hardware.h" | 40 | #include "hardware.h" |
| 40 | #include "iomux-mx27.h" | 41 | #include "iomux-mx27.h" |
| 41 | #include "ulpi.h" | 42 | #include "ulpi.h" |
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index 81b8affb9448..8eb1570f7851 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c | |||
| @@ -45,6 +45,7 @@ | |||
| 45 | 45 | ||
| 46 | #include "common.h" | 46 | #include "common.h" |
| 47 | #include "devices-imx31.h" | 47 | #include "devices-imx31.h" |
| 48 | #include "ehci.h" | ||
| 48 | #include "hardware.h" | 49 | #include "hardware.h" |
| 49 | #include "iomux-mx3.h" | 50 | #include "iomux-mx3.h" |
| 50 | #include "pcm037.h" | 51 | #include "pcm037.h" |
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 6c56fb5553c7..ee862ad6b6fc 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | #include "board-pcm038.h" | 36 | #include "board-pcm038.h" |
| 37 | #include "common.h" | 37 | #include "common.h" |
| 38 | #include "devices-imx27.h" | 38 | #include "devices-imx27.h" |
| 39 | #include "ehci.h" | ||
| 39 | #include "hardware.h" | 40 | #include "hardware.h" |
| 40 | #include "iomux-mx27.h" | 41 | #include "iomux-mx27.h" |
| 41 | #include "ulpi.h" | 42 | #include "ulpi.h" |
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index c62b5d261345..b623bcaca76c 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c | |||
| @@ -35,6 +35,7 @@ | |||
| 35 | 35 | ||
| 36 | #include "common.h" | 36 | #include "common.h" |
| 37 | #include "devices-imx35.h" | 37 | #include "devices-imx35.h" |
| 38 | #include "ehci.h" | ||
| 38 | #include "hardware.h" | 39 | #include "hardware.h" |
| 39 | #include "iomux-mx35.h" | 40 | #include "iomux-mx35.h" |
| 40 | #include "ulpi.h" | 41 | #include "ulpi.h" |
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c index c44602758120..ee7e57b752a7 100644 --- a/arch/arm/mach-imx/mach-vf610.c +++ b/arch/arm/mach-imx/mach-vf610.c | |||
| @@ -20,7 +20,7 @@ static void __init vf610_init_machine(void) | |||
| 20 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 20 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | static const char *vf610_dt_compat[] __initconst = { | 23 | static const char * const vf610_dt_compat[] __initconst = { |
| 24 | "fsl,vf610", | 24 | "fsl,vf610", |
| 25 | NULL, | 25 | NULL, |
| 26 | }; | 26 | }; |
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index 872b3c6ba408..97836e94451c 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c | |||
| @@ -34,6 +34,7 @@ | |||
| 34 | 34 | ||
| 35 | #include "common.h" | 35 | #include "common.h" |
| 36 | #include "devices-imx35.h" | 36 | #include "devices-imx35.h" |
| 37 | #include "ehci.h" | ||
| 37 | #include "hardware.h" | 38 | #include "hardware.h" |
| 38 | #include "iomux-mx35.h" | 39 | #include "iomux-mx35.h" |
| 39 | 40 | ||
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c deleted file mode 100644 index 4c112021aa4e..000000000000 --- a/arch/arm/mach-imx/mm-imx5.c +++ /dev/null | |||
| @@ -1,155 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | * | ||
| 11 | * Create static mapping between physical to virtual memory. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/mm.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/clk.h> | ||
| 17 | #include <linux/pinctrl/machine.h> | ||
| 18 | #include <linux/of_address.h> | ||
| 19 | |||
| 20 | #include <asm/mach/map.h> | ||
| 21 | |||
| 22 | #include "common.h" | ||
| 23 | #include "devices/devices-common.h" | ||
| 24 | #include "hardware.h" | ||
| 25 | #include "iomux-v3.h" | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Define the MX51 memory map. | ||
| 29 | */ | ||
| 30 | static struct map_desc mx51_io_desc[] __initdata = { | ||
| 31 | imx_map_entry(MX51, TZIC, MT_DEVICE), | ||
| 32 | imx_map_entry(MX51, IRAM, MT_DEVICE), | ||
| 33 | imx_map_entry(MX51, AIPS1, MT_DEVICE), | ||
| 34 | imx_map_entry(MX51, SPBA0, MT_DEVICE), | ||
| 35 | imx_map_entry(MX51, AIPS2, MT_DEVICE), | ||
| 36 | }; | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Define the MX53 memory map. | ||
| 40 | */ | ||
| 41 | static struct map_desc mx53_io_desc[] __initdata = { | ||
| 42 | imx_map_entry(MX53, TZIC, MT_DEVICE), | ||
| 43 | imx_map_entry(MX53, AIPS1, MT_DEVICE), | ||
| 44 | imx_map_entry(MX53, SPBA0, MT_DEVICE), | ||
| 45 | imx_map_entry(MX53, AIPS2, MT_DEVICE), | ||
| 46 | }; | ||
| 47 | |||
| 48 | /* | ||
| 49 | * This function initializes the memory map. It is called during the | ||
| 50 | * system startup to create static physical to virtual memory mappings | ||
| 51 | * for the IO modules. | ||
| 52 | */ | ||
| 53 | void __init mx51_map_io(void) | ||
| 54 | { | ||
| 55 | iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); | ||
| 56 | } | ||
| 57 | |||
| 58 | void __init mx53_map_io(void) | ||
| 59 | { | ||
| 60 | iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); | ||
| 61 | } | ||
| 62 | |||
| 63 | /* | ||
| 64 | * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by | ||
| 65 | * the Freescale marketing division. However this did not remove the | ||
| 66 | * hardware from the chip which still needs to be configured for proper | ||
| 67 | * IPU support. | ||
| 68 | */ | ||
| 69 | static void __init imx51_ipu_mipi_setup(void) | ||
| 70 | { | ||
| 71 | void __iomem *hsc_addr; | ||
| 72 | hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR); | ||
| 73 | |||
| 74 | /* setup MIPI module to legacy mode */ | ||
| 75 | __raw_writel(0xf00, hsc_addr); | ||
| 76 | |||
| 77 | /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ | ||
| 78 | __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff, | ||
| 79 | hsc_addr + 0x800); | ||
| 80 | } | ||
| 81 | |||
| 82 | void __init imx51_init_early(void) | ||
| 83 | { | ||
| 84 | imx51_ipu_mipi_setup(); | ||
| 85 | mxc_set_cpu_type(MXC_CPU_MX51); | ||
| 86 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); | ||
| 87 | imx_src_init(); | ||
| 88 | } | ||
| 89 | |||
| 90 | void __init imx53_init_early(void) | ||
| 91 | { | ||
| 92 | mxc_set_cpu_type(MXC_CPU_MX53); | ||
| 93 | imx_src_init(); | ||
| 94 | } | ||
| 95 | |||
| 96 | void __init mx51_init_irq(void) | ||
| 97 | { | ||
| 98 | tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); | ||
| 99 | } | ||
| 100 | |||
| 101 | void __init mx53_init_irq(void) | ||
| 102 | { | ||
| 103 | struct device_node *np; | ||
| 104 | void __iomem *base; | ||
| 105 | |||
| 106 | np = of_find_compatible_node(NULL, NULL, "fsl,imx53-tzic"); | ||
| 107 | base = of_iomap(np, 0); | ||
| 108 | WARN_ON(!base); | ||
| 109 | |||
| 110 | tzic_init_irq(base); | ||
| 111 | } | ||
| 112 | |||
| 113 | static struct sdma_platform_data imx51_sdma_pdata __initdata = { | ||
| 114 | .fw_name = "sdma-imx51.bin", | ||
| 115 | }; | ||
| 116 | |||
| 117 | static const struct resource imx51_audmux_res[] __initconst = { | ||
| 118 | DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), | ||
| 119 | }; | ||
| 120 | |||
| 121 | void __init imx51_soc_init(void) | ||
| 122 | { | ||
| 123 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); | ||
| 124 | mxc_device_init(); | ||
| 125 | |||
| 126 | /* i.mx51 has the i.mx35 type gpio */ | ||
| 127 | mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH); | ||
| 128 | mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH); | ||
| 129 | mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH); | ||
| 130 | mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH); | ||
| 131 | |||
| 132 | pinctrl_provide_dummies(); | ||
| 133 | |||
| 134 | /* i.mx51 has the i.mx35 type sdma */ | ||
| 135 | imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); | ||
| 136 | |||
| 137 | /* Setup AIPS registers */ | ||
| 138 | imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR)); | ||
| 139 | imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR)); | ||
| 140 | |||
| 141 | /* i.mx51 has the i.mx31 type audmux */ | ||
| 142 | platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res, | ||
| 143 | ARRAY_SIZE(imx51_audmux_res)); | ||
| 144 | } | ||
| 145 | |||
| 146 | void __init imx51_init_late(void) | ||
| 147 | { | ||
| 148 | mx51_neon_fixup(); | ||
| 149 | imx5_pm_init(); | ||
| 150 | } | ||
| 151 | |||
| 152 | void __init imx53_init_late(void) | ||
| 153 | { | ||
| 154 | imx5_pm_init(); | ||
| 155 | } | ||
diff --git a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c deleted file mode 100644 index fb38436ca67f..000000000000 --- a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Exported ksyms of ARCH_MX1 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008, Darius Augulis <augulis.darius@gmail.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | |||
| 14 | #include <linux/platform_data/camera-mx1.h> | ||
| 15 | |||
| 16 | /* IMX camera FIQ handler */ | ||
| 17 | EXPORT_SYMBOL(mx1_camera_sof_fiq_start); | ||
| 18 | EXPORT_SYMBOL(mx1_camera_sof_fiq_end); | ||
diff --git a/arch/arm/mach-imx/mx1-camera-fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S deleted file mode 100644 index 9c69aa65bf17..000000000000 --- a/arch/arm/mach-imx/mx1-camera-fiq.S +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 3 | * | ||
| 4 | * Based on linux/arch/arm/lib/floppydma.S | ||
| 5 | * Copyright (C) 1995, 1996 Russell King | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/linkage.h> | ||
| 12 | #include <asm/assembler.h> | ||
| 13 | |||
| 14 | .text | ||
| 15 | .global mx1_camera_sof_fiq_end | ||
| 16 | .global mx1_camera_sof_fiq_start | ||
| 17 | mx1_camera_sof_fiq_start: | ||
| 18 | @ enable dma | ||
| 19 | ldr r12, [r9] | ||
| 20 | orr r12, r12, #0x00000001 | ||
| 21 | str r12, [r9] | ||
| 22 | @ unmask DMA interrupt | ||
| 23 | ldr r12, [r8] | ||
| 24 | bic r12, r12, r13 | ||
| 25 | str r12, [r8] | ||
| 26 | @ disable SOF interrupt | ||
| 27 | ldr r12, [r10] | ||
| 28 | bic r12, r12, #0x00010000 | ||
| 29 | str r12, [r10] | ||
| 30 | @ clear SOF flag | ||
| 31 | mov r12, #0x00010000 | ||
| 32 | str r12, [r11] | ||
| 33 | @ return from FIQ | ||
| 34 | subs pc, lr, #4 | ||
| 35 | mx1_camera_sof_fiq_end: | ||
diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c index 52d5b1574721..1e91a0918e83 100644 --- a/arch/arm/mach-imx/mx31moboard-devboard.c +++ b/arch/arm/mach-imx/mx31moboard-devboard.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | 24 | ||
| 25 | #include "common.h" | 25 | #include "common.h" |
| 26 | #include "devices-imx31.h" | 26 | #include "devices-imx31.h" |
| 27 | #include "ehci.h" | ||
| 27 | #include "hardware.h" | 28 | #include "hardware.h" |
| 28 | #include "iomux-mx3.h" | 29 | #include "iomux-mx3.h" |
| 29 | #include "ulpi.h" | 30 | #include "ulpi.h" |
| @@ -213,10 +214,8 @@ static int __init devboard_usbh1_init(void) | |||
| 213 | usbh1_pdata.otg = phy; | 214 | usbh1_pdata.otg = phy; |
| 214 | 215 | ||
| 215 | pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); | 216 | pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); |
| 216 | if (IS_ERR(pdev)) | ||
| 217 | return PTR_ERR(pdev); | ||
| 218 | 217 | ||
| 219 | return 0; | 218 | return PTR_ERR_OR_ZERO(pdev); |
| 220 | } | 219 | } |
| 221 | 220 | ||
| 222 | 221 | ||
diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c index a4f43e90f3c1..2e895a82a6eb 100644 --- a/arch/arm/mach-imx/mx31moboard-marxbot.c +++ b/arch/arm/mach-imx/mx31moboard-marxbot.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | 28 | ||
| 29 | #include "common.h" | 29 | #include "common.h" |
| 30 | #include "devices-imx31.h" | 30 | #include "devices-imx31.h" |
| 31 | #include "ehci.h" | ||
| 31 | #include "hardware.h" | 32 | #include "hardware.h" |
| 32 | #include "iomux-mx3.h" | 33 | #include "iomux-mx3.h" |
| 33 | #include "ulpi.h" | 34 | #include "ulpi.h" |
| @@ -327,10 +328,8 @@ static int __init marxbot_usbh1_init(void) | |||
| 327 | usbh1_pdata.otg = phy; | 328 | usbh1_pdata.otg = phy; |
| 328 | 329 | ||
| 329 | pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); | 330 | pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); |
| 330 | if (IS_ERR(pdev)) | ||
| 331 | return PTR_ERR(pdev); | ||
| 332 | 331 | ||
| 333 | return 0; | 332 | return PTR_ERR_OR_ZERO(pdev); |
| 334 | } | 333 | } |
| 335 | 334 | ||
| 336 | static const struct fsl_usb2_platform_data usb_pdata __initconst = { | 335 | static const struct fsl_usb2_platform_data usb_pdata __initconst = { |
diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c index 04ae45dbfaa7..89fc35a64448 100644 --- a/arch/arm/mach-imx/mx31moboard-smartbot.c +++ b/arch/arm/mach-imx/mx31moboard-smartbot.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include "board-mx31moboard.h" | 28 | #include "board-mx31moboard.h" |
| 29 | #include "common.h" | 29 | #include "common.h" |
| 30 | #include "devices-imx31.h" | 30 | #include "devices-imx31.h" |
| 31 | #include "ehci.h" | ||
| 31 | #include "hardware.h" | 32 | #include "hardware.h" |
| 32 | #include "iomux-mx3.h" | 33 | #include "iomux-mx3.h" |
| 33 | #include "ulpi.h" | 34 | #include "ulpi.h" |
| @@ -141,10 +142,8 @@ static int __init smartbot_otg_host_init(void) | |||
| 141 | return -ENODEV; | 142 | return -ENODEV; |
| 142 | 143 | ||
| 143 | pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); | 144 | pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); |
| 144 | if (IS_ERR(pdev)) | ||
| 145 | return PTR_ERR(pdev); | ||
| 146 | 145 | ||
| 147 | return 0; | 146 | return PTR_ERR_OR_ZERO(pdev); |
| 148 | } | 147 | } |
| 149 | #else | 148 | #else |
| 150 | static inline int smartbot_otg_host_init(void) { return 0; } | 149 | static inline int smartbot_otg_host_init(void) { return 0; } |
diff --git a/arch/arm/mach-imx/mx51.h b/arch/arm/mach-imx/mx51.h deleted file mode 100644 index af844f76261a..000000000000 --- a/arch/arm/mach-imx/mx51.h +++ /dev/null | |||
| @@ -1,346 +0,0 @@ | |||
| 1 | #ifndef __MACH_MX51_H__ | ||
| 2 | #define __MACH_MX51_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * IROM | ||
| 6 | */ | ||
| 7 | #define MX51_IROM_BASE_ADDR 0x0 | ||
| 8 | #define MX51_IROM_SIZE SZ_64K | ||
| 9 | |||
| 10 | /* | ||
| 11 | * IRAM | ||
| 12 | */ | ||
| 13 | #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ | ||
| 14 | #define MX51_IRAM_PARTITIONS 16 | ||
| 15 | #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ | ||
| 16 | |||
| 17 | #define MX51_GPU_BASE_ADDR 0x20000000 | ||
| 18 | #define MX51_GPU_CTRL_BASE_ADDR 0x30000000 | ||
| 19 | #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 | ||
| 20 | |||
| 21 | /* | ||
| 22 | * SPBA global module enabled #0 | ||
| 23 | */ | ||
| 24 | #define MX51_SPBA0_BASE_ADDR 0x70000000 | ||
| 25 | #define MX51_SPBA0_SIZE SZ_1M | ||
| 26 | |||
| 27 | #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) | ||
| 28 | #define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) | ||
| 29 | #define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) | ||
| 30 | #define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) | ||
| 31 | #define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) | ||
| 32 | #define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) | ||
| 33 | #define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) | ||
| 34 | #define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000) | ||
| 35 | #define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000) | ||
| 36 | #define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000) | ||
| 37 | #define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000) | ||
| 38 | #define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000) | ||
| 39 | |||
| 40 | /* | ||
| 41 | * AIPS 1 | ||
| 42 | */ | ||
| 43 | #define MX51_AIPS1_BASE_ADDR 0x73f00000 | ||
| 44 | #define MX51_AIPS1_SIZE SZ_1M | ||
| 45 | |||
| 46 | #define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) | ||
| 47 | #define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000) | ||
| 48 | #define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200) | ||
| 49 | #define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400) | ||
| 50 | #define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) | ||
| 51 | #define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) | ||
| 52 | #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) | ||
| 53 | #define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) | ||
| 54 | #define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) | ||
| 55 | #define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) | ||
| 56 | #define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) | ||
| 57 | #define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) | ||
| 58 | #define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) | ||
| 59 | #define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000) | ||
| 60 | #define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000) | ||
| 61 | #define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000) | ||
| 62 | #define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000) | ||
| 63 | #define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000) | ||
| 64 | #define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000) | ||
| 65 | #define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000) | ||
| 66 | #define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000) | ||
| 67 | #define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000) | ||
| 68 | #define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000) | ||
| 69 | |||
| 70 | /* | ||
| 71 | * AIPS 2 | ||
| 72 | */ | ||
| 73 | #define MX51_AIPS2_BASE_ADDR 0x83f00000 | ||
| 74 | #define MX51_AIPS2_SIZE SZ_1M | ||
| 75 | |||
| 76 | #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) | ||
| 77 | #define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000) | ||
| 78 | #define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000) | ||
| 79 | #define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000) | ||
| 80 | #define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000) | ||
| 81 | #define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000) | ||
| 82 | #define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) | ||
| 83 | #define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) | ||
| 84 | #define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) | ||
| 85 | #define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) | ||
| 86 | #define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) | ||
| 87 | #define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) | ||
| 88 | #define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) | ||
| 89 | #define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) | ||
| 90 | #define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) | ||
| 91 | #define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) | ||
| 92 | #define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) | ||
| 93 | #define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) | ||
| 94 | #define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000) | ||
| 95 | #define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000) | ||
| 96 | #define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000) | ||
| 97 | #define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000) | ||
| 98 | #define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000) | ||
| 99 | #define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00) | ||
| 100 | #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) | ||
| 101 | #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) | ||
| 102 | #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) | ||
| 103 | #define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) | ||
| 104 | #define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) | ||
| 105 | #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) | ||
| 106 | #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) | ||
| 107 | #define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000) | ||
| 108 | |||
| 109 | #define MX51_CSD0_BASE_ADDR 0x90000000 | ||
| 110 | #define MX51_CSD1_BASE_ADDR 0xa0000000 | ||
| 111 | #define MX51_CS0_BASE_ADDR 0xb0000000 | ||
| 112 | #define MX51_CS1_BASE_ADDR 0xb8000000 | ||
| 113 | #define MX51_CS2_BASE_ADDR 0xc0000000 | ||
| 114 | #define MX51_CS3_BASE_ADDR 0xc8000000 | ||
| 115 | #define MX51_CS4_BASE_ADDR 0xcc000000 | ||
| 116 | #define MX51_CS5_BASE_ADDR 0xce000000 | ||
| 117 | |||
| 118 | /* | ||
| 119 | * NFC | ||
| 120 | */ | ||
| 121 | #define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */ | ||
| 122 | #define MX51_NFC_AXI_SIZE SZ_64K | ||
| 123 | |||
| 124 | #define MX51_GPU2D_BASE_ADDR 0xd0000000 | ||
| 125 | #define MX51_TZIC_BASE_ADDR 0xe0000000 | ||
| 126 | #define MX51_TZIC_SIZE SZ_16K | ||
| 127 | |||
| 128 | #define MX51_IO_P2V(x) IMX_IO_P2V(x) | ||
| 129 | #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) | ||
| 130 | |||
| 131 | /* | ||
| 132 | * defines for SPBA modules | ||
| 133 | */ | ||
| 134 | #define MX51_SPBA_SDHC1 0x04 | ||
| 135 | #define MX51_SPBA_SDHC2 0x08 | ||
| 136 | #define MX51_SPBA_UART3 0x0c | ||
| 137 | #define MX51_SPBA_CSPI1 0x10 | ||
| 138 | #define MX51_SPBA_SSI2 0x14 | ||
| 139 | #define MX51_SPBA_SDHC3 0x20 | ||
| 140 | #define MX51_SPBA_SDHC4 0x24 | ||
| 141 | #define MX51_SPBA_SPDIF 0x28 | ||
| 142 | #define MX51_SPBA_ATA 0x30 | ||
| 143 | #define MX51_SPBA_SLIM 0x34 | ||
| 144 | #define MX51_SPBA_HSI2C 0x38 | ||
| 145 | #define MX51_SPBA_CTRL 0x3c | ||
| 146 | |||
| 147 | /* | ||
| 148 | * Defines for modules using static and dynamic DMA channels | ||
| 149 | */ | ||
| 150 | #define MX51_MXC_DMA_CHANNEL_IRAM 30 | ||
| 151 | #define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL | ||
| 152 | #define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL | ||
| 153 | #define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL | ||
| 154 | #define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL | ||
| 155 | #define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL | ||
| 156 | #define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL | ||
| 157 | #define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL | ||
| 158 | #define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL | ||
| 159 | #define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL | ||
| 160 | #define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL | ||
| 161 | #define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL | ||
| 162 | #define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL | ||
| 163 | #ifdef CONFIG_SDMA_IRAM | ||
| 164 | #define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1) | ||
| 165 | #else /*CONFIG_SDMA_IRAM */ | ||
| 166 | #define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL | ||
| 167 | #endif /*CONFIG_SDMA_IRAM */ | ||
| 168 | #define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL | ||
| 169 | #define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL | ||
| 170 | #define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL | ||
| 171 | #define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL | ||
| 172 | #define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL | ||
| 173 | #define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL | ||
| 174 | #define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL | ||
| 175 | #define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL | ||
| 176 | #define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL | ||
| 177 | |||
| 178 | #define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 | ||
| 179 | |||
| 180 | /* | ||
| 181 | * DMA request assignments | ||
| 182 | */ | ||
| 183 | #define MX51_DMA_REQ_VPU 0 | ||
| 184 | #define MX51_DMA_REQ_GPC 1 | ||
| 185 | #define MX51_DMA_REQ_ATA_RX 2 | ||
| 186 | #define MX51_DMA_REQ_ATA_TX 3 | ||
| 187 | #define MX51_DMA_REQ_ATA_TX_END 4 | ||
| 188 | #define MX51_DMA_REQ_SLIM_B 5 | ||
| 189 | #define MX51_DMA_REQ_CSPI1_RX 6 | ||
| 190 | #define MX51_DMA_REQ_CSPI1_TX 7 | ||
| 191 | #define MX51_DMA_REQ_CSPI2_RX 8 | ||
| 192 | #define MX51_DMA_REQ_CSPI2_TX 9 | ||
| 193 | #define MX51_DMA_REQ_HS_I2C_TX 10 | ||
| 194 | #define MX51_DMA_REQ_HS_I2C_RX 11 | ||
| 195 | #define MX51_DMA_REQ_FIRI_RX 12 | ||
| 196 | #define MX51_DMA_REQ_FIRI_TX 13 | ||
| 197 | #define MX51_DMA_REQ_EXTREQ1 14 | ||
| 198 | #define MX51_DMA_REQ_GPU 15 | ||
| 199 | #define MX51_DMA_REQ_UART2_RX 16 | ||
| 200 | #define MX51_DMA_REQ_UART2_TX 17 | ||
| 201 | #define MX51_DMA_REQ_UART1_RX 18 | ||
| 202 | #define MX51_DMA_REQ_UART1_TX 19 | ||
| 203 | #define MX51_DMA_REQ_SDHC1 20 | ||
| 204 | #define MX51_DMA_REQ_SDHC2 21 | ||
| 205 | #define MX51_DMA_REQ_SSI2_RX1 22 | ||
| 206 | #define MX51_DMA_REQ_SSI2_TX1 23 | ||
| 207 | #define MX51_DMA_REQ_SSI2_RX0 24 | ||
| 208 | #define MX51_DMA_REQ_SSI2_TX0 25 | ||
| 209 | #define MX51_DMA_REQ_SSI1_RX1 26 | ||
| 210 | #define MX51_DMA_REQ_SSI1_TX1 27 | ||
| 211 | #define MX51_DMA_REQ_SSI1_RX0 28 | ||
| 212 | #define MX51_DMA_REQ_SSI1_TX0 29 | ||
| 213 | #define MX51_DMA_REQ_EMI_RD 30 | ||
| 214 | #define MX51_DMA_REQ_CTI2_0 31 | ||
| 215 | #define MX51_DMA_REQ_EMI_WR 32 | ||
| 216 | #define MX51_DMA_REQ_CTI2_1 33 | ||
| 217 | #define MX51_DMA_REQ_EPIT2 34 | ||
| 218 | #define MX51_DMA_REQ_SSI3_RX1 35 | ||
| 219 | #define MX51_DMA_REQ_IPU 36 | ||
| 220 | #define MX51_DMA_REQ_SSI3_TX1 37 | ||
| 221 | #define MX51_DMA_REQ_CSPI_RX 38 | ||
| 222 | #define MX51_DMA_REQ_CSPI_TX 39 | ||
| 223 | #define MX51_DMA_REQ_SDHC3 40 | ||
| 224 | #define MX51_DMA_REQ_SDHC4 41 | ||
| 225 | #define MX51_DMA_REQ_SLIM_B_TX 42 | ||
| 226 | #define MX51_DMA_REQ_UART3_RX 43 | ||
| 227 | #define MX51_DMA_REQ_UART3_TX 44 | ||
| 228 | #define MX51_DMA_REQ_SPDIF 45 | ||
| 229 | #define MX51_DMA_REQ_SSI3_RX0 46 | ||
| 230 | #define MX51_DMA_REQ_SSI3_TX0 47 | ||
| 231 | |||
| 232 | /* | ||
| 233 | * Interrupt numbers | ||
| 234 | */ | ||
| 235 | #include <asm/irq.h> | ||
| 236 | #define MX51_INT_BASE (NR_IRQS_LEGACY + 0) | ||
| 237 | #define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0) | ||
| 238 | #define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1) | ||
| 239 | #define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2) | ||
| 240 | #define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3) | ||
| 241 | #define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4) | ||
| 242 | #define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5) | ||
| 243 | #define MX51_INT_SDMA (NR_IRQS_LEGACY + 6) | ||
| 244 | #define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7) | ||
| 245 | #define MX51_INT_NFC (NR_IRQS_LEGACY + 8) | ||
| 246 | #define MX51_INT_VPU (NR_IRQS_LEGACY + 9) | ||
| 247 | #define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10) | ||
| 248 | #define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11) | ||
| 249 | #define MX51_INT_GPU (NR_IRQS_LEGACY + 12) | ||
| 250 | #define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13) | ||
| 251 | #define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14) | ||
| 252 | #define MX51_INT_EMI (NR_IRQS_LEGACY + 15) | ||
| 253 | #define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16) | ||
| 254 | #define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17) | ||
| 255 | #define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18) | ||
| 256 | #define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) | ||
| 257 | #define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) | ||
| 258 | #define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21) | ||
| 259 | #define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22) | ||
| 260 | #define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23) | ||
| 261 | #define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) | ||
| 262 | #define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) | ||
| 263 | #define MX51_INT_RTIC (NR_IRQS_LEGACY + 26) | ||
| 264 | #define MX51_INT_CSU (NR_IRQS_LEGACY + 27) | ||
| 265 | #define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28) | ||
| 266 | #define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29) | ||
| 267 | #define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30) | ||
| 268 | #define MX51_INT_UART1 (NR_IRQS_LEGACY + 31) | ||
| 269 | #define MX51_INT_UART2 (NR_IRQS_LEGACY + 32) | ||
| 270 | #define MX51_INT_UART3 (NR_IRQS_LEGACY + 33) | ||
| 271 | #define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34) | ||
| 272 | #define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35) | ||
| 273 | #define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36) | ||
| 274 | #define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37) | ||
| 275 | #define MX51_INT_CSPI (NR_IRQS_LEGACY + 38) | ||
| 276 | #define MX51_INT_GPT (NR_IRQS_LEGACY + 39) | ||
| 277 | #define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40) | ||
| 278 | #define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41) | ||
| 279 | #define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) | ||
| 280 | #define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) | ||
| 281 | #define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) | ||
| 282 | #define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) | ||
| 283 | #define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) | ||
| 284 | #define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) | ||
| 285 | #define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) | ||
| 286 | #define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) | ||
| 287 | #define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) | ||
| 288 | #define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) | ||
| 289 | #define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) | ||
| 290 | #define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) | ||
| 291 | #define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) | ||
| 292 | #define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) | ||
| 293 | #define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) | ||
| 294 | #define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) | ||
| 295 | #define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58) | ||
| 296 | #define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59) | ||
| 297 | #define MX51_INT_KPP (NR_IRQS_LEGACY + 60) | ||
| 298 | #define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61) | ||
| 299 | #define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62) | ||
| 300 | #define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63) | ||
| 301 | #define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64) | ||
| 302 | #define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65) | ||
| 303 | #define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66) | ||
| 304 | #define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67) | ||
| 305 | #define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68) | ||
| 306 | #define MX51_INT_IIM (NR_IRQS_LEGACY + 69) | ||
| 307 | #define MX51_INT_ATA (NR_IRQS_LEGACY + 70) | ||
| 308 | #define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71) | ||
| 309 | #define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72) | ||
| 310 | #define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73) | ||
| 311 | #define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74) | ||
| 312 | #define MX51_INT_SRC (NR_IRQS_LEGACY + 75) | ||
| 313 | #define MX51_INT_NM (NR_IRQS_LEGACY + 76) | ||
| 314 | #define MX51_INT_PMU (NR_IRQS_LEGACY + 77) | ||
| 315 | #define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) | ||
| 316 | #define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) | ||
| 317 | #define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) | ||
| 318 | #define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81) | ||
| 319 | #define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82) | ||
| 320 | #define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83) | ||
| 321 | #define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) | ||
| 322 | #define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) | ||
| 323 | #define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86) | ||
| 324 | #define MX51_INT_FEC (NR_IRQS_LEGACY + 87) | ||
| 325 | #define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88) | ||
| 326 | #define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) | ||
| 327 | #define MX51_INT_SJC (NR_IRQS_LEGACY + 90) | ||
| 328 | #define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91) | ||
| 329 | #define MX51_INT_TVE (NR_IRQS_LEGACY + 92) | ||
| 330 | #define MX51_INT_FIRI (NR_IRQS_LEGACY + 93) | ||
| 331 | #define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94) | ||
| 332 | #define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) | ||
| 333 | #define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96) | ||
| 334 | #define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) | ||
| 335 | #define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) | ||
| 336 | #define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99) | ||
| 337 | #define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) | ||
| 338 | #define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101) | ||
| 339 | #define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) | ||
| 340 | |||
| 341 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | ||
| 342 | extern int mx51_revision(void); | ||
| 343 | extern void mx51_display_revision(void); | ||
| 344 | #endif | ||
| 345 | |||
| 346 | #endif /* ifndef __MACH_MX51_H__ */ | ||
diff --git a/arch/arm/mach-imx/mx53.h b/arch/arm/mach-imx/mx53.h deleted file mode 100644 index f829d1c22501..000000000000 --- a/arch/arm/mach-imx/mx53.h +++ /dev/null | |||
| @@ -1,342 +0,0 @@ | |||
| 1 | #ifndef __MACH_MX53_H__ | ||
| 2 | #define __MACH_MX53_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * IROM | ||
| 6 | */ | ||
| 7 | #define MX53_IROM_BASE_ADDR 0x0 | ||
| 8 | #define MX53_IROM_SIZE SZ_64K | ||
| 9 | |||
| 10 | /* TZIC */ | ||
| 11 | #define MX53_TZIC_BASE_ADDR 0x0FFFC000 | ||
| 12 | #define MX53_TZIC_SIZE SZ_16K | ||
| 13 | |||
| 14 | /* | ||
| 15 | * AHCI SATA | ||
| 16 | */ | ||
| 17 | #define MX53_SATA_BASE_ADDR 0x10000000 | ||
| 18 | |||
| 19 | /* | ||
| 20 | * NFC | ||
| 21 | */ | ||
| 22 | #define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ | ||
| 23 | #define MX53_NFC_AXI_SIZE SZ_64K | ||
| 24 | |||
| 25 | /* | ||
| 26 | * IRAM | ||
| 27 | */ | ||
| 28 | #define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ | ||
| 29 | #define MX53_IRAM_PARTITIONS 16 | ||
| 30 | #define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */ | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Graphics Memory of GPU | ||
| 34 | */ | ||
| 35 | #define MX53_IPU_CTRL_BASE_ADDR 0x18000000 | ||
| 36 | #define MX53_GPU2D_BASE_ADDR 0x20000000 | ||
| 37 | #define MX53_GPU_BASE_ADDR 0x30000000 | ||
| 38 | #define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 | ||
| 39 | |||
| 40 | #define MX53_DEBUG_BASE_ADDR 0x40000000 | ||
| 41 | #define MX53_DEBUG_SIZE SZ_1M | ||
| 42 | #define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000) | ||
| 43 | #define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000) | ||
| 44 | #define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000) | ||
| 45 | #define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000) | ||
| 46 | #define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000) | ||
| 47 | #define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000) | ||
| 48 | #define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000) | ||
| 49 | #define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000) | ||
| 50 | |||
| 51 | /* | ||
| 52 | * SPBA global module enabled #0 | ||
| 53 | */ | ||
| 54 | #define MX53_SPBA0_BASE_ADDR 0x50000000 | ||
| 55 | #define MX53_SPBA0_SIZE SZ_1M | ||
| 56 | |||
| 57 | #define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) | ||
| 58 | #define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) | ||
| 59 | #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) | ||
| 60 | #define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) | ||
| 61 | #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) | ||
| 62 | #define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) | ||
| 63 | #define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) | ||
| 64 | #define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) | ||
| 65 | #define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) | ||
| 66 | #define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) | ||
| 67 | #define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) | ||
| 68 | #define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) | ||
| 69 | #define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) | ||
| 70 | |||
| 71 | /* | ||
| 72 | * AIPS 1 | ||
| 73 | */ | ||
| 74 | #define MX53_AIPS1_BASE_ADDR 0x53F00000 | ||
| 75 | #define MX53_AIPS1_SIZE SZ_1M | ||
| 76 | |||
| 77 | #define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) | ||
| 78 | #define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) | ||
| 79 | #define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) | ||
| 80 | #define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) | ||
| 81 | #define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) | ||
| 82 | #define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) | ||
| 83 | #define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) | ||
| 84 | #define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) | ||
| 85 | #define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) | ||
| 86 | #define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) | ||
| 87 | #define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) | ||
| 88 | #define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) | ||
| 89 | #define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) | ||
| 90 | #define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) | ||
| 91 | #define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) | ||
| 92 | #define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) | ||
| 93 | #define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) | ||
| 94 | #define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) | ||
| 95 | #define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) | ||
| 96 | #define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) | ||
| 97 | #define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) | ||
| 98 | #define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) | ||
| 99 | #define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) | ||
| 100 | #define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) | ||
| 101 | #define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) | ||
| 102 | #define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) | ||
| 103 | |||
| 104 | /* | ||
| 105 | * AIPS 2 | ||
| 106 | */ | ||
| 107 | #define MX53_AIPS2_BASE_ADDR 0x63F00000 | ||
| 108 | #define MX53_AIPS2_SIZE SZ_1M | ||
| 109 | |||
| 110 | #define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) | ||
| 111 | #define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) | ||
| 112 | #define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) | ||
| 113 | #define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) | ||
| 114 | #define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) | ||
| 115 | #define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) | ||
| 116 | #define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) | ||
| 117 | #define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) | ||
| 118 | #define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) | ||
| 119 | #define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) | ||
| 120 | #define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) | ||
| 121 | #define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) | ||
| 122 | #define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) | ||
| 123 | #define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) | ||
| 124 | #define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) | ||
| 125 | #define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) | ||
| 126 | #define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) | ||
| 127 | #define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) | ||
| 128 | #define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) | ||
| 129 | #define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) | ||
| 130 | #define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) | ||
| 131 | #define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) | ||
| 132 | #define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) | ||
| 133 | #define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) | ||
| 134 | #define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) | ||
| 135 | #define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) | ||
| 136 | #define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) | ||
| 137 | #define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) | ||
| 138 | #define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) | ||
| 139 | #define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) | ||
| 140 | #define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) | ||
| 141 | #define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) | ||
| 142 | #define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) | ||
| 143 | #define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) | ||
| 144 | #define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) | ||
| 145 | |||
| 146 | /* | ||
| 147 | * Memory regions and CS | ||
| 148 | */ | ||
| 149 | #define MX53_CSD0_BASE_ADDR 0x70000000 | ||
| 150 | #define MX53_CSD1_BASE_ADDR 0xB0000000 | ||
| 151 | #define MX53_CS0_BASE_ADDR 0xF0000000 | ||
| 152 | #define MX53_CS1_32MB_BASE_ADDR 0xF2000000 | ||
| 153 | #define MX53_CS1_64MB_BASE_ADDR 0xF4000000 | ||
| 154 | #define MX53_CS2_64MB_BASE_ADDR 0xF4000000 | ||
| 155 | #define MX53_CS2_96MB_BASE_ADDR 0xF6000000 | ||
| 156 | #define MX53_CS3_BASE_ADDR 0xF6000000 | ||
| 157 | |||
| 158 | #define MX53_IO_P2V(x) IMX_IO_P2V(x) | ||
| 159 | #define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) | ||
| 160 | |||
| 161 | /* | ||
| 162 | * defines for SPBA modules | ||
| 163 | */ | ||
| 164 | #define MX53_SPBA_SDHC1 0x04 | ||
| 165 | #define MX53_SPBA_SDHC2 0x08 | ||
| 166 | #define MX53_SPBA_UART3 0x0C | ||
| 167 | #define MX53_SPBA_CSPI1 0x10 | ||
| 168 | #define MX53_SPBA_SSI2 0x14 | ||
| 169 | #define MX53_SPBA_SDHC3 0x20 | ||
| 170 | #define MX53_SPBA_SDHC4 0x24 | ||
| 171 | #define MX53_SPBA_SPDIF 0x28 | ||
| 172 | #define MX53_SPBA_ATA 0x30 | ||
| 173 | #define MX53_SPBA_SLIM 0x34 | ||
| 174 | #define MX53_SPBA_HSI2C 0x38 | ||
| 175 | #define MX53_SPBA_CTRL 0x3C | ||
| 176 | |||
| 177 | /* | ||
| 178 | * DMA request assignments | ||
| 179 | */ | ||
| 180 | #define MX53_DMA_REQ_SSI3_TX0 47 | ||
| 181 | #define MX53_DMA_REQ_SSI3_RX0 46 | ||
| 182 | #define MX53_DMA_REQ_SSI3_TX1 45 | ||
| 183 | #define MX53_DMA_REQ_SSI3_RX1 44 | ||
| 184 | #define MX53_DMA_REQ_UART3_TX 43 | ||
| 185 | #define MX53_DMA_REQ_UART3_RX 42 | ||
| 186 | #define MX53_DMA_REQ_ESAI_TX 41 | ||
| 187 | #define MX53_DMA_REQ_ESAI_RX 40 | ||
| 188 | #define MX53_DMA_REQ_CSPI_TX 39 | ||
| 189 | #define MX53_DMA_REQ_CSPI_RX 38 | ||
| 190 | #define MX53_DMA_REQ_ASRC_DMA6 37 | ||
| 191 | #define MX53_DMA_REQ_ASRC_DMA5 36 | ||
| 192 | #define MX53_DMA_REQ_ASRC_DMA4 35 | ||
| 193 | #define MX53_DMA_REQ_ASRC_DMA3 34 | ||
| 194 | #define MX53_DMA_REQ_ASRC_DMA2 33 | ||
| 195 | #define MX53_DMA_REQ_ASRC_DMA1 32 | ||
| 196 | #define MX53_DMA_REQ_EMI_WR 31 | ||
| 197 | #define MX53_DMA_REQ_EMI_RD 30 | ||
| 198 | #define MX53_DMA_REQ_SSI1_TX0 29 | ||
| 199 | #define MX53_DMA_REQ_SSI1_RX0 28 | ||
| 200 | #define MX53_DMA_REQ_SSI1_TX1 27 | ||
| 201 | #define MX53_DMA_REQ_SSI1_RX1 26 | ||
| 202 | #define MX53_DMA_REQ_SSI2_TX0 25 | ||
| 203 | #define MX53_DMA_REQ_SSI2_RX0 24 | ||
| 204 | #define MX53_DMA_REQ_SSI2_TX1 23 | ||
| 205 | #define MX53_DMA_REQ_SSI2_RX1 22 | ||
| 206 | #define MX53_DMA_REQ_I2C2_SDHC2 21 | ||
| 207 | #define MX53_DMA_REQ_I2C1_SDHC1 20 | ||
| 208 | #define MX53_DMA_REQ_UART1_TX 19 | ||
| 209 | #define MX53_DMA_REQ_UART1_RX 18 | ||
| 210 | #define MX53_DMA_REQ_UART5_TX 17 | ||
| 211 | #define MX53_DMA_REQ_UART5_RX 16 | ||
| 212 | #define MX53_DMA_REQ_SPDIF_TX 15 | ||
| 213 | #define MX53_DMA_REQ_SPDIF_RX 14 | ||
| 214 | #define MX53_DMA_REQ_UART2_FIRI_TX 13 | ||
| 215 | #define MX53_DMA_REQ_UART2_FIRI_RX 12 | ||
| 216 | #define MX53_DMA_REQ_SDHC4 11 | ||
| 217 | #define MX53_DMA_REQ_I2C3_SDHC3 10 | ||
| 218 | #define MX53_DMA_REQ_CSPI2_TX 9 | ||
| 219 | #define MX53_DMA_REQ_CSPI2_RX 8 | ||
| 220 | #define MX53_DMA_REQ_CSPI1_TX 7 | ||
| 221 | #define MX53_DMA_REQ_CSPI1_RX 6 | ||
| 222 | #define MX53_DMA_REQ_IPU 5 | ||
| 223 | #define MX53_DMA_REQ_ATA_TX_END 4 | ||
| 224 | #define MX53_DMA_REQ_ATA_UART4_TX 3 | ||
| 225 | #define MX53_DMA_REQ_ATA_UART4_RX 2 | ||
| 226 | #define MX53_DMA_REQ_GPC 1 | ||
| 227 | #define MX53_DMA_REQ_VPU 0 | ||
| 228 | |||
| 229 | /* | ||
| 230 | * Interrupt numbers | ||
| 231 | */ | ||
| 232 | #include <asm/irq.h> | ||
| 233 | #define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0) | ||
| 234 | #define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1) | ||
| 235 | #define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2) | ||
| 236 | #define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3) | ||
| 237 | #define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4) | ||
| 238 | #define MX53_INT_DAP (NR_IRQS_LEGACY + 5) | ||
| 239 | #define MX53_INT_SDMA (NR_IRQS_LEGACY + 6) | ||
| 240 | #define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7) | ||
| 241 | #define MX53_INT_NFC (NR_IRQS_LEGACY + 8) | ||
| 242 | #define MX53_INT_VPU (NR_IRQS_LEGACY + 9) | ||
| 243 | #define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10) | ||
| 244 | #define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11) | ||
| 245 | #define MX53_INT_GPU (NR_IRQS_LEGACY + 12) | ||
| 246 | #define MX53_INT_UART4 (NR_IRQS_LEGACY + 13) | ||
| 247 | #define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14) | ||
| 248 | #define MX53_INT_EMI (NR_IRQS_LEGACY + 15) | ||
| 249 | #define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16) | ||
| 250 | #define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17) | ||
| 251 | #define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18) | ||
| 252 | #define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) | ||
| 253 | #define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) | ||
| 254 | #define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21) | ||
| 255 | #define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22) | ||
| 256 | #define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23) | ||
| 257 | #define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) | ||
| 258 | #define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) | ||
| 259 | #define MX53_INT_RTIC (NR_IRQS_LEGACY + 26) | ||
| 260 | #define MX53_INT_CSU (NR_IRQS_LEGACY + 27) | ||
| 261 | #define MX53_INT_SATA (NR_IRQS_LEGACY + 28) | ||
| 262 | #define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29) | ||
| 263 | #define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30) | ||
| 264 | #define MX53_INT_UART1 (NR_IRQS_LEGACY + 31) | ||
| 265 | #define MX53_INT_UART2 (NR_IRQS_LEGACY + 32) | ||
| 266 | #define MX53_INT_UART3 (NR_IRQS_LEGACY + 33) | ||
| 267 | #define MX53_INT_RTC (NR_IRQS_LEGACY + 34) | ||
| 268 | #define MX53_INT_PTP (NR_IRQS_LEGACY + 35) | ||
| 269 | #define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36) | ||
| 270 | #define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37) | ||
| 271 | #define MX53_INT_CSPI (NR_IRQS_LEGACY + 38) | ||
| 272 | #define MX53_INT_GPT (NR_IRQS_LEGACY + 39) | ||
| 273 | #define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40) | ||
| 274 | #define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41) | ||
| 275 | #define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) | ||
| 276 | #define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) | ||
| 277 | #define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) | ||
| 278 | #define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) | ||
| 279 | #define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) | ||
| 280 | #define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) | ||
| 281 | #define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) | ||
| 282 | #define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) | ||
| 283 | #define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) | ||
| 284 | #define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) | ||
| 285 | #define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) | ||
| 286 | #define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) | ||
| 287 | #define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) | ||
| 288 | #define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) | ||
| 289 | #define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) | ||
| 290 | #define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) | ||
| 291 | #define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58) | ||
| 292 | #define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59) | ||
| 293 | #define MX53_INT_KPP (NR_IRQS_LEGACY + 60) | ||
| 294 | #define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61) | ||
| 295 | #define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62) | ||
| 296 | #define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63) | ||
| 297 | #define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64) | ||
| 298 | #define MX53_INT_MLB (NR_IRQS_LEGACY + 65) | ||
| 299 | #define MX53_INT_ASRC (NR_IRQS_LEGACY + 66) | ||
| 300 | #define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67) | ||
| 301 | #define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68) | ||
| 302 | #define MX53_INT_IIM (NR_IRQS_LEGACY + 69) | ||
| 303 | #define MX53_INT_ATA (NR_IRQS_LEGACY + 70) | ||
| 304 | #define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71) | ||
| 305 | #define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72) | ||
| 306 | #define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73) | ||
| 307 | #define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74) | ||
| 308 | #define MX53_INT_SRC (NR_IRQS_LEGACY + 75) | ||
| 309 | #define MX53_INT_NM (NR_IRQS_LEGACY + 76) | ||
| 310 | #define MX53_INT_PMU (NR_IRQS_LEGACY + 77) | ||
| 311 | #define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) | ||
| 312 | #define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) | ||
| 313 | #define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) | ||
| 314 | #define MX53_INT_ESAI (NR_IRQS_LEGACY + 81) | ||
| 315 | #define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82) | ||
| 316 | #define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83) | ||
| 317 | #define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) | ||
| 318 | #define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) | ||
| 319 | #define MX53_INT_UART5 (NR_IRQS_LEGACY + 86) | ||
| 320 | #define MX53_INT_FEC (NR_IRQS_LEGACY + 87) | ||
| 321 | #define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88) | ||
| 322 | #define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) | ||
| 323 | #define MX53_INT_SJC (NR_IRQS_LEGACY + 90) | ||
| 324 | #define MX53_INT_TVE (NR_IRQS_LEGACY + 92) | ||
| 325 | #define MX53_INT_FIRI (NR_IRQS_LEGACY + 93) | ||
| 326 | #define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94) | ||
| 327 | #define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) | ||
| 328 | #define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96) | ||
| 329 | #define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) | ||
| 330 | #define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) | ||
| 331 | #define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99) | ||
| 332 | #define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) | ||
| 333 | #define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101) | ||
| 334 | #define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) | ||
| 335 | #define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) | ||
| 336 | #define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) | ||
| 337 | #define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) | ||
| 338 | #define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) | ||
| 339 | #define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107) | ||
| 340 | #define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108) | ||
| 341 | |||
| 342 | #endif /* ifndef __MACH_MX53_H__ */ | ||
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 75d6a37e1ae4..a39b69ef4301 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h | |||
| @@ -154,10 +154,17 @@ extern unsigned int __mxc_cpu_type; | |||
| 154 | #endif | 154 | #endif |
| 155 | 155 | ||
| 156 | #ifndef __ASSEMBLY__ | 156 | #ifndef __ASSEMBLY__ |
| 157 | #ifdef CONFIG_SOC_IMX6SL | ||
| 157 | static inline bool cpu_is_imx6sl(void) | 158 | static inline bool cpu_is_imx6sl(void) |
| 158 | { | 159 | { |
| 159 | return __mxc_cpu_type == MXC_CPU_IMX6SL; | 160 | return __mxc_cpu_type == MXC_CPU_IMX6SL; |
| 160 | } | 161 | } |
| 162 | #else | ||
| 163 | static inline bool cpu_is_imx6sl(void) | ||
| 164 | { | ||
| 165 | return false; | ||
| 166 | } | ||
| 167 | #endif | ||
| 161 | 168 | ||
| 162 | static inline bool cpu_is_imx6dl(void) | 169 | static inline bool cpu_is_imx6dl(void) |
| 163 | { | 170 | { |
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c index 58aeaf5baaf6..f1f80ab73e69 100644 --- a/arch/arm/mach-imx/pm-imx5.c +++ b/arch/arm/mach-imx/pm-imx5.c | |||
| @@ -19,9 +19,26 @@ | |||
| 19 | 19 | ||
| 20 | #include "common.h" | 20 | #include "common.h" |
| 21 | #include "cpuidle.h" | 21 | #include "cpuidle.h" |
| 22 | #include "crm-regs-imx5.h" | ||
| 23 | #include "hardware.h" | 22 | #include "hardware.h" |
| 24 | 23 | ||
| 24 | #define MXC_CCM_CLPCR 0x54 | ||
| 25 | #define MXC_CCM_CLPCR_LPM_OFFSET 0 | ||
| 26 | #define MXC_CCM_CLPCR_LPM_MASK 0x3 | ||
| 27 | #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 | ||
| 28 | #define MXC_CCM_CLPCR_VSTBY (0x1 << 8) | ||
| 29 | #define MXC_CCM_CLPCR_SBYOS (0x1 << 6) | ||
| 30 | |||
| 31 | #define MXC_CORTEXA8_PLAT_LPC 0xc | ||
| 32 | #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) | ||
| 33 | #define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) | ||
| 34 | |||
| 35 | #define MXC_SRPG_NEON_SRPGCR 0x280 | ||
| 36 | #define MXC_SRPG_ARM_SRPGCR 0x2a0 | ||
| 37 | #define MXC_SRPG_EMPGC0_SRPGCR 0x2c0 | ||
| 38 | #define MXC_SRPG_EMPGC1_SRPGCR 0x2d0 | ||
| 39 | |||
| 40 | #define MXC_SRPGCR_PCR 1 | ||
| 41 | |||
| 25 | /* | 42 | /* |
| 26 | * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit. | 43 | * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit. |
| 27 | * This is also the lowest power state possible without affecting | 44 | * This is also the lowest power state possible without affecting |
| @@ -32,6 +49,30 @@ | |||
| 32 | */ | 49 | */ |
| 33 | #define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF | 50 | #define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF |
| 34 | 51 | ||
| 52 | struct imx5_pm_data { | ||
| 53 | phys_addr_t cortex_addr; | ||
| 54 | phys_addr_t gpc_addr; | ||
| 55 | }; | ||
| 56 | |||
| 57 | static const struct imx5_pm_data imx51_pm_data __initconst = { | ||
| 58 | .cortex_addr = 0x83fa0000, | ||
| 59 | .gpc_addr = 0x73fd8000, | ||
| 60 | }; | ||
| 61 | |||
| 62 | static const struct imx5_pm_data imx53_pm_data __initconst = { | ||
| 63 | .cortex_addr = 0x63fa0000, | ||
| 64 | .gpc_addr = 0x53fd8000, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static void __iomem *ccm_base; | ||
| 68 | static void __iomem *cortex_base; | ||
| 69 | static void __iomem *gpc_base; | ||
| 70 | |||
| 71 | void __init imx5_pm_set_ccm_base(void __iomem *base) | ||
| 72 | { | ||
| 73 | ccm_base = base; | ||
| 74 | } | ||
| 75 | |||
| 35 | /* | 76 | /* |
| 36 | * set cpu low power mode before WFI instruction. This function is called | 77 | * set cpu low power mode before WFI instruction. This function is called |
| 37 | * mx5 because it can be used for mx51, and mx53. | 78 | * mx5 because it can be used for mx51, and mx53. |
| @@ -43,12 +84,16 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) | |||
| 43 | int stop_mode = 0; | 84 | int stop_mode = 0; |
| 44 | 85 | ||
| 45 | /* always allow platform to issue a deep sleep mode request */ | 86 | /* always allow platform to issue a deep sleep mode request */ |
| 46 | plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & | 87 | plat_lpc = __raw_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) & |
| 47 | ~(MXC_CORTEXA8_PLAT_LPC_DSM); | 88 | ~(MXC_CORTEXA8_PLAT_LPC_DSM); |
| 48 | ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); | 89 | ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) & |
| 49 | arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); | 90 | ~(MXC_CCM_CLPCR_LPM_MASK); |
| 50 | empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); | 91 | arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & |
| 51 | empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); | 92 | ~(MXC_SRPGCR_PCR); |
| 93 | empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & | ||
| 94 | ~(MXC_SRPGCR_PCR); | ||
| 95 | empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & | ||
| 96 | ~(MXC_SRPGCR_PCR); | ||
| 52 | 97 | ||
| 53 | switch (mode) { | 98 | switch (mode) { |
| 54 | case WAIT_CLOCKED: | 99 | case WAIT_CLOCKED: |
| @@ -82,17 +127,17 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) | |||
| 82 | return; | 127 | return; |
| 83 | } | 128 | } |
| 84 | 129 | ||
| 85 | __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); | 130 | __raw_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC); |
| 86 | __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); | 131 | __raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); |
| 87 | __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); | 132 | __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR); |
| 88 | __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); | 133 | __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR); |
| 89 | 134 | ||
| 90 | if (stop_mode) { | 135 | if (stop_mode) { |
| 91 | empgc0 |= MXC_SRPGCR_PCR; | 136 | empgc0 |= MXC_SRPGCR_PCR; |
| 92 | empgc1 |= MXC_SRPGCR_PCR; | 137 | empgc1 |= MXC_SRPGCR_PCR; |
| 93 | 138 | ||
| 94 | __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); | 139 | __raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); |
| 95 | __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); | 140 | __raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); |
| 96 | } | 141 | } |
| 97 | } | 142 | } |
| 98 | 143 | ||
| @@ -114,8 +159,8 @@ static int mx5_suspend_enter(suspend_state_t state) | |||
| 114 | flush_cache_all(); | 159 | flush_cache_all(); |
| 115 | 160 | ||
| 116 | /*clear the EMPGC0/1 bits */ | 161 | /*clear the EMPGC0/1 bits */ |
| 117 | __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); | 162 | __raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); |
| 118 | __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); | 163 | __raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); |
| 119 | } | 164 | } |
| 120 | cpu_do_idle(); | 165 | cpu_do_idle(); |
| 121 | 166 | ||
| @@ -149,7 +194,7 @@ static void imx5_pm_idle(void) | |||
| 149 | imx5_cpu_do_idle(); | 194 | imx5_cpu_do_idle(); |
| 150 | } | 195 | } |
| 151 | 196 | ||
| 152 | static int __init imx5_pm_common_init(void) | 197 | static int __init imx5_pm_common_init(const struct imx5_pm_data *data) |
| 153 | { | 198 | { |
| 154 | int ret; | 199 | int ret; |
| 155 | struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); | 200 | struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); |
| @@ -163,15 +208,28 @@ static int __init imx5_pm_common_init(void) | |||
| 163 | 208 | ||
| 164 | arm_pm_idle = imx5_pm_idle; | 209 | arm_pm_idle = imx5_pm_idle; |
| 165 | 210 | ||
| 211 | cortex_base = ioremap(data->cortex_addr, SZ_16K); | ||
| 212 | gpc_base = ioremap(data->gpc_addr, SZ_16K); | ||
| 213 | WARN_ON(!ccm_base || !cortex_base || !gpc_base); | ||
| 214 | |||
| 166 | /* Set the registers to the default cpu idle state. */ | 215 | /* Set the registers to the default cpu idle state. */ |
| 167 | mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE); | 216 | mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE); |
| 168 | 217 | ||
| 169 | return imx5_cpuidle_init(); | 218 | ret = imx5_cpuidle_init(); |
| 219 | if (ret) | ||
| 220 | pr_warn("%s: cpuidle init failed %d\n", __func__, ret); | ||
| 221 | |||
| 222 | suspend_set_ops(&mx5_suspend_ops); | ||
| 223 | |||
| 224 | return 0; | ||
| 225 | } | ||
| 226 | |||
| 227 | void __init imx51_pm_init(void) | ||
| 228 | { | ||
| 229 | imx5_pm_common_init(&imx51_pm_data); | ||
| 170 | } | 230 | } |
| 171 | 231 | ||
| 172 | void __init imx5_pm_init(void) | 232 | void __init imx53_pm_init(void) |
| 173 | { | 233 | { |
| 174 | int ret = imx5_pm_common_init(); | 234 | imx5_pm_common_init(&imx53_pm_data); |
| 175 | if (!ret) | ||
| 176 | suspend_set_ops(&mx5_suspend_ops); | ||
| 177 | } | 235 | } |
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 9392a8f4ef24..5c3af8f993d0 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c | |||
| @@ -129,6 +129,14 @@ static const u32 imx6sl_mmdc_io_offset[] __initconst = { | |||
| 129 | 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ | 129 | 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ |
| 130 | }; | 130 | }; |
| 131 | 131 | ||
| 132 | static const u32 imx6sx_mmdc_io_offset[] __initconst = { | ||
| 133 | 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ | ||
| 134 | 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ | ||
| 135 | 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */ | ||
| 136 | 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */ | ||
| 137 | 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ | ||
| 138 | }; | ||
| 139 | |||
| 132 | static const struct imx6_pm_socdata imx6q_pm_data __initconst = { | 140 | static const struct imx6_pm_socdata imx6q_pm_data __initconst = { |
| 133 | .cpu_type = MXC_CPU_IMX6Q, | 141 | .cpu_type = MXC_CPU_IMX6Q, |
| 134 | .mmdc_compat = "fsl,imx6q-mmdc", | 142 | .mmdc_compat = "fsl,imx6q-mmdc", |
| @@ -159,6 +167,16 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { | |||
| 159 | .mmdc_io_offset = imx6sl_mmdc_io_offset, | 167 | .mmdc_io_offset = imx6sl_mmdc_io_offset, |
| 160 | }; | 168 | }; |
| 161 | 169 | ||
| 170 | static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { | ||
| 171 | .cpu_type = MXC_CPU_IMX6SX, | ||
| 172 | .mmdc_compat = "fsl,imx6sx-mmdc", | ||
| 173 | .src_compat = "fsl,imx6sx-src", | ||
| 174 | .iomuxc_compat = "fsl,imx6sx-iomuxc", | ||
| 175 | .gpc_compat = "fsl,imx6sx-gpc", | ||
| 176 | .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset), | ||
| 177 | .mmdc_io_offset = imx6sx_mmdc_io_offset, | ||
| 178 | }; | ||
| 179 | |||
| 162 | /* | 180 | /* |
| 163 | * This structure is for passing necessary data for low level ocram | 181 | * This structure is for passing necessary data for low level ocram |
| 164 | * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct | 182 | * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct |
| @@ -181,11 +199,13 @@ struct imx6_cpu_pm_info { | |||
| 181 | u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ | 199 | u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ |
| 182 | } __aligned(8); | 200 | } __aligned(8); |
| 183 | 201 | ||
| 184 | void imx6q_set_int_mem_clk_lpm(void) | 202 | void imx6q_set_int_mem_clk_lpm(bool enable) |
| 185 | { | 203 | { |
| 186 | u32 val = readl_relaxed(ccm_base + CGPR); | 204 | u32 val = readl_relaxed(ccm_base + CGPR); |
| 187 | 205 | ||
| 188 | val |= BM_CGPR_INT_MEM_CLK_LPM; | 206 | val &= ~BM_CGPR_INT_MEM_CLK_LPM; |
| 207 | if (enable) | ||
| 208 | val |= BM_CGPR_INT_MEM_CLK_LPM; | ||
| 189 | writel_relaxed(val, ccm_base + CGPR); | 209 | writel_relaxed(val, ccm_base + CGPR); |
| 190 | } | 210 | } |
| 191 | 211 | ||
| @@ -254,6 +274,14 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) | |||
| 254 | break; | 274 | break; |
| 255 | case STOP_POWER_ON: | 275 | case STOP_POWER_ON: |
| 256 | val |= 0x2 << BP_CLPCR_LPM; | 276 | val |= 0x2 << BP_CLPCR_LPM; |
| 277 | val &= ~BM_CLPCR_VSTBY; | ||
| 278 | val &= ~BM_CLPCR_SBYOS; | ||
| 279 | if (cpu_is_imx6sl()) | ||
| 280 | val |= BM_CLPCR_BYPASS_PMIC_READY; | ||
| 281 | if (cpu_is_imx6sl() || cpu_is_imx6sx()) | ||
| 282 | val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; | ||
| 283 | else | ||
| 284 | val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; | ||
| 257 | break; | 285 | break; |
| 258 | case WAIT_UNCLOCKED_POWER_OFF: | 286 | case WAIT_UNCLOCKED_POWER_OFF: |
| 259 | val |= 0x1 << BP_CLPCR_LPM; | 287 | val |= 0x1 << BP_CLPCR_LPM; |
| @@ -265,12 +293,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) | |||
| 265 | val |= 0x3 << BP_CLPCR_STBY_COUNT; | 293 | val |= 0x3 << BP_CLPCR_STBY_COUNT; |
| 266 | val |= BM_CLPCR_VSTBY; | 294 | val |= BM_CLPCR_VSTBY; |
| 267 | val |= BM_CLPCR_SBYOS; | 295 | val |= BM_CLPCR_SBYOS; |
| 268 | if (cpu_is_imx6sl()) { | 296 | if (cpu_is_imx6sl()) |
| 269 | val |= BM_CLPCR_BYPASS_PMIC_READY; | 297 | val |= BM_CLPCR_BYPASS_PMIC_READY; |
| 298 | if (cpu_is_imx6sl() || cpu_is_imx6sx()) | ||
| 270 | val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; | 299 | val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; |
| 271 | } else { | 300 | else |
| 272 | val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; | 301 | val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; |
| 273 | } | ||
| 274 | break; | 302 | break; |
| 275 | default: | 303 | default: |
| 276 | return -EINVAL; | 304 | return -EINVAL; |
| @@ -314,8 +342,22 @@ static int imx6q_suspend_finish(unsigned long val) | |||
| 314 | static int imx6q_pm_enter(suspend_state_t state) | 342 | static int imx6q_pm_enter(suspend_state_t state) |
| 315 | { | 343 | { |
| 316 | switch (state) { | 344 | switch (state) { |
| 345 | case PM_SUSPEND_STANDBY: | ||
| 346 | imx6q_set_lpm(STOP_POWER_ON); | ||
| 347 | imx6q_set_int_mem_clk_lpm(true); | ||
| 348 | imx_gpc_pre_suspend(false); | ||
| 349 | if (cpu_is_imx6sl()) | ||
| 350 | imx6sl_set_wait_clk(true); | ||
| 351 | /* Zzz ... */ | ||
| 352 | cpu_do_idle(); | ||
| 353 | if (cpu_is_imx6sl()) | ||
| 354 | imx6sl_set_wait_clk(false); | ||
| 355 | imx_gpc_post_resume(); | ||
| 356 | imx6q_set_lpm(WAIT_CLOCKED); | ||
| 357 | break; | ||
| 317 | case PM_SUSPEND_MEM: | 358 | case PM_SUSPEND_MEM: |
| 318 | imx6q_set_lpm(STOP_POWER_OFF); | 359 | imx6q_set_lpm(STOP_POWER_OFF); |
| 360 | imx6q_set_int_mem_clk_lpm(false); | ||
| 319 | imx6q_enable_wb(true); | 361 | imx6q_enable_wb(true); |
| 320 | /* | 362 | /* |
| 321 | * For suspend into ocram, asm code already take care of | 363 | * For suspend into ocram, asm code already take care of |
| @@ -323,7 +365,7 @@ static int imx6q_pm_enter(suspend_state_t state) | |||
| 323 | */ | 365 | */ |
| 324 | if (!imx6_suspend_in_ocram_fn) | 366 | if (!imx6_suspend_in_ocram_fn) |
| 325 | imx6q_enable_rbc(true); | 367 | imx6q_enable_rbc(true); |
| 326 | imx_gpc_pre_suspend(); | 368 | imx_gpc_pre_suspend(true); |
| 327 | imx_anatop_pre_suspend(); | 369 | imx_anatop_pre_suspend(); |
| 328 | imx_set_cpu_jump(0, v7_cpu_resume); | 370 | imx_set_cpu_jump(0, v7_cpu_resume); |
| 329 | /* Zzz ... */ | 371 | /* Zzz ... */ |
| @@ -334,6 +376,7 @@ static int imx6q_pm_enter(suspend_state_t state) | |||
| 334 | imx_gpc_post_resume(); | 376 | imx_gpc_post_resume(); |
| 335 | imx6q_enable_rbc(false); | 377 | imx6q_enable_rbc(false); |
| 336 | imx6q_enable_wb(false); | 378 | imx6q_enable_wb(false); |
| 379 | imx6q_set_int_mem_clk_lpm(true); | ||
| 337 | imx6q_set_lpm(WAIT_CLOCKED); | 380 | imx6q_set_lpm(WAIT_CLOCKED); |
| 338 | break; | 381 | break; |
| 339 | default: | 382 | default: |
| @@ -343,9 +386,14 @@ static int imx6q_pm_enter(suspend_state_t state) | |||
| 343 | return 0; | 386 | return 0; |
| 344 | } | 387 | } |
| 345 | 388 | ||
| 389 | static int imx6q_pm_valid(suspend_state_t state) | ||
| 390 | { | ||
| 391 | return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM); | ||
| 392 | } | ||
| 393 | |||
| 346 | static const struct platform_suspend_ops imx6q_pm_ops = { | 394 | static const struct platform_suspend_ops imx6q_pm_ops = { |
| 347 | .enter = imx6q_pm_enter, | 395 | .enter = imx6q_pm_enter, |
| 348 | .valid = suspend_valid_only_mem, | 396 | .valid = imx6q_pm_valid, |
| 349 | }; | 397 | }; |
| 350 | 398 | ||
| 351 | void __init imx6q_pm_set_ccm_base(void __iomem *base) | 399 | void __init imx6q_pm_set_ccm_base(void __iomem *base) |
| @@ -549,3 +597,8 @@ void __init imx6sl_pm_init(void) | |||
| 549 | { | 597 | { |
| 550 | imx6_pm_common_init(&imx6sl_pm_data); | 598 | imx6_pm_common_init(&imx6sl_pm_data); |
| 551 | } | 599 | } |
| 600 | |||
| 601 | void __init imx6sx_pm_init(void) | ||
| 602 | { | ||
| 603 | imx6_pm_common_init(&imx6sx_pm_data); | ||
| 604 | } | ||
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 3b0733edb68c..d14c33fd6b03 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c | |||
| @@ -42,7 +42,10 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) | |||
| 42 | { | 42 | { |
| 43 | unsigned int wcr_enable; | 43 | unsigned int wcr_enable; |
| 44 | 44 | ||
| 45 | if (wdog_clk) | 45 | if (!wdog_base) |
| 46 | goto reset_fallback; | ||
| 47 | |||
| 48 | if (!IS_ERR(wdog_clk)) | ||
| 46 | clk_enable(wdog_clk); | 49 | clk_enable(wdog_clk); |
| 47 | 50 | ||
| 48 | if (cpu_is_mx1()) | 51 | if (cpu_is_mx1()) |
| @@ -70,6 +73,7 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) | |||
| 70 | /* delay to allow the serial port to show the message */ | 73 | /* delay to allow the serial port to show the message */ |
| 71 | mdelay(50); | 74 | mdelay(50); |
| 72 | 75 | ||
| 76 | reset_fallback: | ||
| 73 | /* we'll take a jump through zero as a poor second */ | 77 | /* we'll take a jump through zero as a poor second */ |
| 74 | soft_restart(0); | 78 | soft_restart(0); |
| 75 | } | 79 | } |
| @@ -79,13 +83,10 @@ void __init mxc_arch_reset_init(void __iomem *base) | |||
| 79 | wdog_base = base; | 83 | wdog_base = base; |
| 80 | 84 | ||
| 81 | wdog_clk = clk_get_sys("imx2-wdt.0", NULL); | 85 | wdog_clk = clk_get_sys("imx2-wdt.0", NULL); |
| 82 | if (IS_ERR(wdog_clk)) { | 86 | if (IS_ERR(wdog_clk)) |
| 83 | pr_warn("%s: failed to get wdog clock\n", __func__); | 87 | pr_warn("%s: failed to get wdog clock\n", __func__); |
| 84 | wdog_clk = NULL; | 88 | else |
| 85 | return; | 89 | clk_prepare(wdog_clk); |
| 86 | } | ||
| 87 | |||
| 88 | clk_prepare(wdog_clk); | ||
| 89 | } | 90 | } |
| 90 | 91 | ||
| 91 | void __init mxc_arch_reset_init_dt(void) | 92 | void __init mxc_arch_reset_init_dt(void) |
| @@ -97,13 +98,10 @@ void __init mxc_arch_reset_init_dt(void) | |||
| 97 | WARN_ON(!wdog_base); | 98 | WARN_ON(!wdog_base); |
| 98 | 99 | ||
| 99 | wdog_clk = of_clk_get(np, 0); | 100 | wdog_clk = of_clk_get(np, 0); |
| 100 | if (IS_ERR(wdog_clk)) { | 101 | if (IS_ERR(wdog_clk)) |
| 101 | pr_warn("%s: failed to get wdog clock\n", __func__); | 102 | pr_warn("%s: failed to get wdog clock\n", __func__); |
| 102 | wdog_clk = NULL; | 103 | else |
| 103 | return; | 104 | clk_prepare(wdog_clk); |
| 104 | } | ||
| 105 | |||
| 106 | clk_prepare(wdog_clk); | ||
| 107 | } | 105 | } |
| 108 | 106 | ||
| 109 | #ifdef CONFIG_CACHE_L2X0 | 107 | #ifdef CONFIG_CACHE_L2X0 |
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index bed081e58262..bf92e5a351c0 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c | |||
| @@ -290,25 +290,20 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) | |||
| 290 | return 0; | 290 | return 0; |
| 291 | } | 291 | } |
| 292 | 292 | ||
| 293 | void __init mxc_timer_init(void __iomem *base, int irq) | 293 | static void __init _mxc_timer_init(int irq, |
| 294 | struct clk *clk_per, struct clk *clk_ipg) | ||
| 294 | { | 295 | { |
| 295 | uint32_t tctl_val; | 296 | uint32_t tctl_val; |
| 296 | struct clk *timer_clk; | ||
| 297 | struct clk *timer_ipg_clk; | ||
| 298 | 297 | ||
| 299 | timer_clk = clk_get_sys("imx-gpt.0", "per"); | 298 | if (IS_ERR(clk_per)) { |
| 300 | if (IS_ERR(timer_clk)) { | ||
| 301 | pr_err("i.MX timer: unable to get clk\n"); | 299 | pr_err("i.MX timer: unable to get clk\n"); |
| 302 | return; | 300 | return; |
| 303 | } | 301 | } |
| 304 | 302 | ||
| 305 | timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg"); | 303 | if (!IS_ERR(clk_ipg)) |
| 306 | if (!IS_ERR(timer_ipg_clk)) | 304 | clk_prepare_enable(clk_ipg); |
| 307 | clk_prepare_enable(timer_ipg_clk); | ||
| 308 | |||
| 309 | clk_prepare_enable(timer_clk); | ||
| 310 | 305 | ||
| 311 | timer_base = base; | 306 | clk_prepare_enable(clk_per); |
| 312 | 307 | ||
| 313 | /* | 308 | /* |
| 314 | * Initialise to a known state (all timers off, and timing reset) | 309 | * Initialise to a known state (all timers off, and timing reset) |
| @@ -325,21 +320,45 @@ void __init mxc_timer_init(void __iomem *base, int irq) | |||
| 325 | __raw_writel(tctl_val, timer_base + MXC_TCTL); | 320 | __raw_writel(tctl_val, timer_base + MXC_TCTL); |
| 326 | 321 | ||
| 327 | /* init and register the timer to the framework */ | 322 | /* init and register the timer to the framework */ |
| 328 | mxc_clocksource_init(timer_clk); | 323 | mxc_clocksource_init(clk_per); |
| 329 | mxc_clockevent_init(timer_clk); | 324 | mxc_clockevent_init(clk_per); |
| 330 | 325 | ||
| 331 | /* Make irqs happen */ | 326 | /* Make irqs happen */ |
| 332 | setup_irq(irq, &mxc_timer_irq); | 327 | setup_irq(irq, &mxc_timer_irq); |
| 333 | } | 328 | } |
| 334 | 329 | ||
| 335 | void __init mxc_timer_init_dt(struct device_node *np) | 330 | void __init mxc_timer_init(void __iomem *base, int irq) |
| 336 | { | 331 | { |
| 337 | void __iomem *base; | 332 | struct clk *clk_per = clk_get_sys("imx-gpt.0", "per"); |
| 333 | struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); | ||
| 334 | |||
| 335 | timer_base = base; | ||
| 336 | |||
| 337 | _mxc_timer_init(irq, clk_per, clk_ipg); | ||
| 338 | } | ||
| 339 | |||
| 340 | static void __init mxc_timer_init_dt(struct device_node *np) | ||
| 341 | { | ||
| 342 | struct clk *clk_per, *clk_ipg; | ||
| 338 | int irq; | 343 | int irq; |
| 339 | 344 | ||
| 340 | base = of_iomap(np, 0); | 345 | if (timer_base) |
| 341 | WARN_ON(!base); | 346 | return; |
| 347 | |||
| 348 | timer_base = of_iomap(np, 0); | ||
| 349 | WARN_ON(!timer_base); | ||
| 342 | irq = irq_of_parse_and_map(np, 0); | 350 | irq = irq_of_parse_and_map(np, 0); |
| 343 | 351 | ||
| 344 | mxc_timer_init(base, irq); | 352 | clk_per = of_clk_get_by_name(np, "per"); |
| 353 | clk_ipg = of_clk_get_by_name(np, "ipg"); | ||
| 354 | |||
| 355 | _mxc_timer_init(irq, clk_per, clk_ipg); | ||
| 345 | } | 356 | } |
| 357 | CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt); | ||
| 358 | CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt); | ||
| 359 | CLOCKSOURCE_OF_DECLARE(mx50_timer, "fsl,imx50-gpt", mxc_timer_init_dt); | ||
| 360 | CLOCKSOURCE_OF_DECLARE(mx51_timer, "fsl,imx51-gpt", mxc_timer_init_dt); | ||
| 361 | CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt); | ||
| 362 | CLOCKSOURCE_OF_DECLARE(mx6q_timer, "fsl,imx6q-gpt", mxc_timer_init_dt); | ||
| 363 | CLOCKSOURCE_OF_DECLARE(mx6sl_timer, "fsl,imx6sl-gpt", mxc_timer_init_dt); | ||
| 364 | CLOCKSOURCE_OF_DECLARE(mx6sx_timer, "fsl,imx6sx-gpt", mxc_timer_init_dt); | ||
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c index 7828af4b2022..1d4f384ca773 100644 --- a/arch/arm/mach-imx/tzic.c +++ b/arch/arm/mach-imx/tzic.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/irqdomain.h> | 18 | #include <linux/irqdomain.h> |
| 19 | #include <linux/of.h> | 19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> | ||
| 20 | 21 | ||
| 21 | #include <asm/mach/irq.h> | 22 | #include <asm/mach/irq.h> |
| 22 | #include <asm/exception.h> | 23 | #include <asm/exception.h> |
| @@ -153,13 +154,16 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) | |||
| 153 | * interrupts. It registers the interrupt enable and disable functions | 154 | * interrupts. It registers the interrupt enable and disable functions |
| 154 | * to the kernel for each interrupt source. | 155 | * to the kernel for each interrupt source. |
| 155 | */ | 156 | */ |
| 156 | void __init tzic_init_irq(void __iomem *irqbase) | 157 | void __init tzic_init_irq(void) |
| 157 | { | 158 | { |
| 158 | struct device_node *np; | 159 | struct device_node *np; |
| 159 | int irq_base; | 160 | int irq_base; |
| 160 | int i; | 161 | int i; |
| 161 | 162 | ||
| 162 | tzic_base = irqbase; | 163 | np = of_find_compatible_node(NULL, NULL, "fsl,tzic"); |
| 164 | tzic_base = of_iomap(np, 0); | ||
| 165 | WARN_ON(!tzic_base); | ||
| 166 | |||
| 163 | /* put the TZIC into the reset value with | 167 | /* put the TZIC into the reset value with |
| 164 | * all interrupts disabled | 168 | * all interrupts disabled |
| 165 | */ | 169 | */ |
| @@ -181,7 +185,6 @@ void __init tzic_init_irq(void __iomem *irqbase) | |||
| 181 | irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id()); | 185 | irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id()); |
| 182 | WARN_ON(irq_base < 0); | 186 | WARN_ON(irq_base < 0); |
| 183 | 187 | ||
| 184 | np = of_find_compatible_node(NULL, NULL, "fsl,tzic"); | ||
| 185 | domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0, | 188 | domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0, |
| 186 | &irq_domain_simple_ops, NULL); | 189 | &irq_domain_simple_ops, NULL); |
| 187 | WARN_ON(!domain); | 190 | WARN_ON(!domain); |
diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index f8ee13c7bf7b..75c9681f8021 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c | |||
| @@ -162,7 +162,9 @@ static int __init weim_parse_dt(struct platform_device *pdev, | |||
| 162 | } | 162 | } |
| 163 | } | 163 | } |
| 164 | 164 | ||
| 165 | ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); | 165 | ret = of_platform_populate(pdev->dev.of_node, |
| 166 | of_default_bus_match_table, | ||
| 167 | NULL, &pdev->dev); | ||
| 166 | if (ret) | 168 | if (ret) |
| 167 | dev_err(&pdev->dev, "%s fail to create devices.\n", | 169 | dev_err(&pdev->dev, "%s fail to create devices.\n", |
| 168 | pdev->dev.of_node->full_name); | 170 | pdev->dev.of_node->full_name); |
diff --git a/include/dt-bindings/clock/imx1-clock.h b/include/dt-bindings/clock/imx1-clock.h new file mode 100644 index 000000000000..607bf01a31dd --- /dev/null +++ b/include/dt-bindings/clock/imx1-clock.h | |||
| @@ -0,0 +1,40 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DT_BINDINGS_CLOCK_IMX1_H | ||
| 11 | #define __DT_BINDINGS_CLOCK_IMX1_H | ||
| 12 | |||
| 13 | #define IMX1_CLK_DUMMY 0 | ||
| 14 | #define IMX1_CLK_CLK32 1 | ||
| 15 | #define IMX1_CLK_CLK16M_EXT 2 | ||
| 16 | #define IMX1_CLK_CLK16M 3 | ||
| 17 | #define IMX1_CLK_CLK32_PREMULT 4 | ||
| 18 | #define IMX1_CLK_PREM 5 | ||
| 19 | #define IMX1_CLK_MPLL 6 | ||
| 20 | #define IMX1_CLK_MPLL_GATE 7 | ||
| 21 | #define IMX1_CLK_SPLL 8 | ||
| 22 | #define IMX1_CLK_SPLL_GATE 9 | ||
| 23 | #define IMX1_CLK_MCU 10 | ||
| 24 | #define IMX1_CLK_FCLK 11 | ||
| 25 | #define IMX1_CLK_HCLK 12 | ||
| 26 | #define IMX1_CLK_CLK48M 13 | ||
| 27 | #define IMX1_CLK_PER1 14 | ||
| 28 | #define IMX1_CLK_PER2 15 | ||
| 29 | #define IMX1_CLK_PER3 16 | ||
| 30 | #define IMX1_CLK_CLKO 17 | ||
| 31 | #define IMX1_CLK_UART3_GATE 18 | ||
| 32 | #define IMX1_CLK_SSI2_GATE 19 | ||
| 33 | #define IMX1_CLK_BROM_GATE 20 | ||
| 34 | #define IMX1_CLK_DMA_GATE 21 | ||
| 35 | #define IMX1_CLK_CSI_GATE 22 | ||
| 36 | #define IMX1_CLK_MMA_GATE 23 | ||
| 37 | #define IMX1_CLK_USBD_GATE 24 | ||
| 38 | #define IMX1_CLK_MAX 25 | ||
| 39 | |||
| 40 | #endif | ||
diff --git a/include/dt-bindings/clock/imx21-clock.h b/include/dt-bindings/clock/imx21-clock.h new file mode 100644 index 000000000000..b13596cf51b2 --- /dev/null +++ b/include/dt-bindings/clock/imx21-clock.h | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DT_BINDINGS_CLOCK_IMX21_H | ||
| 11 | #define __DT_BINDINGS_CLOCK_IMX21_H | ||
| 12 | |||
| 13 | #define IMX21_CLK_DUMMY 0 | ||
| 14 | #define IMX21_CLK_CKIL 1 | ||
| 15 | #define IMX21_CLK_CKIH 2 | ||
| 16 | #define IMX21_CLK_FPM 3 | ||
| 17 | #define IMX21_CLK_CKIH_DIV1P5 4 | ||
| 18 | #define IMX21_CLK_MPLL_GATE 5 | ||
| 19 | #define IMX21_CLK_SPLL_GATE 6 | ||
| 20 | #define IMX21_CLK_FPM_GATE 7 | ||
| 21 | #define IMX21_CLK_CKIH_GATE 8 | ||
| 22 | #define IMX21_CLK_MPLL_OSC_SEL 9 | ||
| 23 | #define IMX21_CLK_IPG 10 | ||
| 24 | #define IMX21_CLK_HCLK 11 | ||
| 25 | #define IMX21_CLK_MPLL_SEL 12 | ||
| 26 | #define IMX21_CLK_SPLL_SEL 13 | ||
| 27 | #define IMX21_CLK_SSI1_SEL 14 | ||
| 28 | #define IMX21_CLK_SSI2_SEL 15 | ||
| 29 | #define IMX21_CLK_USB_DIV 16 | ||
| 30 | #define IMX21_CLK_FCLK 17 | ||
| 31 | #define IMX21_CLK_MPLL 18 | ||
| 32 | #define IMX21_CLK_SPLL 19 | ||
| 33 | #define IMX21_CLK_NFC_DIV 20 | ||
| 34 | #define IMX21_CLK_SSI1_DIV 21 | ||
| 35 | #define IMX21_CLK_SSI2_DIV 22 | ||
| 36 | #define IMX21_CLK_PER1 23 | ||
| 37 | #define IMX21_CLK_PER2 24 | ||
| 38 | #define IMX21_CLK_PER3 25 | ||
| 39 | #define IMX21_CLK_PER4 26 | ||
| 40 | #define IMX21_CLK_UART1_IPG_GATE 27 | ||
| 41 | #define IMX21_CLK_UART2_IPG_GATE 28 | ||
| 42 | #define IMX21_CLK_UART3_IPG_GATE 29 | ||
| 43 | #define IMX21_CLK_UART4_IPG_GATE 30 | ||
| 44 | #define IMX21_CLK_CSPI1_IPG_GATE 31 | ||
| 45 | #define IMX21_CLK_CSPI2_IPG_GATE 32 | ||
| 46 | #define IMX21_CLK_SSI1_GATE 33 | ||
| 47 | #define IMX21_CLK_SSI2_GATE 34 | ||
| 48 | #define IMX21_CLK_SDHC1_IPG_GATE 35 | ||
| 49 | #define IMX21_CLK_SDHC2_IPG_GATE 36 | ||
| 50 | #define IMX21_CLK_GPIO_GATE 37 | ||
| 51 | #define IMX21_CLK_I2C_GATE 38 | ||
| 52 | #define IMX21_CLK_DMA_GATE 39 | ||
| 53 | #define IMX21_CLK_USB_GATE 40 | ||
| 54 | #define IMX21_CLK_EMMA_GATE 41 | ||
| 55 | #define IMX21_CLK_SSI2_BAUD_GATE 42 | ||
| 56 | #define IMX21_CLK_SSI1_BAUD_GATE 43 | ||
| 57 | #define IMX21_CLK_LCDC_IPG_GATE 44 | ||
| 58 | #define IMX21_CLK_NFC_GATE 45 | ||
| 59 | #define IMX21_CLK_LCDC_HCLK_GATE 46 | ||
| 60 | #define IMX21_CLK_PER4_GATE 47 | ||
| 61 | #define IMX21_CLK_BMI_GATE 48 | ||
| 62 | #define IMX21_CLK_USB_HCLK_GATE 49 | ||
| 63 | #define IMX21_CLK_SLCDC_GATE 50 | ||
| 64 | #define IMX21_CLK_SLCDC_HCLK_GATE 51 | ||
| 65 | #define IMX21_CLK_EMMA_HCLK_GATE 52 | ||
| 66 | #define IMX21_CLK_BROM_GATE 53 | ||
| 67 | #define IMX21_CLK_DMA_HCLK_GATE 54 | ||
| 68 | #define IMX21_CLK_CSI_HCLK_GATE 55 | ||
| 69 | #define IMX21_CLK_CSPI3_IPG_GATE 56 | ||
| 70 | #define IMX21_CLK_WDOG_GATE 57 | ||
| 71 | #define IMX21_CLK_GPT1_IPG_GATE 58 | ||
| 72 | #define IMX21_CLK_GPT2_IPG_GATE 59 | ||
| 73 | #define IMX21_CLK_GPT3_IPG_GATE 60 | ||
| 74 | #define IMX21_CLK_PWM_IPG_GATE 61 | ||
| 75 | #define IMX21_CLK_RTC_GATE 62 | ||
| 76 | #define IMX21_CLK_KPP_GATE 63 | ||
| 77 | #define IMX21_CLK_OWIRE_GATE 64 | ||
| 78 | #define IMX21_CLK_MAX 65 | ||
| 79 | |||
| 80 | #endif | ||
diff --git a/include/dt-bindings/clock/imx27-clock.h b/include/dt-bindings/clock/imx27-clock.h new file mode 100644 index 000000000000..148b053e54ec --- /dev/null +++ b/include/dt-bindings/clock/imx27-clock.h | |||
| @@ -0,0 +1,108 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DT_BINDINGS_CLOCK_IMX27_H | ||
| 11 | #define __DT_BINDINGS_CLOCK_IMX27_H | ||
| 12 | |||
| 13 | #define IMX27_CLK_DUMMY 0 | ||
| 14 | #define IMX27_CLK_CKIH 1 | ||
| 15 | #define IMX27_CLK_CKIL 2 | ||
| 16 | #define IMX27_CLK_MPLL 3 | ||
| 17 | #define IMX27_CLK_SPLL 4 | ||
| 18 | #define IMX27_CLK_MPLL_MAIN2 5 | ||
| 19 | #define IMX27_CLK_AHB 6 | ||
| 20 | #define IMX27_CLK_IPG 7 | ||
| 21 | #define IMX27_CLK_NFC_DIV 8 | ||
| 22 | #define IMX27_CLK_PER1_DIV 9 | ||
| 23 | #define IMX27_CLK_PER2_DIV 10 | ||
| 24 | #define IMX27_CLK_PER3_DIV 11 | ||
| 25 | #define IMX27_CLK_PER4_DIV 12 | ||
| 26 | #define IMX27_CLK_VPU_SEL 13 | ||
| 27 | #define IMX27_CLK_VPU_DIV 14 | ||
| 28 | #define IMX27_CLK_USB_DIV 15 | ||
| 29 | #define IMX27_CLK_CPU_SEL 16 | ||
| 30 | #define IMX27_CLK_CLKO_SEL 17 | ||
| 31 | #define IMX27_CLK_CPU_DIV 18 | ||
| 32 | #define IMX27_CLK_CLKO_DIV 19 | ||
| 33 | #define IMX27_CLK_SSI1_SEL 20 | ||
| 34 | #define IMX27_CLK_SSI2_SEL 21 | ||
| 35 | #define IMX27_CLK_SSI1_DIV 22 | ||
| 36 | #define IMX27_CLK_SSI2_DIV 23 | ||
| 37 | #define IMX27_CLK_CLKO_EN 24 | ||
| 38 | #define IMX27_CLK_SSI2_IPG_GATE 25 | ||
| 39 | #define IMX27_CLK_SSI1_IPG_GATE 26 | ||
| 40 | #define IMX27_CLK_SLCDC_IPG_GATE 27 | ||
| 41 | #define IMX27_CLK_SDHC3_IPG_GATE 28 | ||
| 42 | #define IMX27_CLK_SDHC2_IPG_GATE 29 | ||
| 43 | #define IMX27_CLK_SDHC1_IPG_GATE 30 | ||
| 44 | #define IMX27_CLK_SCC_IPG_GATE 31 | ||
| 45 | #define IMX27_CLK_SAHARA_IPG_GATE 32 | ||
| 46 | #define IMX27_CLK_RTC_IPG_GATE 33 | ||
| 47 | #define IMX27_CLK_PWM_IPG_GATE 34 | ||
| 48 | #define IMX27_CLK_OWIRE_IPG_GATE 35 | ||
| 49 | #define IMX27_CLK_LCDC_IPG_GATE 36 | ||
| 50 | #define IMX27_CLK_KPP_IPG_GATE 37 | ||
| 51 | #define IMX27_CLK_IIM_IPG_GATE 38 | ||
| 52 | #define IMX27_CLK_I2C2_IPG_GATE 39 | ||
| 53 | #define IMX27_CLK_I2C1_IPG_GATE 40 | ||
| 54 | #define IMX27_CLK_GPT6_IPG_GATE 41 | ||
| 55 | #define IMX27_CLK_GPT5_IPG_GATE 42 | ||
| 56 | #define IMX27_CLK_GPT4_IPG_GATE 43 | ||
| 57 | #define IMX27_CLK_GPT3_IPG_GATE 44 | ||
| 58 | #define IMX27_CLK_GPT2_IPG_GATE 45 | ||
| 59 | #define IMX27_CLK_GPT1_IPG_GATE 46 | ||
| 60 | #define IMX27_CLK_GPIO_IPG_GATE 47 | ||
| 61 | #define IMX27_CLK_FEC_IPG_GATE 48 | ||
| 62 | #define IMX27_CLK_EMMA_IPG_GATE 49 | ||
| 63 | #define IMX27_CLK_DMA_IPG_GATE 50 | ||
| 64 | #define IMX27_CLK_CSPI3_IPG_GATE 51 | ||
| 65 | #define IMX27_CLK_CSPI2_IPG_GATE 52 | ||
| 66 | #define IMX27_CLK_CSPI1_IPG_GATE 53 | ||
| 67 | #define IMX27_CLK_NFC_BAUD_GATE 54 | ||
| 68 | #define IMX27_CLK_SSI2_BAUD_GATE 55 | ||
| 69 | #define IMX27_CLK_SSI1_BAUD_GATE 56 | ||
| 70 | #define IMX27_CLK_VPU_BAUD_GATE 57 | ||
| 71 | #define IMX27_CLK_PER4_GATE 58 | ||
| 72 | #define IMX27_CLK_PER3_GATE 59 | ||
| 73 | #define IMX27_CLK_PER2_GATE 60 | ||
| 74 | #define IMX27_CLK_PER1_GATE 61 | ||
| 75 | #define IMX27_CLK_USB_AHB_GATE 62 | ||
| 76 | #define IMX27_CLK_SLCDC_AHB_GATE 63 | ||
| 77 | #define IMX27_CLK_SAHARA_AHB_GATE 64 | ||
| 78 | #define IMX27_CLK_LCDC_AHB_GATE 65 | ||
| 79 | #define IMX27_CLK_VPU_AHB_GATE 66 | ||
| 80 | #define IMX27_CLK_FEC_AHB_GATE 67 | ||
| 81 | #define IMX27_CLK_EMMA_AHB_GATE 68 | ||
| 82 | #define IMX27_CLK_EMI_AHB_GATE 69 | ||
| 83 | #define IMX27_CLK_DMA_AHB_GATE 70 | ||
| 84 | #define IMX27_CLK_CSI_AHB_GATE 71 | ||
| 85 | #define IMX27_CLK_BROM_AHB_GATE 72 | ||
| 86 | #define IMX27_CLK_ATA_AHB_GATE 73 | ||
| 87 | #define IMX27_CLK_WDOG_IPG_GATE 74 | ||
| 88 | #define IMX27_CLK_USB_IPG_GATE 75 | ||
| 89 | #define IMX27_CLK_UART6_IPG_GATE 76 | ||
| 90 | #define IMX27_CLK_UART5_IPG_GATE 77 | ||
| 91 | #define IMX27_CLK_UART4_IPG_GATE 78 | ||
| 92 | #define IMX27_CLK_UART3_IPG_GATE 79 | ||
| 93 | #define IMX27_CLK_UART2_IPG_GATE 80 | ||
| 94 | #define IMX27_CLK_UART1_IPG_GATE 81 | ||
| 95 | #define IMX27_CLK_CKIH_DIV1P5 82 | ||
| 96 | #define IMX27_CLK_FPM 83 | ||
| 97 | #define IMX27_CLK_MPLL_OSC_SEL 84 | ||
| 98 | #define IMX27_CLK_MPLL_SEL 85 | ||
| 99 | #define IMX27_CLK_SPLL_GATE 86 | ||
| 100 | #define IMX27_CLK_MSHC_DIV 87 | ||
| 101 | #define IMX27_CLK_RTIC_IPG_GATE 88 | ||
| 102 | #define IMX27_CLK_MSHC_IPG_GATE 89 | ||
| 103 | #define IMX27_CLK_RTIC_AHB_GATE 90 | ||
| 104 | #define IMX27_CLK_MSHC_BAUD_GATE 91 | ||
| 105 | #define IMX27_CLK_CKIH_GATE 92 | ||
| 106 | #define IMX27_CLK_MAX 93 | ||
| 107 | |||
| 108 | #endif | ||
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h new file mode 100644 index 000000000000..654151e24288 --- /dev/null +++ b/include/dt-bindings/clock/imx6qdl-clock.h | |||
| @@ -0,0 +1,224 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H | ||
| 10 | #define __DT_BINDINGS_CLOCK_IMX6QDL_H | ||
| 11 | |||
| 12 | #define IMX6QDL_CLK_DUMMY 0 | ||
| 13 | #define IMX6QDL_CLK_CKIL 1 | ||
| 14 | #define IMX6QDL_CLK_CKIH 2 | ||
| 15 | #define IMX6QDL_CLK_OSC 3 | ||
| 16 | #define IMX6QDL_CLK_PLL2_PFD0_352M 4 | ||
| 17 | #define IMX6QDL_CLK_PLL2_PFD1_594M 5 | ||
| 18 | #define IMX6QDL_CLK_PLL2_PFD2_396M 6 | ||
| 19 | #define IMX6QDL_CLK_PLL3_PFD0_720M 7 | ||
| 20 | #define IMX6QDL_CLK_PLL3_PFD1_540M 8 | ||
| 21 | #define IMX6QDL_CLK_PLL3_PFD2_508M 9 | ||
| 22 | #define IMX6QDL_CLK_PLL3_PFD3_454M 10 | ||
| 23 | #define IMX6QDL_CLK_PLL2_198M 11 | ||
| 24 | #define IMX6QDL_CLK_PLL3_120M 12 | ||
| 25 | #define IMX6QDL_CLK_PLL3_80M 13 | ||
| 26 | #define IMX6QDL_CLK_PLL3_60M 14 | ||
| 27 | #define IMX6QDL_CLK_TWD 15 | ||
| 28 | #define IMX6QDL_CLK_STEP 16 | ||
| 29 | #define IMX6QDL_CLK_PLL1_SW 17 | ||
| 30 | #define IMX6QDL_CLK_PERIPH_PRE 18 | ||
| 31 | #define IMX6QDL_CLK_PERIPH2_PRE 19 | ||
| 32 | #define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 | ||
| 33 | #define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 | ||
| 34 | #define IMX6QDL_CLK_AXI_SEL 22 | ||
| 35 | #define IMX6QDL_CLK_ESAI_SEL 23 | ||
| 36 | #define IMX6QDL_CLK_ASRC_SEL 24 | ||
| 37 | #define IMX6QDL_CLK_SPDIF_SEL 25 | ||
| 38 | #define IMX6QDL_CLK_GPU2D_AXI 26 | ||
| 39 | #define IMX6QDL_CLK_GPU3D_AXI 27 | ||
| 40 | #define IMX6QDL_CLK_GPU2D_CORE_SEL 28 | ||
| 41 | #define IMX6QDL_CLK_GPU3D_CORE_SEL 29 | ||
| 42 | #define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 | ||
| 43 | #define IMX6QDL_CLK_IPU1_SEL 31 | ||
| 44 | #define IMX6QDL_CLK_IPU2_SEL 32 | ||
| 45 | #define IMX6QDL_CLK_LDB_DI0_SEL 33 | ||
| 46 | #define IMX6QDL_CLK_LDB_DI1_SEL 34 | ||
| 47 | #define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 | ||
| 48 | #define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 | ||
| 49 | #define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 | ||
| 50 | #define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 | ||
| 51 | #define IMX6QDL_CLK_IPU1_DI0_SEL 39 | ||
| 52 | #define IMX6QDL_CLK_IPU1_DI1_SEL 40 | ||
| 53 | #define IMX6QDL_CLK_IPU2_DI0_SEL 41 | ||
| 54 | #define IMX6QDL_CLK_IPU2_DI1_SEL 42 | ||
| 55 | #define IMX6QDL_CLK_HSI_TX_SEL 43 | ||
| 56 | #define IMX6QDL_CLK_PCIE_AXI_SEL 44 | ||
| 57 | #define IMX6QDL_CLK_SSI1_SEL 45 | ||
| 58 | #define IMX6QDL_CLK_SSI2_SEL 46 | ||
| 59 | #define IMX6QDL_CLK_SSI3_SEL 47 | ||
| 60 | #define IMX6QDL_CLK_USDHC1_SEL 48 | ||
| 61 | #define IMX6QDL_CLK_USDHC2_SEL 49 | ||
| 62 | #define IMX6QDL_CLK_USDHC3_SEL 50 | ||
| 63 | #define IMX6QDL_CLK_USDHC4_SEL 51 | ||
| 64 | #define IMX6QDL_CLK_ENFC_SEL 52 | ||
| 65 | #define IMX6QDL_CLK_EMI_SEL 53 | ||
| 66 | #define IMX6QDL_CLK_EMI_SLOW_SEL 54 | ||
| 67 | #define IMX6QDL_CLK_VDO_AXI_SEL 55 | ||
| 68 | #define IMX6QDL_CLK_VPU_AXI_SEL 56 | ||
| 69 | #define IMX6QDL_CLK_CKO1_SEL 57 | ||
| 70 | #define IMX6QDL_CLK_PERIPH 58 | ||
| 71 | #define IMX6QDL_CLK_PERIPH2 59 | ||
| 72 | #define IMX6QDL_CLK_PERIPH_CLK2 60 | ||
| 73 | #define IMX6QDL_CLK_PERIPH2_CLK2 61 | ||
| 74 | #define IMX6QDL_CLK_IPG 62 | ||
| 75 | #define IMX6QDL_CLK_IPG_PER 63 | ||
| 76 | #define IMX6QDL_CLK_ESAI_PRED 64 | ||
| 77 | #define IMX6QDL_CLK_ESAI_PODF 65 | ||
| 78 | #define IMX6QDL_CLK_ASRC_PRED 66 | ||
| 79 | #define IMX6QDL_CLK_ASRC_PODF 67 | ||
| 80 | #define IMX6QDL_CLK_SPDIF_PRED 68 | ||
| 81 | #define IMX6QDL_CLK_SPDIF_PODF 69 | ||
| 82 | #define IMX6QDL_CLK_CAN_ROOT 70 | ||
| 83 | #define IMX6QDL_CLK_ECSPI_ROOT 71 | ||
| 84 | #define IMX6QDL_CLK_GPU2D_CORE_PODF 72 | ||
| 85 | #define IMX6QDL_CLK_GPU3D_CORE_PODF 73 | ||
| 86 | #define IMX6QDL_CLK_GPU3D_SHADER 74 | ||
| 87 | #define IMX6QDL_CLK_IPU1_PODF 75 | ||
| 88 | #define IMX6QDL_CLK_IPU2_PODF 76 | ||
| 89 | #define IMX6QDL_CLK_LDB_DI0_PODF 77 | ||
| 90 | #define IMX6QDL_CLK_LDB_DI1_PODF 78 | ||
| 91 | #define IMX6QDL_CLK_IPU1_DI0_PRE 79 | ||
| 92 | #define IMX6QDL_CLK_IPU1_DI1_PRE 80 | ||
| 93 | #define IMX6QDL_CLK_IPU2_DI0_PRE 81 | ||
| 94 | #define IMX6QDL_CLK_IPU2_DI1_PRE 82 | ||
| 95 | #define IMX6QDL_CLK_HSI_TX_PODF 83 | ||
| 96 | #define IMX6QDL_CLK_SSI1_PRED 84 | ||
| 97 | #define IMX6QDL_CLK_SSI1_PODF 85 | ||
| 98 | #define IMX6QDL_CLK_SSI2_PRED 86 | ||
| 99 | #define IMX6QDL_CLK_SSI2_PODF 87 | ||
| 100 | #define IMX6QDL_CLK_SSI3_PRED 88 | ||
| 101 | #define IMX6QDL_CLK_SSI3_PODF 89 | ||
| 102 | #define IMX6QDL_CLK_UART_SERIAL_PODF 90 | ||
| 103 | #define IMX6QDL_CLK_USDHC1_PODF 91 | ||
| 104 | #define IMX6QDL_CLK_USDHC2_PODF 92 | ||
| 105 | #define IMX6QDL_CLK_USDHC3_PODF 93 | ||
| 106 | #define IMX6QDL_CLK_USDHC4_PODF 94 | ||
| 107 | #define IMX6QDL_CLK_ENFC_PRED 95 | ||
| 108 | #define IMX6QDL_CLK_ENFC_PODF 96 | ||
| 109 | #define IMX6QDL_CLK_EMI_PODF 97 | ||
| 110 | #define IMX6QDL_CLK_EMI_SLOW_PODF 98 | ||
| 111 | #define IMX6QDL_CLK_VPU_AXI_PODF 99 | ||
| 112 | #define IMX6QDL_CLK_CKO1_PODF 100 | ||
| 113 | #define IMX6QDL_CLK_AXI 101 | ||
| 114 | #define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 | ||
| 115 | #define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 | ||
| 116 | #define IMX6QDL_CLK_ARM 104 | ||
| 117 | #define IMX6QDL_CLK_AHB 105 | ||
| 118 | #define IMX6QDL_CLK_APBH_DMA 106 | ||
| 119 | #define IMX6QDL_CLK_ASRC 107 | ||
| 120 | #define IMX6QDL_CLK_CAN1_IPG 108 | ||
| 121 | #define IMX6QDL_CLK_CAN1_SERIAL 109 | ||
| 122 | #define IMX6QDL_CLK_CAN2_IPG 110 | ||
| 123 | #define IMX6QDL_CLK_CAN2_SERIAL 111 | ||
| 124 | #define IMX6QDL_CLK_ECSPI1 112 | ||
| 125 | #define IMX6QDL_CLK_ECSPI2 113 | ||
| 126 | #define IMX6QDL_CLK_ECSPI3 114 | ||
| 127 | #define IMX6QDL_CLK_ECSPI4 115 | ||
| 128 | #define IMX6Q_CLK_ECSPI5 116 | ||
| 129 | #define IMX6DL_CLK_I2C4 116 | ||
| 130 | #define IMX6QDL_CLK_ENET 117 | ||
| 131 | #define IMX6QDL_CLK_ESAI 118 | ||
| 132 | #define IMX6QDL_CLK_GPT_IPG 119 | ||
| 133 | #define IMX6QDL_CLK_GPT_IPG_PER 120 | ||
| 134 | #define IMX6QDL_CLK_GPU2D_CORE 121 | ||
| 135 | #define IMX6QDL_CLK_GPU3D_CORE 122 | ||
| 136 | #define IMX6QDL_CLK_HDMI_IAHB 123 | ||
| 137 | #define IMX6QDL_CLK_HDMI_ISFR 124 | ||
| 138 | #define IMX6QDL_CLK_I2C1 125 | ||
| 139 | #define IMX6QDL_CLK_I2C2 126 | ||
| 140 | #define IMX6QDL_CLK_I2C3 127 | ||
| 141 | #define IMX6QDL_CLK_IIM 128 | ||
| 142 | #define IMX6QDL_CLK_ENFC 129 | ||
| 143 | #define IMX6QDL_CLK_IPU1 130 | ||
| 144 | #define IMX6QDL_CLK_IPU1_DI0 131 | ||
| 145 | #define IMX6QDL_CLK_IPU1_DI1 132 | ||
| 146 | #define IMX6QDL_CLK_IPU2 133 | ||
| 147 | #define IMX6QDL_CLK_IPU2_DI0 134 | ||
| 148 | #define IMX6QDL_CLK_LDB_DI0 135 | ||
| 149 | #define IMX6QDL_CLK_LDB_DI1 136 | ||
| 150 | #define IMX6QDL_CLK_IPU2_DI1 137 | ||
| 151 | #define IMX6QDL_CLK_HSI_TX 138 | ||
| 152 | #define IMX6QDL_CLK_MLB 139 | ||
| 153 | #define IMX6QDL_CLK_MMDC_CH0_AXI 140 | ||
| 154 | #define IMX6QDL_CLK_MMDC_CH1_AXI 141 | ||
| 155 | #define IMX6QDL_CLK_OCRAM 142 | ||
| 156 | #define IMX6QDL_CLK_OPENVG_AXI 143 | ||
| 157 | #define IMX6QDL_CLK_PCIE_AXI 144 | ||
| 158 | #define IMX6QDL_CLK_PWM1 145 | ||
| 159 | #define IMX6QDL_CLK_PWM2 146 | ||
| 160 | #define IMX6QDL_CLK_PWM3 147 | ||
| 161 | #define IMX6QDL_CLK_PWM4 148 | ||
| 162 | #define IMX6QDL_CLK_PER1_BCH 149 | ||
| 163 | #define IMX6QDL_CLK_GPMI_BCH_APB 150 | ||
| 164 | #define IMX6QDL_CLK_GPMI_BCH 151 | ||
| 165 | #define IMX6QDL_CLK_GPMI_IO 152 | ||
| 166 | #define IMX6QDL_CLK_GPMI_APB 153 | ||
| 167 | #define IMX6QDL_CLK_SATA 154 | ||
| 168 | #define IMX6QDL_CLK_SDMA 155 | ||
| 169 | #define IMX6QDL_CLK_SPBA 156 | ||
| 170 | #define IMX6QDL_CLK_SSI1 157 | ||
| 171 | #define IMX6QDL_CLK_SSI2 158 | ||
| 172 | #define IMX6QDL_CLK_SSI3 159 | ||
| 173 | #define IMX6QDL_CLK_UART_IPG 160 | ||
| 174 | #define IMX6QDL_CLK_UART_SERIAL 161 | ||
| 175 | #define IMX6QDL_CLK_USBOH3 162 | ||
| 176 | #define IMX6QDL_CLK_USDHC1 163 | ||
| 177 | #define IMX6QDL_CLK_USDHC2 164 | ||
| 178 | #define IMX6QDL_CLK_USDHC3 165 | ||
| 179 | #define IMX6QDL_CLK_USDHC4 166 | ||
| 180 | #define IMX6QDL_CLK_VDO_AXI 167 | ||
| 181 | #define IMX6QDL_CLK_VPU_AXI 168 | ||
| 182 | #define IMX6QDL_CLK_CKO1 169 | ||
| 183 | #define IMX6QDL_CLK_PLL1_SYS 170 | ||
| 184 | #define IMX6QDL_CLK_PLL2_BUS 171 | ||
| 185 | #define IMX6QDL_CLK_PLL3_USB_OTG 172 | ||
| 186 | #define IMX6QDL_CLK_PLL4_AUDIO 173 | ||
| 187 | #define IMX6QDL_CLK_PLL5_VIDEO 174 | ||
| 188 | #define IMX6QDL_CLK_PLL8_MLB 175 | ||
| 189 | #define IMX6QDL_CLK_PLL7_USB_HOST 176 | ||
| 190 | #define IMX6QDL_CLK_PLL6_ENET 177 | ||
| 191 | #define IMX6QDL_CLK_SSI1_IPG 178 | ||
| 192 | #define IMX6QDL_CLK_SSI2_IPG 179 | ||
| 193 | #define IMX6QDL_CLK_SSI3_IPG 180 | ||
| 194 | #define IMX6QDL_CLK_ROM 181 | ||
| 195 | #define IMX6QDL_CLK_USBPHY1 182 | ||
| 196 | #define IMX6QDL_CLK_USBPHY2 183 | ||
| 197 | #define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 | ||
| 198 | #define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 | ||
| 199 | #define IMX6QDL_CLK_SATA_REF 186 | ||
| 200 | #define IMX6QDL_CLK_SATA_REF_100M 187 | ||
| 201 | #define IMX6QDL_CLK_PCIE_REF 188 | ||
| 202 | #define IMX6QDL_CLK_PCIE_REF_125M 189 | ||
| 203 | #define IMX6QDL_CLK_ENET_REF 190 | ||
| 204 | #define IMX6QDL_CLK_USBPHY1_GATE 191 | ||
| 205 | #define IMX6QDL_CLK_USBPHY2_GATE 192 | ||
| 206 | #define IMX6QDL_CLK_PLL4_POST_DIV 193 | ||
| 207 | #define IMX6QDL_CLK_PLL5_POST_DIV 194 | ||
| 208 | #define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 | ||
| 209 | #define IMX6QDL_CLK_EIM_SLOW 196 | ||
| 210 | #define IMX6QDL_CLK_SPDIF 197 | ||
| 211 | #define IMX6QDL_CLK_CKO2_SEL 198 | ||
| 212 | #define IMX6QDL_CLK_CKO2_PODF 199 | ||
| 213 | #define IMX6QDL_CLK_CKO2 200 | ||
| 214 | #define IMX6QDL_CLK_CKO 201 | ||
| 215 | #define IMX6QDL_CLK_VDOA 202 | ||
| 216 | #define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 | ||
| 217 | #define IMX6QDL_CLK_LVDS1_SEL 204 | ||
| 218 | #define IMX6QDL_CLK_LVDS2_SEL 205 | ||
| 219 | #define IMX6QDL_CLK_LVDS1_GATE 206 | ||
| 220 | #define IMX6QDL_CLK_LVDS2_GATE 207 | ||
| 221 | #define IMX6QDL_CLK_ESAI_AHB 208 | ||
| 222 | #define IMX6QDL_CLK_END 209 | ||
| 223 | |||
| 224 | #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ | ||
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index a91602951d3d..00953d9484cb 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h | |||
| @@ -164,6 +164,8 @@ | |||
| 164 | #define VF610_CLK_DMAMUX1 151 | 164 | #define VF610_CLK_DMAMUX1 151 |
| 165 | #define VF610_CLK_DMAMUX2 152 | 165 | #define VF610_CLK_DMAMUX2 152 |
| 166 | #define VF610_CLK_DMAMUX3 153 | 166 | #define VF610_CLK_DMAMUX3 153 |
| 167 | #define VF610_CLK_END 154 | 167 | #define VF610_CLK_FLEXCAN0_EN 154 |
| 168 | #define VF610_CLK_FLEXCAN1_EN 155 | ||
| 169 | #define VF610_CLK_END 156 | ||
| 168 | 170 | ||
| 169 | #endif /* __DT_BINDINGS_CLOCK_VF610_H */ | 171 | #endif /* __DT_BINDINGS_CLOCK_VF610_H */ |
diff --git a/include/linux/platform_data/camera-mx1.h b/include/linux/platform_data/camera-mx1.h deleted file mode 100644 index 4fd6c70314b4..000000000000 --- a/include/linux/platform_data/camera-mx1.h +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * mx1_camera.h - i.MX1/i.MXL camera driver header file | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 5 | * Copyright (C) 2009, Darius Augulis <augulis.darius@gmail.com> | ||
| 6 | * | ||
| 7 | * Based on PXA camera.h file: | ||
| 8 | * Copyright (C) 2003, Intel Corporation | ||
| 9 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_CAMERA_H_ | ||
| 17 | #define __ASM_ARCH_CAMERA_H_ | ||
| 18 | |||
| 19 | #define MX1_CAMERA_DATA_HIGH 1 | ||
| 20 | #define MX1_CAMERA_PCLK_RISING 2 | ||
| 21 | #define MX1_CAMERA_VSYNC_HIGH 4 | ||
| 22 | |||
| 23 | extern unsigned char mx1_camera_sof_fiq_start, mx1_camera_sof_fiq_end; | ||
| 24 | |||
| 25 | /** | ||
| 26 | * struct mx1_camera_pdata - i.MX1/i.MXL camera platform data | ||
| 27 | * @mclk_10khz: master clock frequency in 10kHz units | ||
| 28 | * @flags: MX1 camera platform flags | ||
| 29 | */ | ||
| 30 | struct mx1_camera_pdata { | ||
| 31 | unsigned long mclk_10khz; | ||
| 32 | unsigned long flags; | ||
| 33 | }; | ||
| 34 | |||
| 35 | #endif /* __ASM_ARCH_CAMERA_H_ */ | ||
diff --git a/include/linux/platform_data/usb-ehci-mxc.h b/include/linux/platform_data/usb-ehci-mxc.h index 7eb9d1329671..157e71f79f99 100644 --- a/include/linux/platform_data/usb-ehci-mxc.h +++ b/include/linux/platform_data/usb-ehci-mxc.h | |||
| @@ -1,46 +1,6 @@ | |||
| 1 | #ifndef __INCLUDE_ASM_ARCH_MXC_EHCI_H | 1 | #ifndef __INCLUDE_ASM_ARCH_MXC_EHCI_H |
| 2 | #define __INCLUDE_ASM_ARCH_MXC_EHCI_H | 2 | #define __INCLUDE_ASM_ARCH_MXC_EHCI_H |
| 3 | 3 | ||
| 4 | /* values for portsc field */ | ||
| 5 | #define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) | ||
| 6 | #define MXC_EHCI_FORCE_FS (1 << 24) | ||
| 7 | #define MXC_EHCI_UTMI_8BIT (0 << 28) | ||
| 8 | #define MXC_EHCI_UTMI_16BIT (1 << 28) | ||
| 9 | #define MXC_EHCI_SERIAL (1 << 29) | ||
| 10 | #define MXC_EHCI_MODE_UTMI (0 << 30) | ||
| 11 | #define MXC_EHCI_MODE_PHILIPS (1 << 30) | ||
| 12 | #define MXC_EHCI_MODE_ULPI (2 << 30) | ||
| 13 | #define MXC_EHCI_MODE_SERIAL (3 << 30) | ||
| 14 | |||
| 15 | /* values for flags field */ | ||
| 16 | #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) | ||
| 17 | #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) | ||
| 18 | #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) | ||
| 19 | #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) | ||
| 20 | #define MXC_EHCI_INTERFACE_MASK (0xf) | ||
| 21 | |||
| 22 | #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) | ||
| 23 | #define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) | ||
| 24 | #define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) | ||
| 25 | #define MXC_EHCI_TTL_ENABLED (1 << 8) | ||
| 26 | |||
| 27 | #define MXC_EHCI_INTERNAL_PHY (1 << 9) | ||
| 28 | #define MXC_EHCI_IPPUE_DOWN (1 << 10) | ||
| 29 | #define MXC_EHCI_IPPUE_UP (1 << 11) | ||
| 30 | #define MXC_EHCI_WAKEUP_ENABLED (1 << 12) | ||
| 31 | #define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13) | ||
| 32 | |||
| 33 | #define MXC_USBCTRL_OFFSET 0 | ||
| 34 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 | ||
| 35 | #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc | ||
| 36 | #define MXC_USBH2CTRL_OFFSET 0x14 | ||
| 37 | |||
| 38 | #define MX5_USBOTHER_REGS_OFFSET 0x800 | ||
| 39 | |||
| 40 | /* USB_PHY_CTRL_FUNC2*/ | ||
| 41 | #define MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK 0x3 | ||
| 42 | #define MX5_USB_UTMI_PHYCTRL1_PLLDIV_SHIFT 0 | ||
| 43 | |||
| 44 | struct mxc_usbh_platform_data { | 4 | struct mxc_usbh_platform_data { |
| 45 | int (*init)(struct platform_device *pdev); | 5 | int (*init)(struct platform_device *pdev); |
| 46 | int (*exit)(struct platform_device *pdev); | 6 | int (*exit)(struct platform_device *pdev); |
| @@ -49,11 +9,5 @@ struct mxc_usbh_platform_data { | |||
| 49 | struct usb_phy *otg; | 9 | struct usb_phy *otg; |
| 50 | }; | 10 | }; |
| 51 | 11 | ||
| 52 | int mx51_initialize_usb_hw(int port, unsigned int flags); | ||
| 53 | int mx25_initialize_usb_hw(int port, unsigned int flags); | ||
| 54 | int mx31_initialize_usb_hw(int port, unsigned int flags); | ||
| 55 | int mx35_initialize_usb_hw(int port, unsigned int flags); | ||
| 56 | int mx27_initialize_usb_hw(int port, unsigned int flags); | ||
| 57 | |||
| 58 | #endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ | 12 | #endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ |
| 59 | 13 | ||
diff --git a/include/linux/platform_data/usb-imx_udc.h b/include/linux/platform_data/usb-imx_udc.h deleted file mode 100644 index be273371f34a..000000000000 --- a/include/linux/platform_data/usb-imx_udc.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_MXC_USB | ||
| 16 | #define __ASM_ARCH_MXC_USB | ||
| 17 | |||
| 18 | struct imxusb_platform_data { | ||
| 19 | int (*init)(struct device *); | ||
| 20 | void (*exit)(struct device *); | ||
| 21 | }; | ||
| 22 | |||
| 23 | #endif /* __ASM_ARCH_MXC_USB */ | ||