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authorTomi Valkeinen <tomi.valkeinen@ti.com>2012-08-06 09:50:14 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-09-07 13:02:12 -0400
commitb3e93cbddd6ab0c529a747a910e3bf9615e89982 (patch)
tree2cbe2380bbbb43766a134b5b9261f363a50196c3
parentfed62e54ae1f80f4631ce154225cf019f1219e59 (diff)
Revert "OMAPDSS: APPLY: add fifo-merge support"
This reverts commit 1d71f42b35ed66d90a9a39bc515bb16cfe2d4a46. Adding fifo merge feature as an omapdss internal configuration was a mistake. We cannot hide from the users of omapdss the complexities of fifo merge. This commit removes the fifo merge support, which luckily is easily done as it was handled totally inside apply.c. Note that this is not a 1:1 revert, but some resolving was needed for the dss_ovl_setup_fifo. The plan is to try fifo merge again later when it is more clear how the hardware acts in various situations, and how the omapdrm wants to use fifo merge. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
-rw-r--r--drivers/video/omap2/dss/apply.c154
1 files changed, 8 insertions, 146 deletions
diff --git a/drivers/video/omap2/dss/apply.c b/drivers/video/omap2/dss/apply.c
index 385b6df9925d..484751f15e2d 100644
--- a/drivers/video/omap2/dss/apply.c
+++ b/drivers/video/omap2/dss/apply.c
@@ -993,11 +993,11 @@ static void dss_apply_fifo_merge(bool use_fifo_merge)
993 dss_data.fifo_merge_dirty = true; 993 dss_data.fifo_merge_dirty = true;
994} 994}
995 995
996static void dss_ovl_setup_fifo(struct omap_overlay *ovl, 996static void dss_ovl_setup_fifo(struct omap_overlay *ovl)
997 bool use_fifo_merge)
998{ 997{
999 struct ovl_priv_data *op = get_ovl_priv(ovl); 998 struct ovl_priv_data *op = get_ovl_priv(ovl);
1000 u32 fifo_low, fifo_high; 999 u32 fifo_low, fifo_high;
1000 bool use_fifo_merge = false;
1001 1001
1002 if (!op->enabled && !op->enabling) 1002 if (!op->enabled && !op->enabling)
1003 return; 1003 return;
@@ -1008,8 +1008,7 @@ static void dss_ovl_setup_fifo(struct omap_overlay *ovl,
1008 dss_apply_ovl_fifo_thresholds(ovl, fifo_low, fifo_high); 1008 dss_apply_ovl_fifo_thresholds(ovl, fifo_low, fifo_high);
1009} 1009}
1010 1010
1011static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr, 1011static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr)
1012 bool use_fifo_merge)
1013{ 1012{
1014 struct omap_overlay *ovl; 1013 struct omap_overlay *ovl;
1015 struct mgr_priv_data *mp; 1014 struct mgr_priv_data *mp;
@@ -1020,10 +1019,10 @@ static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr,
1020 return; 1019 return;
1021 1020
1022 list_for_each_entry(ovl, &mgr->overlays, list) 1021 list_for_each_entry(ovl, &mgr->overlays, list)
1023 dss_ovl_setup_fifo(ovl, use_fifo_merge); 1022 dss_ovl_setup_fifo(ovl);
1024} 1023}
1025 1024
1026static void dss_setup_fifos(bool use_fifo_merge) 1025static void dss_setup_fifos(void)
1027{ 1026{
1028 const int num_mgrs = omap_dss_get_num_overlay_managers(); 1027 const int num_mgrs = omap_dss_get_num_overlay_managers();
1029 struct omap_overlay_manager *mgr; 1028 struct omap_overlay_manager *mgr;
@@ -1031,91 +1030,15 @@ static void dss_setup_fifos(bool use_fifo_merge)
1031 1030
1032 for (i = 0; i < num_mgrs; ++i) { 1031 for (i = 0; i < num_mgrs; ++i) {
1033 mgr = omap_dss_get_overlay_manager(i); 1032 mgr = omap_dss_get_overlay_manager(i);
1034 dss_mgr_setup_fifos(mgr, use_fifo_merge); 1033 dss_mgr_setup_fifos(mgr);
1035 } 1034 }
1036} 1035}
1037 1036
1038static int get_num_used_managers(void)
1039{
1040 const int num_mgrs = omap_dss_get_num_overlay_managers();
1041 struct omap_overlay_manager *mgr;
1042 struct mgr_priv_data *mp;
1043 int i;
1044 int enabled_mgrs;
1045
1046 enabled_mgrs = 0;
1047
1048 for (i = 0; i < num_mgrs; ++i) {
1049 mgr = omap_dss_get_overlay_manager(i);
1050 mp = get_mgr_priv(mgr);
1051
1052 if (!mp->enabled)
1053 continue;
1054
1055 enabled_mgrs++;
1056 }
1057
1058 return enabled_mgrs;
1059}
1060
1061static int get_num_used_overlays(void)
1062{
1063 const int num_ovls = omap_dss_get_num_overlays();
1064 struct omap_overlay *ovl;
1065 struct ovl_priv_data *op;
1066 struct mgr_priv_data *mp;
1067 int i;
1068 int enabled_ovls;
1069
1070 enabled_ovls = 0;
1071
1072 for (i = 0; i < num_ovls; ++i) {
1073 ovl = omap_dss_get_overlay(i);
1074 op = get_ovl_priv(ovl);
1075
1076 if (!op->enabled && !op->enabling)
1077 continue;
1078
1079 mp = get_mgr_priv(ovl->manager);
1080
1081 if (!mp->enabled)
1082 continue;
1083
1084 enabled_ovls++;
1085 }
1086
1087 return enabled_ovls;
1088}
1089
1090static bool get_use_fifo_merge(void)
1091{
1092 int enabled_mgrs = get_num_used_managers();
1093 int enabled_ovls = get_num_used_overlays();
1094
1095 if (!dss_has_feature(FEAT_FIFO_MERGE))
1096 return false;
1097
1098 /*
1099 * In theory the only requirement for fifomerge is enabled_ovls <= 1.
1100 * However, if we have two managers enabled and set/unset the fifomerge,
1101 * we need to set the GO bits in particular sequence for the managers,
1102 * and wait in between.
1103 *
1104 * This is rather difficult as new apply calls can happen at any time,
1105 * so we simplify the problem by requiring also that enabled_mgrs <= 1.
1106 * In practice this shouldn't matter, because when only one overlay is
1107 * enabled, most likely only one output is enabled.
1108 */
1109
1110 return enabled_mgrs <= 1 && enabled_ovls <= 1;
1111}
1112
1113int dss_mgr_enable(struct omap_overlay_manager *mgr) 1037int dss_mgr_enable(struct omap_overlay_manager *mgr)
1114{ 1038{
1115 struct mgr_priv_data *mp = get_mgr_priv(mgr); 1039 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1116 unsigned long flags; 1040 unsigned long flags;
1117 int r; 1041 int r;
1118 bool fifo_merge;
1119 1042
1120 mutex_lock(&apply_lock); 1043 mutex_lock(&apply_lock);
1121 1044
@@ -1133,23 +1056,11 @@ int dss_mgr_enable(struct omap_overlay_manager *mgr)
1133 goto err; 1056 goto err;
1134 } 1057 }
1135 1058
1136 /* step 1: setup fifos/fifomerge before enabling the manager */ 1059 dss_setup_fifos();
1137
1138 fifo_merge = get_use_fifo_merge();
1139 dss_setup_fifos(fifo_merge);
1140 dss_apply_fifo_merge(fifo_merge);
1141 1060
1142 dss_write_regs(); 1061 dss_write_regs();
1143 dss_set_go_bits(); 1062 dss_set_go_bits();
1144 1063
1145 spin_unlock_irqrestore(&data_lock, flags);
1146
1147 /* wait until fifo config is in */
1148 wait_pending_extra_info_updates();
1149
1150 /* step 2: enable the manager */
1151 spin_lock_irqsave(&data_lock, flags);
1152
1153 if (!mgr_manual_update(mgr)) 1064 if (!mgr_manual_update(mgr))
1154 mp->updating = true; 1065 mp->updating = true;
1155 1066
@@ -1174,7 +1085,6 @@ void dss_mgr_disable(struct omap_overlay_manager *mgr)
1174{ 1085{
1175 struct mgr_priv_data *mp = get_mgr_priv(mgr); 1086 struct mgr_priv_data *mp = get_mgr_priv(mgr);
1176 unsigned long flags; 1087 unsigned long flags;
1177 bool fifo_merge;
1178 1088
1179 mutex_lock(&apply_lock); 1089 mutex_lock(&apply_lock);
1180 1090
@@ -1189,16 +1099,8 @@ void dss_mgr_disable(struct omap_overlay_manager *mgr)
1189 mp->updating = false; 1099 mp->updating = false;
1190 mp->enabled = false; 1100 mp->enabled = false;
1191 1101
1192 fifo_merge = get_use_fifo_merge();
1193 dss_setup_fifos(fifo_merge);
1194 dss_apply_fifo_merge(fifo_merge);
1195
1196 dss_write_regs();
1197 dss_set_go_bits();
1198
1199 spin_unlock_irqrestore(&data_lock, flags); 1102 spin_unlock_irqrestore(&data_lock, flags);
1200 1103
1201 wait_pending_extra_info_updates();
1202out: 1104out:
1203 mutex_unlock(&apply_lock); 1105 mutex_unlock(&apply_lock);
1204} 1106}
@@ -1505,7 +1407,6 @@ int dss_ovl_enable(struct omap_overlay *ovl)
1505{ 1407{
1506 struct ovl_priv_data *op = get_ovl_priv(ovl); 1408 struct ovl_priv_data *op = get_ovl_priv(ovl);
1507 unsigned long flags; 1409 unsigned long flags;
1508 bool fifo_merge;
1509 int r; 1410 int r;
1510 1411
1511 mutex_lock(&apply_lock); 1412 mutex_lock(&apply_lock);
@@ -1531,22 +1432,7 @@ int dss_ovl_enable(struct omap_overlay *ovl)
1531 goto err2; 1432 goto err2;
1532 } 1433 }
1533 1434
1534 /* step 1: configure fifos/fifomerge for currently enabled ovls */ 1435 dss_setup_fifos();
1535
1536 fifo_merge = get_use_fifo_merge();
1537 dss_setup_fifos(fifo_merge);
1538 dss_apply_fifo_merge(fifo_merge);
1539
1540 dss_write_regs();
1541 dss_set_go_bits();
1542
1543 spin_unlock_irqrestore(&data_lock, flags);
1544
1545 /* wait for fifo configs to go in */
1546 wait_pending_extra_info_updates();
1547
1548 /* step 2: enable the overlay */
1549 spin_lock_irqsave(&data_lock, flags);
1550 1436
1551 op->enabling = false; 1437 op->enabling = false;
1552 dss_apply_ovl_enable(ovl, true); 1438 dss_apply_ovl_enable(ovl, true);
@@ -1556,9 +1442,6 @@ int dss_ovl_enable(struct omap_overlay *ovl)
1556 1442
1557 spin_unlock_irqrestore(&data_lock, flags); 1443 spin_unlock_irqrestore(&data_lock, flags);
1558 1444
1559 /* wait for overlay to be enabled */
1560 wait_pending_extra_info_updates();
1561
1562 mutex_unlock(&apply_lock); 1445 mutex_unlock(&apply_lock);
1563 1446
1564 return 0; 1447 return 0;
@@ -1574,7 +1457,6 @@ int dss_ovl_disable(struct omap_overlay *ovl)
1574{ 1457{
1575 struct ovl_priv_data *op = get_ovl_priv(ovl); 1458 struct ovl_priv_data *op = get_ovl_priv(ovl);
1576 unsigned long flags; 1459 unsigned long flags;
1577 bool fifo_merge;
1578 int r; 1460 int r;
1579 1461
1580 mutex_lock(&apply_lock); 1462 mutex_lock(&apply_lock);
@@ -1589,34 +1471,14 @@ int dss_ovl_disable(struct omap_overlay *ovl)
1589 goto err; 1471 goto err;
1590 } 1472 }
1591 1473
1592 /* step 1: disable the overlay */
1593 spin_lock_irqsave(&data_lock, flags); 1474 spin_lock_irqsave(&data_lock, flags);
1594 1475
1595 dss_apply_ovl_enable(ovl, false); 1476 dss_apply_ovl_enable(ovl, false);
1596
1597 dss_write_regs(); 1477 dss_write_regs();
1598 dss_set_go_bits(); 1478 dss_set_go_bits();
1599 1479
1600 spin_unlock_irqrestore(&data_lock, flags); 1480 spin_unlock_irqrestore(&data_lock, flags);
1601 1481
1602 /* wait for the overlay to be disabled */
1603 wait_pending_extra_info_updates();
1604
1605 /* step 2: configure fifos/fifomerge */
1606 spin_lock_irqsave(&data_lock, flags);
1607
1608 fifo_merge = get_use_fifo_merge();
1609 dss_setup_fifos(fifo_merge);
1610 dss_apply_fifo_merge(fifo_merge);
1611
1612 dss_write_regs();
1613 dss_set_go_bits();
1614
1615 spin_unlock_irqrestore(&data_lock, flags);
1616
1617 /* wait for fifo config to go in */
1618 wait_pending_extra_info_updates();
1619
1620 mutex_unlock(&apply_lock); 1482 mutex_unlock(&apply_lock);
1621 1483
1622 return 0; 1484 return 0;