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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-09-04 11:30:06 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-09-17 04:03:39 -0400
commitb397c96b6d6478910cd4263af3124ee07d304e8b (patch)
tree7c75c1696de4c40cdcac01c82d8493d35c6480ec
parent1d1d0e277ee706413e2a3b3c671e3cf29c8d0dd2 (diff)
drm/i915: Fix up pipe vs. double wide confusion
Double wide mode is only available on pipe A, except on GDG where pipe B is also double wide capable. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9bbb6ea34d06..4dd6561cb7c8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4153,10 +4153,10 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
4153 * Enable pixel doubling when the dot clock 4153 * Enable pixel doubling when the dot clock
4154 * is > 90% of the (display) core speed. 4154 * is > 90% of the (display) core speed.
4155 * 4155 *
4156 * XXX: No double-wide on 915GM pipe B. Is that 4156 * GDG double wide on either pipe,
4157 * the only reason for the pipe == PIPE_A check? 4157 * otherwise pipe A only.
4158 */ 4158 */
4159 if (crtc->pipe == PIPE_A && 4159 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4160 adjusted_mode->clock > clock_limit * 9 / 10) { 4160 adjusted_mode->clock > clock_limit * 9 / 10) {
4161 clock_limit *= 2; 4161 clock_limit *= 2;
4162 pipe_config->double_wide = true; 4162 pipe_config->double_wide = true;