drm/nv50-/disp: add support for completion events

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

11 files changed, 173 insertions, 11 deletions

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
index d54da8b5f87e..c8e4e60b86f1 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
@@ -68,6 +68,10 @@ gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = gm107_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nvd0_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 4b5bb5d58a54..86fda5d51ed4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -29,6 +29,7 @@
 #include <core/enum.h>
 #include <nvif/unpack.h>
 #include <nvif/class.h>
+#include <nvif/event.h>
 
 #include <subdev/bios.h>
 #include <subdev/bios/dcb.h>
@@ -82,6 +83,71 @@ nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
         nouveau_namedb_destroy(&chan->base);
 }
 
+static void
+nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
+{
+        struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
+        nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000000 << index);
+}
+
+static void
+nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
+{
+        struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
+        nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000001 << index);
+}
+
+void
+nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid)
+{
+        struct nvif_notify_uevent_rep {
+        } rep;
+
+        nvkm_event_send(&priv->uevent, 1, chid, &rep, sizeof(rep));
+}
+
+int
+nv50_disp_chan_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
+                           struct nvkm_notify *notify)
+{
+        struct nv50_disp_dmac *dmac = (void *)object;
+        union {
+                struct nvif_notify_uevent_req none;
+        } *args = data;
+        int ret;
+
+        if (nvif_unvers(args->none)) {
+                notify->size  = sizeof(struct nvif_notify_uevent_rep);
+                notify->types = 1;
+                notify->index = dmac->base.chid;
+                return 0;
+        }
+
+        return ret;
+}
+
+const struct nvkm_event_func
+nv50_disp_chan_uevent = {
+        .ctor = nv50_disp_chan_uevent_ctor,
+        .init = nv50_disp_chan_uevent_init,
+        .fini = nv50_disp_chan_uevent_fini,
+};
+
+int
+nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type,
+                    struct nvkm_event **pevent)
+{
+        struct nv50_disp_priv *priv = (void *)object->engine;
+        switch (type) {
+        case NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT:
+                *pevent = &priv->uevent;
+                return 0;
+        default:
+                break;
+        }
+        return -EINVAL;
+}
+
 int
 nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size)
 {
@@ -195,7 +261,7 @@ nv50_disp_dmac_init(struct nouveau_object *object)
                 return ret;
 
         /* enable error reporting */
-        nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid);
+        nv_mask(priv, 0x610028, 0x00010000 << chid, 0x00010000 << chid);
 
         /* initialise channel for dma command submission */
         nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);
@@ -232,7 +298,7 @@ nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
                         return -EBUSY;
         }
 
-        /* disable error reporting */
+        /* disable error reporting and completion notifications */
         nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid);
 
         return nv50_disp_chan_fini(&dmac->base, suspend);
@@ -454,7 +520,7 @@ nv50_disp_mast_init(struct nouveau_object *object)
                 return ret;
 
         /* enable error reporting */
-        nv_mask(priv, 0x610028, 0x00010001, 0x00010001);
+        nv_mask(priv, 0x610028, 0x00010000, 0x00010000);
 
         /* attempt to unstick channel from some unknown state */
         if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000)
@@ -494,7 +560,7 @@ nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
                         return -EBUSY;
         }
 
-        /* disable error reporting */
+        /* disable error reporting and completion notifications */
         nv_mask(priv, 0x610028, 0x00010001, 0x00000000);
 
         return nv50_disp_chan_fini(&mast->base, suspend);
@@ -507,6 +573,7 @@ nv50_disp_mast_ofuncs = {
         .base.init = nv50_disp_mast_init,
         .base.fini = nv50_disp_mast_fini,
         .base.map  = nv50_disp_chan_map,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
         .chid = 0,
@@ -607,6 +674,7 @@ nv50_disp_sync_ofuncs = {
         .base.dtor = nv50_disp_dmac_dtor,
         .base.init = nv50_disp_dmac_init,
         .base.fini = nv50_disp_dmac_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -696,6 +764,7 @@ nv50_disp_ovly_ofuncs = {
         .base.dtor = nv50_disp_dmac_dtor,
         .base.init = nv50_disp_dmac_init,
         .base.fini = nv50_disp_dmac_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -813,6 +882,7 @@ nv50_disp_oimm_ofuncs = {
         .base.dtor = nv50_disp_pioc_dtor,
         .base.init = nv50_disp_pioc_init,
         .base.fini = nv50_disp_pioc_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -860,6 +930,7 @@ nv50_disp_curs_ofuncs = {
         .base.dtor = nv50_disp_pioc_dtor,
         .base.init = nv50_disp_pioc_init,
         .base.fini = nv50_disp_pioc_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -1846,6 +1917,12 @@ nv50_disp_intr(struct nouveau_subdev *subdev)
                 intr0 &= ~(0x00010000 << chid);
         }
 
+        while (intr0 & 0x0000001f) {
+                u32 chid = __ffs(intr0 & 0x0000001f);
+                nv50_disp_chan_uevent_send(priv, chid);
+                intr0 &= ~(0x00000001 << chid);
+        }
+
         if (intr1 & 0x00000004) {
                 nouveau_disp_vblank(&priv->base, 0);
                 nv_wr32(priv, 0x610024, 0x00000004);
@@ -1880,6 +1957,10 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nv50_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nv50_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
index 8ab14461f70c..a288a7f454aa 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
@@ -26,6 +26,8 @@ struct nv50_disp_priv {
         struct work_struct supervisor;
         u32 super;
 
+        struct nvkm_event uevent;
+
         struct {
                 int nr;
         } head;
@@ -116,9 +118,16 @@ struct nv50_disp_chan {
         int chid;
 };
 
+int  nv50_disp_chan_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
 int  nv50_disp_chan_map(struct nouveau_object *, u64 *, u32 *);
 u32  nv50_disp_chan_rd32(struct nouveau_object *, u64);
 void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
+extern const struct nvkm_event_func nv50_disp_chan_uevent;
+int  nv50_disp_chan_uevent_ctor(struct nouveau_object *, void *, u32,
+                                struct nvkm_notify *);
+void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int);
+
+extern const struct nvkm_event_func nvd0_disp_chan_uevent;
 
 #define nv50_disp_chan_init(a)                                                 \
         nouveau_namedb_init(&(a)->base)
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
index 788ced1b6182..d36284715b2a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
@@ -236,6 +236,10 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nv84_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nv50_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
index fa79de906eae..a117064002b1 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
@@ -95,6 +95,10 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nv94_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nv50_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
index 7af15f5d48dc..c67e68aadd45 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
@@ -112,6 +112,10 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nva0_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nv50_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
index 6bd39448f8da..22969f355aae 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
@@ -67,6 +67,10 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nva3_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nv50_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index a4bb3c774ee1..a571c4fd6d53 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -43,6 +43,31 @@
 #include "nv50.h"
 
 /*******************************************************************************
+ * EVO channel base class
+ ******************************************************************************/
+
+static void
+nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
+{
+        struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
+        nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index);
+}
+
+static void
+nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
+{
+        struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
+        nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000001 << index);
+}
+
+const struct nvkm_event_func
+nvd0_disp_chan_uevent = {
+        .ctor = nv50_disp_chan_uevent_ctor,
+        .init = nvd0_disp_chan_uevent_init,
+        .fini = nvd0_disp_chan_uevent_fini,
+};
+
+/*******************************************************************************
  * EVO DMA channel base class
  ******************************************************************************/
 
@@ -77,7 +102,6 @@ nvd0_disp_dmac_init(struct nouveau_object *object)
                 return ret;
 
         /* enable error reporting */
-        nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
 
         /* initialise channel for dma command submission */
@@ -115,7 +139,7 @@ nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
                         return -EBUSY;
         }
 
-        /* disable error reporting */
+        /* disable error reporting and completion notification */
         nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
 
@@ -278,7 +302,6 @@ nvd0_disp_mast_init(struct nouveau_object *object)
                 return ret;
 
         /* enable error reporting */
-        nv_mask(priv, 0x610090, 0x00000001, 0x00000001);
         nv_mask(priv, 0x6100a0, 0x00000001, 0x00000001);
 
         /* initialise channel for dma command submission */
@@ -313,7 +336,7 @@ nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend)
                         return -EBUSY;
         }
 
-        /* disable error reporting */
+        /* disable error reporting and completion notification */
         nv_mask(priv, 0x610090, 0x00000001, 0x00000000);
         nv_mask(priv, 0x6100a0, 0x00000001, 0x00000000);
 
@@ -326,6 +349,7 @@ nvd0_disp_mast_ofuncs = {
         .base.dtor = nv50_disp_dmac_dtor,
         .base.init = nvd0_disp_mast_init,
         .base.fini = nvd0_disp_mast_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -419,6 +443,7 @@ nvd0_disp_sync_ofuncs = {
         .base.dtor = nv50_disp_dmac_dtor,
         .base.init = nvd0_disp_dmac_init,
         .base.fini = nvd0_disp_dmac_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -499,6 +524,7 @@ nvd0_disp_ovly_ofuncs = {
         .base.dtor = nv50_disp_dmac_dtor,
         .base.init = nvd0_disp_dmac_init,
         .base.fini = nvd0_disp_dmac_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -524,7 +550,6 @@ nvd0_disp_pioc_init(struct nouveau_object *object)
                 return ret;
 
         /* enable error reporting */
-        nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
 
         /* activate channel */
@@ -553,7 +578,7 @@ nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
                         return -EBUSY;
         }
 
-        /* disable error reporting */
+        /* disable error reporting and completion notification */
         nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
 
@@ -570,6 +595,7 @@ nvd0_disp_oimm_ofuncs = {
         .base.dtor = nv50_disp_pioc_dtor,
         .base.init = nvd0_disp_pioc_init,
         .base.fini = nvd0_disp_pioc_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -586,6 +612,7 @@ nvd0_disp_curs_ofuncs = {
         .base.dtor = nv50_disp_pioc_dtor,
         .base.init = nvd0_disp_pioc_init,
         .base.fini = nvd0_disp_pioc_fini,
+        .base.ntfy = nv50_disp_chan_ntfy,
         .base.map  = nv50_disp_chan_map,
         .base.rd32 = nv50_disp_chan_rd32,
         .base.wr32 = nv50_disp_chan_wr32,
@@ -1153,7 +1180,11 @@ nvd0_disp_intr(struct nouveau_subdev *subdev)
 
         if (intr & 0x00000001) {
                 u32 stat = nv_rd32(priv, 0x61008c);
-                nv_wr32(priv, 0x61008c, stat);
+                while (stat) {
+                        int chid = __ffs(stat); stat &= ~(1 << chid);
+                        nv50_disp_chan_uevent_send(priv, chid);
+                        nv_wr32(priv, 0x61008c, 1 << chid);
+                }
                 intr &= ~0x00000001;
         }
 
@@ -1209,6 +1240,10 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nvd0_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nvd0_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
index 47fef1e398c4..3ed47e187f89 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
@@ -233,6 +233,10 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nve0_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nvd0_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
index 04bda4ac4ed3..07f337695007 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
@@ -68,6 +68,10 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+        if (ret)
+                return ret;
+
         nv_engine(priv)->sclass = nvf0_disp_base_oclass;
         nv_engine(priv)->cclass = &nv50_disp_cclass;
         nv_subdev(priv)->intr = nvd0_disp_intr;
diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h
index 573491f84792..e5a27df0672b 100644
--- a/drivers/gpu/drm/nouveau/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/nvif/class.h
@@ -479,6 +479,8 @@ struct nv50_disp_core_channel_dma_v0 {
         __u32 pushbuf;
 };
 
+#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
+
 /* cursor immediate */
 struct nv50_disp_cursor_v0 {
         __u8  version;
@@ -486,6 +488,8 @@ struct nv50_disp_cursor_v0 {
         __u8  pad02[6];
 };
 
+#define NV50_DISP_CURSOR_V0_NTFY_UEVENT                                    0x00
+
 /* base */
 struct nv50_disp_base_channel_dma_v0 {
         __u8  version;
@@ -494,6 +498,8 @@ struct nv50_disp_base_channel_dma_v0 {
         __u32 pushbuf;
 };
 
+#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
+
 /* overlay */
 struct nv50_disp_overlay_channel_dma_v0 {
         __u8  version;
@@ -502,6 +508,8 @@ struct nv50_disp_overlay_channel_dma_v0 {
         __u32 pushbuf;
 };
 
+#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT                       0x00
+
 /* overlay immediate */
 struct nv50_disp_overlay_v0 {
         __u8  version;
@@ -509,6 +517,7 @@ struct nv50_disp_overlay_v0 {
         __u8  pad02[6];
 };
 
+#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT                                   0x00
 
 /*******************************************************************************
  * fermi