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authorAndrew Bresticker <abrestic@chromium.org>2015-02-24 22:56:04 -0500
committerRalf Baechle <ralf@linux-mips.org>2015-03-31 05:59:10 -0400
commitb35d7c33419cb0d000d23d3a5ab524ab8d3d8bf9 (patch)
treef016d8bffef6b5988e1606073030b2dd9b0b2754
parent43049b0c83f177083a56d69e64e47c82bcc04185 (diff)
CLK: Pistachio: Register core clocks
Register the clocks generated by the core clock controller. This includes the 7 PLLs and clocks for the CPU, RPU co-processor, audio, WiFi, bluetooth, and several other peripherals. The MIPS and PERIPH_SYS clocks must remain enabled at all times. Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: James Hartley <james.hartley@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Patchwork: https://patchwork.linux-mips.org/patch/9317/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--drivers/clk/pistachio/Makefile1
-rw-r--r--drivers/clk/pistachio/clk-pistachio.c199
2 files changed, 200 insertions, 0 deletions
diff --git a/drivers/clk/pistachio/Makefile b/drivers/clk/pistachio/Makefile
index a93490dbe3e1..f1e151fbef65 100644
--- a/drivers/clk/pistachio/Makefile
+++ b/drivers/clk/pistachio/Makefile
@@ -1,2 +1,3 @@
1obj-y += clk.o 1obj-y += clk.o
2obj-y += clk-pll.o 2obj-y += clk-pll.o
3obj-y += clk-pistachio.o
diff --git a/drivers/clk/pistachio/clk-pistachio.c b/drivers/clk/pistachio/clk-pistachio.c
new file mode 100644
index 000000000000..12a45e246fd1
--- /dev/null
+++ b/drivers/clk/pistachio/clk-pistachio.c
@@ -0,0 +1,199 @@
1/*
2 * Pistachio SoC clock controllers
3 *
4 * Copyright (C) 2014 Google, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/of.h>
16
17#include <dt-bindings/clock/pistachio-clk.h>
18
19#include "clk.h"
20
21static struct pistachio_gate pistachio_gates[] __initdata = {
22 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
23 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
24 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
25 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
26 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
27 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
28 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
29 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
30 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
31 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
32 GATE(CLK_RPU_CORE, "rpu_core", "rpu_core_div", 0x104, 10),
33 GATE(CLK_WIFI_ADC, "wifi_adc", "wifi_div8_mux", 0x104, 11),
34 GATE(CLK_WIFI_DAC, "wifi_dac", "wifi_div4_mux", 0x104, 12),
35 GATE(CLK_USB_PHY, "usb_phy", "usb_phy_div", 0x104, 13),
36 GATE(CLK_ENET_IN, "enet_in", "enet_clk_in_gate", 0x104, 14),
37 GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
38 GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
39 GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
40 GATE(CLK_PERIPH_SYS, "periph_sys", "sys_internal_div", 0x104, 18),
41 GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
42 GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
43 GATE(CLK_EVENT_TIMER, "event_timer", "event_timer_div", 0x104, 21),
44 GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
45 0x104, 22),
46 GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
47 GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
48 GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
49 GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
50 GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
51 GATE(CLK_BT_1MHZ, "bt_1mhz", "bt_1mhz_div", 0x104, 28),
52};
53
54static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
55 FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
56 FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
57};
58
59static struct pistachio_div pistachio_divs[] __initdata = {
60 DIV(CLK_MIPS_INTERNAL_DIV, "mips_internal_div", "mips_pll_mux",
61 0x204, 2),
62 DIV(CLK_MIPS_DIV, "mips_div", "mips_internal_div", 0x208, 8),
63 DIV_F(CLK_AUDIO_DIV, "audio_div", "audio_mux",
64 0x20c, 8, CLK_DIVIDER_ROUND_CLOSEST),
65 DIV_F(CLK_I2S_DIV, "i2s_div", "audio_pll_mux",
66 0x210, 8, CLK_DIVIDER_ROUND_CLOSEST),
67 DIV_F(CLK_SPDIF_DIV, "spdif_div", "audio_pll_mux",
68 0x214, 8, CLK_DIVIDER_ROUND_CLOSEST),
69 DIV_F(CLK_AUDIO_DAC_DIV, "audio_dac_div", "audio_pll_mux",
70 0x218, 8, CLK_DIVIDER_ROUND_CLOSEST),
71 DIV(CLK_RPU_V_DIV, "rpu_v_div", "rpu_v_pll_mux", 0x21c, 2),
72 DIV(CLK_RPU_L_DIV, "rpu_l_div", "rpu_l_mux", 0x220, 2),
73 DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
74 DIV(CLK_RPU_CORE_DIV, "rpu_core_div", "rpu_core_mux", 0x228, 3),
75 DIV(CLK_USB_PHY_DIV, "usb_phy_div", "sys_internal_div", 0x22c, 6),
76 DIV(CLK_ENET_DIV, "enet_div", "enet_mux", 0x230, 6),
77 DIV_F(CLK_UART0_INTERNAL_DIV, "uart0_internal_div", "sys_pll_mux",
78 0x234, 3, CLK_DIVIDER_ROUND_CLOSEST),
79 DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,
80 CLK_DIVIDER_ROUND_CLOSEST),
81 DIV_F(CLK_UART1_INTERNAL_DIV, "uart1_internal_div", "sys_pll_mux",
82 0x23c, 3, CLK_DIVIDER_ROUND_CLOSEST),
83 DIV_F(CLK_UART1_DIV, "uart1_div", "uart1_internal_div", 0x240, 10,
84 CLK_DIVIDER_ROUND_CLOSEST),
85 DIV(CLK_SYS_INTERNAL_DIV, "sys_internal_div", "sys_pll_mux", 0x244, 3),
86 DIV(CLK_SPI0_INTERNAL_DIV, "spi0_internal_div", "sys_pll_mux",
87 0x248, 3),
88 DIV(CLK_SPI0_DIV, "spi0_div", "spi0_internal_div", 0x24c, 7),
89 DIV(CLK_SPI1_INTERNAL_DIV, "spi1_internal_div", "sys_pll_mux",
90 0x250, 3),
91 DIV(CLK_SPI1_DIV, "spi1_div", "spi1_internal_div", 0x254, 7),
92 DIV(CLK_EVENT_TIMER_INTERNAL_DIV, "event_timer_internal_div",
93 "event_timer_mux", 0x258, 3),
94 DIV(CLK_EVENT_TIMER_DIV, "event_timer_div", "event_timer_internal_div",
95 0x25c, 12),
96 DIV(CLK_AUX_ADC_INTERNAL_DIV, "aux_adc_internal_div",
97 "aux_adc_internal", 0x260, 3),
98 DIV(CLK_AUX_ADC_DIV, "aux_adc_div", "aux_adc_internal_div", 0x264, 10),
99 DIV(CLK_SD_HOST_DIV, "sd_host_div", "sd_host_mux", 0x268, 6),
100 DIV(CLK_BT_DIV, "bt_div", "bt_pll_mux", 0x26c, 6),
101 DIV(CLK_BT_DIV4_DIV, "bt_div4_div", "bt_pll_mux", 0x270, 6),
102 DIV(CLK_BT_DIV8_DIV, "bt_div8_div", "bt_pll_mux", 0x274, 6),
103 DIV(CLK_BT_1MHZ_INTERNAL_DIV, "bt_1mhz_internal_div", "bt_pll_mux",
104 0x278, 3),
105 DIV(CLK_BT_1MHZ_DIV, "bt_1mhz_div", "bt_1mhz_internal_div", 0x27c, 10),
106};
107
108PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
109PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
110PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
111PNAME(mux_audio_debug) = { "audio_pll_mux", "debug_mux" };
112PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
113PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
114PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" };
115PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
116PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
117PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
118PNAME(mux_wifi_div4_rpu_l) = { "wifi_pll_gate", "wifi_div4_mux",
119 "rpu_l_pll_mux" };
120PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };
121PNAME(mux_sys_enet) = { "sys_internal_div", "enet_in" };
122PNAME(mux_audio_sys) = { "audio_pll_mux", "sys_internal_div" };
123PNAME(mux_sys_bt) = { "sys_internal_div", "bt_pll_mux" };
124PNAME(mux_xtal_bt) = { "xtal", "bt_pll" };
125
126static struct pistachio_mux pistachio_muxes[] __initdata = {
127 MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk,
128 0x200, 0),
129 MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),
130 MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),
131 MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),
132 MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),
133 MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6),
134 MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),
135 MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),
136 MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9),
137 MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10),
138 MUX(CLK_RPU_CORE_MUX, "rpu_core_mux", mux_wifi_div4_rpu_l, 0x200, 11),
139 MUX(CLK_SYS_PLL_MUX, "sys_pll_mux", mux_xtal_sys, 0x200, 13),
140 MUX(CLK_ENET_MUX, "enet_mux", mux_sys_enet, 0x200, 14),
141 MUX(CLK_EVENT_TIMER_MUX, "event_timer_mux", mux_audio_sys, 0x200, 15),
142 MUX(CLK_SD_HOST_MUX, "sd_host_mux", mux_sys_bt, 0x200, 16),
143 MUX(CLK_BT_PLL_MUX, "bt_pll_mux", mux_xtal_bt, 0x200, 17),
144};
145
146static struct pistachio_pll pistachio_plls[] __initdata = {
147 PLL_FIXED(CLK_MIPS_PLL, "mips_pll", "xtal", PLL_GF40LP_LAINT, 0x0),
148 PLL_FIXED(CLK_AUDIO_PLL, "audio_pll", "audio_refclk_mux",
149 PLL_GF40LP_FRAC, 0xc),
150 PLL_FIXED(CLK_RPU_V_PLL, "rpu_v_pll", "xtal", PLL_GF40LP_LAINT, 0x20),
151 PLL_FIXED(CLK_RPU_L_PLL, "rpu_l_pll", "xtal", PLL_GF40LP_LAINT, 0x2c),
152 PLL_FIXED(CLK_SYS_PLL, "sys_pll", "xtal", PLL_GF40LP_FRAC, 0x38),
153 PLL_FIXED(CLK_WIFI_PLL, "wifi_pll", "xtal", PLL_GF40LP_FRAC, 0x4c),
154 PLL_FIXED(CLK_BT_PLL, "bt_pll", "xtal", PLL_GF40LP_LAINT, 0x60),
155};
156
157PNAME(mux_debug) = { "mips_pll_mux", "rpu_v_pll_mux",
158 "rpu_l_pll_mux", "sys_pll_mux",
159 "wifi_pll_mux", "bt_pll_mux" };
160static u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };
161
162static unsigned int pistachio_critical_clks[] __initdata = {
163 CLK_MIPS,
164 CLK_PERIPH_SYS,
165};
166
167static void __init pistachio_clk_init(struct device_node *np)
168{
169 struct pistachio_clk_provider *p;
170 struct clk *debug_clk;
171
172 p = pistachio_clk_alloc_provider(np, CLK_NR_CLKS);
173 if (!p)
174 return;
175
176 pistachio_clk_register_pll(p, pistachio_plls,
177 ARRAY_SIZE(pistachio_plls));
178 pistachio_clk_register_mux(p, pistachio_muxes,
179 ARRAY_SIZE(pistachio_muxes));
180 pistachio_clk_register_div(p, pistachio_divs,
181 ARRAY_SIZE(pistachio_divs));
182 pistachio_clk_register_fixed_factor(p, pistachio_ffs,
183 ARRAY_SIZE(pistachio_ffs));
184 pistachio_clk_register_gate(p, pistachio_gates,
185 ARRAY_SIZE(pistachio_gates));
186
187 debug_clk = clk_register_mux_table(NULL, "debug_mux", mux_debug,
188 ARRAY_SIZE(mux_debug),
189 CLK_SET_RATE_NO_REPARENT,
190 p->base + 0x200, 18, 0x1f, 0,
191 mux_debug_idx, NULL);
192 p->clk_data.clks[CLK_DEBUG_MUX] = debug_clk;
193
194 pistachio_clk_register_provider(p);
195
196 pistachio_clk_force_enable(p, pistachio_critical_clks,
197 ARRAY_SIZE(pistachio_critical_clks));
198}
199CLK_OF_DECLARE(pistachio_clk, "img,pistachio-clk", pistachio_clk_init);
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