diff options
author | Jingoo Han <jg1.han@samsung.com> | 2013-06-21 03:26:14 -0400 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2013-06-26 14:16:31 -0400 |
commit | b342e64c6794aed1f8742d44d7dfc78a9c2c1cba (patch) | |
tree | 418e5abfa47c1d5b6ca6f13ead2bbe14993c02cd | |
parent | 406a9324b4d90e52e610bc898a624f597371c7b6 (diff) |
ARM: dts: Add pcie controller node for exynos5440-ssdk5440
This patch adds pcie controller node for exynos5440-ssdk5440,
and also adds a phandle for pin controller node.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r-- | arch/arm/boot/dts/exynos5440-ssdk5440.dts | 8 | ||||
-rw-r--r-- | arch/arm/boot/dts/exynos5440.dtsi | 2 |
2 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index d55042beb5c5..f96de398c965 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts | |||
@@ -30,4 +30,12 @@ | |||
30 | clock-frequency = <50000000>; | 30 | clock-frequency = <50000000>; |
31 | }; | 31 | }; |
32 | }; | 32 | }; |
33 | |||
34 | pcie@290000 { | ||
35 | reset-gpio = <&pin_ctrl 5 0>; | ||
36 | }; | ||
37 | |||
38 | pcie@2a0000 { | ||
39 | reset-gpio = <&pin_ctrl 22 0>; | ||
40 | }; | ||
33 | }; | 41 | }; |
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 0709767b7248..b7ffc4dfe219 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi | |||
@@ -113,7 +113,7 @@ | |||
113 | clock-names = "spi", "spi_busclk0"; | 113 | clock-names = "spi", "spi_busclk0"; |
114 | }; | 114 | }; |
115 | 115 | ||
116 | pinctrl { | 116 | pin_ctrl: pinctrl { |
117 | compatible = "samsung,exynos5440-pinctrl"; | 117 | compatible = "samsung,exynos5440-pinctrl"; |
118 | reg = <0xE0000 0x1000>; | 118 | reg = <0xE0000 0x1000>; |
119 | interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, | 119 | interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, |