diff options
| author | Tony Lindgren <tony@atomide.com> | 2013-05-30 15:53:06 -0400 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2013-05-30 16:09:31 -0400 |
| commit | b30e321b6a3ebd019c7be9019946017d73e18989 (patch) | |
| tree | 844fe08a846cc274663a439f4f37fd20a2e98422 | |
| parent | c99eb41c3eac3d66530960d896d59bfe806e5c04 (diff) | |
ARM: OMAP2+: Remove omap4 pdata from hsmmc.c
This is no longer needed as omap4 is now booted using
device tree.
Signed-off-by: Tony Lindgren <tony@atomide.com>
| -rw-r--r-- | arch/arm/mach-omap2/hsmmc.c | 103 |
1 files changed, 10 insertions, 93 deletions
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 2ef1f8714fcf..07d4c7b35754 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c | |||
| @@ -29,7 +29,6 @@ | |||
| 29 | 29 | ||
| 30 | static u16 control_pbias_offset; | 30 | static u16 control_pbias_offset; |
| 31 | static u16 control_devconf1_offset; | 31 | static u16 control_devconf1_offset; |
| 32 | static u16 control_mmc1; | ||
| 33 | 32 | ||
| 34 | #define HSMMC_NAME_LEN 9 | 33 | #define HSMMC_NAME_LEN 9 |
| 35 | 34 | ||
| @@ -121,57 +120,6 @@ static void omap_hsmmc1_after_set_reg(struct device *dev, int slot, | |||
| 121 | } | 120 | } |
| 122 | } | 121 | } |
| 123 | 122 | ||
| 124 | static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, | ||
| 125 | int power_on, int vdd) | ||
| 126 | { | ||
| 127 | u32 reg; | ||
| 128 | |||
| 129 | /* | ||
| 130 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | ||
| 131 | * card with Vcc regulator (from twl4030 or whatever). OMAP has both | ||
| 132 | * 1.8V and 3.0V modes, controlled by the PBIAS register. | ||
| 133 | */ | ||
| 134 | reg = omap4_ctrl_pad_readl(control_pbias_offset); | ||
| 135 | reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | | ||
| 136 | OMAP4_MMC1_PWRDNZ_MASK | | ||
| 137 | OMAP4_MMC1_PBIASLITE_VMODE_MASK); | ||
| 138 | omap4_ctrl_pad_writel(reg, control_pbias_offset); | ||
| 139 | } | ||
| 140 | |||
| 141 | static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, | ||
| 142 | int power_on, int vdd) | ||
| 143 | { | ||
| 144 | u32 reg; | ||
| 145 | unsigned long timeout; | ||
| 146 | |||
| 147 | if (power_on) { | ||
| 148 | reg = omap4_ctrl_pad_readl(control_pbias_offset); | ||
| 149 | reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; | ||
| 150 | if ((1 << vdd) <= MMC_VDD_165_195) | ||
| 151 | reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; | ||
| 152 | else | ||
| 153 | reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; | ||
| 154 | reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | | ||
| 155 | OMAP4_MMC1_PWRDNZ_MASK); | ||
| 156 | omap4_ctrl_pad_writel(reg, control_pbias_offset); | ||
| 157 | |||
| 158 | timeout = jiffies + msecs_to_jiffies(5); | ||
| 159 | do { | ||
| 160 | reg = omap4_ctrl_pad_readl(control_pbias_offset); | ||
| 161 | if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK)) | ||
| 162 | break; | ||
| 163 | usleep_range(100, 200); | ||
| 164 | } while (!time_after(jiffies, timeout)); | ||
| 165 | |||
| 166 | if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { | ||
| 167 | pr_err("Pbias Voltage is not same as LDO\n"); | ||
| 168 | /* Caution : On VMODE_ERROR Power Down MMC IO */ | ||
| 169 | reg &= ~(OMAP4_MMC1_PWRDNZ_MASK); | ||
| 170 | omap4_ctrl_pad_writel(reg, control_pbias_offset); | ||
| 171 | } | ||
| 172 | } | ||
| 173 | } | ||
| 174 | |||
| 175 | static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) | 123 | static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) |
| 176 | { | 124 | { |
| 177 | u32 reg; | 125 | u32 reg; |
| @@ -317,11 +265,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, | |||
| 317 | mmc->slots[0].pm_caps = c->pm_caps; | 265 | mmc->slots[0].pm_caps = c->pm_caps; |
| 318 | mmc->slots[0].internal_clock = !c->ext_clock; | 266 | mmc->slots[0].internal_clock = !c->ext_clock; |
| 319 | mmc->max_freq = c->max_freq; | 267 | mmc->max_freq = c->max_freq; |
| 320 | if (cpu_is_omap44xx()) | 268 | mmc->reg_offset = 0; |
| 321 | mmc->reg_offset = OMAP4_MMC_REG_OFFSET; | ||
| 322 | else | ||
| 323 | mmc->reg_offset = 0; | ||
| 324 | |||
| 325 | mmc->get_context_loss_count = hsmmc_get_context_loss; | 269 | mmc->get_context_loss_count = hsmmc_get_context_loss; |
| 326 | 270 | ||
| 327 | mmc->slots[0].switch_pin = c->gpio_cd; | 271 | mmc->slots[0].switch_pin = c->gpio_cd; |
| @@ -368,24 +312,14 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, | |||
| 368 | if (!soc_is_am35xx()) | 312 | if (!soc_is_am35xx()) |
| 369 | mmc->slots[0].features |= HSMMC_HAS_PBIAS; | 313 | mmc->slots[0].features |= HSMMC_HAS_PBIAS; |
| 370 | 314 | ||
| 371 | if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) | ||
| 372 | mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; | ||
| 373 | |||
| 374 | switch (c->mmc) { | 315 | switch (c->mmc) { |
| 375 | case 1: | 316 | case 1: |
| 376 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { | 317 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { |
| 377 | /* on-chip level shifting via PBIAS0/PBIAS1 */ | 318 | /* on-chip level shifting via PBIAS0/PBIAS1 */ |
| 378 | if (cpu_is_omap44xx()) { | 319 | mmc->slots[0].before_set_reg = |
| 379 | mmc->slots[0].before_set_reg = | 320 | omap_hsmmc1_before_set_reg; |
| 380 | omap4_hsmmc1_before_set_reg; | 321 | mmc->slots[0].after_set_reg = |
| 381 | mmc->slots[0].after_set_reg = | 322 | omap_hsmmc1_after_set_reg; |
| 382 | omap4_hsmmc1_after_set_reg; | ||
| 383 | } else { | ||
| 384 | mmc->slots[0].before_set_reg = | ||
| 385 | omap_hsmmc1_before_set_reg; | ||
| 386 | mmc->slots[0].after_set_reg = | ||
| 387 | omap_hsmmc1_after_set_reg; | ||
| 388 | } | ||
| 389 | } | 323 | } |
| 390 | 324 | ||
| 391 | if (soc_is_am35xx()) | 325 | if (soc_is_am35xx()) |
| @@ -563,34 +497,17 @@ free_mmc: | |||
| 563 | 497 | ||
| 564 | void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers) | 498 | void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers) |
| 565 | { | 499 | { |
| 566 | u32 reg; | ||
| 567 | |||
| 568 | if (omap_hsmmc_done) | 500 | if (omap_hsmmc_done) |
| 569 | return; | 501 | return; |
| 570 | 502 | ||
| 571 | omap_hsmmc_done = 1; | 503 | omap_hsmmc_done = 1; |
| 572 | 504 | ||
| 573 | if (!cpu_is_omap44xx()) { | 505 | if (cpu_is_omap2430()) { |
| 574 | if (cpu_is_omap2430()) { | 506 | control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; |
| 575 | control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; | 507 | control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; |
| 576 | control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; | ||
| 577 | } else { | ||
| 578 | control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; | ||
| 579 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; | ||
| 580 | } | ||
| 581 | } else { | 508 | } else { |
| 582 | control_pbias_offset = | 509 | control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; |
| 583 | OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; | 510 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; |
| 584 | control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; | ||
| 585 | reg = omap4_ctrl_pad_readl(control_mmc1); | ||
| 586 | reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | | ||
| 587 | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); | ||
| 588 | reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | | ||
| 589 | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); | ||
| 590 | reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK | | ||
| 591 | OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | | ||
| 592 | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); | ||
| 593 | omap4_ctrl_pad_writel(reg, control_mmc1); | ||
| 594 | } | 511 | } |
| 595 | 512 | ||
| 596 | for (; controllers->mmc; controllers++) | 513 | for (; controllers->mmc; controllers++) |
