Merge branch 'drm/next/du' of git://linuxtv.org/pinchartl/fbdev into drm-next

* 'drm/next/du' of git://linuxtv.org/pinchartl/fbdev:
  drm: rcar-du: Implement support for interlaced modes
  drm: rcar-du: Clamp DPMS states to on and off
  drm: rcar-du: Enable hotplug detection on HDMI connector
  drm: rcar-du: Output HSYNC instead of CSYNC
  drm: rcar-du: Add support for external pixel clock
  drm: rcar-du: Refactor DEFR8 feature
  drm: rcar-du: Remove LVDS and HDMI encoders chaining restriction
  drm: rcar-du: Configure pitch for chroma plane of multiplanar formats
  drm: rcar-du: Don't fail probe in case of partial encoder init error
  drm: adv7511: Remove interlaced mode check

14 files changed, 180 insertions, 47 deletions

diff --git a/Documentation/devicetree/bindings/video/renesas,du.txt b/Documentation/devicetree/bindings/video/renesas,du.txt
index 5102830f2760..c902323928f7 100644
--- a/Documentation/devicetree/bindings/video/renesas,du.txt
+++ b/Documentation/devicetree/bindings/video/renesas,du.txt
@@ -26,6 +26,10 @@ Required Properties:
       per LVDS encoder. The functional clocks must be named "du.x" with "x"
       being the channel numerical index. The LVDS clocks must be named
       "lvds.x" with "x" being the LVDS encoder numerical index.
+    - In addition to the functional and encoder clocks, all DU versions also
+      support externally supplied pixel clocks. Those clocks are optional.
+      When supplied they must be named "dclkin.x" with "x" being the input
+      clock numerical index.
 
 Required nodes:
 
diff --git a/drivers/gpu/drm/i2c/adv7511.c b/drivers/gpu/drm/i2c/adv7511.c
index faf1c0c5ab2e..fa140e04d5fa 100644
--- a/drivers/gpu/drm/i2c/adv7511.c
+++ b/drivers/gpu/drm/i2c/adv7511.c
@@ -644,9 +644,6 @@ static int adv7511_encoder_mode_valid(struct drm_encoder *encoder,
         if (mode->clock > 165000)
                 return MODE_CLOCK_HIGH;
 
-        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
-                return MODE_NO_INTERLACE;
-
         return MODE_OK;
 }
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 23cc910951f4..25c7a998fc2c 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -74,39 +74,77 @@ static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
         if (ret < 0)
                 return ret;
 
+        ret = clk_prepare_enable(rcrtc->extclock);
+        if (ret < 0)
+                goto error_clock;
+
         ret = rcar_du_group_get(rcrtc->group);
         if (ret < 0)
-                clk_disable_unprepare(rcrtc->clock);
+                goto error_group;
+
+        return 0;
 
+error_group:
+        clk_disable_unprepare(rcrtc->extclock);
+error_clock:
+        clk_disable_unprepare(rcrtc->clock);
         return ret;
 }
 
 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
 {
         rcar_du_group_put(rcrtc->group);
+
+        clk_disable_unprepare(rcrtc->extclock);
         clk_disable_unprepare(rcrtc->clock);
 }
 
 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 {
         const struct drm_display_mode *mode = &rcrtc->crtc.mode;
+        unsigned long mode_clock = mode->clock * 1000;
         unsigned long clk;
         u32 value;
+        u32 escr;
         u32 div;
 
-        /* Dot clock */
+        /* Compute the clock divisor and select the internal or external dot
+         * clock based on the requested frequency.
+         */
         clk = clk_get_rate(rcrtc->clock);
-        div = DIV_ROUND_CLOSEST(clk, mode->clock * 1000);
+        div = DIV_ROUND_CLOSEST(clk, mode_clock);
         div = clamp(div, 1U, 64U) - 1;
+        escr = div | ESCR_DCLKSEL_CLKS;
+
+        if (rcrtc->extclock) {
+                unsigned long extclk;
+                unsigned long extrate;
+                unsigned long rate;
+                u32 extdiv;
+
+                extclk = clk_get_rate(rcrtc->extclock);
+                extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
+                extdiv = clamp(extdiv, 1U, 64U) - 1;
+
+                rate = clk / (div + 1);
+                extrate = extclk / (extdiv + 1);
+
+                if (abs((long)extrate - (long)mode_clock) <
+                    abs((long)rate - (long)mode_clock)) {
+                        dev_dbg(rcrtc->group->dev->dev,
+                                "crtc%u: using external clock\n", rcrtc->index);
+                        escr = extdiv | ESCR_DCLKSEL_DCLKIN;
+                }
+        }
 
         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
-                            ESCR_DCLKSEL_CLKS | div);
+                            escr);
         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 
         /* Signal polarities */
         value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
               | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
-              | DSMR_DIPM_DE;
+              | DSMR_DIPM_DE | DSMR_CSPM;
         rcar_du_crtc_write(rcrtc, DSMR, value);
 
         /* Display timings */
@@ -117,12 +155,15 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
                                         mode->hsync_start - 1);
         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 
-        rcar_du_crtc_write(rcrtc, VDSR, mode->vtotal - mode->vsync_end - 2);
-        rcar_du_crtc_write(rcrtc, VDER, mode->vtotal - mode->vsync_end +
-                                        mode->vdisplay - 2);
-        rcar_du_crtc_write(rcrtc, VSPR, mode->vtotal - mode->vsync_end +
-                                        mode->vsync_start - 1);
-        rcar_du_crtc_write(rcrtc, VCR,  mode->vtotal - 1);
+        rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
+                                        mode->crtc_vsync_end - 2);
+        rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
+                                        mode->crtc_vsync_end +
+                                        mode->crtc_vdisplay - 2);
+        rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
+                                        mode->crtc_vsync_end +
+                                        mode->crtc_vsync_start - 1);
+        rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 
         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
@@ -139,9 +180,10 @@ void rcar_du_crtc_route_output(struct drm_crtc *crtc,
          */
         rcrtc->outputs |= BIT(output);