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authorJason Cooper <jason@lakedaemon.net>2014-03-03 21:17:23 -0500
committerJason Cooper <jason@lakedaemon.net>2014-03-03 21:17:23 -0500
commitb2d7c52603a96fa6fe0a02d3b66b90087a7f8407 (patch)
treea98b2d00df13a8e4e51da138fdc57dbfc5694caf
parent7a98c18f71a23b70775327d7f993cf36db162b43 (diff)
parentd11548e3113961b3d3c0b362f0dbe72d72a7959b (diff)
Merge branch 'mvebu/dt-3xx' into mvebu/dt
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/armada-375-db.dts130
-rw-r--r--arch/arm/boot/dts/armada-375.dtsi464
-rw-r--r--arch/arm/boot/dts/armada-380.dtsi117
-rw-r--r--arch/arm/boot/dts/armada-385-db.dts101
-rw-r--r--arch/arm/boot/dts/armada-385.dtsi149
-rw-r--r--arch/arm/boot/dts/armada-38x.dtsi351
7 files changed, 1314 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7b54b05b9395..46c54a2dac71 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -147,6 +147,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
147 armada-370-netgear-rn102.dtb \ 147 armada-370-netgear-rn102.dtb \
148 armada-370-netgear-rn104.dtb \ 148 armada-370-netgear-rn104.dtb \
149 armada-370-rd.dtb \ 149 armada-370-rd.dtb \
150 armada-375-db.dtb \
151 armada-385-db.dtb \
150 armada-xp-axpwifiap.dtb \ 152 armada-xp-axpwifiap.dtb \
151 armada-xp-db.dtb \ 153 armada-xp-db.dtb \
152 armada-xp-gp.dtb \ 154 armada-xp-gp.dtb \
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
new file mode 100644
index 000000000000..9378d3136b41
--- /dev/null
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -0,0 +1,130 @@
1/*
2 * Device Tree file for Marvell Armada 375 evaluation board
3 * (DB-88F6720)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15/dts-v1/;
16#include <dt-bindings/gpio/gpio.h>
17#include "armada-375.dtsi"
18
19/ {
20 model = "Marvell Armada 375 Development Board";
21 compatible = "marvell,a375-db", "marvell,armada375";
22
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x00000000 0x40000000>; /* 1 GB */
30 };
31
32 soc {
33 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
34 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
35
36 internal-regs {
37 spi@10600 {
38 pinctrl-0 = <&spi0_pins>;
39 pinctrl-names = "default";
40 /*
41 * SPI conflicts with NAND, so we disable it
42 * here, and select NAND as the enabled device
43 * by default.
44 */
45 status = "disabled";
46
47 spi-flash@0 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "n25q128a13";
51 reg = <0>; /* Chip select 0 */
52 spi-max-frequency = <108000000>;
53 };
54 };
55
56 i2c@11000 {
57 status = "okay";
58 clock-frequency = <100000>;
59 pinctrl-0 = <&i2c0_pins>;
60 pinctrl-names = "default";
61 };
62
63 i2c@11100 {
64 status = "okay";
65 clock-frequency = <100000>;
66 pinctrl-0 = <&i2c1_pins>;
67 pinctrl-names = "default";
68 };
69
70 serial@12000 {
71 clock-frequency = <200000000>;
72 status = "okay";
73 };
74
75 pinctrl {
76 sdio_st_pins: sdio-st-pins {
77 marvell,pins = "mpp44", "mpp45";
78 marvell,function = "gpio";
79 };
80 };
81
82 nand: nand@d0000 {
83 pinctrl-0 = <&nand_pins>;
84 pinctrl-names = "default";
85 status = "okay";
86 num-cs = <1>;
87 marvell,nand-keep-config;
88 marvell,nand-enable-arbiter;
89 nand-on-flash-bbt;
90
91 partition@0 {
92 label = "U-Boot";
93 reg = <0 0x800000>;
94 };
95 partition@800000 {
96 label = "Linux";
97 reg = <0x800000 0x800000>;
98 };
99 partition@1000000 {
100 label = "Filesystem";
101 reg = <0x1000000 0x3f000000>;
102 };
103 };
104
105 mvsdio@d4000 {
106 pinctrl-0 = <&sdio_pins &sdio_st_pins>;
107 pinctrl-names = "default";
108 status = "okay";
109 cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
110 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
111 };
112 };
113
114 pcie-controller {
115 status = "okay";
116 /*
117 * The two PCIe units are accessible through
118 * standard PCIe slots on the board.
119 */
120 pcie@1,0 {
121 /* Port 0, Lane 0 */
122 status = "okay";
123 };
124 pcie@2,0 {
125 /* Port 1, Lane 0 */
126 status = "okay";
127 };
128 };
129 };
130};
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
new file mode 100644
index 000000000000..3877693fb2d8
--- /dev/null
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -0,0 +1,464 @@
1/*
2 * Device Tree Include file for Marvell Armada 375 family SoC
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include "skeleton.dtsi"
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/interrupt-controller/irq.h>
17
18#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
19
20/ {
21 model = "Marvell Armada 375 family SoC";
22 compatible = "marvell,armada375";
23
24 aliases {
25 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 gpio2 = &gpio2;
28 };
29
30 clocks {
31 /* 2 GHz fixed main PLL */
32 mainpll: mainpll {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <2000000000>;
36 };
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42 cpu@0 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a9";
45 reg = <0>;
46 };
47 cpu@1 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 reg = <1>;
51 };
52 };
53
54 soc {
55 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
56 #address-cells = <2>;
57 #size-cells = <1>;
58 controller = <&mbusc>;
59 interrupt-parent = <&gic>;
60 pcie-mem-aperture = <0xe0000000 0x8000000>;
61 pcie-io-aperture = <0xe8000000 0x100000>;
62
63 bootrom {
64 compatible = "marvell,bootrom";
65 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
66 };
67
68 devbus-bootcs {
69 compatible = "marvell,mvebu-devbus";
70 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
71 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
72 #address-cells = <1>;
73 #size-cells = <1>;
74 clocks = <&coreclk 0>;
75 status = "disabled";
76 };
77
78 devbus-cs0 {
79 compatible = "marvell,mvebu-devbus";
80 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
81 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
82 #address-cells = <1>;
83 #size-cells = <1>;
84 clocks = <&coreclk 0>;
85 status = "disabled";
86 };
87
88 devbus-cs1 {
89 compatible = "marvell,mvebu-devbus";
90 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
91 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 clocks = <&coreclk 0>;
95 status = "disabled";
96 };
97
98 devbus-cs2 {
99 compatible = "marvell,mvebu-devbus";
100 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
101 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104 clocks = <&coreclk 0>;
105 status = "disabled";
106 };
107
108 devbus-cs3 {
109 compatible = "marvell,mvebu-devbus";
110 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
111 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
112 #address-cells = <1>;
113 #size-cells = <1>;
114 clocks = <&coreclk 0>;
115 status = "disabled";
116 };
117
118 internal-regs {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
123
124 L2: cache-controller@8000 {
125 compatible = "arm,pl310-cache";
126 reg = <0x8000 0x1000>;
127 cache-unified;
128 cache-level = <2>;
129 };
130
131 timer@c600 {
132 compatible = "arm,cortex-a9-twd-timer";
133 reg = <0xc600 0x20>;
134 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
135 clocks = <&coreclk 2>;
136 };
137
138 gic: interrupt-controller@d000 {
139 compatible = "arm,cortex-a9-gic";
140 #interrupt-cells = <3>;
141 #size-cells = <0>;
142 interrupt-controller;
143 reg = <0xd000 0x1000>,
144 <0xc100 0x100>;
145 };
146
147 spi0: spi@10600 {
148 compatible = "marvell,orion-spi";
149 reg = <0x10600 0x50>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 cell-index = <0>;
153 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&coreclk 0>;
155 status = "disabled";
156 };
157
158 spi1: spi@10680 {
159 compatible = "marvell,orion-spi";
160 reg = <0x10680 0x50>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 cell-index = <1>;
164 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&coreclk 0>;
166 status = "disabled";
167 };
168
169 i2c0: i2c@11000 {
170 compatible = "marvell,mv64xxx-i2c";
171 reg = <0x11000 0x20>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
175 timeout-ms = <1000>;
176 clocks = <&coreclk 0>;
177 status = "disabled";
178 };
179
180 i2c1: i2c@11100 {
181 compatible = "marvell,mv64xxx-i2c";
182 reg = <0x11100 0x20>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
186 timeout-ms = <1000>;
187 clocks = <&coreclk 0>;
188 status = "disabled";
189 };
190
191 serial@12000 {
192 compatible = "snps,dw-apb-uart";
193 reg = <0x12000 0x100>;
194 reg-shift = <2>;
195 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
196 reg-io-width = <1>;
197 status = "disabled";
198 };
199
200 serial@12100 {
201 compatible = "snps,dw-apb-uart";
202 reg = <0x12100 0x100>;
203 reg-shift = <2>;
204 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
205 reg-io-width = <1>;
206 status = "disabled";
207 };
208
209 pinctrl {
210 compatible = "marvell,mv88f6720-pinctrl";
211 reg = <0x18000 0x24>;
212
213 i2c0_pins: i2c0-pins {
214 marvell,pins = "mpp14", "mpp15";
215 marvell,function = "i2c0";
216 };
217
218 i2c1_pins: i2c1-pins {
219 marvell,pins = "mpp61", "mpp62";
220 marvell,function = "i2c1";
221 };
222
223 nand_pins: nand-pins {
224 marvell,pins = "mpp0", "mpp1", "mpp2",
225 "mpp3", "mpp4", "mpp5",
226 "mpp6", "mpp7", "mpp8",
227 "mpp9", "mpp10", "mpp11",
228 "mpp12", "mpp13";
229 marvell,function = "nand";
230 };
231
232 sdio_pins: sdio-pins {
233 marvell,pins = "mpp24", "mpp25", "mpp26",
234 "mpp27", "mpp28", "mpp29";
235 marvell,function = "sd";
236 };
237
238 spi0_pins: spi0-pins {
239 marvell,pins = "mpp0", "mpp1", "mpp4",
240 "mpp5", "mpp8", "mpp9";
241 marvell,function = "spi0";
242 };
243 };
244
245 gpio0: gpio@18100 {
246 compatible = "marvell,orion-gpio";
247 reg = <0x18100 0x40>;
248 ngpios = <32>;
249 gpio-controller;
250 #gpio-cells = <2>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
257 };
258
259 gpio1: gpio@18140 {
260 compatible = "marvell,orion-gpio";
261 reg = <0x18140 0x40>;
262 ngpios = <32>;
263 gpio-controller;
264 #gpio-cells = <2>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
267 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
271 };
272
273 gpio2: gpio@18180 {
274 compatible = "marvell,orion-gpio";
275 reg = <0x18180 0x40>;
276 ngpios = <3>;
277 gpio-controller;
278 #gpio-cells = <2>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
282 };
283
284 system-controller@18200 {
285 compatible = "marvell,armada-375-system-controller";
286 reg = <0x18200 0x100>;
287 };
288
289 gateclk: clock-gating-control@18220 {
290 compatible = "marvell,armada-375-gating-clock";
291 reg = <0x18220 0x4>;
292 clocks = <&coreclk 0>;
293 #clock-cells = <1>;
294 };
295
296 mbusc: mbus-controller@20000 {
297 compatible = "marvell,mbus-controller";
298 reg = <0x20000 0x100>, <0x20180 0x20>;
299 };
300
301 mpic: interrupt-controller@20000 {
302 compatible = "marvell,mpic";
303 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
304 #interrupt-cells = <1>;
305 #size-cells = <1>;
306 interrupt-controller;
307 msi-controller;
308 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
309 };
310
311 timer@20300 {
312 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
313 reg = <0x20300 0x30>, <0x21040 0x30>;
314 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
315 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
316 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
317 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
318 <&mpic 5>,
319 <&mpic 6>;
320 clocks = <&coreclk 0>;
321 };
322
323 xor@60800 {
324 compatible = "marvell,orion-xor";
325 reg = <0x60800 0x100
326 0x60A00 0x100>;
327 clocks = <&gateclk 22>;
328 status = "okay";
329
330 xor00 {
331 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
332 dmacap,memcpy;
333 dmacap,xor;
334 };
335 xor01 {
336 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
337 dmacap,memcpy;
338 dmacap,xor;
339 dmacap,memset;
340 };
341 };
342
343 xor@60900 {
344 compatible = "marvell,orion-xor";
345 reg = <0x60900 0x100
346 0x60b00 0x100>;
347 clocks = <&gateclk 23>;
348 status = "okay";
349
350 xor10 {
351 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
352 dmacap,memcpy;
353 dmacap,xor;
354 };
355 xor11 {
356 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
357 dmacap,memcpy;
358 dmacap,xor;
359 dmacap,memset;
360 };
361 };
362
363 sata@a0000 {
364 compatible = "marvell,orion-sata";
365 reg = <0xa0000 0x5000>;
366 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&gateclk 14>, <&gateclk 20>;
368 clock-names = "0", "1";
369 status = "disabled";
370 };
371
372 nand@d0000 {
373 compatible = "marvell,armada370-nand";
374 reg = <0xd0000 0x54>;
375 #address-cells = <1>;
376 #size-cells = <1>;
377 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&gateclk 11>;
379 status = "disabled";
380 };
381
382 mvsdio@d4000 {
383 compatible = "marvell,orion-sdio";
384 reg = <0xd4000 0x200>;
385 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&gateclk 17>;
387 bus-width = <4>;
388 cap-sdio-irq;
389 cap-sd-highspeed;
390 cap-mmc-highspeed;
391 status = "disabled";
392 };
393
394 coreclk: mvebu-sar@e8204 {
395 compatible = "marvell,armada-375-core-clock";
396 reg = <0xe8204 0x04>;
397 #clock-cells = <1>;
398 };
399
400 coredivclk: corediv-clock@e8250 {
401 compatible = "marvell,armada-375-corediv-clock";
402 reg = <0xe8250 0xc>;
403 #clock-cells = <1>;
404 clocks = <&mainpll>;
405 clock-output-names = "nand";
406 };
407 };
408
409 pcie-controller {
410 compatible = "marvell,armada-370-pcie";
411 status = "disabled";
412 device_type = "pci";
413
414 #address-cells = <3>;
415 #size-cells = <2>;
416
417 msi-parent = <&mpic>;
418 bus-range = <0x00 0xff>;
419
420 ranges =
421 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
422 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
423 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
424 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
425 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
426 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
427
428 pcie@1,0 {
429 device_type = "pci";
430 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
431 reg = <0x0800 0 0 0 0>;
432 #address-cells = <3>;
433 #size-cells = <2>;
434 #interrupt-cells = <1>;
435 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
436 0x81000000 0 0 0x81000000 0x1 0 1 0>;
437 interrupt-map-mask = <0 0 0 0>;
438 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
439 marvell,pcie-port = <0>;
440 marvell,pcie-lane = <0>;
441 clocks = <&gateclk 5>;
442 status = "disabled";
443 };
444
445 pcie@2,0 {
446 device_type = "pci";
447 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
448 reg = <0x1000 0 0 0 0>;
449 #address-cells = <3>;
450 #size-cells = <2>;
451 #interrupt-cells = <1>;
452 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
453 0x81000000 0 0 0x81000000 0x2 0 1 0>;
454 interrupt-map-mask = <0 0 0 0>;
455 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
456 marvell,pcie-port = <0>;
457 marvell,pcie-lane = <1>;
458 clocks = <&gateclk 6>;
459 status = "disabled";
460 };
461
462 };
463 };
464};
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
new file mode 100644
index 000000000000..068031f0f263
--- /dev/null
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -0,0 +1,117 @@
1/*
2 * Device Tree Include file for Marvell Armada 380 SoC.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "armada-38x.dtsi"
16
17/ {
18 model = "Marvell Armada 380 family SoC";
19 compatible = "marvell,armada380", "marvell,armada38x";
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a9";
27 reg = <0>;
28 };
29 };
30
31 soc {
32 internal-regs {
33 pinctrl {
34 compatible = "marvell,mv88f6810-pinctrl";
35 reg = <0x18000 0x20>;
36 };
37 };
38
39 pcie-controller {
40 compatible = "marvell,armada-370-pcie";
41 status = "disabled";
42 device_type = "pci";
43
44 #address-cells = <3>;
45 #size-cells = <2>;
46
47 msi-parent = <&mpic>;
48 bus-range = <0x00 0xff>;
49
50 ranges =
51 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
53 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
54 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
55 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
56 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
57 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
58 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
59 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
60 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
61
62 /* x1 port */
63 pcie@1,0 {
64 device_type = "pci";
65 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
66 reg = <0x0800 0 0 0 0>;
67 #address-cells = <3>;
68 #size-cells = <2>;
69 #interrupt-cells = <1>;
70 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
71 0x81000000 0 0 0x81000000 0x1 0 1 0>;
72 interrupt-map-mask = <0 0 0 0>;
73 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
74 marvell,pcie-port = <0>;
75 marvell,pcie-lane = <0>;
76 clocks = <&gateclk 8>;
77 status = "disabled";
78 };
79
80 /* x1 port */
81 pcie@2,0 {
82 device_type = "pci";
83 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
84 reg = <0x1000 0 0 0 0>;
85 #address-cells = <3>;
86 #size-cells = <2>;
87 #interrupt-cells = <1>;
88 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
89 0x81000000 0 0 0x81000000 0x2 0 1 0>;
90 interrupt-map-mask = <0 0 0 0>;
91 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
92 marvell,pcie-port = <1>;
93 marvell,pcie-lane = <0>;
94 clocks = <&gateclk 5>;
95 status = "disabled";
96 };
97
98 /* x1 port */
99 pcie@3,0 {
100 device_type = "pci";
101 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
102 reg = <0x1000 0 0 0 0>;
103 #address-cells = <3>;
104 #size-cells = <2>;
105 #interrupt-cells = <1>;
106 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
107 0x81000000 0 0 0x81000000 0x3 0 1 0>;
108 interrupt-map-mask = <0 0 0 0>;
109 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
110 marvell,pcie-port = <2>;
111 marvell,pcie-lane = <0>;
112 clocks = <&gateclk 6>;
113 status = "disabled";
114 };
115 };
116 };
117};
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
new file mode 100644
index 000000000000..01b6cc76ddc8
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -0,0 +1,101 @@
1/*
2 * Device Tree file for Marvell Armada 385 evaluation board
3 * (DB-88F6820)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14/dts-v1/;
15#include "armada-385.dtsi"
16
17/ {
18 model = "Marvell Armada 385 Development Board";
19 compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x";
20
21 chosen {
22 bootargs = "console=ttyS0,115200 earlyprintk";
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0x00000000 0x10000000>; /* 256 MB */
28 };
29
30 soc {
31 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
32 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
33
34 internal-regs {
35 spi@10600 {
36 status = "okay";
37
38 spi-flash@0 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 compatible = "w25q32";
42 reg = <0>; /* Chip select 0 */
43 spi-max-frequency = <108000000>;
44 };
45 };
46
47 i2c@11000 {
48 status = "okay";
49 clock-frequency = <100000>;
50 };
51
52 i2c@11100 {
53 status = "okay";
54 clock-frequency = <100000>;
55 };
56
57 serial@12000 {
58 clock-frequency = <200000000>;
59 status = "okay";
60 };
61
62 ethernet@30000 {
63 status = "okay";
64 phy = <&phy1>;
65 phy-mode = "rgmii";
66 };
67
68 ethernet@70000 {
69 status = "okay";
70 phy = <&phy0>;
71 phy-mode = "rgmii";
72 };
73
74 mdio {
75 phy0: ethernet-phy@0 {
76 reg = <0>;
77 };
78
79 phy1: ethernet-phy@1 {
80 reg = <1>;
81 };
82 };
83 };
84
85 pcie-controller {
86 status = "okay";
87 /*
88 * The two PCIe units are accessible through
89 * standard PCIe slots on the board.
90 */
91 pcie@1,0 {
92 /* Port 0, Lane 0 */
93 status = "okay";
94 };
95 pcie@2,0 {
96 /* Port 1, Lane 0 */
97 status = "okay";
98 };
99 };
100 };
101};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
new file mode 100644
index 000000000000..e2919f02e1d4
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -0,0 +1,149 @@
1/*
2 * Device Tree Include file for Marvell Armada 385 SoC.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "armada-38x.dtsi"
16
17/ {
18 model = "Marvell Armada 385 family SoC";
19 compatible = "marvell,armada385", "marvell,armada38x";
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a9";
27 reg = <0>;
28 };
29 cpu@1 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 reg = <1>;
33 };
34 };
35
36 soc {
37 internal-regs {
38 pinctrl {
39 compatible = "marvell,mv88f6820-pinctrl";
40 reg = <0x18000 0x20>;
41 };
42 };
43
44 pcie-controller {
45 compatible = "marvell,armada-370-pcie";
46 status = "disabled";
47 device_type = "pci";
48
49 #address-cells = <3>;
50 #size-cells = <2>;
51
52 msi-parent = <&mpic>;
53 bus-range = <0x00 0xff>;
54
55 ranges =
56 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
57 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
58 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
59 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
60 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
61 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
62 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
63 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
64 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
65 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
66 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
67 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
68
69 /*
70 * This port can be either x4 or x1. When
71 * configured in x4 by the bootloader, then
72 * pcie@4,0 is not available.
73 */
74 pcie@1,0 {
75 device_type = "pci";
76 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
77 reg = <0x0800 0 0 0 0>;
78 #address-cells = <3>;
79 #size-cells = <2>;
80 #interrupt-cells = <1>;
81 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
82 0x81000000 0 0 0x81000000 0x1 0 1 0>;
83 interrupt-map-mask = <0 0 0 0>;
84 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
85 marvell,pcie-port = <0>;
86 marvell,pcie-lane = <0>;
87 clocks = <&gateclk 8>;
88 status = "disabled";
89 };
90
91 /* x1 port */
92 pcie@2,0 {
93 device_type = "pci";
94 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
95 reg = <0x1000 0 0 0 0>;
96 #address-cells = <3>;
97 #size-cells = <2>;
98 #interrupt-cells = <1>;
99 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
100 0x81000000 0 0 0x81000000 0x2 0 1 0>;
101 interrupt-map-mask = <0 0 0 0>;
102 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
103 marvell,pcie-port = <1>;
104 marvell,pcie-lane = <0>;
105 clocks = <&gateclk 5>;
106 status = "disabled";
107 };
108
109 /* x1 port */
110 pcie@3,0 {
111 device_type = "pci";
112 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
113 reg = <0x1000 0 0 0 0>;
114 #address-cells = <3>;
115 #size-cells = <2>;
116 #interrupt-cells = <1>;
117 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
118 0x81000000 0 0 0x81000000 0x3 0 1 0>;
119 interrupt-map-mask = <0 0 0 0>;
120 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
121 marvell,pcie-port = <2>;
122 marvell,pcie-lane = <0>;
123 clocks = <&gateclk 6>;
124 status = "disabled";
125 };
126
127 /*
128 * x1 port only available when pcie@1,0 is
129 * configured as a x1 port
130 */
131 pcie@4,0 {
132 device_type = "pci";
133 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
134 reg = <0x1000 0 0 0 0>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
138 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
139 0x81000000 0 0 0x81000000 0x4 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
142 marvell,pcie-port = <3>;
143 marvell,pcie-lane = <0>;
144 clocks = <&gateclk 7>;
145 status = "disabled";
146 };
147 };
148 };
149};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
new file mode 100644
index 000000000000..812ce280b349
--- /dev/null
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -0,0 +1,351 @@
1/*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "skeleton.dtsi"
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
20
21/ {
22 model = "Marvell Armada 38x family SoC";
23 compatible = "marvell,armada38x";
24
25 aliases {
26 gpio0 = &gpio0;
27 gpio1 = &gpio1;
28 eth0 = &eth0;
29 eth1 = &eth1;
30 eth2 = &eth2;
31 };
32
33 soc {
34 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
35 "simple-bus";
36 #address-cells = <2>;
37 #size-cells = <1>;
38 controller = <&mbusc>;
39 interrupt-parent = <&gic>;
40 pcie-mem-aperture = <0xe0000000 0x8000000>;
41 pcie-io-aperture = <0xe8000000 0x100000>;
42
43 bootrom {
44 compatible = "marvell,bootrom";
45 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
46 };
47
48 devbus-bootcs {
49 compatible = "marvell,mvebu-devbus";
50 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
51 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
52 #address-cells = <1>;
53 #size-cells = <1>;
54 clocks = <&coreclk 0>;
55 status = "disabled";
56 };
57
58 devbus-cs0 {
59 compatible = "marvell,mvebu-devbus";
60 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
61 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 clocks = <&coreclk 0>;
65 status = "disabled";
66 };
67
68 devbus-cs1 {
69 compatible = "marvell,mvebu-devbus";
70 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
71 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
72 #address-cells = <1>;
73 #size-cells = <1>;
74 clocks = <&coreclk 0>;
75 status = "disabled";
76 };
77
78 devbus-cs2 {
79 compatible = "marvell,mvebu-devbus";
80 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
81 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
82 #address-cells = <1>;
83 #size-cells = <1>;
84 clocks = <&coreclk 0>;
85 status = "disabled";
86 };
87
88 devbus-cs3 {
89 compatible = "marvell,mvebu-devbus";
90 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
91 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 clocks = <&coreclk 0>;
95 status = "disabled";
96 };
97
98 internal-regs {
99 compatible = "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
103
104 L2: cache-controller@8000 {
105 compatible = "arm,pl310-cache";
106 reg = <0x8000 0x1000>;
107 cache-unified;
108 cache-level = <2>;
109 };
110
111 timer@c600 {
112 compatible = "arm,cortex-a9-twd-timer";
113 reg = <0xc600 0x20>;
114 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
115 clocks = <&coreclk 2>;
116 };
117
118 gic: interrupt-controller@d000 {
119 compatible = "arm,cortex-a9-gic";
120 #interrupt-cells = <3>;
121 #size-cells = <0>;
122 interrupt-controller;
123 reg = <0xd000 0x1000>,
124 <0xc100 0x100>;
125 };
126
127 spi0: spi@10600 {
128 compatible = "marvell,orion-spi";
129 reg = <0x10600 0x50>;
130 #address-cells = <1>;
131 #size-cells = <0>;
132 cell-index = <0>;
133 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&coreclk 0>;
135 status = "disabled";
136 };
137
138 spi1: spi@10680 {
139 compatible = "marvell,orion-spi";
140 reg = <0x10680 0x50>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143 cell-index = <1>;
144 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&coreclk 0>;
146 status = "disabled";
147 };
148
149 i2c0: i2c@11000 {
150 compatible = "marvell,mv64xxx-i2c";
151 reg = <0x11000 0x20>;
152 #address-cells = <1>;
153 #size-cells = <0>;
154 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
155 timeout-ms = <1000>;
156 clocks = <&coreclk 0>;
157 status = "disabled";
158 };
159
160 i2c1: i2c@11100 {
161 compatible = "marvell,mv64xxx-i2c";
162 reg = <0x11100 0x20>;
163 #address-cells = <1>;
164 #size-cells = <0>;
165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
166 timeout-ms = <1000>;
167 clocks = <&coreclk 0>;
168 status = "disabled";
169 };
170
171 serial@12000 {
172 compatible = "snps,dw-apb-uart";
173 reg = <0x12000 0x100>;
174 reg-shift = <2>;
175 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
176 reg-io-width = <1>;
177 status = "disabled";
178 };
179
180 serial@12100 {
181 compatible = "snps,dw-apb-uart";
182 reg = <0x12100 0x100>;
183 reg-shift = <2>;
184 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
185 reg-io-width = <1>;
186 status = "disabled";
187 };
188
189 pinctrl {
190 compatible = "marvell,mv88f6820-pinctrl";
191 reg = <0x18000 0x20>;
192 };
193
194 gpio0: gpio@18100 {
195 compatible = "marvell,orion-gpio";
196 reg = <0x18100 0x40>;
197 ngpios = <32>;
198 gpio-controller;
199 #gpio-cells = <2>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
202 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
206 };
207
208 gpio1: gpio@18140 {
209 compatible = "marvell,orion-gpio";
210 reg = <0x18140 0x40>;
211 ngpios = <28>;
212 gpio-controller;
213 #gpio-cells = <2>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
216 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
220 };
221
222 system-controller@18200 {
223 compatible = "marvell,armada-380-system-controller",
224 "marvell,armada-370-xp-system-controller";
225 reg = <0x18200 0x100>;
226 };
227
228 gateclk: clock-gating-control@18220 {
229 compatible = "marvell,armada-380-gating-clock";
230 reg = <0x18220 0x4>;
231 clocks = <&coreclk 0>;
232 #clock-cells = <1>;
233 };
234
235 coreclk: mvebu-sar@18600 {
236 compatible = "marvell,armada-380-core-clock";
237 reg = <0x18600 0x04>;
238 #clock-cells = <1>;
239 };
240
241 mbusc: mbus-controller@20000 {
242 compatible = "marvell,mbus-controller";
243 reg = <0x20000 0x100>, <0x20180 0x20>;
244 };
245
246 mpic: interrupt-controller@20000 {
247 compatible = "marvell,mpic";
248 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
249 #interrupt-cells = <1>;
250 #size-cells = <1>;
251 interrupt-controller;
252 msi-controller;
253 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
254 };
255
256 timer@20300 {
257 compatible = "marvell,armada-380-timer",
258 "marvell,armada-xp-timer";
259 reg = <0x20300 0x30>, <0x21040 0x30>;
260 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
261 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
262 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
263 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
264 <&mpic 5>,
265 <&mpic 6>;
266 clocks = <&coreclk 2>, <&refclk>;
267 clock-names = "nbclk", "fixed";
268 };
269
270 eth1: ethernet@30000 {
271 compatible = "marvell,armada-370-neta";
272 reg = <0x30000 0x4000>;
273 interrupts-extended = <&mpic 10>;
274 clocks = <&gateclk 3>;
275 status = "disabled";
276 };
277
278 eth2: ethernet@34000 {
279 compatible = "marvell,armada-370-neta";
280 reg = <0x34000 0x4000>;
281 interrupts-extended = <&mpic 12>;
282 clocks = <&gateclk 2>;
283 status = "disabled";
284 };
285
286 xor@60800 {
287 compatible = "marvell,orion-xor";
288 reg = <0x60800 0x100
289 0x60a00 0x100>;
290 clocks = <&gateclk 22>;
291 status = "okay";
292
293 xor00 {
294 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
295 dmacap,memcpy;
296 dmacap,xor;
297 };
298 xor01 {
299 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
300 dmacap,memcpy;
301 dmacap,xor;
302 dmacap,memset;
303 };
304 };
305
306 xor@60900 {
307 compatible = "marvell,orion-xor";
308 reg = <0x60900 0x100
309 0x60b00 0x100>;
310 clocks = <&gateclk 28>;
311 status = "okay";
312
313 xor10 {
314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
315 dmacap,memcpy;
316 dmacap,xor;
317 };
318 xor11 {
319 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
320 dmacap,memcpy;
321 dmacap,xor;
322 dmacap,memset;
323 };
324 };
325
326 eth0: ethernet@70000 {
327 compatible = "marvell,armada-370-neta";
328 reg = <0x70000 0x4000>;
329 interrupts-extended = <&mpic 8>;
330 clocks = <&gateclk 4>;
331 status = "disabled";
332 };
333
334 mdio {
335 #address-cells = <1>;
336 #size-cells = <0>;
337 compatible = "marvell,orion-mdio";
338 reg = <0x72004 0x4>;
339 };
340 };
341 };
342
343 clocks {
344 /* 25 MHz reference crystal */
345 refclk: oscillator {
346 compatible = "fixed-clock";
347 #clock-cells = <0>;
348 clock-frequency = <25000000>;
349 };
350 };
351};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 14:55:38 -0400