aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorYoshinori Sato <ysato@users.sourceforge.jp>2006-11-05 02:18:08 -0500
committerPaul Mundt <lethal@linux-sh.org>2006-12-05 20:45:36 -0500
commitb229632abd451ab2c797010b9788e48c9314db4f (patch)
treebe097331d66985376057ff3ffbab742d60ac55ed
parentde39840646a223ae13a346048c280b7c871bf56e (diff)
sh: Add SH-2A platform headers.
Mostly SH-2 wrappers.. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat
-rw-r--r--include/asm-sh/bugs.h6
-rw-r--r--include/asm-sh/cpu-sh2/cache.h22
-rw-r--r--include/asm-sh/cpu-sh2/freq.h18
-rw-r--r--include/asm-sh/cpu-sh2/irq.h84
-rw-r--r--include/asm-sh/cpu-sh2/mmu_context.h16
-rw-r--r--include/asm-sh/cpu-sh2a/addrspace.h1
-rw-r--r--include/asm-sh/cpu-sh2a/cache.h39
-rw-r--r--include/asm-sh/cpu-sh2a/cacheflush.h1
-rw-r--r--include/asm-sh/cpu-sh2a/dma.h1
-rw-r--r--include/asm-sh/cpu-sh2a/freq.h18
-rw-r--r--include/asm-sh/cpu-sh2a/irq.h75
-rw-r--r--include/asm-sh/cpu-sh2a/mmu_context.h1
-rw-r--r--include/asm-sh/cpu-sh2a/timer.h1
-rw-r--r--include/asm-sh/cpu-sh2a/ubc.h1
-rw-r--r--include/asm-sh/cpu-sh2a/watchdog.h1
-rw-r--r--include/asm-sh/entry-macros.S32
-rw-r--r--include/asm-sh/irq.h70
-rw-r--r--include/asm-sh/processor.h5
-rw-r--r--include/asm-sh/unistd.h32
19 files changed, 415 insertions, 9 deletions
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index beeea40f549e..51cc9e38d16a 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -23,9 +23,13 @@ static void __init check_bugs(void)
23 cpu_data->loops_per_jiffy = loops_per_jiffy; 23 cpu_data->loops_per_jiffy = loops_per_jiffy;
24 24
25 switch (cpu_data->type) { 25 switch (cpu_data->type) {
26 case CPU_SH7604: 26 case CPU_SH7604 ... CPU_SH7619:
27 *p++ = '2'; 27 *p++ = '2';
28 break; 28 break;
29 case CPU_SH7206:
30 *p++ = '2';
31 *p++ = 'a';
32 break;
29 case CPU_SH7705 ... CPU_SH7300: 33 case CPU_SH7705 ... CPU_SH7300:
30 *p++ = '3'; 34 *p++ = '3';
31 break; 35 break;
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index cd96402e8562..20b9796842dc 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -12,6 +12,7 @@
12 12
13#define L1_CACHE_SHIFT 4 13#define L1_CACHE_SHIFT 4
14 14
15#if defined(CONFIG_CPU_SUBTYPE_SH7604)
15#define CCR 0xfffffe92 /* Address of Cache Control Register */ 16#define CCR 0xfffffe92 /* Address of Cache Control Register */
16 17
17#define CCR_CACHE_CE 0x01 /* Cache enable */ 18#define CCR_CACHE_CE 0x01 /* Cache enable */
@@ -27,5 +28,26 @@
27#define CCR_CACHE_ORA CCR_CACHE_TW 28#define CCR_CACHE_ORA CCR_CACHE_TW
28#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */ 29#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
29 30
31#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
32#define CCR1 0xffffffec
33#define CCR CCR1
34
35#define CCR_CACHE_CE 0x01 /* Cache enable */
36#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
37 /* 0x00000000-0x7fffffff: Write-through */
38 /* 0x80000000-0x9fffffff: Write-back */
39 /* 0xc0000000-0xdfffffff: Write-through */
40#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */
41 /* 0x00000000-0x7fffffff: Write-back */
42 /* 0x80000000-0x9fffffff: Write-through */
43 /* 0xc0000000-0xdfffffff: Write-back */
44#define CCR_CACHE_CF 0x08 /* Cache invalidate */
45
46#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
47#define CACHE_OC_DATA_ARRAY 0xf1000000
48
49#define CCR_CACHE_ENABLE CCR_CACHE_CE
50#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
51#endif
30#endif /* __ASM_CPU_SH2_CACHE_H */ 52#endif /* __ASM_CPU_SH2_CACHE_H */
31 53
diff --git a/include/asm-sh/cpu-sh2/freq.h b/include/asm-sh/cpu-sh2/freq.h
new file mode 100644
index 000000000000..31de475da70b
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/freq.h
@@ -0,0 +1,18 @@
1/*
2 * include/asm-sh/cpu-sh2/freq.h
3 *
4 * Copyright (C) 2006 Yoshinori Sato
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_FREQ_H
11#define __ASM_CPU_SH2_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7619)
14#define FREQCR 0xf815ff80
15#endif
16
17#endif /* __ASM_CPU_SH2_FREQ_H */
18
diff --git a/include/asm-sh/cpu-sh2/irq.h b/include/asm-sh/cpu-sh2/irq.h
new file mode 100644
index 000000000000..4032a14d0f41
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/irq.h
@@ -0,0 +1,84 @@
1#ifndef __ASM_SH_CPU_SH2_IRQ_H
2#define __ASM_SH_CPU_SH2_IRQ_H
3
4/*
5 *
6 * linux/include/asm-sh/cpu-sh2/irq.h
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
11 *
12 */
13
14#include <linux/config.h>
15
16#if defined(CONFIG_CPU_SUBTYPE_SH7044)
17#define INTC_IPRA 0xffff8348UL
18#define INTC_IPRB 0xffff834aUL
19#define INTC_IPRC 0xffff834cUL
20#define INTC_IPRD 0xffff834eUL
21#define INTC_IPRE 0xffff8350UL
22#define INTC_IPRF 0xffff8352UL
23#define INTC_IPRG 0xffff8354UL
24#define INTC_IPRH 0xffff8356UL
25
26#define INTC_ICR 0xffff8358UL
27#define INTC_ISR 0xffff835aUL
28#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
29#define INTC_IPRA 0xfffffee2UL
30#define INTC_IPRB 0xfffffe60UL
31
32#define INTC_VCRA 0xfffffe62UL
33#define INTC_VCRB 0xfffffe64UL
34#define INTC_VCRC 0xfffffe66UL
35#define INTC_VCRD 0xfffffe68UL
36
37#define INTC_VCRWDT 0xfffffee4UL
38#define INTC_VCRDIV 0xffffff0cUL
39#define INTC_VCRDMA0 0xffffffa0UL
40#define INTC_VCRDMA1 0xffffffa8UL
41
42#define INTC_ICR 0xfffffee0UL
43#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
44#define INTC_IPRA 0xf8140006UL
45#define INTC_IPRB 0xf8140008UL
46#define INTC_IPRC 0xf8080000UL
47#define INTC_IPRD 0xf8080002UL
48#define INTC_IPRE 0xf8080004UL
49#define INTC_IPRF 0xf8080006UL
50#define INTC_IPRG 0xf8080008UL
51
52#define INTC_ICR0 0xf8140000UL
53#define INTC_IRQCR 0xf8140002UL
54#define INTC_IRQSR 0xf8140004UL
55
56#define CMI0_IRQ 86
57#define CMI1_IRQ 87
58
59#define SCIF_ERI_IRQ 88
60#define SCIF_RXI_IRQ 89
61#define SCIF_BRI_IRQ 90
62#define SCIF_TXI_IRQ 91
63#define SCIF_IPR_ADDR INTC_IPRD
64#define SCIF_IPR_POS 3
65#define SCIF_PRIORITY 3
66
67#define SCIF1_ERI_IRQ 92
68#define SCIF1_RXI_IRQ 93
69#define SCIF1_BRI_IRQ 94
70#define SCIF1_TXI_IRQ 95
71#define SCIF1_IPR_ADDR INTC_IPRD
72#define SCIF1_IPR_POS 2
73#define SCIF1_PRIORITY 3
74
75#define SCIF2_BRI_IRQ 96
76#define SCIF2_RXI_IRQ 97
77#define SCIF2_ERI_IRQ 98
78#define SCIF2_TXI_IRQ 99
79#define SCIF2_IPR_ADDR INTC_IPRD
80#define SCIF2_IPR_POS 1
81#define SCIF2_PRIORITY 3
82#endif
83
84#endif /* __ASM_SH_CPU_SH2_IRQ_H */
diff --git a/include/asm-sh/cpu-sh2/mmu_context.h b/include/asm-sh/cpu-sh2/mmu_context.h
new file mode 100644
index 000000000000..beeb299e01ec
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/mmu_context.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-sh/cpu-sh2/mmu_context.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
11#define __ASM_CPU_SH2_MMU_CONTEXT_H
12
13/* No MMU */
14
15#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
16
diff --git a/include/asm-sh/cpu-sh2a/addrspace.h b/include/asm-sh/cpu-sh2a/addrspace.h
new file mode 100644
index 000000000000..3d2e9aa21522
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/addrspace.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/addrspace.h>
diff --git a/include/asm-sh/cpu-sh2a/cache.h b/include/asm-sh/cpu-sh2a/cache.h
new file mode 100644
index 000000000000..3e4b9e480982
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/cache.h
@@ -0,0 +1,39 @@
1/*
2 * include/asm-sh/cpu-sh2a/cache.h
3 *
4 * Copyright (C) 2004 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2A_CACHE_H
11#define __ASM_CPU_SH2A_CACHE_H
12
13#define L1_CACHE_SHIFT 4
14
15#define CCR1 0xfffc1000
16#define CCR2 0xfffc1004
17
18/* CCR1 behaves more like the traditional CCR */
19#define CCR CCR1
20
21/*
22 * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
23 * listed here are reserved.
24 */
25#define CCR_CACHE_CB 0x0000 /* Hack */
26#define CCR_CACHE_OCE 0x0001
27#define CCR_CACHE_WT 0x0002
28#define CCR_CACHE_OCI 0x0008 /* OCF */
29#define CCR_CACHE_ICE 0x0100
30#define CCR_CACHE_ICI 0x0800 /* ICF */
31
32#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
33#define CACHE_OC_ADDRESS_ARRAY 0xf0800000
34
35#define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE)
36#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI)
37
38#endif /* __ASM_CPU_SH2A_CACHE_H */
39
diff --git a/include/asm-sh/cpu-sh2a/cacheflush.h b/include/asm-sh/cpu-sh2a/cacheflush.h
new file mode 100644
index 000000000000..fa3186c73350
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/cacheflush.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/cacheflush.h>
diff --git a/include/asm-sh/cpu-sh2a/dma.h b/include/asm-sh/cpu-sh2a/dma.h
new file mode 100644
index 000000000000..0d5ad85c1de8
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/dma.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/dma.h>
diff --git a/include/asm-sh/cpu-sh2a/freq.h b/include/asm-sh/cpu-sh2a/freq.h
new file mode 100644
index 000000000000..e518fff6d10f
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/freq.h
@@ -0,0 +1,18 @@
1/*
2 * include/asm-sh/cpu-sh2a/freq.h
3 *
4 * Copyright (C) 2006 Yoshinori Sato
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2A_FREQ_H
11#define __ASM_CPU_SH2A_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7206)
14#define FREQCR 0xfffe0010
15#endif
16
17#endif /* __ASM_CPU_SH2A_FREQ_H */
18
diff --git a/include/asm-sh/cpu-sh2a/irq.h b/include/asm-sh/cpu-sh2a/irq.h
new file mode 100644
index 000000000000..d3d42f64148c
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/irq.h
@@ -0,0 +1,75 @@
1#ifndef __ASM_SH_CPU_SH2A_IRQ_H
2#define __ASM_SH_CPU_SH2A_IRQ_H
3
4#define INTC_IPR01 0xfffe0818UL
5#define INTC_IPR02 0xfffe081aUL
6#define INTC_IPR05 0xfffe0820UL
7#define INTC_IPR06 0xfffe0c00UL
8#define INTC_IPR07 0xfffe0c02UL
9#define INTC_IPR08 0xfffe0c04UL
10#define INTC_IPR09 0xfffe0c06UL
11#define INTC_IPR10 0xfffe0c08UL
12#define INTC_IPR11 0xfffe0c0aUL
13#define INTC_IPR12 0xfffe0c0cUL
14#define INTC_IPR13 0xfffe0c0eUL
15#define INTC_IPR14 0xfffe0c10UL
16
17#define INTC_ICR0 0xfffe0800UL
18#define INTC_ICR1 0xfffe0802UL
19#define INTC_ICR2 0xfffe0804UL
20#define INTC_ISR 0xfffe0806UL
21
22#define IRQ0_IRQ 64
23#define IRQ1_IRQ 65
24#define IRQ2_IRQ 66
25#define IRQ3_IRQ 67
26#define IRQ4_IRQ 68
27#define IRQ5_IRQ 69
28#define IRQ6_IRQ 70
29#define IRQ7_IRQ 71
30
31#define PINT0_IRQ 80
32#define PINT1_IRQ 81
33#define PINT2_IRQ 82
34#define PINT3_IRQ 83
35#define PINT4_IRQ 84
36#define PINT5_IRQ 85
37#define PINT6_IRQ 86
38#define PINT7_IRQ 87
39
40#define CMI0_IRQ 140
41#define CMI1_IRQ 141
42
43#define SCIF_BRI_IRQ 240
44#define SCIF_ERI_IRQ 241
45#define SCIF_RXI_IRQ 242
46#define SCIF_TXI_IRQ 243
47#define SCIF_IPR_ADDR INTC_IPR14
48#define SCIF_IPR_POS 3
49#define SCIF_PRIORITY 3
50
51#define SCIF1_BRI_IRQ 244
52#define SCIF1_ERI_IRQ 245
53#define SCIF1_RXI_IRQ 246
54#define SCIF1_TXI_IRQ 247
55#define SCIF1_IPR_ADDR INTC_IPR14
56#define SCIF1_IPR_POS 2
57#define SCIF1_PRIORITY 3
58
59#define SCIF2_BRI_IRQ 248
60#define SCIF2_ERI_IRQ 249
61#define SCIF2_RXI_IRQ 250
62#define SCIF2_TXI_IRQ 251
63#define SCIF2_IPR_ADDR INTC_IPR14
64#define SCIF2_IPR_POS 1
65#define SCIF2_PRIORITY 3
66
67#define SCIF3_BRI_IRQ 252
68#define SCIF3_ERI_IRQ 253
69#define SCIF3_RXI_IRQ 254
70#define SCIF3_TXI_IRQ 255
71#define SCIF3_IPR_ADDR INTC_IPR14
72#define SCIF3_IPR_POS 0
73#define SCIF3_PRIORITY 3
74
75#endif /* __ASM_SH_CPU_SH2A_IRQ_H */
diff --git a/include/asm-sh/cpu-sh2a/mmu_context.h b/include/asm-sh/cpu-sh2a/mmu_context.h
new file mode 100644
index 000000000000..cd2387f7db9e
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/mmu_context.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/mmu_context.h>
diff --git a/include/asm-sh/cpu-sh2a/timer.h b/include/asm-sh/cpu-sh2a/timer.h
new file mode 100644
index 000000000000..fee504adf11e
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/timer.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/timer.h>
diff --git a/include/asm-sh/cpu-sh2a/ubc.h b/include/asm-sh/cpu-sh2a/ubc.h
new file mode 100644
index 000000000000..cf28062b96a2
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/ubc.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/ubc.h>
diff --git a/include/asm-sh/cpu-sh2a/watchdog.h b/include/asm-sh/cpu-sh2a/watchdog.h
new file mode 100644
index 000000000000..c1b3e2488478
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/watchdog.h
@@ -0,0 +1 @@
#include <asm/cpu-sh2/watchdog.h>
diff --git a/include/asm-sh/entry-macros.S b/include/asm-sh/entry-macros.S
new file mode 100644
index 000000000000..099fe8189bbe
--- /dev/null
+++ b/include/asm-sh/entry-macros.S
@@ -0,0 +1,32 @@
1! entry.S macro define
2
3 .macro cli
4 stc sr, r0
5 or #0xf0, r0
6 ldc r0, sr
7 .endm
8
9 .macro sti
10 mov #0xf0, r11
11 extu.b r11, r11
12 not r11, r11
13 stc sr, r10
14 and r11, r10
15#ifdef CONFIG_HAS_SR_RB
16 stc k_g_imask, r11
17 or r11, r10
18#endif
19 ldc r10, sr
20 .endm
21
22 .macro get_current_thread_info, ti, tmp
23#ifdef CONFIG_HAS_SR_RB
24 stc r7_bank, \ti
25#else
26 mov #((THREAD_SIZE - 1)>> 8) ^ 0xff, \tmp
27 shll8 \tmp
28 mov r15, \ti
29 and \tmp, \ti
30#endif
31 .endm
32
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 6cd3e9e2a76a..d71326b3c90c 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -14,6 +14,10 @@
14#include <asm/machvec.h> 14#include <asm/machvec.h>
15#include <asm/ptrace.h> /* for pt_regs */ 15#include <asm/ptrace.h> /* for pt_regs */
16 16
17#if defined(CONFIG_CPU_SH2)
18#include <asm/cpu/irq.h>
19#endif
20
17#ifndef CONFIG_CPU_SUBTYPE_SH7780 21#ifndef CONFIG_CPU_SUBTYPE_SH7780
18 22
19#define INTC_DMAC0_MSK 0 23#define INTC_DMAC0_MSK 0
@@ -28,6 +32,31 @@
28#define INTC_IPRD 0xffd00010UL 32#define INTC_IPRD 0xffd00010UL
29#endif 33#endif
30 34
35#if defined(CONFIG_CPU_SUBTYPE_SH7206)
36#ifdef CONFIG_SH_CMT
37#define TIMER_IRQ CMI0_IRQ
38#define TIMER_IPR_ADDR INTC_IPR08
39#define TIMER_IPR_POS 3
40#define TIMER_PRIORITY 2
41
42#define TIMER1_IRQ CMI1_IRQ
43#define TIMER1_IPR_ADDR INTC_IPR08
44#define TIMER1_IPR_POS 2
45#define TIMER1_PRIORITY 2
46#endif
47
48#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
49#define TIMER_IRQ CMI0_IRQ
50#define TIMER_IPR_ADDR INTC_IPRC
51#define TIMER_IPR_POS 1
52#define TIMER_PRIORITY 2
53
54#define TIMER1_IRQ CMI1_IRQ
55#define TIMER1_IPR_ADDR INTC_IPRC
56#define TIMER1_IPR_POS 0
57#define TIMER1_PRIORITY 4
58
59#else
31#define TIMER_IRQ 16 60#define TIMER_IRQ 16
32#define TIMER_IPR_ADDR INTC_IPRA 61#define TIMER_IPR_ADDR INTC_IPRA
33#define TIMER_IPR_POS 3 62#define TIMER_IPR_POS 3
@@ -37,11 +66,14 @@
37#define TIMER1_IPR_ADDR INTC_IPRA 66#define TIMER1_IPR_ADDR INTC_IPRA
38#define TIMER1_IPR_POS 2 67#define TIMER1_IPR_POS 2
39#define TIMER1_PRIORITY 4 68#define TIMER1_PRIORITY 4
69#endif
40 70
71#if !defined(CONFIG_CPU_SH2)
41#define RTC_IRQ 22 72#define RTC_IRQ 22
42#define RTC_IPR_ADDR INTC_IPRA 73#define RTC_IPR_ADDR INTC_IPRA
43#define RTC_IPR_POS 0 74#define RTC_IPR_POS 0
44#define RTC_PRIORITY TIMER_PRIORITY 75#define RTC_PRIORITY TIMER_PRIORITY
76#endif
45 77
46#if defined(CONFIG_CPU_SH3) 78#if defined(CONFIG_CPU_SH3)
47#define DMTE0_IRQ 48 79#define DMTE0_IRQ 48
@@ -265,6 +297,10 @@
265# define ONCHIP_NR_IRQS 109 297# define ONCHIP_NR_IRQS 109
266#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 298#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
267# define ONCHIP_NR_IRQS 111 299# define ONCHIP_NR_IRQS 111
300#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
301# define ONCHIP_NR_IRQS 256
302#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
303# define ONCHIP_NR_IRQS 128
268#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */ 304#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
269# define ONCHIP_NR_IRQS 144 305# define ONCHIP_NR_IRQS 144
270#endif 306#endif
@@ -322,6 +358,40 @@ extern void enable_irq(unsigned int);
322extern void make_maskreg_irq(unsigned int irq); 358extern void make_maskreg_irq(unsigned int irq);
323extern unsigned short *irq_mask_register; 359extern unsigned short *irq_mask_register;
324 360
361#if defined(CONFIG_CPU_SUBTYPE_SH7619)
362#define IRQ0_IRQ 16
363#define IRQ1_IRQ 17
364#define IRQ2_IRQ 18
365#define IRQ3_IRQ 19
366#define IRQ4_IRQ 32
367#define IRQ5_IRQ 33
368#define IRQ6_IRQ 34
369#define IRQ7_IRQ 35
370#elif !defined(CONFIG_CPU_SUBTYPE_SH7206)
371#define IRQ0_IRQ 32
372#define IRQ1_IRQ 33
373#define IRQ2_IRQ 34
374#define IRQ3_IRQ 35
375#define IRQ4_IRQ 36
376#define IRQ5_IRQ 37
377#endif
378
379#define IRQ0_PRIORITY 1
380#define IRQ1_PRIORITY 1
381#define IRQ2_PRIORITY 1
382#define IRQ3_PRIORITY 1
383#define IRQ4_PRIORITY 1
384#define IRQ5_PRIORITY 1
385
386#ifndef IRQ0_IPR_POS
387#define IRQ0_IPR_POS 0
388#define IRQ1_IPR_POS 1
389#define IRQ2_IPR_POS 2
390#define IRQ3_IPR_POS 3
391#define IRQ4_IPR_POS 0
392#define IRQ5_IPR_POS 1
393#endif
394
325/* 395/*
326 * PINT IRQs 396 * PINT IRQs
327 */ 397 */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 45bb74e35d32..29a56c505ae5 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -36,7 +36,10 @@
36 */ 36 */
37enum cpu_type { 37enum cpu_type {
38 /* SH-2 types */ 38 /* SH-2 types */
39 CPU_SH7604, 39 CPU_SH7604, CPU_SH7619,
40
41 /* SH-2A types */
42 CPU_SH7206,
40 43
41 /* SH-3 types */ 44 /* SH-3 types */
42 CPU_SH7705, CPU_SH7706, CPU_SH7707, 45 CPU_SH7705, CPU_SH7706, CPU_SH7707,
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
index 1c2abde122cd..0cae1d248761 100644
--- a/include/asm-sh/unistd.h
+++ b/include/asm-sh/unistd.h
@@ -349,12 +349,30 @@ do { \
349 return (type) (res); \ 349 return (type) (res); \
350} while (0) 350} while (0)
351 351
352#if defined(__sh2__) || defined(__SH2E__) || defined(__SH2A__)
353#define SYSCALL_ARG0 "trapa #0x20"
354#define SYSCALL_ARG1 "trapa #0x21"
355#define SYSCALL_ARG2 "trapa #0x22"
356#define SYSCALL_ARG3 "trapa #0x23"
357#define SYSCALL_ARG4 "trapa #0x24"
358#define SYSCALL_ARG5 "trapa #0x25"
359#define SYSCALL_ARG6 "trapa #0x26"
360#else
361#define SYSCALL_ARG0 "trapa #0x10"
362#define SYSCALL_ARG1 "trapa #0x11"
363#define SYSCALL_ARG2 "trapa #0x12"
364#define SYSCALL_ARG3 "trapa #0x13"
365#define SYSCALL_ARG4 "trapa #0x14"
366#define SYSCALL_ARG5 "trapa #0x15"
367#define SYSCALL_ARG6 "trapa #0x16"
368#endif
369
352/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ 370/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
353#define _syscall0(type,name) \ 371#define _syscall0(type,name) \
354type name(void) \ 372type name(void) \
355{ \ 373{ \
356register long __sc0 __asm__ ("r3") = __NR_##name; \ 374register long __sc0 __asm__ ("r3") = __NR_##name; \
357__asm__ __volatile__ ("trapa #0x10" \ 375__asm__ __volatile__ (SYSCALL_ARG0 \
358 : "=z" (__sc0) \ 376 : "=z" (__sc0) \
359 : "0" (__sc0) \ 377 : "0" (__sc0) \
360 : "memory" ); \ 378 : "memory" ); \
@@ -366,7 +384,7 @@ type name(type1 arg1) \
366{ \ 384{ \
367register long __sc0 __asm__ ("r3") = __NR_##name; \ 385register long __sc0 __asm__ ("r3") = __NR_##name; \
368register long __sc4 __asm__ ("r4") = (long) arg1; \ 386register long __sc4 __asm__ ("r4") = (long) arg1; \
369__asm__ __volatile__ ("trapa #0x11" \ 387__asm__ __volatile__ (SYSCALL_ARG1 \
370 : "=z" (__sc0) \ 388 : "=z" (__sc0) \
371 : "0" (__sc0), "r" (__sc4) \ 389 : "0" (__sc0), "r" (__sc4) \
372 : "memory"); \ 390 : "memory"); \
@@ -379,7 +397,7 @@ type name(type1 arg1,type2 arg2) \
379register long __sc0 __asm__ ("r3") = __NR_##name; \ 397register long __sc0 __asm__ ("r3") = __NR_##name; \
380register long __sc4 __asm__ ("r4") = (long) arg1; \ 398register long __sc4 __asm__ ("r4") = (long) arg1; \
381register long __sc5 __asm__ ("r5") = (long) arg2; \ 399register long __sc5 __asm__ ("r5") = (long) arg2; \
382__asm__ __volatile__ ("trapa #0x12" \ 400__asm__ __volatile__ (SYSCALL_ARG2 \
383 : "=z" (__sc0) \ 401 : "=z" (__sc0) \
384 : "0" (__sc0), "r" (__sc4), "r" (__sc5) \ 402 : "0" (__sc0), "r" (__sc4), "r" (__sc5) \
385 : "memory"); \ 403 : "memory"); \
@@ -393,7 +411,7 @@ register long __sc0 __asm__ ("r3") = __NR_##name; \
393register long __sc4 __asm__ ("r4") = (long) arg1; \ 411register long __sc4 __asm__ ("r4") = (long) arg1; \
394register long __sc5 __asm__ ("r5") = (long) arg2; \ 412register long __sc5 __asm__ ("r5") = (long) arg2; \
395register long __sc6 __asm__ ("r6") = (long) arg3; \ 413register long __sc6 __asm__ ("r6") = (long) arg3; \
396__asm__ __volatile__ ("trapa #0x13" \ 414__asm__ __volatile__ (SYSCALL_ARG3 \
397 : "=z" (__sc0) \ 415 : "=z" (__sc0) \
398 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \ 416 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \
399 : "memory"); \ 417 : "memory"); \
@@ -408,7 +426,7 @@ register long __sc4 __asm__ ("r4") = (long) arg1; \
408register long __sc5 __asm__ ("r5") = (long) arg2; \ 426register long __sc5 __asm__ ("r5") = (long) arg2; \
409register long __sc6 __asm__ ("r6") = (long) arg3; \ 427register long __sc6 __asm__ ("r6") = (long) arg3; \
410register long __sc7 __asm__ ("r7") = (long) arg4; \ 428register long __sc7 __asm__ ("r7") = (long) arg4; \
411__asm__ __volatile__ ("trapa #0x14" \ 429__asm__ __volatile__ (SYSCALL_ARG4 \
412 : "=z" (__sc0) \ 430 : "=z" (__sc0) \
413 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), \ 431 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), \
414 "r" (__sc7) \ 432 "r" (__sc7) \
@@ -425,7 +443,7 @@ register long __sc5 __asm__ ("r5") = (long) arg2; \
425register long __sc6 __asm__ ("r6") = (long) arg3; \ 443register long __sc6 __asm__ ("r6") = (long) arg3; \
426register long __sc7 __asm__ ("r7") = (long) arg4; \ 444register long __sc7 __asm__ ("r7") = (long) arg4; \
427register long __sc0 __asm__ ("r0") = (long) arg5; \ 445register long __sc0 __asm__ ("r0") = (long) arg5; \
428__asm__ __volatile__ ("trapa #0x15" \ 446__asm__ __volatile__ (SYSCALL_ARG5 \
429 : "=z" (__sc0) \ 447 : "=z" (__sc0) \
430 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \ 448 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
431 "r" (__sc3) \ 449 "r" (__sc3) \
@@ -443,7 +461,7 @@ register long __sc6 __asm__ ("r6") = (long) arg3; \
443register long __sc7 __asm__ ("r7") = (long) arg4; \ 461register long __sc7 __asm__ ("r7") = (long) arg4; \
444register long __sc0 __asm__ ("r0") = (long) arg5; \ 462register long __sc0 __asm__ ("r0") = (long) arg5; \
445register long __sc1 __asm__ ("r1") = (long) arg6; \ 463register long __sc1 __asm__ ("r1") = (long) arg6; \
446__asm__ __volatile__ ("trapa #0x16" \ 464__asm__ __volatile__ (SYSCALL_ARG6 \
447 : "=z" (__sc0) \ 465 : "=z" (__sc0) \
448 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \ 466 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
449 "r" (__sc3), "r" (__sc1) \ 467 "r" (__sc3), "r" (__sc1) \
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 23:10:31 -0400