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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2013-04-12 10:29:07 -0400
committerJason Cooper <jason@lakedaemon.net>2013-04-15 11:00:17 -0400
commitb18ea4dc7746f1270bbe3a0817f9a034eec031a8 (patch)
treed7043bd99e911ad6bfd84eebabe5a85d27f09fe7
parent1b2529d018b7f8e3faa0011a49116d4df9e44777 (diff)
ARM: dts: mvebu: move all peripherals inside soc
reorganize the .dts and .dtsi files so that all devices are under the soc { } node (currently some devices such as the interrupt controller, the L2 cache and a few others are outside). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi26
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi23
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi32
3 files changed, 41 insertions, 40 deletions
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 9693f796bcfe..972448c4880c 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -28,19 +28,6 @@
28 }; 28 };
29 }; 29 };
30 30
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
34 #size-cells = <1>;
35 interrupt-controller;
36 };
37
38 coherency-fabric@d0020200 {
39 compatible = "marvell,coherency-fabric";
40 reg = <0xd0020200 0xb0>,
41 <0xd0021810 0x1c>;
42 };
43
44 soc { 31 soc {
45 #address-cells = <1>; 32 #address-cells = <1>;
46 #size-cells = <1>; 33 #size-cells = <1>;
@@ -48,6 +35,19 @@
48 interrupt-parent = <&mpic>; 35 interrupt-parent = <&mpic>;
49 ranges; 36 ranges;
50 37
38 mpic: interrupt-controller@d0020000 {
39 compatible = "marvell,mpic";
40 #interrupt-cells = <1>;
41 #size-cells = <1>;
42 interrupt-controller;
43 };
44
45 coherency-fabric@d0020200 {
46 compatible = "marvell,coherency-fabric";
47 reg = <0xd0020200 0xb0>,
48 <0xd0021810 0x1c>;
49 };
50
51 serial@d0012000 { 51 serial@d0012000 {
52 compatible = "snps,dw-apb-uart"; 52 compatible = "snps,dw-apb-uart";
53 reg = <0xd0012000 0x100>; 53 reg = <0xd0012000 0x100>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 18f6eb47cc50..209caeb748fa 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -20,12 +20,6 @@
20/ { 20/ {
21 model = "Marvell Armada 370 family SoC"; 21 model = "Marvell Armada 370 family SoC";
22 compatible = "marvell,armada370", "marvell,armada-370-xp"; 22 compatible = "marvell,armada370", "marvell,armada-370-xp";
23 L2: l2-cache {
24 compatible = "marvell,aurora-outer-cache";
25 reg = <0xd0008000 0x1000>;
26 cache-id-part = <0x100>;
27 wt-override;
28 };
29 23
30 aliases { 24 aliases {
31 gpio0 = &gpio0; 25 gpio0 = &gpio0;
@@ -33,17 +27,24 @@
33 gpio2 = &gpio2; 27 gpio2 = &gpio2;
34 }; 28 };
35 29
36 mpic: interrupt-controller@d0020000 {
37 reg = <0xd0020a00 0x1d0>,
38 <0xd0021870 0x58>;
39 };
40
41 soc { 30 soc {
31 mpic: interrupt-controller@d0020000 {
32 reg = <0xd0020a00 0x1d0>,
33 <0xd0021870 0x58>;
34 };
35
42 system-controller@d0018200 { 36 system-controller@d0018200 {
43 compatible = "marvell,armada-370-xp-system-controller"; 37 compatible = "marvell,armada-370-xp-system-controller";
44 reg = <0xd0018200 0x100>; 38 reg = <0xd0018200 0x100>;
45 }; 39 };
46 40
41 L2: l2-cache {
42 compatible = "marvell,aurora-outer-cache";
43 reg = <0xd0008000 0x1000>;
44 cache-id-part = <0x100>;
45 wt-override;
46 };
47
47 pinctrl { 48 pinctrl {
48 compatible = "marvell,mv88f6710-pinctrl"; 49 compatible = "marvell,mv88f6710-pinctrl";
49 reg = <0xd0018000 0x38>; 50 reg = <0xd0018000 0x38>;
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 29dfeb6d4a26..ef3d41362241 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,25 +22,25 @@
22 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24 24
25 L2: l2-cache { 25 soc {
26 compatible = "marvell,aurora-system-cache"; 26 L2: l2-cache {
27 reg = <0xd0008000 0x1000>; 27 compatible = "marvell,aurora-system-cache";
28 cache-id-part = <0x100>; 28 reg = <0xd0008000 0x1000>;
29 wt-override; 29 cache-id-part = <0x100>;
30 }; 30 wt-override;
31 };
31 32
32 mpic: interrupt-controller@d0020000 { 33 mpic: interrupt-controller@d0020000 {
33 reg = <0xd0020a00 0x2d0>, 34 reg = <0xd0020a00 0x2d0>,
34 <0xd0021070 0x58>; 35 <0xd0021070 0x58>;
35 }; 36 };
36 37
37 armada-370-xp-pmsu@d0022000 { 38 armada-370-xp-pmsu@d0022000 {
38 compatible = "marvell,armada-370-xp-pmsu"; 39 compatible = "marvell,armada-370-xp-pmsu";
39 reg = <0xd0022100 0x430>, 40 reg = <0xd0022100 0x430>,
40 <0xd0020800 0x20>; 41 <0xd0020800 0x20>;
41 }; 42 };
42 43
43 soc {
44 serial@d0012200 { 44 serial@d0012200 {
45 compatible = "snps,dw-apb-uart"; 45 compatible = "snps,dw-apb-uart";
46 reg = <0xd0012200 0x100>; 46 reg = <0xd0012200 0x100>;