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authorAbhilash Kesavan <a.kesavan@samsung.com>2014-11-06 19:27:33 -0500
committerKukjin Kim <kgene.kim@samsung.com>2014-11-21 08:49:45 -0500
commitaf2e0a0754accf2276d58d6dfaa15563133130aa (patch)
treec0dc13a58af2ca6a61fd6b4c9a261f5c8d82f621
parent6b7bfd8292ab27180662bcba175e7a3822486c2d (diff)
ARM: EXYNOS: Add PMU support for exynos5420
Adds initial PMU settings for exynos5420. This is required for future S2R and Switching support. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-exynos/pmu.c287
-rw-r--r--arch/arm/mach-exynos/regs-pmu.h227
2 files changed, 514 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 88d3f793e267..6c8a76dd5494 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -12,6 +12,8 @@
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/delay.h>
16
15 17
16#include "exynos-pmu.h" 18#include "exynos-pmu.h"
17#include "regs-pmu.h" 19#include "regs-pmu.h"
@@ -348,6 +350,151 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
348 { PMU_TABLE_END,}, 350 { PMU_TABLE_END,},
349}; 351};
350 352
353static struct exynos_pmu_conf exynos5420_pmu_config[] = {
354 /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
355 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
356 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
357 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
358 { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
359 { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
360 { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
361 { EXYNOS5420_ARM_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
362 { EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
363 { EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
364 { EXYNOS5420_ARM_CORE3_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
365 { EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
366 { EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
367 { EXYNOS5420_KFC_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
368 { EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
369 { EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
370 { EXYNOS5420_KFC_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
371 { EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
372 { EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
373 { EXYNOS5420_KFC_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
374 { EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
375 { EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
376 { EXYNOS5420_KFC_CORE3_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
377 { EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
378 { EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
379 { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
380 { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
381 { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
382 { EXYNOS5420_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
383 { EXYNOS5420_KFC_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
384 { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
385 { EXYNOS5420_KFC_L2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
386 { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
387 { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
388 { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
389 { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
390 { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
391 { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
392 { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
393 { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
394 { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
395 { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
396 { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
397 { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
398 { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
399 { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
400 { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
401 { EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
402 { EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
403 { EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
404 { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
405 { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
406 { EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
407 { EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
408 { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
409 { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
410 { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x0} },
411 { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
412 { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
413 { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
414 { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
415 { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
416 { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
417 { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
418 { EXYNOS5420_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
419 { EXYNOS5420_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
420 { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
421 { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
422 { EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
423 { EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
424 { EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
425 { EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
426 { EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
427 { EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
428 { EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
429 { EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
430 { EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
431 { EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
432 { EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
433 { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
434 { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
435 { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
436 { EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
437 { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
438 { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
439 { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
440 { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
441 { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
442 { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
443 { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
444 { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
445 { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
446 { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
447 { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
448 { EXYNOS5420_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
449 { EXYNOS5420_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
450 { EXYNOS5420_G2D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
451 { EXYNOS5420_MSC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
452 { EXYNOS5420_FSYS_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
453 { EXYNOS5420_FSYS2_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
454 { EXYNOS5420_PSGEN_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
455 { EXYNOS5420_PERIC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
456 { EXYNOS5420_WCORE_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
457 { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
458 { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
459 { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
460 { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
461 { EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
462 { EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
463 { EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
464 { EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
465 { EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
466 { EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
467 { EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
468 { EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
469 { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
470 { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
471 { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
472 { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
473 { EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
474 { EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
475 { EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
476 { EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
477 { EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
478 { EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
479 { EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
480 { EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
481 { EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
482 { EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
483 { EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
484 { EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
485 { EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
486 { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
487 { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
488 { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
489 { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
490 { EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
491 { EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
492 { EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
493 { EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
494 { EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
495 { PMU_TABLE_END,},
496};
497
351static unsigned int const exynos5_list_both_cnt_feed[] = { 498static unsigned int const exynos5_list_both_cnt_feed[] = {
352 EXYNOS5_ARM_CORE0_OPTION, 499 EXYNOS5_ARM_CORE0_OPTION,
353 EXYNOS5_ARM_CORE1_OPTION, 500 EXYNOS5_ARM_CORE1_OPTION,
@@ -368,6 +515,75 @@ static unsigned int const exynos5_list_disable_wfi_wfe[] = {
368 EXYNOS5_ISP_ARM_OPTION, 515 EXYNOS5_ISP_ARM_OPTION,
369}; 516};
370 517
518static unsigned int const exynos5420_list_disable_pmu_reg[] = {
519 EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
520 EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
521 EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
522 EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
523 EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,
524 EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,
525 EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,
526 EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,
527 EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,
528 EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,
529 EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,
530 EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
531 EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
532 EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
533 EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,
534 EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,
535 EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,
536 EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,
537 EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,
538 EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,
539 EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,
540 EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,
541 EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,
542 EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,
543 EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,
544 EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,
545 EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,
546 EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
547 EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
548 EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
549 EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,
550 EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,
551 EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,
552 EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,
553 EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
554};
555
556static void exynos5_power_off(void)
557{
558 unsigned int tmp;
559
560 pr_info("Power down.\n");
561 tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL);
562 tmp ^= (1 << 8);
563 pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL);
564
565 /* Wait a little so we don't give a false warning below */
566 mdelay(100);
567
568 pr_err("Power down failed, please power off system manually.\n");
569 while (1)
570 ;
571}
572
573void exynos5420_powerdown_conf(enum sys_powerdown mode)
574{
575 u32 this_cluster;
576
577 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
578
579 /*
580 * set the cluster id to IROM register to ensure that we wake
581 * up with the current cluster.
582 */
583 pmu_raw_writel(this_cluster, EXYNOS_IROM_DATA2);
584}
585
586
371static void exynos5_powerdown_conf(enum sys_powerdown mode) 587static void exynos5_powerdown_conf(enum sys_powerdown mode)
372{ 588{
373 unsigned int i; 589 unsigned int i;
@@ -439,6 +655,68 @@ static void exynos5250_pmu_init(void)
439 pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); 655 pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
440} 656}
441 657
658static void exynos5420_pmu_init(void)
659{
660 unsigned int value;
661 int i;
662
663 /*
664 * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers
665 * for local power blocks to Low initially as per Table 8-4:
666 * "System-Level Power-Down Configuration Registers".
667 */
668 for (i = 0; i < ARRAY_SIZE(exynos5420_list_disable_pmu_reg); i++)
669 pmu_raw_writel(0, exynos5420_list_disable_pmu_reg[i]);
670
671 /* Enable USE_STANDBY_WFI for all CORE */
672 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
673
674 value = pmu_raw_readl(EXYNOS_L2_OPTION(0));
675 value &= ~EXYNOS5_USE_RETENTION;
676 pmu_raw_writel(value, EXYNOS_L2_OPTION(0));
677
678 value = pmu_raw_readl(EXYNOS_L2_OPTION(1));
679 value &= ~EXYNOS5_USE_RETENTION;
680 pmu_raw_writel(value, EXYNOS_L2_OPTION(1));
681
682 /*
683 * If L2_COMMON is turned off, clocks related to ATB async
684 * bridge are gated. Thus, when ISP power is gated, LPI
685 * may get stuck.
686 */
687 value = pmu_raw_readl(EXYNOS5420_LPI_MASK);
688 value |= EXYNOS5420_ATB_ISP_ARM;
689 pmu_raw_writel(value, EXYNOS5420_LPI_MASK);
690
691 value = pmu_raw_readl(EXYNOS5420_LPI_MASK1);
692 value |= EXYNOS5420_ATB_KFC;
693 pmu_raw_writel(value, EXYNOS5420_LPI_MASK1);
694
695 /* Prevent issue of new bus request from L2 memory */
696 value = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
697 value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
698 pmu_raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION);
699
700 value = pmu_raw_readl(EXYNOS5420_KFC_COMMON_OPTION);
701 value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
702 pmu_raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION);
703
704 /* This setting is to reduce suspend/resume time */
705 pmu_raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3);
706
707 /* Serialized CPU wakeup of Eagle */
708 pmu_raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE);
709
710 pmu_raw_writel(SPREAD_USE_STANDWFI,
711 EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI);
712
713 pmu_raw_writel(0x1, EXYNOS5420_UP_SCHEDULER);
714
715 pm_power_off = exynos5_power_off;
716 pr_info("EXYNOS5420 PMU initialized\n");
717}
718
719
442static const struct exynos_pmu_data exynos4210_pmu_data = { 720static const struct exynos_pmu_data exynos4210_pmu_data = {
443 .pmu_config = exynos4210_pmu_config, 721 .pmu_config = exynos4210_pmu_config,
444}; 722};
@@ -458,6 +736,12 @@ static const struct exynos_pmu_data exynos5250_pmu_data = {
458 .powerdown_conf = exynos5_powerdown_conf, 736 .powerdown_conf = exynos5_powerdown_conf,
459}; 737};
460 738
739static struct exynos_pmu_data exynos5420_pmu_data = {
740 .pmu_config = exynos5420_pmu_config,
741 .pmu_init = exynos5420_pmu_init,
742 .powerdown_conf = exynos5420_powerdown_conf,
743};
744
461/* 745/*
462 * PMU platform driver and devicetree bindings. 746 * PMU platform driver and devicetree bindings.
463 */ 747 */
@@ -474,6 +758,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = {
474 }, { 758 }, {
475 .compatible = "samsung,exynos5250-pmu", 759 .compatible = "samsung,exynos5250-pmu",
476 .data = &exynos5250_pmu_data, 760 .data = &exynos5250_pmu_data,
761 }, {
762 .compatible = "samsung,exynos5420-pmu",
763 .data = &exynos5420_pmu_data,
477 }, 764 },
478 { /*sentinel*/ }, 765 { /*sentinel*/ },
479}; 766};
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 322f13277c3b..46b973b8cd83 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -38,6 +38,7 @@
38#define S5P_INFORM7 0x081C 38#define S5P_INFORM7 0x081C
39#define S5P_PMU_SPARE3 0x090C 39#define S5P_PMU_SPARE3 0x090C
40 40
41#define EXYNOS_IROM_DATA2 0x0988
41#define S5P_ARM_CORE0_LOWPWR 0x1000 42#define S5P_ARM_CORE0_LOWPWR 0x1000
42#define S5P_DIS_IRQ_CORE0 0x1004 43#define S5P_DIS_IRQ_CORE0 0x1004
43#define S5P_DIS_IRQ_CENTRAL0 0x1008 44#define S5P_DIS_IRQ_CENTRAL0 0x1008
@@ -120,6 +121,31 @@
120#define EXYNOS_COMMON_OPTION(_nr) \ 121#define EXYNOS_COMMON_OPTION(_nr) \
121 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) 122 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
122 123
124#define EXYNOS_CORE_LOCAL_PWR_EN 0x3
125
126#define EXYNOS_ARM_COMMON_STATUS 0x2504
127#define EXYNOS_COMMON_OPTION(_nr) \
128 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
129
130#define EXYNOS_ARM_L2_CONFIGURATION 0x2600
131#define EXYNOS_L2_CONFIGURATION(_nr) \
132 (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80))
133#define EXYNOS_L2_STATUS(_nr) \
134 (EXYNOS_L2_CONFIGURATION(_nr) + 0x4)
135#define EXYNOS_L2_OPTION(_nr) \
136 (EXYNOS_L2_CONFIGURATION(_nr) + 0x8)
137#define EXYNOS_L2_COMMON_PWR_EN 0x3
138
139#define EXYNOS_ARM_CORE_X_STATUS_OFFSET 0x4
140
141#define EXYNOS5_APLL_SYSCLK_CONFIGURATION 0x2A00
142#define EXYNOS5_APLL_SYSCLK_STATUS 0x2A04
143
144#define EXYNOS5_ARM_L2_OPTION 0x2608
145#define EXYNOS5_USE_RETENTION BIT(4)
146
147#define EXYNOS5_L2RSTDISABLE_VALUE BIT(3)
148
123#define S5P_PAD_RET_MAUDIO_OPTION 0x3028 149#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
124#define S5P_PAD_RET_GPIO_OPTION 0x3108 150#define S5P_PAD_RET_GPIO_OPTION 0x3108
125#define S5P_PAD_RET_UART_OPTION 0x3128 151#define S5P_PAD_RET_UART_OPTION 0x3128
@@ -193,6 +219,7 @@
193#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408 219#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
194#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C 220#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C
195 221
222#define EXYNOS5_USE_RETENTION BIT(4)
196#define EXYNOS5_SYS_WDTRESET (1 << 20) 223#define EXYNOS5_SYS_WDTRESET (1 << 20)
197 224
198#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000 225#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000
@@ -332,4 +359,204 @@ static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
332 + MPIDR_AFFINITY_LEVEL(mpidr, 0)); 359 + MPIDR_AFFINITY_LEVEL(mpidr, 0));
333} 360}
334 361
362/* Only for EXYNOS5420 */
363#define EXYNOS5420_ISP_ARM_OPTION 0x2488
364#define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3)
365
366#define EXYNOS5420_LPI_MASK 0x0004
367#define EXYNOS5420_LPI_MASK1 0x0008
368#define EXYNOS5420_UFS BIT(8)
369#define EXYNOS5420_ATB_KFC BIT(13)
370#define EXYNOS5420_ATB_ISP_ARM BIT(19)
371#define EXYNOS5420_EMULATION BIT(31)
372#define ATB_ISP_ARM BIT(12)
373#define ATB_KFC BIT(13)
374#define ATB_NOC BIT(14)
375
376#define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 0x0100
377#define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI 0x0104
378#define EXYNOS5420_UP_SCHEDULER 0x0120
379#define SPREAD_ENABLE 0xF
380#define SPREAD_USE_STANDWFI 0xF
381
382#define EXYNOS5420_BB_CON1 0x0784
383#define EXYNOS5420_BB_SEL_EN BIT(31)
384#define EXYNOS5420_BB_PMOS_EN BIT(7)
385#define EXYNOS5420_BB_1300X 0XF
386
387#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020
388#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024
389#define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG 0x1028
390#define EXYNOS5420_ARM_CORE3_SYS_PWR_REG 0x1030
391#define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG 0x1034
392#define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG 0x1038
393#define EXYNOS5420_KFC_CORE0_SYS_PWR_REG 0x1040
394#define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG 0x1044
395#define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG 0x1048
396#define EXYNOS5420_KFC_CORE1_SYS_PWR_REG 0x1050
397#define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG 0x1054
398#define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG 0x1058
399#define EXYNOS5420_KFC_CORE2_SYS_PWR_REG 0x1060
400#define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG 0x1064
401#define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG 0x1068
402#define EXYNOS5420_KFC_CORE3_SYS_PWR_REG 0x1070
403#define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG 0x1074
404#define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG 0x1078
405#define EXYNOS5420_ISP_ARM_SYS_PWR_REG 0x1090
406#define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1094
407#define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1098
408#define EXYNOS5420_ARM_COMMON_SYS_PWR_REG 0x10A0
409#define EXYNOS5420_KFC_COMMON_SYS_PWR_REG 0x10B0
410#define EXYNOS5420_KFC_L2_SYS_PWR_REG 0x10D0
411#define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG 0x1158
412#define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG 0x115C
413#define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG 0x1160
414#define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG 0x1174
415#define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 0x1178
416#define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 0x11B8
417#define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 0x11BC
418#define EXYNOS5420_ONENANDXL_MEM_SYS_PWR 0x11C0
419#define EXYNOS5420_USBDEV_MEM_SYS_PWR 0x11CC
420#define EXYNOS5420_USBDEV1_MEM_SYS_PWR 0x11D0
421#define EXYNOS5420_SDMMC_MEM_SYS_PWR 0x11D4
422#define EXYNOS5420_CSSYS_MEM_SYS_PWR 0x11D8
423#define EXYNOS5420_SECSS_MEM_SYS_PWR 0x11DC
424#define EXYNOS5420_ROTATOR_MEM_SYS_PWR 0x11E0
425#define EXYNOS5420_INTRAM_MEM_SYS_PWR 0x11E4
426#define EXYNOS5420_INTROM_MEM_SYS_PWR 0x11E8
427#define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1208
428#define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1210
429#define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG 0x1214
430#define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1218
431#define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG 0x121C
432#define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1220
433#define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG 0x1224
434#define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1228
435#define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG 0x122C
436#define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG 0x1230
437#define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG 0x1234
438#define EXYNOS5420_DISP1_SYS_PWR_REG 0x1410
439#define EXYNOS5420_MAU_SYS_PWR_REG 0x1414
440#define EXYNOS5420_G2D_SYS_PWR_REG 0x1418
441#define EXYNOS5420_MSC_SYS_PWR_REG 0x141C
442#define EXYNOS5420_FSYS_SYS_PWR_REG 0x1420
443#define EXYNOS5420_FSYS2_SYS_PWR_REG 0x1424
444#define EXYNOS5420_PSGEN_SYS_PWR_REG 0x1428
445#define EXYNOS5420_PERIC_SYS_PWR_REG 0x142C
446#define EXYNOS5420_WCORE_SYS_PWR_REG 0x1430
447#define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1490
448#define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1494
449#define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG 0x1498
450#define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG 0x149C
451#define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG 0x14A0
452#define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG 0x14A4
453#define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG 0x14A8
454#define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG 0x14AC
455#define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG 0x14B0
456#define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG 0x14BC
457#define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D0
458#define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D4
459#define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG 0x14D8
460#define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG 0x14DC
461#define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG 0x14E0
462#define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG 0x14E4
463#define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG 0x14E8
464#define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG 0x14EC
465#define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG 0x14F0
466#define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG 0x14F4
467#define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG 0x1570
468#define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG 0x1574
469#define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG 0x1578
470#define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG 0x157C
471#define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG 0x1590
472#define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG 0x1594
473#define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG 0x1598
474#define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 0x159C
475#define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 0x15A0
476#define EXYNOS5420_SFR_AXI_CGDIS1 0x15E4
477#define EXYNOS_ARM_CORE2_CONFIGURATION 0x2100
478#define EXYNOS5420_ARM_CORE2_OPTION 0x2108
479#define EXYNOS_ARM_CORE3_CONFIGURATION 0x2180
480#define EXYNOS5420_ARM_CORE3_OPTION 0x2188
481#define EXYNOS5420_ARM_COMMON_STATUS 0x2504
482#define EXYNOS5420_ARM_COMMON_OPTION 0x2508
483#define EXYNOS5420_KFC_COMMON_STATUS 0x2584
484#define EXYNOS5420_KFC_COMMON_OPTION 0x2588
485#define EXYNOS5420_LOGIC_RESET_DURATION3 0x2D1C
486
487#define EXYNOS5420_PAD_RET_GPIO_OPTION 0x30C8
488#define EXYNOS5420_PAD_RET_UART_OPTION 0x30E8
489#define EXYNOS5420_PAD_RET_MMCA_OPTION 0x3108
490#define EXYNOS5420_PAD_RET_MMCB_OPTION 0x3128
491#define EXYNOS5420_PAD_RET_MMCC_OPTION 0x3148
492#define EXYNOS5420_PAD_RET_HSI_OPTION 0x3168
493#define EXYNOS5420_PAD_RET_SPI_OPTION 0x31C8
494#define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION 0x31E8
495#define EXYNOS_PAD_RET_DRAM_OPTION 0x3008
496#define EXYNOS_PAD_RET_MAUDIO_OPTION 0x3028
497#define EXYNOS_PAD_RET_JTAG_OPTION 0x3048
498#define EXYNOS_PAD_RET_GPIO_OPTION 0x3108
499#define EXYNOS_PAD_RET_UART_OPTION 0x3128
500#define EXYNOS_PAD_RET_MMCA_OPTION 0x3148
501#define EXYNOS_PAD_RET_MMCB_OPTION 0x3168
502#define EXYNOS_PAD_RET_EBIA_OPTION 0x3188
503#define EXYNOS_PAD_RET_EBIB_OPTION 0x31A8
504
505#define EXYNOS_PS_HOLD_CONTROL 0x330C
506
507/* For SYS_PWR_REG */
508#define EXYNOS_SYS_PWR_CFG BIT(0)
509
510#define EXYNOS5420_MFC_CONFIGURATION 0x4060
511#define EXYNOS5420_MFC_STATUS 0x4064
512#define EXYNOS5420_MFC_OPTION 0x4068
513#define EXYNOS5420_G3D_CONFIGURATION 0x4080
514#define EXYNOS5420_G3D_STATUS 0x4084
515#define EXYNOS5420_G3D_OPTION 0x4088
516#define EXYNOS5420_DISP0_CONFIGURATION 0x40A0
517#define EXYNOS5420_DISP0_STATUS 0x40A4
518#define EXYNOS5420_DISP0_OPTION 0x40A8
519#define EXYNOS5420_DISP1_CONFIGURATION 0x40C0
520#define EXYNOS5420_DISP1_STATUS 0x40C4
521#define EXYNOS5420_DISP1_OPTION 0x40C8
522#define EXYNOS5420_MAU_CONFIGURATION 0x40E0
523#define EXYNOS5420_MAU_STATUS 0x40E4
524#define EXYNOS5420_MAU_OPTION 0x40E8
525#define EXYNOS5420_FSYS2_OPTION 0x4168
526#define EXYNOS5420_PSGEN_OPTION 0x4188
527
528/* For EXYNOS_CENTRAL_SEQ_OPTION */
529#define EXYNOS5_USE_STANDBYWFI_ARM_CORE0 BIT(16)
530#define EXYNOS5_USE_STANDBYWFI_ARM_CORE1 BUT(17)
531#define EXYNOS5_USE_STANDBYWFE_ARM_CORE0 BIT(24)
532#define EXYNOS5_USE_STANDBYWFE_ARM_CORE1 BIT(25)
533
534#define EXYNOS5420_ARM_USE_STANDBY_WFI0 BIT(4)
535#define EXYNOS5420_ARM_USE_STANDBY_WFI1 BIT(5)
536#define EXYNOS5420_ARM_USE_STANDBY_WFI2 BIT(6)
537#define EXYNOS5420_ARM_USE_STANDBY_WFI3 BIT(7)
538#define EXYNOS5420_KFC_USE_STANDBY_WFI0 BIT(8)
539#define EXYNOS5420_KFC_USE_STANDBY_WFI1 BIT(9)
540#define EXYNOS5420_KFC_USE_STANDBY_WFI2 BIT(10)
541#define EXYNOS5420_KFC_USE_STANDBY_WFI3 BIT(11)
542#define EXYNOS5420_ARM_USE_STANDBY_WFE0 BIT(16)
543#define EXYNOS5420_ARM_USE_STANDBY_WFE1 BIT(17)
544#define EXYNOS5420_ARM_USE_STANDBY_WFE2 BIT(18)
545#define EXYNOS5420_ARM_USE_STANDBY_WFE3 BIT(19)
546#define EXYNOS5420_KFC_USE_STANDBY_WFE0 BIT(20)
547#define EXYNOS5420_KFC_USE_STANDBY_WFE1 BIT(21)
548#define EXYNOS5420_KFC_USE_STANDBY_WFE2 BIT(22)
549#define EXYNOS5420_KFC_USE_STANDBY_WFE3 BIT(23)
550
551#define DUR_WAIT_RESET 0xF
552
553#define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNOS5420_ARM_USE_STANDBY_WFI0 \
554 | EXYNOS5420_ARM_USE_STANDBY_WFI1 \
555 | EXYNOS5420_ARM_USE_STANDBY_WFI2 \
556 | EXYNOS5420_ARM_USE_STANDBY_WFI3 \
557 | EXYNOS5420_KFC_USE_STANDBY_WFI0 \
558 | EXYNOS5420_KFC_USE_STANDBY_WFI1 \
559 | EXYNOS5420_KFC_USE_STANDBY_WFI2 \
560 | EXYNOS5420_KFC_USE_STANDBY_WFI3)
561
335#endif /* __ASM_ARCH_REGS_PMU_H */ 562#endif /* __ASM_ARCH_REGS_PMU_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 05:20:28 -0400