ARM: rockchip: decrease the wait time for resume

The register-default delay time for wait the 24MHz OSC stabilization as well
as PMU stabilization is 750ms, let's decrease them to a still safe 30ms.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

2 files changed, 7 insertions, 0 deletions

diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index 50cb781aaa36..a3ab3979923c 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -209,6 +209,9 @@ static int rk3288_suspend_init(struct device_node *np)
         memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
                rk3288_bootram_sz);
 
+        regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);
+        regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
index 7c889c04604b..91a542df5791 100644
--- a/arch/arm/mach-rockchip/pm.h
+++ b/arch/arm/mach-rockchip/pm.h
@@ -63,6 +63,10 @@ static inline void rockchip_suspend_init(void)
 /* PMU_WAKEUP_CFG1 bits */
 #define PMU_ARMINT_WAKEUP_EN            BIT(0)
 
+/* wait 30ms for OSC stable and 30ms for pmic stable */
+#define OSC_STABL_CNT_THRESH    (32 * 30)
+#define PMU_STABL_CNT_THRESH    (32 * 30)
+
 enum rk3288_pwr_mode_con {
         PMU_PWR_MODE_EN = 0,
         PMU_CLK_CORE_SRC_GATE_EN,