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authorTony Lindgren <tony@atomide.com>2013-04-04 14:22:33 -0400
committerTony Lindgren <tony@atomide.com>2013-04-04 14:22:33 -0400
commitaecb65a34a780cd07fbaa652cc5d640f13f3ed5f (patch)
treed105fe18ce217db7231a332db5e4232b1b32bc6e
parentdca3a783400a18e2bf4503b1d4a85c4d0ca1a7e4 (diff)
parent5330dc161cb41e399e85d30e6908f1b93b956d1e (diff)
Merge branch 'omap-gpmc-for-v3.10-take2' of git://github.com/jonhunter/linux into omap-for-v3.10/gpmc
Diffstat
-rw-r--r--Documentation/devicetree/bindings/bus/ti-gpmc.txt103
-rw-r--r--Documentation/devicetree/bindings/mtd/gpmc-nor.txt98
-rw-r--r--Documentation/devicetree/bindings/mtd/gpmc-onenand.txt3
-rw-r--r--Documentation/devicetree/bindings/net/gpmc-eth.txt97
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c42
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c118
-rw-r--r--arch/arm/mach-omap2/gpmc-smc91x.c30
-rw-r--r--arch/arm/mach-omap2/gpmc.c544
-rw-r--r--arch/arm/mach-omap2/gpmc.h43
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c62
10 files changed, 831 insertions, 309 deletions
diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
index 5ddb2e9efaaa..4b87ea1194e3 100644
--- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -35,36 +35,83 @@ Required properties:
35 35
36Timing properties for child nodes. All are optional and default to 0. 36Timing properties for child nodes. All are optional and default to 0.
37 37
38 - gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds 38 - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
39 39
40 Chip-select signal timings corresponding to GPMC_CONFIG2: 40 Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
41 - gpmc,cs-on: Assertion time 41 - gpmc,cs-on-ns: Assertion time
42 - gpmc,cs-rd-off: Read deassertion time 42 - gpmc,cs-rd-off-ns: Read deassertion time
43 - gpmc,cs-wr-off: Write deassertion time 43 - gpmc,cs-wr-off-ns: Write deassertion time
44 44
45 ADV signal timings corresponding to GPMC_CONFIG3: 45 ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
46 - gpmc,adv-on: Assertion time 46 - gpmc,adv-on-ns: Assertion time
47 - gpmc,adv-rd-off: Read deassertion time 47 - gpmc,adv-rd-off-ns: Read deassertion time
48 - gpmc,adv-wr-off: Write deassertion time 48 - gpmc,adv-wr-off-ns: Write deassertion time
49 49
50 WE signals timings corresponding to GPMC_CONFIG4: 50 WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
51 - gpmc,we-on: Assertion time 51 - gpmc,we-on-ns Assertion time
52 - gpmc,we-off: Deassertion time 52 - gpmc,we-off-ns: Deassertion time
53 53
54 OE signals timings corresponding to GPMC_CONFIG4: 54 OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
55 - gpmc,oe-on: Assertion time 55 - gpmc,oe-on-ns: Assertion time
56 - gpmc,oe-off: Deassertion time 56 - gpmc,oe-off-ns: Deassertion time
57 57
58 Access time and cycle time timings corresponding to GPMC_CONFIG5: 58 Access time and cycle time timings (in nanoseconds) corresponding to
59 - gpmc,page-burst-access: Multiple access word delay 59 GPMC_CONFIG5:
60 - gpmc,access: Start-cycle to first data valid delay 60 - gpmc,page-burst-access-ns: Multiple access word delay
61 - gpmc,rd-cycle: Total read cycle time 61 - gpmc,access-ns: Start-cycle to first data valid delay
62 - gpmc,wr-cycle: Total write cycle time 62 - gpmc,rd-cycle-ns: Total read cycle time
63 - gpmc,wr-cycle-ns: Total write cycle time
64 - gpmc,bus-turnaround-ns: Turn-around time between successive accesses
65 - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
66 - gpmc,clk-activation-ns: GPMC clock activation time
67 - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
68 data
69
70Boolean timing parameters. If property is present parameter enabled and
71disabled if omitted:
72 - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
73 - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
74 - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
75 accesses to a different CS
76 - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
77 accesses to the same CS
78 - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
79 - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
80 - gpmc,time-para-granularity: Multiply all access times by 2
63 81
64The following are only applicable to OMAP3+ and AM335x: 82The following are only applicable to OMAP3+ and AM335x:
65 - gpmc,wr-access 83 - gpmc,wr-access-ns: In synchronous write mode, for single or
66 - gpmc,wr-data-mux-bus 84 burst accesses, defines the number of
67 85 GPMC_FCLK cycles from start access time
86 to the GPMC_CLK rising edge used by the
87 memory device for the first data capture.
88 - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
89 the time when the first data is driven on
90 the address-data bus.
91
92GPMC chip-select settings properties for child nodes. All are optional.
93
94- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
95- gpmc,burst-wrap Enables wrap bursting
96- gpmc,burst-read Enables read page/burst mode
97- gpmc,burst-write Enables write page/burst mode
98- gpmc,device-nand Device is NAND
99- gpmc,device-width Total width of device(s) connected to a GPMC
100 chip-select in bytes. The GPMC supports 8-bit
101 and 16-bit devices and so this property must be
102 1 or 2.
103- gpmc,mux-add-data Address and data multiplexing configuration.
104 Valid values are 1 for address-address-data
105 multiplexing mode and 2 for address-data
106 multiplexing mode.
107- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
108 is this is not set.
109- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
110 is this is not set.
111- gpmc,wait-pin Wait-pin used by client. Must be less than
112 "gpmc,num-waitpins".
113- gpmc,wait-on-read Enables wait monitoring on reads.
114- gpmc,wait-on-write Enables wait monitoring on writes.
68 115
69Example for an AM33xx board: 116Example for an AM33xx board:
70 117
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nor.txt b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt
new file mode 100644
index 000000000000..420b3ab18890
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt
@@ -0,0 +1,98 @@
1Device tree bindings for NOR flash connect to TI GPMC
2
3NOR flash connected to the TI GPMC (found on OMAP boards) are represented as
4child nodes of the GPMC controller with a name of "nor".
5
6All timing relevant properties as well as generic GPMC child properties are
7explained in a separate documents. Please refer to
8Documentation/devicetree/bindings/bus/ti-gpmc.txt
9
10Required properties:
11- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
14- gpmc,cs-on-ns: Chip-select assertion time
15- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17- gpmc,oe-on-ns: Output-enable assertion time
18- gpmc,oe-off-ns: Output-enable de-assertion time
19- gpmc,we-on-ns Write-enable assertion time
20- gpmc,we-off-ns: Write-enable de-assertion time
21- gpmc,access-ns: Start cycle to first data capture (read access)
22- gpmc,rd-cycle-ns: Total read cycle time
23- gpmc,wr-cycle-ns: Total write cycle time
24- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
25- reg: Chip-select, base address (relative to chip-select)
26 and size of NOR flash. Note that base address will be
27 typically 0 as this is the start of the chip-select.
28
29Optional properties:
30- gpmc,XXX Additional GPMC timings and settings parameters. See
31 Documentation/devicetree/bindings/bus/ti-gpmc.txt
32
33Optional properties for partiton table parsing:
34- #address-cells: should be set to 1
35- #size-cells: should be set to 1
36
37Example:
38
39gpmc: gpmc@6e000000 {
40 compatible = "ti,omap3430-gpmc", "simple-bus";
41 ti,hwmods = "gpmc";
42 reg = <0x6e000000 0x1000>;
43 interrupts = <20>;
44 gpmc,num-cs = <8>;
45 gpmc,num-waitpins = <4>;
46 #address-cells = <2>;
47 #size-cells = <1>;
48
49 ranges = <0 0 0x10000000 0x08000000>;
50
51 nor@0,0 {
52 compatible = "cfi-flash";
53 linux,mtd-name= "intel,pf48f6000m0y1be";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 reg = <0 0 0x08000000>;
57 bank-width = <2>;
58
59 gpmc,mux-add-data;
60 gpmc,cs-on-ns = <0>;
61 gpmc,cs-rd-off-ns = <186>;
62 gpmc,cs-wr-off-ns = <186>;
63 gpmc,adv-on-ns = <12>;
64 gpmc,adv-rd-off-ns = <48>;
65 gpmc,adv-wr-off-ns = <48>;
66 gpmc,oe-on-ns = <54>;
67 gpmc,oe-off-ns = <168>;
68 gpmc,we-on-ns = <54>;
69 gpmc,we-off-ns = <168>;
70 gpmc,rd-cycle-ns = <186>;
71 gpmc,wr-cycle-ns = <186>;
72 gpmc,access-ns = <114>;
73 gpmc,page-burst-access-ns = <6>;
74 gpmc,bus-turnaround-ns = <12>;
75 gpmc,cycle2cycle-delay-ns = <18>;
76 gpmc,wr-data-mux-bus-ns = <90>;
77 gpmc,wr-access-ns = <186>;
78 gpmc,cycle2cycle-samecsen;
79 gpmc,cycle2cycle-diffcsen;
80
81 partition@0 {
82 label = "bootloader-nor";
83 reg = <0 0x40000>;
84 };
85 partition@0x40000 {
86 label = "params-nor";
87 reg = <0x40000 0x40000>;
88 };
89 partition@0x80000 {
90 label = "kernel-nor";
91 reg = <0x80000 0x200000>;
92 };
93 partition@0x280000 {
94 label = "filesystem-nor";
95 reg = <0x240000 0x7d80000>;
96 };
97 };
98};
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
index deec9da224a2..b7529424ac88 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
@@ -10,6 +10,8 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt
10Required properties: 10Required properties:
11 11
12 - reg: The CS line the peripheral is connected to 12 - reg: The CS line the peripheral is connected to
13 - gpmc,device-width Width of the ONENAND device connected to the GPMC
14 in bytes. Must be 1 or 2.
13 15
14Optional properties: 16Optional properties:
15 17
@@ -34,6 +36,7 @@ Example for an OMAP3430 board:
34 36
35 onenand@0 { 37 onenand@0 {
36 reg = <0 0 0>; /* CS0, offset 0 */ 38 reg = <0 0 0>; /* CS0, offset 0 */
39 gpmc,device-width = <2>;
37 40
38 #address-cells = <1>; 41 #address-cells = <1>;
39 #size-cells = <1>; 42 #size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/net/gpmc-eth.txt b/Documentation/devicetree/bindings/net/gpmc-eth.txt
new file mode 100644
index 000000000000..24cb4e46f675
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/gpmc-eth.txt
@@ -0,0 +1,97 @@
1Device tree bindings for Ethernet chip connected to TI GPMC
2
3Besides being used to interface with external memory devices, the
4General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
5such as ethernet controllers to processors using the TI GPMC as a data bus.
6
7Ethernet controllers connected to TI GPMC are represented as child nodes of
8the GPMC controller with an "ethernet" name.
9
10All timing relevant properties as well as generic GPMC child properties are
11explained in a separate documents. Please refer to
12Documentation/devicetree/bindings/bus/ti-gpmc.txt
13
14For the properties relevant to the ethernet controller connected to the GPMC
15refer to the binding documentation of the device. For example, the documentation
16for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt
17
18Child nodes need to specify the GPMC bus address width using the "bank-width"
19property but is possible that an ethernet controller also has a property to
20specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21address width, it supports devices with 32-bit word registers.
22For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
23OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
24
25Required properties:
26- bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28- compatible: Compatible string property for the ethernet child device.
29- gpmc,cs-on: Chip-select assertion time
30- gpmc,cs-rd-off: Chip-select de-assertion time for reads
31- gpmc,cs-wr-off: Chip-select de-assertion time for writes
32- gpmc,oe-on: Output-enable assertion time
33- gpmc,oe-off Output-enable de-assertion time
34- gpmc,we-on: Write-enable assertion time
35- gpmc,we-off: Write-enable de-assertion time
36- gpmc,access: Start cycle to first data capture (read access)
37- gpmc,rd-cycle: Total read cycle time
38- gpmc,wr-cycle: Total write cycle time
39- reg: Chip-select, base address (relative to chip-select)
40 and size of the memory mapped for the device.
41 Note that base address will be typically 0 as this
42 is the start of the chip-select.
43
44Optional properties:
45- gpmc,XXX Additional GPMC timings and settings parameters. See
46 Documentation/devicetree/bindings/bus/ti-gpmc.txt
47
48Example:
49
50gpmc: gpmc@6e000000 {
51 compatible = "ti,omap3430-gpmc";
52 ti,hwmods = "gpmc";
53 reg = <0x6e000000 0x1000>;
54 interrupts = <20>;
55 gpmc,num-cs = <8>;
56 gpmc,num-waitpins = <4>;
57 #address-cells = <2>;
58 #size-cells = <1>;
59
60 ranges = <5 0 0x2c000000 0x1000000>;
61
62 ethernet@5,0 {
63 compatible = "smsc,lan9221", "smsc,lan9115";
64 reg = <5 0 0xff>;
65 bank-width = <2>;
66
67 gpmc,mux-add-data;
68 gpmc,cs-on = <0>;
69 gpmc,cs-rd-off = <186>;
70 gpmc,cs-wr-off = <186>;
71 gpmc,adv-on = <12>;
72 gpmc,adv-rd-off = <48>;
73 gpmc,adv-wr-off = <48>;
74 gpmc,oe-on = <54>;
75 gpmc,oe-off = <168>;
76 gpmc,we-on = <54>;
77 gpmc,we-off = <168>;
78 gpmc,rd-cycle = <186>;
79 gpmc,wr-cycle = <186>;
80 gpmc,access = <114>;
81 gpmc,page-burst-access = <6>;
82 gpmc,bus-turnaround = <12>;
83 gpmc,cycle2cycle-delay = <18>;
84 gpmc,wr-data-mux-bus = <90>;
85 gpmc,wr-access = <186>;
86 gpmc,cycle2cycle-samecsen;
87 gpmc,cycle2cycle-diffcsen;
88
89 interrupt-parent = <&gpio6>;
90 interrupts = <16>;
91 vmmc-supply = <&vddvario>;
92 vmmc_aux-supply = <&vdd33a>;
93 reg-io-width = <4>;
94
95 smsc,save-mac-address;
96 };
97};
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index afc1e8c32d6c..d9c27195caf0 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -74,14 +74,6 @@ static int omap2_nand_gpmc_retime(
74 t.cs_wr_off = gpmc_t->cs_wr_off; 74 t.cs_wr_off = gpmc_t->cs_wr_off;
75 t.wr_cycle = gpmc_t->wr_cycle; 75 t.wr_cycle = gpmc_t->wr_cycle;
76 76
77 /* Configure GPMC */
78 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
79 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
80 else
81 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
82 gpmc_cs_configure(gpmc_nand_data->cs,
83 GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
84 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
85 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); 77 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
86 if (err) 78 if (err)
87 return err; 79 return err;
@@ -115,14 +107,18 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
115 struct gpmc_timings *gpmc_t) 107 struct gpmc_timings *gpmc_t)
116{ 108{
117 int err = 0; 109 int err = 0;
110 struct gpmc_settings s;
118 struct device *dev = &gpmc_nand_device.dev; 111 struct device *dev = &gpmc_nand_device.dev;
119 112
113 memset(&s, 0, sizeof(struct gpmc_settings));
114
120 gpmc_nand_device.dev.platform_data = gpmc_nand_data; 115 gpmc_nand_device.dev.platform_data = gpmc_nand_data;
121 116
122 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, 117 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
123 (unsigned long *)&gpmc_nand_resource[0].start); 118 (unsigned long *)&gpmc_nand_resource[0].start);
124 if (err < 0) { 119 if (err < 0) {
125 dev_err(dev, "Cannot request GPMC CS\n"); 120 dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
121 gpmc_nand_data->cs, err);
126 return err; 122 return err;
127 } 123 }
128 124
@@ -140,11 +136,31 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
140 dev_err(dev, "Unable to set gpmc timings: %d\n", err); 136 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
141 return err; 137 return err;
142 } 138 }
143 }
144 139
145 /* Enable RD PIN Monitoring Reg */ 140 if (gpmc_nand_data->of_node) {
146 if (gpmc_nand_data->dev_ready) { 141 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
147 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); 142 } else {
143 s.device_nand = true;
144
145 /* Enable RD PIN Monitoring Reg */
146 if (gpmc_nand_data->dev_ready) {
147 s.wait_on_read = true;
148 s.wait_on_write = true;
149 }
150 }
151
152 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
153 s.device_width = GPMC_DEVWIDTH_16BIT;
154 else
155 s.device_width = GPMC_DEVWIDTH_8BIT;
156
157 err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
158 if (err < 0)
159 goto out_free_cs;
160
161 err = gpmc_configure(GPMC_CONFIG_WP, 0);
162 if (err < 0)
163 goto out_free_cs;
148 } 164 }
149 165
150 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); 166 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 0d75889c0a6f..64b5a8346982 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -47,11 +47,23 @@ static struct platform_device gpmc_onenand_device = {
47 .resource = &gpmc_onenand_resource, 47 .resource = &gpmc_onenand_resource,
48}; 48};
49 49
50static struct gpmc_timings omap2_onenand_calc_async_timings(void) 50static struct gpmc_settings onenand_async = {
51 .device_width = GPMC_DEVWIDTH_16BIT,
52 .mux_add_data = GPMC_MUX_AD,
53};
54
55static struct gpmc_settings onenand_sync = {
56 .burst_read = true,
57 .burst_wrap = true,
58 .burst_len = GPMC_BURST_16,
59 .device_width = GPMC_DEVWIDTH_16BIT,
60 .mux_add_data = GPMC_MUX_AD,
61 .wait_pin = 0,
62};
63
64static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
51{ 65{
52 struct gpmc_device_timings dev_t; 66 struct gpmc_device_timings dev_t;
53 struct gpmc_timings t;
54
55 const int t_cer = 15; 67 const int t_cer = 15;
56 const int t_avdp = 12; 68 const int t_avdp = 12;
57 const int t_aavdh = 7; 69 const int t_aavdh = 7;
@@ -64,7 +76,6 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
64 76
65 memset(&dev_t, 0, sizeof(dev_t)); 77 memset(&dev_t, 0, sizeof(dev_t));
66 78
67 dev_t.mux = true;
68 dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000; 79 dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
69 dev_t.t_avdp_w = dev_t.t_avdp_r; 80 dev_t.t_avdp_w = dev_t.t_avdp_r;
70 dev_t.t_aavdh = t_aavdh * 1000; 81 dev_t.t_aavdh = t_aavdh * 1000;
@@ -76,19 +87,7 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
76 dev_t.t_wpl = t_wpl * 1000; 87 dev_t.t_wpl = t_wpl * 1000;
77 dev_t.t_wph = t_wph * 1000; 88 dev_t.t_wph = t_wph * 1000;
78 89
79 gpmc_calc_timings(&t, &dev_t); 90 gpmc_calc_timings(t, &onenand_async, &dev_t);
80
81 return t;
82}
83
84static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
85{
86 /* Configure GPMC for asynchronous read */
87 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
88 GPMC_CONFIG1_DEVICESIZE_16 |
89 GPMC_CONFIG1_MUXADDDATA);
90
91 return gpmc_cs_set_timings(cs, t);
92} 91}
93 92
94static void omap2_onenand_set_async_mode(void __iomem *onenand_base) 93static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
@@ -158,12 +157,11 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
158 return freq; 157 return freq;
159} 158}
160 159
161static struct gpmc_timings 160static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
162omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg, 161 unsigned int flags,
163 int freq) 162 int freq)
164{ 163{
165 struct gpmc_device_timings dev_t; 164 struct gpmc_device_timings dev_t;
166 struct gpmc_timings t;
167 const int t_cer = 15; 165 const int t_cer = 15;
168 const int t_avdp = 12; 166 const int t_avdp = 12;
169 const int t_cez = 20; /* max of t_cez, t_oez */ 167 const int t_cez = 20; /* max of t_cez, t_oez */
@@ -172,9 +170,9 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
172 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 170 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
173 int div, gpmc_clk_ns; 171 int div, gpmc_clk_ns;
174 172
175 if (cfg->flags & ONENAND_SYNC_READ) 173 if (flags & ONENAND_SYNC_READ)
176 onenand_flags = ONENAND_FLAG_SYNCREAD; 174 onenand_flags = ONENAND_FLAG_SYNCREAD;
177 else if (cfg->flags & ONENAND_SYNC_READWRITE) 175 else if (flags & ONENAND_SYNC_READWRITE)
178 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE; 176 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
179 177
180 switch (freq) { 178 switch (freq) {
@@ -239,10 +237,11 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
239 /* Set synchronous read timings */ 237 /* Set synchronous read timings */
240 memset(&dev_t, 0, sizeof(dev_t)); 238 memset(&dev_t, 0, sizeof(dev_t));
241 239
242 dev_t.mux = true; 240 if (onenand_flags & ONENAND_FLAG_SYNCREAD)
243 dev_t.sync_read = true; 241 onenand_sync.sync_read = true;
244 if (onenand_flags & ONENAND_FLAG_SYNCWRITE) { 242 if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
245 dev_t.sync_write = true; 243 onenand_sync.sync_write = true;
244 onenand_sync.burst_write = true;
246 } else { 245 } else {
247 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; 246 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
248 dev_t.t_wpl = t_wpl * 1000; 247 dev_t.t_wpl = t_wpl * 1000;
@@ -265,32 +264,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
265 dev_t.cyc_aavdh_oe = 1; 264 dev_t.cyc_aavdh_oe = 1;
266 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; 265 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
267 266
268 gpmc_calc_timings(&t, &dev_t); 267 gpmc_calc_timings(t, &onenand_sync, &dev_t);
269
270 return t;
271}
272
273static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
274{
275 unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
276 unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
277
278 /* Configure GPMC for synchronous read */
279 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
280 GPMC_CONFIG1_WRAPBURST_SUPP |
281 GPMC_CONFIG1_READMULTIPLE_SUPP |
282 (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
283 (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
284 (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
285 GPMC_CONFIG1_PAGE_LEN(2) |
286 (cpu_is_omap34xx() ? 0 :
287 (GPMC_CONFIG1_WAIT_READ_MON |
288 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
289 GPMC_CONFIG1_DEVICESIZE_16 |
290 GPMC_CONFIG1_DEVICETYPE_NOR |
291 GPMC_CONFIG1_MUXADDDATA);
292
293 return gpmc_cs_set_timings(cs, t);
294} 268}
295 269
296static int omap2_onenand_setup_async(void __iomem *onenand_base) 270static int omap2_onenand_setup_async(void __iomem *onenand_base)
@@ -298,11 +272,19 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
298 struct gpmc_timings t; 272 struct gpmc_timings t;
299 int ret; 273 int ret;
300 274
275 if (gpmc_onenand_data->of_node)
276 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
277 &onenand_async);
278
301 omap2_onenand_set_async_mode(onenand_base); 279 omap2_onenand_set_async_mode(onenand_base);
302 280
303 t = omap2_onenand_calc_async_timings(); 281 omap2_onenand_calc_async_timings(&t);
282
283 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
284 if (ret < 0)
285 return ret;
304 286
305 ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t); 287 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
306 if (ret < 0) 288 if (ret < 0)
307 return ret; 289 return ret;
308 290
@@ -322,9 +304,25 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
322 set_onenand_cfg(onenand_base); 304 set_onenand_cfg(onenand_base);
323 } 305 }
324 306
325 t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq); 307 if (gpmc_onenand_data->of_node) {
308 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
309 &onenand_sync);
310 } else {
311 /*
312 * FIXME: Appears to be legacy code from initial ONENAND commit.
313 * Unclear what boards this is for and if this can be removed.
314 */
315 if (!cpu_is_omap34xx())
316 onenand_sync.wait_on_read = true;
317 }
326 318
327 ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t); 319 omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
320
321 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
322 if (ret < 0)
323 return ret;
324
325 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
328 if (ret < 0) 326 if (ret < 0)
329 return ret; 327 return ret;
330 328
@@ -359,6 +357,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
359void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) 357void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
360{ 358{
361 int err; 359 int err;
360 struct device *dev = &gpmc_onenand_device.dev;
362 361
363 gpmc_onenand_data = _onenand_data; 362 gpmc_onenand_data = _onenand_data;
364 gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; 363 gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
@@ -366,7 +365,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
366 365
367 if (cpu_is_omap24xx() && 366 if (cpu_is_omap24xx() &&
368 (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) { 367 (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
369 printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n"); 368 dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
370 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE; 369 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
371 gpmc_onenand_data->flags |= ONENAND_SYNC_READ; 370 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
372 } 371 }
@@ -379,7 +378,8 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
379 err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, 378 err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
380 (unsigned long *)&gpmc_onenand_resource.start); 379 (unsigned long *)&gpmc_onenand_resource.start);
381 if (err < 0) { 380 if (err < 0) {
382 pr_err("%s: Cannot request GPMC CS\n", __func__); 381 dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
382 gpmc_onenand_data->cs, err);
383 return; 383 return;
384 } 384 }
385 385
@@ -387,7 +387,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
387 ONENAND_IO_SIZE - 1; 387 ONENAND_IO_SIZE - 1;
388 388
389 if (platform_device_register(&gpmc_onenand_device) < 0) { 389 if (platform_device_register(&gpmc_onenand_device) < 0) {
390 pr_err("%s: Unable to register OneNAND device\n", __func__); 390 dev_err(dev, "Unable to register OneNAND device\n");
391 gpmc_cs_free(gpmc_onenand_data->cs); 391 gpmc_cs_free(gpmc_onenand_data->cs);
392 return; 392 return;
393 } 393 }
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 11d0b756f098..61a063595e66 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -49,6 +49,10 @@ static struct platform_device gpmc_smc91x_device = {
49 .resource = gpmc_smc91x_resources, 49 .resource = gpmc_smc91x_resources,
50}; 50};
51 51
52static struct gpmc_settings smc91x_settings = {
53 .device_width = GPMC_DEVWIDTH_16BIT,
54};
55
52/* 56/*
53 * Set the gpmc timings for smc91c96. The timings are taken 57 * Set the gpmc timings for smc91c96. The timings are taken
54 * from the data sheet available at: 58 * from the data sheet available at:
@@ -67,18 +71,6 @@ static int smc91c96_gpmc_retime(void)
67 const int t7 = 5; /* Figure 12.4 write */ 71 const int t7 = 5; /* Figure 12.4 write */
68 const int t8 = 5; /* Figure 12.4 write */ 72 const int t8 = 5; /* Figure 12.4 write */
69 const int t20 = 185; /* Figure 12.2 read and 12.4 write */ 73 const int t20 = 185; /* Figure 12.2 read and 12.4 write */
70 u32 l;
71
72 l = GPMC_CONFIG1_DEVICESIZE_16;
73 if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
74 l |= GPMC_CONFIG1_MUXADDDATA;
75 if (gpmc_cfg->flags & GPMC_READ_MON)
76 l |= GPMC_CONFIG1_WAIT_READ_MON;
77 if (gpmc_cfg->flags & GPMC_WRITE_MON)
78 l |= GPMC_CONFIG1_WAIT_WRITE_MON;
79 if (gpmc_cfg->wait_pin)
80 l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin);
81 gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l);
82 74
83 /* 75 /*
84 * FIXME: Calculate the address and data bus muxed timings. 76 * FIXME: Calculate the address and data bus muxed timings.
@@ -104,7 +96,7 @@ static int smc91c96_gpmc_retime(void)
104 dev_t.t_cez_w = t4_w * 1000; 96 dev_t.t_cez_w = t4_w * 1000;
105 dev_t.t_wr_cycle = (t20 - t3) * 1000; 97 dev_t.t_wr_cycle = (t20 - t3) * 1000;
106 98
107 gpmc_calc_timings(&t, &dev_t); 99 gpmc_calc_timings(&t, &smc91x_settings, &dev_t);
108 100
109 return gpmc_cs_set_timings(gpmc_cfg->cs, &t); 101 return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
110} 102}
@@ -133,6 +125,18 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
133 gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f; 125 gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
134 gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK); 126 gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
135 127
128 if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
129 smc91x_settings.mux_add_data = GPMC_MUX_AD;
130 if (gpmc_cfg->flags & GPMC_READ_MON)
131 smc91x_settings.wait_on_read = true;
132 if (gpmc_cfg->flags & GPMC_WRITE_MON)
133 smc91x_settings.wait_on_write = true;
134 if (gpmc_cfg->wait_pin)
135 smc91x_settings.wait_pin = gpmc_cfg->wait_pin;
136 ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings);
137 if (ret < 0)
138 goto free1;
139
136 if (gpmc_cfg->retime) { 140 if (gpmc_cfg->retime) {
137 ret = gpmc_cfg->retime(); 141 ret = gpmc_cfg->retime();
138 if (ret != 0) 142 if (ret != 0)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6de31739b45c..ed946df5ad8a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -26,6 +26,7 @@
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/of.h> 28#include <linux/of.h>
29#include <linux/of_address.h>
29#include <linux/of_mtd.h> 30#include <linux/of_mtd.h>
30#include <linux/of_device.h> 31#include <linux/of_device.h>
31#include <linux/mtd/nand.h> 32#include <linux/mtd/nand.h>
@@ -91,9 +92,7 @@
91#define GPMC_CS_SIZE 0x30 92#define GPMC_CS_SIZE 0x30
92#define GPMC_BCH_SIZE 0x10 93#define GPMC_BCH_SIZE 0x10
93 94
94#define GPMC_MEM_START 0x00000000
95#define GPMC_MEM_END 0x3FFFFFFF 95#define GPMC_MEM_END 0x3FFFFFFF
96#define BOOT_ROM_SPACE 0x100000 /* 1MB */
97 96
98#define GPMC_CHUNK_SHIFT 24 /* 16 MB */ 97#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
99#define GPMC_SECTION_SHIFT 28 /* 128 MB */ 98#define GPMC_SECTION_SHIFT 28 /* 128 MB */
@@ -107,6 +106,9 @@
107 106
108#define GPMC_HAS_WR_ACCESS 0x1 107#define GPMC_HAS_WR_ACCESS 0x1
109#define GPMC_HAS_WR_DATA_MUX_BUS 0x2 108#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
109#define GPMC_HAS_MUX_AAD 0x4
110
111#define GPMC_NR_WAITPINS 4
110 112
111/* XXX: Only NAND irq has been considered,currently these are the only ones used 113/* XXX: Only NAND irq has been considered,currently these are the only ones used
112 */ 114 */
@@ -153,6 +155,7 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
153static DEFINE_SPINLOCK(gpmc_mem_lock); 155static DEFINE_SPINLOCK(gpmc_mem_lock);
154/* Define chip-selects as reserved by default until probe completes */ 156/* Define chip-selects as reserved by default until probe completes */
155static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); 157static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
158static unsigned int gpmc_nr_waitpins;
156static struct device *gpmc_dev; 159static struct device *gpmc_dev;
157static int gpmc_irq; 160static int gpmc_irq;
158static resource_size_t phys_base, mem_size; 161static resource_size_t phys_base, mem_size;
@@ -181,7 +184,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
181 __raw_writel(val, reg_addr); 184 __raw_writel(val, reg_addr);
182} 185}
183 186
184u32 gpmc_cs_read_reg(int cs, int idx) 187static u32 gpmc_cs_read_reg(int cs, int idx)
185{ 188{
186 void __iomem *reg_addr; 189 void __iomem *reg_addr;
187 190
@@ -190,7 +193,7 @@ u32 gpmc_cs_read_reg(int cs, int idx)
190} 193}
191 194
192/* TODO: Add support for gpmc_fck to clock framework and use it */ 195/* TODO: Add support for gpmc_fck to clock framework and use it */
193unsigned long gpmc_get_fclk_period(void) 196static unsigned long gpmc_get_fclk_period(void)
194{ 197{
195 unsigned long rate = clk_get_rate(gpmc_l3_clk); 198 unsigned long rate = clk_get_rate(gpmc_l3_clk);
196 199
@@ -205,7 +208,7 @@ unsigned long gpmc_get_fclk_period(void)
205 return rate; 208 return rate;
206} 209}
207 210
208unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 211static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
209{ 212{
210 unsigned long tick_ps; 213 unsigned long tick_ps;
211 214
@@ -215,7 +218,7 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
215 return (time_ns * 1000 + tick_ps - 1) / tick_ps; 218 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
216} 219}
217 220
218unsigned int gpmc_ps_to_ticks(unsigned int time_ps) 221static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
219{ 222{
220 unsigned long tick_ps; 223 unsigned long tick_ps;
221 224
@@ -230,13 +233,6 @@ unsigned int gpmc_ticks_to_ns(unsigned int ticks)
230 return ticks * gpmc_get_fclk_period() / 1000; 233 return ticks * gpmc_get_fclk_period() / 1000;
231} 234}
232 235
233unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
234{
235 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
236
237 return ticks * gpmc_get_fclk_period() / 1000;
238}
239
240static unsigned int gpmc_ticks_to_ps(unsigned int ticks) 236static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
241{ 237{
242 return ticks * gpmc_get_fclk_period(); 238 return ticks * gpmc_get_fclk_period();
@@ -405,11 +401,18 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
405 return 0; 401 return 0;
406} 402}
407 403
408static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) 404static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
409{ 405{
410 u32 l; 406 u32 l;
411 u32 mask; 407 u32 mask;
412 408
409 /*
410 * Ensure that base address is aligned on a
411 * boundary equal to or greater than size.
412 */
413 if (base & (size - 1))
414 return -EINVAL;
415
413 mask = (1 << GPMC_SECTION_SHIFT) - size; 416 mask = (1 << GPMC_SECTION_SHIFT) - size;
414 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 417 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
415 l &= ~0x3f; 418 l &= ~0x3f;
@@ -418,6 +421,8 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
418 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; 421 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
419 l |= GPMC_CONFIG7_CSVALID; 422 l |= GPMC_CONFIG7_CSVALID;
420 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 423 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
424
425 return 0;
421} 426}
422 427
423static void gpmc_cs_disable_mem(int cs) 428static void gpmc_cs_disable_mem(int cs)
@@ -448,22 +453,14 @@ static int gpmc_cs_mem_enabled(int cs)
448 return l & GPMC_CONFIG7_CSVALID; 453 return l & GPMC_CONFIG7_CSVALID;
449} 454}
450 455
451int gpmc_cs_set_reserved(int cs, int reserved) 456static void gpmc_cs_set_reserved(int cs, int reserved)
452{ 457{
453 if (cs > GPMC_CS_NUM)
454 return -ENODEV;
455
456 gpmc_cs_map &= ~(1 << cs); 458 gpmc_cs_map &= ~(1 << cs);
457 gpmc_cs_map |= (reserved ? 1 : 0) << cs; 459 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
458
459 return 0;
460} 460}
461 461
462int gpmc_cs_reserved(int cs) 462static bool gpmc_cs_reserved(int cs)
463{ 463{
464 if (cs > GPMC_CS_NUM)
465 return -ENODEV;
466
467 return gpmc_cs_map & (1 << cs); 464 return gpmc_cs_map & (1 << cs);
468} 465}
469 466
@@ -510,6 +507,39 @@ static int gpmc_cs_delete_mem(int cs)
510 return r; 507 return r;
511} 508}
512 509
510/**
511 * gpmc_cs_remap - remaps a chip-select physical base address
512 * @cs: chip-select to remap
513 * @base: physical base address to re-map chip-select to
514 *
515 * Re-maps a chip-select to a new physical base address specified by
516 * "base". Returns 0 on success and appropriate negative error code
517 * on failure.
518 */
519static int gpmc_cs_remap(int cs, u32 base)
520{
521 int ret;
522 u32 old_base, size;
523
524 if (cs > GPMC_CS_NUM)
525 return -ENODEV;
526 gpmc_cs_get_memconf(cs, &old_base, &size);
527 if (base == old_base)
528 return 0;
529 gpmc_cs_disable_mem(cs);
530 ret = gpmc_cs_delete_mem(cs);
531 if (ret < 0)
532 return ret;
533 ret = gpmc_cs_insert_mem(cs, base, size);
534 if (ret < 0)
535 return ret;
536 ret = gpmc_cs_enable_mem(cs, base, size);
537 if (ret < 0)
538 return ret;
539
540 return 0;
541}
542
513int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) 543int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
514{ 544{
515 struct resource *res = &gpmc_cs_mem[cs]; 545 struct resource *res = &gpmc_cs_mem[cs];
@@ -535,7 +565,12 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
535 if (r < 0) 565 if (r < 0)
536 goto out; 566 goto out;
537 567
538 gpmc_cs_enable_mem(cs, res->start, resource_size(res)); 568 r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
569 if (r < 0) {
570 release_resource(res);
571 goto out;
572 }
573
539 *base = res->start; 574 *base = res->start;
540 gpmc_cs_set_reserved(cs, 1); 575 gpmc_cs_set_reserved(cs, 1);
541out: 576out:
@@ -561,16 +596,14 @@ void gpmc_cs_free(int cs)
561EXPORT_SYMBOL(gpmc_cs_free); 596EXPORT_SYMBOL(gpmc_cs_free);
562 597
563/** 598/**
564 * gpmc_cs_configure - write request to configure gpmc 599 * gpmc_configure - write request to configure gpmc
565 * @cs: chip select number
566 * @cmd: command type 600 * @cmd: command type
567 * @wval: value to write 601 * @wval: value to write
568 * @return status of the operation 602 * @return status of the operation
569 */ 603 */
570int gpmc_cs_configure(int cs, int cmd, int wval) 604int gpmc_configure(int cmd, int wval)
571{ 605{
572 int err = 0; 606 u32 regval;
573 u32 regval = 0;
574 607
575 switch (cmd) { 608 switch (cmd) {
576 case GPMC_ENABLE_IRQ: 609 case GPMC_ENABLE_IRQ:
@@ -590,43 +623,14 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
590 gpmc_write_reg(GPMC_CONFIG, regval); 623 gpmc_write_reg(GPMC_CONFIG, regval);
591 break; 624 break;
592 625
593 case GPMC_CONFIG_RDY_BSY:
594 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
595 if (wval)
596 regval |= WR_RD_PIN_MONITORING;
597 else
598 regval &= ~WR_RD_PIN_MONITORING;
599 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
600 break;
601
602 case GPMC_CONFIG_DEV_SIZE:
603 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
604
605 /* clear 2 target bits */
606 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
607
608 /* set the proper value */
609 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
610
611 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
612 break;
613
614 case GPMC_CONFIG_DEV_TYPE:
615 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
616 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
617 if (wval == GPMC_DEVICETYPE_NOR)
618 regval |= GPMC_CONFIG1_MUXADDDATA;
619 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
620 break;
621
622 default: 626 default:
623 printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); 627 pr_err("%s: command not supported\n", __func__);
624 err = -EINVAL; 628 return -EINVAL;
625 } 629 }
626 630
627 return err; 631 return 0;
628} 632}
629EXPORT_SYMBOL(gpmc_cs_configure); 633EXPORT_SYMBOL(gpmc_configure);
630 634
631void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) 635void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
632{ 636{
@@ -781,16 +785,16 @@ static void gpmc_mem_exit(void)
781 785
782} 786}
783 787
784static int gpmc_mem_init(void) 788static void gpmc_mem_init(void)
785{ 789{
786 int cs, rc; 790 int cs;
787 unsigned long boot_rom_space = 0;
788 791
789 /* never allocate the first page, to facilitate bug detection; 792 /*
790 * even if we didn't boot from ROM. 793 * The first 1MB of GPMC address space is typically mapped to
794 * the internal ROM. Never allocate the first page, to
795 * facilitate bug detection; even if we didn't boot from ROM.
791 */ 796 */
792 boot_rom_space = BOOT_ROM_SPACE; 797 gpmc_mem_root.start = SZ_1M;
793 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
794 gpmc_mem_root.end = GPMC_MEM_END; 798 gpmc_mem_root.end = GPMC_MEM_END;
795 799
796 /* Reserve all regions that has been set up by bootloader */ 800 /* Reserve all regions that has been set up by bootloader */
@@ -800,16 +804,12 @@ static int gpmc_mem_init(void)
800 if (!gpmc_cs_mem_enabled(cs)) 804 if (!gpmc_cs_mem_enabled(cs))
801 continue; 805 continue;
802 gpmc_cs_get_memconf(cs, &base, &size); 806 gpmc_cs_get_memconf(cs, &base, &size);
803 rc = gpmc_cs_insert_mem(cs, base, size); 807 if (gpmc_cs_insert_mem(cs, base, size)) {
804 if (rc < 0) { 808 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
805 while (--cs >= 0) 809 __func__, cs, base, base + size);
806 if (gpmc_cs_mem_enabled(cs)) 810 gpmc_cs_disable_mem(cs);
807 gpmc_cs_delete_mem(cs);
808 return rc;
809 } 811 }
810 } 812 }
811
812 return 0;
813} 813}
814 814
815static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) 815static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
@@ -825,9 +825,9 @@ static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
825 825
826/* XXX: can the cycles be avoided ? */ 826/* XXX: can the cycles be avoided ? */
827static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, 827static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
828 struct gpmc_device_timings *dev_t) 828 struct gpmc_device_timings *dev_t,
829 bool mux)
829{ 830{
830 bool mux = dev_t->mux;
831 u32 temp; 831 u32 temp;
832 832
833 /* adv_rd_off */ 833 /* adv_rd_off */
@@ -880,9 +880,9 @@ static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
880} 880}
881 881
882static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, 882static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
883 struct gpmc_device_timings *dev_t) 883 struct gpmc_device_timings *dev_t,
884 bool mux)
884{ 885{
885 bool mux = dev_t->mux;
886 u32 temp; 886 u32 temp;
887 887
888 /* adv_wr_off */ 888 /* adv_wr_off */
@@ -942,9 +942,9 @@ static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
942} 942}
943 943
944static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, 944static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
945 struct gpmc_device_timings *dev_t) 945 struct gpmc_device_timings *dev_t,
946 bool mux)
946{ 947{
947 bool mux = dev_t->mux;
948 u32 temp; 948 u32 temp;
949 949
950 /* adv_rd_off */ 950 /* adv_rd_off */
@@ -982,9 +982,9 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
982} 982}
983 983
984static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, 984static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
985 struct gpmc_device_timings *dev_t) 985 struct gpmc_device_timings *dev_t,
986 bool mux)
986{ 987{
987 bool mux = dev_t->mux;
988 u32 temp; 988 u32 temp;
989 989
990 /* adv_wr_off */ 990 /* adv_wr_off */
@@ -1054,7 +1054,8 @@ static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1054} 1054}
1055 1055
1056static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, 1056static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1057 struct gpmc_device_timings *dev_t) 1057 struct gpmc_device_timings *dev_t,
1058 bool sync)
1058{ 1059{
1059 u32 temp; 1060 u32 temp;
1060 1061
@@ -1068,7 +1069,7 @@ static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1068 gpmc_t->cs_on + dev_t->t_ce_avd); 1069 gpmc_t->cs_on + dev_t->t_ce_avd);
1069 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); 1070 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1070 1071
1071 if (dev_t->sync_write || dev_t->sync_read) 1072 if (sync)
1072 gpmc_calc_sync_common_timings(gpmc_t, dev_t); 1073 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1073 1074
1074 return 0; 1075 return 0;
@@ -1103,21 +1104,29 @@ static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1103} 1104}
1104 1105
1105int gpmc_calc_timings(struct gpmc_timings *gpmc_t, 1106int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1106 struct gpmc_device_timings *dev_t) 1107 struct gpmc_settings *gpmc_s,
1108 struct gpmc_device_timings *dev_t)
1107{ 1109{
1110 bool mux = false, sync = false;
1111
1112 if (gpmc_s) {
1113 mux = gpmc_s->mux_add_data ? true : false;
1114 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1115 }
1116
1108 memset(gpmc_t, 0, sizeof(*gpmc_t)); 1117 memset(gpmc_t, 0, sizeof(*gpmc_t));
1109 1118
1110 gpmc_calc_common_timings(gpmc_t, dev_t); 1119 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1111 1120
1112 if (dev_t->sync_read) 1121 if (gpmc_s && gpmc_s->sync_read)
1113 gpmc_calc_sync_read_timings(gpmc_t, dev_t); 1122 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1114 else 1123 else
1115 gpmc_calc_async_read_timings(gpmc_t, dev_t); 1124 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1116 1125
1117 if (dev_t->sync_write) 1126 if (gpmc_s && gpmc_s->sync_write)
1118 gpmc_calc_sync_write_timings(gpmc_t, dev_t); 1127 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1119 else 1128 else
1120 gpmc_calc_async_write_timings(gpmc_t, dev_t); 1129 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1121 1130
1122 /* TODO: remove, see function definition */ 1131 /* TODO: remove, see function definition */
1123 gpmc_convert_ps_to_ns(gpmc_t); 1132 gpmc_convert_ps_to_ns(gpmc_t);
@@ -1125,6 +1134,90 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1125 return 0; 1134 return 0;
1126} 1135}
1127 1136
1137/**
1138 * gpmc_cs_program_settings - programs non-timing related settings
1139 * @cs: GPMC chip-select to program
1140 * @p: pointer to GPMC settings structure
1141 *
1142 * Programs non-timing related settings for a GPMC chip-select, such as
1143 * bus-width, burst configuration, etc. Function should be called once
1144 * for each chip-select that is being used and must be called before
1145 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1146 * register will be initialised to zero by this function. Returns 0 on
1147 * success and appropriate negative error code on failure.
1148 */
1149int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1150{
1151 u32 config1;
1152
1153 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1154 pr_err("%s: invalid width %d!", __func__, p->device_width);
1155 return -EINVAL;
1156 }
1157
1158 /* Address-data multiplexing not supported for NAND devices */
1159 if (p->device_nand && p->mux_add_data) {
1160 pr_err("%s: invalid configuration!\n", __func__);
1161 return -EINVAL;
1162 }
1163
1164 if ((p->mux_add_data > GPMC_MUX_AD) ||
1165 ((p->mux_add_data == GPMC_MUX_AAD) &&
1166 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1167 pr_err("%s: invalid multiplex configuration!\n", __func__);
1168 return -EINVAL;
1169 }
1170
1171 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1172 if (p->burst_read || p->burst_write) {
1173 switch (p->burst_len) {
1174 case GPMC_BURST_4:
1175 case GPMC_BURST_8:
1176 case GPMC_BURST_16:
1177 break;
1178 default:
1179 pr_err("%s: invalid page/burst-length (%d)\n",
1180 __func__, p->burst_len);
1181 return -EINVAL;
1182 }
1183 }
1184
1185 if ((p->wait_on_read || p->wait_on_write) &&
1186 (p->wait_pin > gpmc_nr_waitpins)) {
1187 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1188 return -EINVAL;
1189 }
1190
1191 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1192
1193 if (p->sync_read)
1194 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1195 if (p->sync_write)
1196 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1197 if (p->wait_on_read)
1198 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1199 if (p->wait_on_write)
1200 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1201 if (p->wait_on_read || p->wait_on_write)
1202 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1203 if (p->device_nand)
1204 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1205 if (p->mux_add_data)
1206 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1207 if (p->burst_read)
1208 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1209 if (p->burst_write)
1210 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1211 if (p->burst_read || p->burst_write) {
1212 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1213 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1214 }
1215
1216 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1217
1218 return 0;
1219}
1220
1128#ifdef CONFIG_OF 1221#ifdef CONFIG_OF
1129static struct of_device_id gpmc_dt_ids[] = { 1222static struct of_device_id gpmc_dt_ids[] = {
1130 { .compatible = "ti,omap2420-gpmc" }, 1223 { .compatible = "ti,omap2420-gpmc" },
@@ -1136,70 +1229,110 @@ static struct of_device_id gpmc_dt_ids[] = {
1136}; 1229};
1137MODULE_DEVICE_TABLE(of, gpmc_dt_ids); 1230MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1138 1231
1232/**
1233 * gpmc_read_settings_dt - read gpmc settings from device-tree
1234 * @np: pointer to device-tree node for a gpmc child device
1235 * @p: pointer to gpmc settings structure
1236 *
1237 * Reads the GPMC settings for a GPMC child device from device-tree and
1238 * stores them in the GPMC settings structure passed. The GPMC settings
1239 * structure is initialised to zero by this function and so any
1240 * previously stored settings will be cleared.
1241 */
1242void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1243{
1244 memset(p, 0, sizeof(struct gpmc_settings));
1245
1246 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1247 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1248 p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
1249 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1250 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1251
1252 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1253 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1254 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1255 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1256 if (!p->burst_read && !p->burst_write)
1257 pr_warn("%s: page/burst-length set but not used!\n",
1258 __func__);
1259 }
1260
1261 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1262 p->wait_on_read = of_property_read_bool(np,
1263 "gpmc,wait-on-read");
1264 p->wait_on_write = of_property_read_bool(np,
1265 "gpmc,wait-on-write");
1266 if (!p->wait_on_read && !p->wait_on_write)
1267 pr_warn("%s: read/write wait monitoring not enabled!\n",
1268 __func__);
1269 }
1270}
1271
1139static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, 1272static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1140 struct gpmc_timings *gpmc_t) 1273 struct gpmc_timings *gpmc_t)
1141{ 1274{
1142 u32 val; 1275 struct gpmc_bool_timings *p;
1276
1277 if (!np || !gpmc_t)
1278 return;
1143 1279
1144 memset(gpmc_t, 0, sizeof(*gpmc_t)); 1280 memset(gpmc_t, 0, sizeof(*gpmc_t));
1145 1281
1146 /* minimum clock period for syncronous mode */ 1282 /* minimum clock period for syncronous mode */
1147 if (!of_property_read_u32(np, "gpmc,sync-clk", &val)) 1283 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1148 gpmc_t->sync_clk = val;
1149 1284
1150 /* chip select timtings */ 1285 /* chip select timtings */
1151 if (!of_property_read_u32(np, "gpmc,cs-on", &val)) 1286 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1152 gpmc_t->cs_on = val; 1287 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1153 1288 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1154 if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
1155 gpmc_t->cs_rd_off = val;
1156
1157 if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
1158 gpmc_t->cs_wr_off = val;
1159 1289
1160 /* ADV signal timings */ 1290 /* ADV signal timings */
1161 if (!of_property_read_u32(np, "gpmc,adv-on", &val)) 1291 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1162 gpmc_t->adv_on = val; 1292 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1163 1293 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1164 if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
1165 gpmc_t->adv_rd_off = val;
1166
1167 if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
1168 gpmc_t->adv_wr_off = val;
1169 1294
1170 /* WE signal timings */ 1295 /* WE signal timings */
1171 if (!of_property_read_u32(np, "gpmc,we-on", &val)) 1296 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1172 gpmc_t->we_on = val; 1297 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1173
1174 if (!of_property_read_u32(np, "gpmc,we-off", &val))
1175 gpmc_t->we_off = val;
1176 1298
1177 /* OE signal timings */ 1299 /* OE signal timings */
1178 if (!of_property_read_u32(np, "gpmc,oe-on", &val)) 1300 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1179 gpmc_t->oe_on = val; 1301 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1180
1181 if (!of_property_read_u32(np, "gpmc,oe-off", &val))
1182 gpmc_t->oe_off = val;
1183 1302
1184 /* access and cycle timings */ 1303 /* access and cycle timings */
1185 if (!of_property_read_u32(np, "gpmc,page-burst-access", &val)) 1304 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1186 gpmc_t->page_burst_access = val; 1305 &gpmc_t->page_burst_access);
1187 1306 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1188 if (!of_property_read_u32(np, "gpmc,access", &val)) 1307 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1189 gpmc_t->access = val; 1308 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1190 1309 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1191 if (!of_property_read_u32(np, "gpmc,rd-cycle", &val)) 1310 &gpmc_t->bus_turnaround);
1192 gpmc_t->rd_cycle = val; 1311 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1193 1312 &gpmc_t->cycle2cycle_delay);
1194 if (!of_property_read_u32(np, "gpmc,wr-cycle", &val)) 1313 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1195 gpmc_t->wr_cycle = val; 1314 &gpmc_t->wait_monitoring);
1196 1315 of_property_read_u32(np, "gpmc,clk-activation-ns",
1197 /* only for OMAP3430 */ 1316 &gpmc_t->clk_activation);
1198 if (!of_property_read_u32(np, "gpmc,wr-access", &val)) 1317
1199 gpmc_t->wr_access = val; 1318 /* only applicable to OMAP3+ */
1200 1319 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1201 if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val)) 1320 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1202 gpmc_t->wr_data_mux_bus = val; 1321 &gpmc_t->wr_data_mux_bus);
1322
1323 /* bool timing parameters */
1324 p = &gpmc_t->bool_timings;
1325
1326 p->cycle2cyclediffcsen =
1327 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1328 p->cycle2cyclesamecsen =
1329 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1330 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1331 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1332 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1333 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1334 p->time_para_granularity =
1335 of_property_read_bool(np, "gpmc,time-para-granularity");
1203} 1336}
1204 1337
1205#ifdef CONFIG_MTD_NAND 1338#ifdef CONFIG_MTD_NAND
@@ -1295,6 +1428,81 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev,
1295} 1428}
1296#endif 1429#endif
1297 1430
1431/**
1432 * gpmc_probe_generic_child - configures the gpmc for a child device
1433 * @pdev: pointer to gpmc platform device
1434 * @child: pointer to device-tree node for child device
1435 *
1436 * Allocates and configures a GPMC chip-select for a child device.
1437 * Returns 0 on success and appropriate negative error code on failure.
1438 */
1439static int gpmc_probe_generic_child(struct platform_device *pdev,
1440 struct device_node *child)
1441{
1442 struct gpmc_settings gpmc_s;
1443 struct gpmc_timings gpmc_t;
1444 struct resource res;
1445 unsigned long base;
1446 int ret, cs;
1447
1448 if (of_property_read_u32(child, "reg", &cs) < 0) {
1449 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1450 child->full_name);
1451 return -ENODEV;
1452 }
1453
1454 if (of_address_to_resource(child, 0, &res) < 0) {
1455 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1456 child->full_name);
1457 return -ENODEV;
1458 }
1459
1460 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1461 if (ret < 0) {
1462 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1463 return ret;
1464 }
1465
1466 /*
1467 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1468 * location in the gpmc address space. When booting with
1469 * device-tree we want the NOR flash to be mapped to the
1470 * location specified in the device-tree blob. So remap the
1471 * CS to this location. Once DT migration is complete should
1472 * just make gpmc_cs_request() map a specific address.
1473 */
1474 ret = gpmc_cs_remap(cs, res.start);
1475 if (ret < 0) {
1476 dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",
1477 cs, res.start);
1478 goto err;
1479 }
1480
1481 gpmc_read_settings_dt(child, &gpmc_s);
1482
1483 ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1484 if (ret < 0)
1485 goto err;
1486
1487 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1488 if (ret < 0)
1489 goto err;
1490
1491 gpmc_read_timings_dt(child, &gpmc_t);
1492 gpmc_cs_set_timings(cs, &gpmc_t);
1493
1494 if (of_platform_device_create(child, NULL, &pdev->dev))
1495 return 0;
1496
1497 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
1498 ret = -ENODEV;
1499
1500err:
1501 gpmc_cs_free(cs);
1502
1503 return ret;
1504}
1505
1298static int gpmc_probe_dt(struct platform_device *pdev) 1506static int gpmc_probe_dt(struct platform_device *pdev)
1299{ 1507{
1300 int ret; 1508 int ret;
@@ -1305,6 +1513,13 @@ static int gpmc_probe_dt(struct platform_device *pdev)
1305 if (!of_id) 1513 if (!of_id)
1306 return 0; 1514 return 0;
1307 1515
1516 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
1517 &gpmc_nr_waitpins);
1518 if (ret < 0) {
1519 pr_err("%s: number of wait pins not found!\n", __func__);
1520 return ret;
1521 }
1522
1308 for_each_node_by_name(child, "nand") { 1523 for_each_node_by_name(child, "nand") {
1309 ret = gpmc_probe_nand_child(pdev, child); 1524 ret = gpmc_probe_nand_child(pdev, child);
1310 if (ret < 0) { 1525 if (ret < 0) {
@@ -1320,6 +1535,23 @@ static int gpmc_probe_dt(struct platform_device *pdev)
1320 return ret; 1535 return ret;
1321 } 1536 }
1322 } 1537 }
1538
1539 for_each_node_by_name(child, "nor") {
1540 ret = gpmc_probe_generic_child(pdev, child);
1541 if (ret < 0) {
1542 of_node_put(child);
1543 return ret;
1544 }
1545 }
1546
1547 for_each_node_by_name(child, "ethernet") {
1548 ret = gpmc_probe_generic_child(pdev, child);
1549 if (ret < 0) {
1550 of_node_put(child);
1551 return ret;
1552 }
1553 }
1554
1323 return 0; 1555 return 0;
1324} 1556}
1325#else 1557#else
@@ -1364,18 +1596,27 @@ static int gpmc_probe(struct platform_device *pdev)
1364 gpmc_dev = &pdev->dev; 1596 gpmc_dev = &pdev->dev;
1365 1597
1366 l = gpmc_read_reg(GPMC_REVISION); 1598 l = gpmc_read_reg(GPMC_REVISION);
1599
1600 /*
1601 * FIXME: Once device-tree migration is complete the below flags
1602 * should be populated based upon the device-tree compatible
1603 * string. For now just use the IP revision. OMAP3+ devices have
1604 * the wr_access and wr_data_mux_bus register fields. OMAP4+
1605 * devices support the addr-addr-data multiplex protocol.
1606 *
1607 * GPMC IP revisions:
1608 * - OMAP24xx = 2.0
1609 * - OMAP3xxx = 5.0
1610 * - OMAP44xx/54xx/AM335x = 6.0
1611 */
1367 if (GPMC_REVISION_MAJOR(l) > 0x4) 1612 if (GPMC_REVISION_MAJOR(l) > 0x4)
1368 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; 1613 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1614 if (GPMC_REVISION_MAJOR(l) > 0x5)
1615 gpmc_capability |= GPMC_HAS_MUX_AAD;
1369 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), 1616 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1370 GPMC_REVISION_MINOR(l)); 1617 GPMC_REVISION_MINOR(l));
1371 1618
1372 rc = gpmc_mem_init(); 1619 gpmc_mem_init();
1373 if (rc < 0) {
1374 clk_disable_unprepare(gpmc_l3_clk);
1375 clk_put(gpmc_l3_clk);
1376 dev_err(gpmc_dev, "failed to reserve memory\n");
1377 return rc;
1378 }
1379 1620
1380 if (gpmc_setup_irq() < 0) 1621 if (gpmc_setup_irq() < 0)
1381 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); 1622 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
@@ -1383,6 +1624,9 @@ static int gpmc_probe(struct platform_device *pdev)
1383 /* Now the GPMC is initialised, unreserve the chip-selects */ 1624 /* Now the GPMC is initialised, unreserve the chip-selects */
1384 gpmc_cs_map = 0; 1625 gpmc_cs_map = 0;
1385 1626
1627 if (!pdev->dev.of_node)
1628 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
1629
1386 rc = gpmc_probe_dt(pdev); 1630 rc = gpmc_probe_dt(pdev);
1387 if (rc < 0) { 1631 if (rc < 0) {
1388 clk_disable_unprepare(gpmc_l3_clk); 1632 clk_disable_unprepare(gpmc_l3_clk);
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index fe0a844d5007..707f6d58edd5 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -58,7 +58,7 @@
58#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 58#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
59#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) 59#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
60#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 60#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
61#define GPMC_CONFIG1_MUXADDDATA (1 << 9) 61#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
62#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 62#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
63#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) 63#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
64#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 64#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
@@ -73,6 +73,13 @@
73#define GPMC_IRQ_FIFOEVENTENABLE 0x01 73#define GPMC_IRQ_FIFOEVENTENABLE 0x01
74#define GPMC_IRQ_COUNT_EVENT 0x02 74#define GPMC_IRQ_COUNT_EVENT 0x02
75 75
76#define GPMC_BURST_4 4 /* 4 word burst */
77#define GPMC_BURST_8 8 /* 8 word burst */
78#define GPMC_BURST_16 16 /* 16 word burst */
79#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
80#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
81#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
82#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
76 83
77/* bool type time settings */ 84/* bool type time settings */
78struct gpmc_bool_timings { 85struct gpmc_bool_timings {
@@ -178,10 +185,6 @@ struct gpmc_device_timings {
178 u8 cyc_wpl; /* write deassertion time in cycles */ 185 u8 cyc_wpl; /* write deassertion time in cycles */
179 u32 cyc_iaa; /* initial access time in cycles */ 186 u32 cyc_iaa; /* initial access time in cycles */
180 187
181 bool mux; /* address & data muxed */
182 bool sync_write;/* synchronous write */
183 bool sync_read; /* synchronous read */
184
185 /* extra delays */ 188 /* extra delays */
186 bool ce_xdelay; 189 bool ce_xdelay;
187 bool avd_xdelay; 190 bool avd_xdelay;
@@ -189,28 +192,40 @@ struct gpmc_device_timings {
189 bool we_xdelay; 192 bool we_xdelay;
190}; 193};
191 194
195struct gpmc_settings {
196 bool burst_wrap; /* enables wrap bursting */
197 bool burst_read; /* enables read page/burst mode */
198 bool burst_write; /* enables write page/burst mode */
199 bool device_nand; /* device is NAND */
200 bool sync_read; /* enables synchronous reads */
201 bool sync_write; /* enables synchronous writes */
202 bool wait_on_read; /* monitor wait on reads */
203 bool wait_on_write; /* monitor wait on writes */
204 u32 burst_len; /* page/burst length */
205 u32 device_width; /* device bus width (8 or 16 bit) */
206 u32 mux_add_data; /* multiplex address & data */
207 u32 wait_pin; /* wait-pin to be used */
208};
209
192extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t, 210extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
193 struct gpmc_device_timings *dev_t); 211 struct gpmc_settings *gpmc_s,
212 struct gpmc_device_timings *dev_t);
194 213
195extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); 214extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
196extern int gpmc_get_client_irq(unsigned irq_config); 215extern int gpmc_get_client_irq(unsigned irq_config);
197 216
198extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
199extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
200extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); 217extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
201extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
202extern unsigned long gpmc_get_fclk_period(void);
203 218
204extern void gpmc_cs_write_reg(int cs, int idx, u32 val); 219extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
205extern u32 gpmc_cs_read_reg(int cs, int idx);
206extern int gpmc_calc_divider(unsigned int sync_clk); 220extern int gpmc_calc_divider(unsigned int sync_clk);
207extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); 221extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
222extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
208extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); 223extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
209extern void gpmc_cs_free(int cs); 224extern void gpmc_cs_free(int cs);
210extern int gpmc_cs_set_reserved(int cs, int reserved);
211extern int gpmc_cs_reserved(int cs);
212extern void omap3_gpmc_save_context(void); 225extern void omap3_gpmc_save_context(void);
213extern void omap3_gpmc_restore_context(void); 226extern void omap3_gpmc_restore_context(void);
214extern int gpmc_cs_configure(int cs, int cmd, int wval); 227extern int gpmc_configure(int cmd, int wval);
228extern void gpmc_read_settings_dt(struct device_node *np,
229 struct gpmc_settings *p);
215 230
216#endif 231#endif
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index c5a3c6f9504e..e832bc7b8e2d 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -8,6 +8,7 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <linux/err.h>
11#include <linux/string.h> 12#include <linux/string.h>
12#include <linux/types.h> 13#include <linux/types.h>
13#include <linux/errno.h> 14#include <linux/errno.h>
@@ -26,6 +27,24 @@
26static u8 async_cs, sync_cs; 27static u8 async_cs, sync_cs;
27static unsigned refclk_psec; 28static unsigned refclk_psec;
28 29
30static struct gpmc_settings tusb_async = {
31 .wait_on_read = true,
32 .wait_on_write = true,
33 .device_width = GPMC_DEVWIDTH_16BIT,
34 .mux_add_data = GPMC_MUX_AD,
35};
36
37static struct gpmc_settings tusb_sync = {
38 .burst_read = true,
39 .burst_write = true,
40 .sync_read = true,
41 .sync_write = true,
42 .wait_on_read = true,
43 .wait_on_write = true,
44 .burst_len = GPMC_BURST_16,
45 .device_width = GPMC_DEVWIDTH_16BIT,
46 .mux_add_data = GPMC_MUX_AD,
47};
29 48
30/* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */ 49/* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
31 50
@@ -37,8 +56,6 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
37 56
38 memset(&dev_t, 0, sizeof(dev_t)); 57 memset(&dev_t, 0, sizeof(dev_t));
39 58
40 dev_t.mux = true;
41
42 dev_t.t_ceasu = 8 * 1000; 59 dev_t.t_ceasu = 8 * 1000;
43 dev_t.t_avdasu = t_acsnh_advnh - 7000; 60 dev_t.t_avdasu = t_acsnh_advnh - 7000;
44 dev_t.t_ce_avd = 1000; 61 dev_t.t_ce_avd = 1000;
@@ -52,7 +69,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
52 dev_t.t_wpl = 300; 69 dev_t.t_wpl = 300;
53 dev_t.cyc_aavdh_we = 1; 70 dev_t.cyc_aavdh_we = 1;
54 71
55 gpmc_calc_timings(&t, &dev_t); 72 gpmc_calc_timings(&t, &tusb_async, &dev_t);
56 73
57 return gpmc_cs_set_timings(async_cs, &t); 74 return gpmc_cs_set_timings(async_cs, &t);
58} 75}
@@ -65,10 +82,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
65 82
66 memset(&dev_t, 0, sizeof(dev_t)); 83 memset(&dev_t, 0, sizeof(dev_t));
67 84
68 dev_t.mux = true;
69 dev_t.sync_read = true;
70 dev_t.sync_write = true;
71
72 dev_t.clk = 11100; 85 dev_t.clk = 11100;
73 dev_t.t_bacc = 1000; 86 dev_t.t_bacc = 1000;
74 dev_t.t_ces = 1000; 87 dev_t.t_ces = 1000;
@@ -84,7 +97,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
84 dev_t.cyc_wpl = 6; 97 dev_t.cyc_wpl = 6;
85 dev_t.t_ce_rdyz = 7000; 98 dev_t.t_ce_rdyz = 7000;
86 99
87 gpmc_calc_timings(&t, &dev_t); 100 gpmc_calc_timings(&t, &tusb_sync, &dev_t);
88 101
89 return gpmc_cs_set_timings(sync_cs, &t); 102 return gpmc_cs_set_timings(sync_cs, &t);
90} 103}
@@ -165,18 +178,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
165 return status; 178 return status;
166 } 179 }
167 tusb_resources[0].end = tusb_resources[0].start + 0x9ff; 180 tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
181 tusb_async.wait_pin = waitpin;
168 async_cs = async; 182 async_cs = async;
169 gpmc_cs_write_reg(async, GPMC_CS_CONFIG1,
170 GPMC_CONFIG1_PAGE_LEN(2)
171 | GPMC_CONFIG1_WAIT_READ_MON
172 | GPMC_CONFIG1_WAIT_WRITE_MON
173 | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
174 | GPMC_CONFIG1_READTYPE_ASYNC
175 | GPMC_CONFIG1_WRITETYPE_ASYNC
176 | GPMC_CONFIG1_DEVICESIZE_16
177 | GPMC_CONFIG1_DEVICETYPE_NOR
178 | GPMC_CONFIG1_MUXADDDATA);
179 183
184 status = gpmc_cs_program_settings(async_cs, &tusb_async);
185 if (status < 0)
186 return status;
180 187
181 /* SYNC region, primarily for DMA */ 188 /* SYNC region, primarily for DMA */
182 status = gpmc_cs_request(sync, SZ_16M, (unsigned long *) 189 status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
@@ -186,21 +193,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
186 return status; 193 return status;
187 } 194 }
188 tusb_resources[1].end = tusb_resources[1].start + 0x9ff; 195 tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
196 tusb_sync.wait_pin = waitpin;
189 sync_cs = sync; 197 sync_cs = sync;
190 gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1, 198
191 GPMC_CONFIG1_READMULTIPLE_SUPP 199 status = gpmc_cs_program_settings(sync_cs, &tusb_sync);
192 | GPMC_CONFIG1_READTYPE_SYNC 200 if (status < 0)
193 | GPMC_CONFIG1_WRITEMULTIPLE_SUPP 201 return status;
194 | GPMC_CONFIG1_WRITETYPE_SYNC
195 | GPMC_CONFIG1_PAGE_LEN(2)
196 | GPMC_CONFIG1_WAIT_READ_MON
197 | GPMC_CONFIG1_WAIT_WRITE_MON
198 | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
199 | GPMC_CONFIG1_DEVICESIZE_16
200 | GPMC_CONFIG1_DEVICETYPE_NOR
201 | GPMC_CONFIG1_MUXADDDATA
202 /* fclk divider gets set later */
203 );
204 202
205 /* IRQ */ 203 /* IRQ */
206 status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq"); 204 status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 02:01:48 -0400