Merge branches 'heads/pinmux' and 'heads/soc' into phy-rcar-usb-base

This branch acts as a base for adding USB support to
r8A7778/BOCK-W and r8A7779/Marzen.

It includes the soc branch to provide dependencies in
the r8A7778 clock code.

It includes pinmux to provide pinmux initialisation for Bock-W
which is a dependency.

Conflicts:
	arch/arm/mach-shmobile/Kconfig
	arch/arm/mach-shmobile/include/mach/r8a7778.h
	arch/arm/mach-shmobile/setup-r8a7778.c

11 files changed, 924 insertions, 132 deletions

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 06da4d36bc7c..5414402938a5 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -36,7 +36,7 @@ config ARCH_R8A7740
         select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7778
-        bool "R-Car M1 (R8A77780)"
+        bool "R-Car M1A (R8A77781)"
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select CPU_V7
         select SH_CLK_CPG
@@ -170,6 +170,8 @@ config MACH_KZM9D
 config MACH_KZM9G
         bool "KZM-A9-GT board"
         depends on ARCH_SH73A0
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select SND_SOC_AK4642 if SND_SIMPLE_CARD
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index e710c00c3822..f6227bb10aca 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -22,15 +22,43 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x270
 
-#define MPCKCR 0xe6150080
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR5 0xe6150144
 
+#define FRQCRA          0xE6150000
+#define FRQCRB          0xE6150004
+#define VCLKCR1         0xE6150008
+#define VCLKCR2         0xE615000C
+#define VCLKCR3         0xE615001C
+#define VCLKCR4         0xE6150014
+#define VCLKCR5         0xE6150034
+#define ZBCKCR          0xE6150010
+#define SD0CKCR         0xE6150074
+#define SD1CKCR         0xE6150078
+#define SD2CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define FSIACKCR        0xE6150018
+#define FSIBCKCR        0xE6150090
+#define MPCKCR          0xe6150080
+#define SPUVCKCR        0xE6150094
+#define HSICKCR         0xE615026C
+#define M4CKCR          0xE6150098
+#define PLLECR          0xE61500D0
+#define PLL1CR          0xE6150028
+#define PLL2CR          0xE615002C
+#define PLL2SCR         0xE61501F4
+#define PLL2HCR         0xE61501E4
+#define CKSCR           0xE61500C0
+
+#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
+
 static struct clk_mapping cpg_mapping = {
         .phys   = CPG_BASE,
         .len    = CPG_LEN,
@@ -51,29 +79,326 @@ static struct clk extal2_clk = {
         .mapping        = &cpg_mapping,
 };
 
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
+};
+
+SH_CLK_RATIO(div2,      1, 2);
+SH_CLK_RATIO(div4,      1, 4);
+
+SH_FIXED_RATIO_CLK(main_div2_clk,       main_clk,               div2);
+SH_FIXED_RATIO_CLK(extal1_div2_clk,     extal1_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div2_clk,     extal2_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div4_clk,     extal2_clk,             div4);
+
+/* External FSIACK/FSIBCK clock */
+static struct clk fsiack_clk = {
+};
+
+static struct clk fsibck_clk = {
+};
+
+/*
+ *              PLL clocks
+ */
+static struct clk *pll_parent_main[] = {
+        [0] = &main_clk,
+        [1] = &main_div2_clk
+};
+
+static struct clk *pll_parent_main_extal[8] = {
+        [0] = &main_div2_clk,
+        [1] = &extal2_div2_clk,
+        [3] = &extal2_div4_clk,
+        [4] = &main_clk,
+        [5] = &extal2_clk,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
+                mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
+
+        return clk->parent->rate * mult;
+}
+
+static int pll_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 val;
+        int i, ret;
+
+        if (!clk->parent_table || !clk->parent_num)
+                return -EINVAL;
+
+        /* Search the parent */
+        for (i = 0; i < clk->parent_num; i++)
+                if (clk->parent_table[i] == parent)
+                        break;
+
+        if (i == clk->parent_num)
+                return -ENODEV;
+
+        ret = clk_reparent(clk, parent);
+        if (ret < 0)
+                return ret;
+
+        val = ioread32(clk->mapped_reg) &
+                ~(((1 << clk->src_width) - 1) << clk->src_shift);
+
+        iowrite32(val | i << clk->src_shift, clk->mapped_reg);
+
+        return 0;
+}
+
+static struct sh_clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+        .set_parent     = pll_set_parent,
+};
+
+#define PLL_CLOCK(name, p, pt, w, s, reg, e)            \
+        static struct clk name = {                      \
+                .ops            = &pll_clk_ops,         \
+                .flags          = CLK_ENABLE_ON_INIT,   \
+                .parent         = p,                    \
+                .parent_table   = pt,                   \
+                .parent_num     = ARRAY_SIZE(pt),       \
+                .src_width      = w,                    \