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authorSimon Horman <horms+renesas@verge.net.au>2013-06-11 01:58:57 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-06-11 01:58:57 -0400
commitae8b378faea7f04d4517b22f5d70d824adcbc4dc (patch)
tree54f50bcbd0baa55be24ac7ffbf547b4b55d046a4
parent5fcf4a3c3a5bc08bf72a50ef1332501a3c1b96bb (diff)
parent413bfd0e67894c930242482cd15ac09a800e2ab8 (diff)
Merge branches 'heads/pinmux' and 'heads/soc' into phy-rcar-usb-base
This branch acts as a base for adding USB support to r8A7778/BOCK-W and r8A7779/Marzen. It includes the soc branch to provide dependencies in the r8A7778 clock code. It includes pinmux to provide pinmux initialisation for Bock-W which is a dependency. Conflicts: arch/arm/mach-shmobile/Kconfig arch/arm/mach-shmobile/include/mach/r8a7778.h arch/arm/mach-shmobile/setup-r8a7778.c
Diffstat
-rw-r--r--arch/arm/mach-shmobile/Kconfig4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a73a4.c375
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c11
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c156
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c238
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c111
-rw-r--r--arch/arm/mach-shmobile/include/mach/clock.h8
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7778.h2
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c52
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c95
11 files changed, 924 insertions, 132 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 06da4d36bc7c..5414402938a5 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -36,7 +36,7 @@ config ARCH_R8A7740
36 select RENESAS_INTC_IRQPIN 36 select RENESAS_INTC_IRQPIN
37 37
38config ARCH_R8A7778 38config ARCH_R8A7778
39 bool "R-Car M1 (R8A77780)" 39 bool "R-Car M1A (R8A77781)"
40 select ARCH_WANT_OPTIONAL_GPIOLIB 40 select ARCH_WANT_OPTIONAL_GPIOLIB
41 select CPU_V7 41 select CPU_V7
42 select SH_CLK_CPG 42 select SH_CLK_CPG
@@ -170,6 +170,8 @@ config MACH_KZM9D
170config MACH_KZM9G 170config MACH_KZM9G
171 bool "KZM-A9-GT board" 171 bool "KZM-A9-GT board"
172 depends on ARCH_SH73A0 172 depends on ARCH_SH73A0
173 select ARCH_HAS_CPUFREQ
174 select ARCH_HAS_OPP
173 select ARCH_REQUIRE_GPIOLIB 175 select ARCH_REQUIRE_GPIOLIB
174 select REGULATOR_FIXED_VOLTAGE if REGULATOR 176 select REGULATOR_FIXED_VOLTAGE if REGULATOR
175 select SND_SOC_AK4642 if SND_SIMPLE_CARD 177 select SND_SOC_AK4642 if SND_SIMPLE_CARD
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index e710c00c3822..f6227bb10aca 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -22,15 +22,43 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/sh_clk.h> 23#include <linux/sh_clk.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <mach/clock.h>
25#include <mach/common.h> 26#include <mach/common.h>
26 27
27#define CPG_BASE 0xe6150000 28#define CPG_BASE 0xe6150000
28#define CPG_LEN 0x270 29#define CPG_LEN 0x270
29 30
30#define MPCKCR 0xe6150080
31#define SMSTPCR2 0xe6150138 31#define SMSTPCR2 0xe6150138
32#define SMSTPCR5 0xe6150144 32#define SMSTPCR5 0xe6150144
33 33
34#define FRQCRA 0xE6150000
35#define FRQCRB 0xE6150004
36#define VCLKCR1 0xE6150008
37#define VCLKCR2 0xE615000C
38#define VCLKCR3 0xE615001C
39#define VCLKCR4 0xE6150014
40#define VCLKCR5 0xE6150034
41#define ZBCKCR 0xE6150010
42#define SD0CKCR 0xE6150074
43#define SD1CKCR 0xE6150078
44#define SD2CKCR 0xE615007C
45#define MMC0CKCR 0xE6150240
46#define MMC1CKCR 0xE6150244
47#define FSIACKCR 0xE6150018
48#define FSIBCKCR 0xE6150090
49#define MPCKCR 0xe6150080
50#define SPUVCKCR 0xE6150094
51#define HSICKCR 0xE615026C
52#define M4CKCR 0xE6150098
53#define PLLECR 0xE61500D0
54#define PLL1CR 0xE6150028
55#define PLL2CR 0xE615002C
56#define PLL2SCR 0xE61501F4
57#define PLL2HCR 0xE61501E4
58#define CKSCR 0xE61500C0
59
60#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
61
34static struct clk_mapping cpg_mapping = { 62static struct clk_mapping cpg_mapping = {
35 .phys = CPG_BASE, 63 .phys = CPG_BASE,
36 .len = CPG_LEN, 64 .len = CPG_LEN,
@@ -51,29 +79,326 @@ static struct clk extal2_clk = {
51 .mapping = &cpg_mapping, 79 .mapping = &cpg_mapping,
52}; 80};
53 81
82static struct sh_clk_ops followparent_clk_ops = {
83 .recalc = followparent_recalc,
84};
85
86static struct clk main_clk = {
87 /* .parent will be set r8a73a4_clock_init */
88 .ops = &followparent_clk_ops,
89};
90
91SH_CLK_RATIO(div2, 1, 2);
92SH_CLK_RATIO(div4, 1, 4);
93
94SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
95SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
96SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
97SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4);
98
99/* External FSIACK/FSIBCK clock */
100static struct clk fsiack_clk = {
101};
102
103static struct clk fsibck_clk = {
104};
105
106/*
107 * PLL clocks
108 */
109static struct clk *pll_parent_main[] = {
110 [0] = &main_clk,
111 [1] = &main_div2_clk
112};
113
114static struct clk *pll_parent_main_extal[8] = {
115 [0] = &main_div2_clk,
116 [1] = &extal2_div2_clk,
117 [3] = &extal2_div4_clk,
118 [4] = &main_clk,
119 [5] = &extal2_clk,
120};
121
122static unsigned long pll_recalc(struct clk *clk)
123{
124 unsigned long mult = 1;
125
126 if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
127 mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
128
129 return clk->parent->rate * mult;
130}
131
132static int pll_set_parent(struct clk *clk, struct clk *parent)
133{
134 u32 val;
135 int i, ret;
136
137 if (!clk->parent_table || !clk->parent_num)
138 return -EINVAL;
139
140 /* Search the parent */
141 for (i = 0; i < clk->parent_num; i++)
142 if (clk->parent_table[i] == parent)
143 break;
144
145 if (i == clk->parent_num)
146 return -ENODEV;
147
148 ret = clk_reparent(clk, parent);
149 if (ret < 0)
150 return ret;
151
152 val = ioread32(clk->mapped_reg) &
153 ~(((1 << clk->src_width) - 1) << clk->src_shift);
154
155 iowrite32(val | i << clk->src_shift, clk->mapped_reg);
156
157 return 0;
158}
159
160static struct sh_clk_ops pll_clk_ops = {
161 .recalc = pll_recalc,
162 .set_parent = pll_set_parent,
163};
164
165#define PLL_CLOCK(name, p, pt, w, s, reg, e) \
166 static struct clk name = { \
167 .ops = &pll_clk_ops, \
168 .flags = CLK_ENABLE_ON_INIT, \
169 .parent = p, \
170 .parent_table = pt, \
171 .parent_num = ARRAY_SIZE(pt), \
172 .src_width = w, \
173 .src_shift = s, \
174 .enable_reg = (void __iomem *)reg, \
175 .enable_bit = e, \
176 .mapping = &cpg_mapping, \
177 }
178
179PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1);
180PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2);
181PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
182PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
183
184SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
185
54static struct clk *main_clks[] = { 186static struct clk *main_clks[] = {
55 &extalr_clk, 187 &extalr_clk,
56 &extal1_clk, 188 &extal1_clk,
189 &extal1_div2_clk,
57 &extal2_clk, 190 &extal2_clk,
191 &extal2_div2_clk,
192 &extal2_div4_clk,
193 &main_clk,
194 &main_div2_clk,
195 &fsiack_clk,
196 &fsibck_clk,
197 &pll1_clk,
198 &pll1_div2_clk,
199 &pll2_clk,
200 &pll2s_clk,
201 &pll2h_clk,
202};
203
204/* DIV4 */
205static void div4_kick(struct clk *clk)
206{
207 unsigned long value;
208
209 /* set KICK bit in FRQCRB to update hardware setting */
210 value = ioread32(CPG_MAP(FRQCRB));
211 value |= (1 << 31);
212 iowrite32(value, CPG_MAP(FRQCRB));
213}
214
215static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
216
217static struct clk_div_mult_table div4_div_mult_table = {
218 .divisors = divisors,
219 .nr_divisors = ARRAY_SIZE(divisors),
220};
221
222static struct clk_div4_table div4_table = {
223 .div_mult_table = &div4_div_mult_table,
224 .kick = div4_kick,
225};
226
227enum {
228 DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
229 DIV4_ZX, DIV4_ZS, DIV4_HP,
230 DIV4_NR };
231
232static struct clk div4_clks[DIV4_NR] = {
233 [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
234 [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
235 [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT),
236 [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0),
237 [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0),
238 [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
239 [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0),
240 [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0),
58}; 241};
59 242
60enum { 243enum {
244 DIV6_ZB,
245 DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
246 DIV6_MMC0, DIV6_MMC1,
247 DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
248 DIV6_FSIA, DIV6_FSIB,
249 DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
250 DIV6_NR };
251
252static struct clk *div6_parents[8] = {
253 [0] = &pll1_div2_clk,
254 [1] = &pll2s_clk,
255 [3] = &extal2_clk,
256 [4] = &main_div2_clk,
257 [6] = &extalr_clk,
258};
259
260static struct clk *fsia_parents[4] = {
261 [0] = &pll1_div2_clk,
262 [1] = &pll2s_clk,
263 [2] = &fsiack_clk,
264};
265
266static struct clk *fsib_parents[4] = {
267 [0] = &pll1_div2_clk,
268 [1] = &pll2s_clk,
269 [2] = &fsibck_clk,
270};
271
272static struct clk *mp_parents[4] = {
273 [0] = &pll1_div2_clk,
274 [1] = &pll2s_clk,
275 [2] = &extal2_clk,
276 [3] = &extal2_clk,
277};
278
279static struct clk *m4_parents[2] = {
280 [0] = &pll2s_clk,
281};
282
283static struct clk *hsi_parents[4] = {
284 [0] = &pll2h_clk,
285 [1] = &pll1_div2_clk,
286 [3] = &pll2s_clk,
287};
288
289/*** FIXME ***
290 * SH_CLK_DIV6_EXT() macro doesn't care .mapping
291 * but, it is necessary on R-Car (= ioremap() base CPG)
292 * The difference between
293 * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
294 * is only .mapping
295 */
296#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \
297 _num_parents, _src_shift, _src_width) \
298{ \
299 .enable_reg = (void __iomem *)_reg, \
300 .enable_bit = 0, /* unused */ \
301 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
302 .div_mask = SH_CLK_DIV6_MSK, \
303 .parent_table = _parents, \
304 .parent_num = _num_parents, \
305 .src_shift = _src_shift, \
306 .src_width = _src_width, \
307 .mapping = &cpg_mapping, \
308}
309
310static struct clk div6_clks[DIV6_NR] = {
311 [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
312 div6_parents, 2, 7, 1),
313 [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
314 div6_parents, 2, 6, 2),
315 [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
316 div6_parents, 2, 6, 2),
317 [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
318 div6_parents, 2, 6, 2),
319 [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
320 div6_parents, 2, 6, 2),
321 [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
322 div6_parents, 2, 6, 2),
323 [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
324 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
325 [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
326 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
327 [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
328 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
329 [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
330 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
331 [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
332 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
333 [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
334 fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
335 [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
336 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
337 [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
338 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
339 /* pll2s will be selected always for M4 */
340 [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
341 m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
342 [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
343 hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
344 [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
345 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
346};
347
348/* MSTP */
349enum {
61 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, 350 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
62 MSTP522, 351 MSTP522,
63 MSTP_NR 352 MSTP_NR
64}; 353};
65 354
66static struct clk mstp_clks[MSTP_NR] = { 355static struct clk mstp_clks[MSTP_NR] = {
67 [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ 356 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0), /* SCIFA0 */
68 [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ 357 [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0), /* SCIFA1 */
69 [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ 358 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0), /* SCIFB0 */
70 [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ 359 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
71 [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ 360 [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
72 [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ 361 [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
73 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ 362 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
74}; 363};
75 364
76static struct clk_lookup lookups[] = { 365static struct clk_lookup lookups[] = {
366 /* main clock */
367 CLKDEV_CON_ID("extal1", &extal1_clk),
368 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
369 CLKDEV_CON_ID("extal2", &extal2_clk),
370 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
371 CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk),
372 CLKDEV_CON_ID("fsiack", &fsiack_clk),
373 CLKDEV_CON_ID("fsibck", &fsibck_clk),
374
375 /* pll clock */
376 CLKDEV_CON_ID("pll1", &pll1_clk),
377 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
378 CLKDEV_CON_ID("pll2", &pll2_clk),
379 CLKDEV_CON_ID("pll2s", &pll2s_clk),
380 CLKDEV_CON_ID("pll2h", &pll2h_clk),
381
382 /* DIV6 */
383 CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),
384 CLKDEV_CON_ID("sdhi0", &div6_clks[DIV6_SDHI0]),
385 CLKDEV_CON_ID("sdhi1", &div6_clks[DIV6_SDHI1]),
386 CLKDEV_CON_ID("sdhi2", &div6_clks[DIV6_SDHI2]),
387 CLKDEV_CON_ID("mmc0", &div6_clks[DIV6_MMC0]),
388 CLKDEV_CON_ID("mmc1", &div6_clks[DIV6_MMC1]),
389 CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]),
390 CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]),
391 CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]),
392 CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]),
393 CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]),
394 CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]),
395 CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]),
396 CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]),
397 CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]),
398 CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]),
399 CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]),
400
401 /* MSTP */
77 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), 402 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
78 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), 403 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
79 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), 404 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -88,22 +413,40 @@ static struct clk_lookup lookups[] = {
88 413
89void __init r8a73a4_clock_init(void) 414void __init r8a73a4_clock_init(void)
90{ 415{
91 void __iomem *cpg_base, *reg; 416 void __iomem *reg;
92 int k, ret = 0; 417 int k, ret = 0;
418 u32 ckscr;
419
420 reg = ioremap_nocache(CKSCR, PAGE_SIZE);
421 BUG_ON(!reg);
422 ckscr = ioread32(reg);
423 iounmap(reg);
93 424
94 /* fix MPCLK to EXTAL2 for now. 425 switch ((ckscr >> 28) & 0x3) {
95 * this is needed until more detailed clock topology is supported 426 case 0:
96 */ 427 main_clk.parent = &extal1_clk;
97 cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN); 428 break;
98 BUG_ON(!cpg_base); 429 case 1:
99 reg = cpg_base + (MPCKCR - CPG_BASE); 430 main_clk.parent = &extal1_div2_clk;
100 iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */ 431 break;
101 iounmap(cpg_base); 432 case 2:
433 main_clk.parent = &extal2_clk;
434 break;
435 case 3:
436 main_clk.parent = &extal2_div2_clk;
437 break;
438 }
102 439
103 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 440 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
104 ret = clk_register(main_clks[k]); 441 ret = clk_register(main_clks[k]);
105 442
106 if (!ret) 443 if (!ret)
444 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
445
446 if (!ret)
447 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
448
449 if (!ret)
107 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 450 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
108 451
109 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 452 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c0d39aa6de50..7fd32d604e34 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -266,7 +266,7 @@ static struct clk fsiack_clk = {
266static struct clk fsibck_clk = { 266static struct clk fsibck_clk = {
267}; 267};
268 268
269struct clk *main_clks[] = { 269static struct clk *main_clks[] = {
270 &extalr_clk, 270 &extalr_clk,
271 &extal1_clk, 271 &extal1_clk,
272 &extal2_clk, 272 &extal2_clk,
@@ -317,7 +317,7 @@ enum {
317 DIV4_NR 317 DIV4_NR
318}; 318};
319 319
320struct clk div4_clks[DIV4_NR] = { 320static struct clk div4_clks[DIV4_NR] = {
321 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), 321 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
322 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), 322 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
323 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), 323 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
@@ -461,7 +461,7 @@ enum {
461 461
462 MSTP329, MSTP328, MSTP323, MSTP320, 462 MSTP329, MSTP328, MSTP323, MSTP320,
463 MSTP314, MSTP313, MSTP312, 463 MSTP314, MSTP313, MSTP312,
464 MSTP309, 464 MSTP309, MSTP304,
465 465
466 MSTP416, MSTP415, MSTP407, MSTP406, 466 MSTP416, MSTP415, MSTP407, MSTP406,
467 467
@@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = {
499 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ 499 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
500 [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ 500 [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
501 [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */ 501 [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */
502 [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP], SMSTPCR3, 4, 0), /* TPU0 */
502 503
503 [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */ 504 [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */
504 [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */ 505 [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
@@ -551,6 +552,7 @@ static struct clk_lookup lookups[] = {
551 CLKDEV_DEV_ID("sh_tmu.4", &mstp_clks[MSTP111]), 552 CLKDEV_DEV_ID("sh_tmu.4", &mstp_clks[MSTP111]),
552 CLKDEV_DEV_ID("sh_tmu.5", &mstp_clks[MSTP111]), 553 CLKDEV_DEV_ID("sh_tmu.5", &mstp_clks[MSTP111]),
553 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), 554 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
555 CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]),
554 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), 556 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
555 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), 557 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
556 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), 558 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]),
@@ -584,6 +586,7 @@ static struct clk_lookup lookups[] = {
584 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), 586 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
585 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), 587 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
586 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), 588 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
589 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]),
587 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), 590 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
588 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), 591 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
589 CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), 592 CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]),
@@ -592,6 +595,8 @@ static struct clk_lookup lookups[] = {
592 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), 595 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
593 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), 596 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]),
594 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), 597 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]),
598 CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]),
599 CLKDEV_DEV_ID("renesas_tpu_pwm", &mstp_clks[MSTP304]),
595 600
596 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), 601 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
597 CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), 602 CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index cd6855290b1f..b251e4d0924d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -23,9 +23,23 @@
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */ 24 */
25 25
26/*
27 * MD MD MD MD PLLA PLLB EXTAL clki clkz
28 * 19 18 12 11 (HMz) (MHz) (MHz)
29 *----------------------------------------------------------------------------
30 * 1 0 0 0 x21 x21 38.00 800 800
31 * 1 0 0 1 x24 x24 33.33 800 800
32 * 1 0 1 0 x28 x28 28.50 800 800
33 * 1 0 1 1 x32 x32 25.00 800 800
34 * 1 1 0 1 x24 x21 33.33 800 700
35 * 1 1 1 0 x28 x21 28.50 800 600
36 * 1 1 1 1 x32 x24 25.00 800 600
37 */
38
26#include <linux/io.h> 39#include <linux/io.h>
27#include <linux/sh_clk.h> 40#include <linux/sh_clk.h>
28#include <linux/clkdev.h> 41#include <linux/clkdev.h>
42#include <mach/clock.h>
29#include <mach/common.h> 43#include <mach/common.h>
30 44
31#define MSTPCR0 IOMEM(0xffc80030) 45#define MSTPCR0 IOMEM(0xffc80030)
@@ -37,6 +51,9 @@
37#define MSTPCR4 IOMEM(0xffc80050) 51#define MSTPCR4 IOMEM(0xffc80050)
38#define MSTPCR5 IOMEM(0xffc80054) 52#define MSTPCR5 IOMEM(0xffc80054)
39#define MSTPCR6 IOMEM(0xffc80058) 53#define MSTPCR6 IOMEM(0xffc80058)
54#define MODEMR 0xFFCC0020
55
56#define MD(nr) BIT(nr)
40 57
41/* ioremap() through clock mapping mandatory to avoid 58/* ioremap() through clock mapping mandatory to avoid
42 * collision with ARM coherent DMA virtual memory range. 59 * collision with ARM coherent DMA virtual memory range.
@@ -47,36 +64,71 @@ static struct clk_mapping cpg_mapping = {
47 .len = 0x80, 64 .len = 0x80,
48}; 65};
49 66
50static struct clk clkp = { 67static struct clk extal_clk = {
51 .rate = 62500000, /* FIXME: shortcut */ 68 /* .rate will be updated on r8a7778_clock_init() */
52 .flags = CLK_ENABLE_ON_INIT,
53 .mapping = &cpg_mapping, 69 .mapping = &cpg_mapping,
54}; 70};
55 71
72/*
73 * clock ratio of these clock will be updated
74 * on r8a7778_clock_init()
75 */
76SH_FIXED_RATIO_CLK_SET(plla_clk, extal_clk, 1, 1);
77SH_FIXED_RATIO_CLK_SET(pllb_clk, extal_clk, 1, 1);
78SH_FIXED_RATIO_CLK_SET(i_clk, plla_clk, 1, 1);
79SH_FIXED_RATIO_CLK_SET(s_clk, plla_clk, 1, 1);
80SH_FIXED_RATIO_CLK_SET(s1_clk, plla_clk, 1, 1);
81SH_FIXED_RATIO_CLK_SET(s3_clk, plla_clk, 1, 1);
82SH_FIXED_RATIO_CLK_SET(s4_clk, plla_clk, 1, 1);
83SH_FIXED_RATIO_CLK_SET(b_clk, plla_clk, 1, 1);
84SH_FIXED_RATIO_CLK_SET(out_clk, plla_clk, 1, 1);
85SH_FIXED_RATIO_CLK_SET(p_clk, plla_clk, 1, 1);
86SH_FIXED_RATIO_CLK_SET(g_clk, plla_clk, 1, 1);
87SH_FIXED_RATIO_CLK_SET(z_clk, pllb_clk, 1, 1);
88
56static struct clk *main_clks[] = { 89static struct clk *main_clks[] = {
57 &clkp, 90 &extal_clk,
91 &plla_clk,
92 &pllb_clk,
93 &i_clk,
94 &s_clk,
95 &s1_clk,
96 &s3_clk,
97 &s4_clk,
98 &b_clk,
99 &out_clk,
100 &p_clk,
101 &g_clk,
102 &z_clk,
58}; 103};
59 104
60enum { 105enum {
106 MSTP323, MSTP322, MSTP321,
61 MSTP114, 107 MSTP114,
62 MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, 108 MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
63 MSTP016, MSTP015, 109 MSTP016, MSTP015,
64 MSTP_NR }; 110 MSTP_NR };
65 111
66static struct clk mstp_clks[MSTP_NR] = { 112static struct clk mstp_clks[MSTP_NR] = {
67 [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */ 113 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
68 [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */ 114 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
69 [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */ 115 [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
70 [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */ 116 [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
71 [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */ 117 [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
72 [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */ 118 [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
73 [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */ 119 [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
74 [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */ 120 [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
75 [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */ 121 [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
122 [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
123 [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
124 [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
76}; 125};
77 126
78static struct clk_lookup lookups[] = { 127static struct clk_lookup lookups[] = {
79 /* MSTP32 clocks */ 128 /* MSTP32 clocks */
129 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
130 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
131 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
80 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ 132 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
81 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ 133 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
82 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ 134 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
@@ -90,8 +142,86 @@ static struct clk_lookup lookups[] = {
90 142
91void __init r8a7778_clock_init(void) 143void __init r8a7778_clock_init(void)
92{ 144{
145 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
146 u32 mode;
93 int k, ret = 0; 147 int k, ret = 0;
94 148
149 BUG_ON(!modemr);
150 mode = ioread32(modemr);
151 iounmap(modemr);
152
153 switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
154 case MD(19):
155 extal_clk.rate = 38000000;
156 SH_CLK_SET_RATIO(&plla_clk_ratio, 21, 1);
157 SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
158 break;
159 case MD(19) | MD(11):
160 extal_clk.rate = 33333333;
161 SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1);
162 SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1);
163 break;
164 case MD(19) | MD(12):
165 extal_clk.rate = 28500000;
166 SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1);
167 SH_CLK_SET_RATIO(&pllb_clk_ratio, 28, 1);
168 break;
169 case MD(19) | MD(12) | MD(11):
170 extal_clk.rate = 25000000;
171 SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1);
172 SH_CLK_SET_RATIO(&pllb_clk_ratio, 32, 1);
173 break;
174 case MD(19) | MD(18) | MD(11):
175 extal_clk.rate = 33333333;
176 SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1);
177 SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
178 break;
179 case MD(19) | MD(18) | MD(12):
180 extal_clk.rate = 28500000;
181 SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1);
182 SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
183 break;
184 case MD(19) | MD(18) | MD(12) | MD(11):
185 extal_clk.rate = 25000000;
186 SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1);
187 SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1);
188 break;
189 default:
190 BUG();
191 }
192
193 if (mode & MD(1)) {
194 SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1);
195 SH_CLK_SET_RATIO(&s_clk_ratio, 1, 3);
196 SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
197 SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
198 SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
199 SH_CLK_SET_RATIO(&p_clk_ratio, 1, 12);
200 SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12);
201 if (mode & MD(2)) {
202 SH_CLK_SET_RATIO(&b_clk_ratio, 1, 18);
203 SH_CLK_SET_RATIO(&out_clk_ratio, 1, 18);
204 } else {
205 SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12);
206 SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12);
207 }
208 } else {
209 SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1);
210 SH_CLK_SET_RATIO(&s_clk_ratio, 1, 4);
211 SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
212 SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
213 SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
214 SH_CLK_SET_RATIO(&p_clk_ratio, 1, 16);
215 SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12);
216 if (mode & MD(2)) {
217 SH_CLK_SET_RATIO(&b_clk_ratio, 1, 16);
218 SH_CLK_SET_RATIO(&out_clk_ratio, 1, 16);
219 } else {
220 SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12);
221 SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12);
222 }
223 }
224
95 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 225 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
96 ret = clk_register(main_clks[k]); 226 ret = clk_register(main_clks[k]);
97 227
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 31d5cd4d9787..9daeb8c37483 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -112,7 +112,7 @@ static struct clk *main_clks[] = {
112}; 112};
113 113
114enum { MSTP323, MSTP322, MSTP321, MSTP320, 114enum { MSTP323, MSTP322, MSTP321, MSTP320,
115 MSTP115, MSTP114, 115 MSTP116, MSTP115, MSTP114,
116 MSTP103, MSTP101, MSTP100, 116 MSTP103, MSTP101, MSTP100,
117 MSTP030, 117 MSTP030,
118 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, 118 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = {
125 [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ 125 [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
126 [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ 126 [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
127 [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ 127 [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
128 [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
128 [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ 129 [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
129 [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */ 130 [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
130 [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ 131 [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */
@@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = {
161 CLKDEV_CON_ID("peripheral_clk", &clkp_clk), 162 CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
162 163
163 /* MSTP32 clocks */ 164 /* MSTP32 clocks */
165 CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
164 CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ 166 CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
165 CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ 167 CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
166 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ 168 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index bad9bf2e34d6..b393592edc83 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -22,39 +22,174 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/sh_clk.h> 23#include <linux/sh_clk.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <mach/clock.h>
25#include <mach/common.h> 26#include <mach/common.h>
26 27
28/*
29 * MD EXTAL PLL0 PLL1 PLL3
30 * 14 13 19 (MHz) *1 *1
31 *---------------------------------------------------
32 * 0 0 0 15 x 1 x172/2 x208/2 x106
33 * 0 0 1 15 x 1 x172/2 x208/2 x88
34 * 0 1 0 20 x 1 x130/2 x156/2 x80
35 * 0 1 1 20 x 1 x130/2 x156/2 x66
36 * 1 0 0 26 / 2 x200/2 x240/2 x122
37 * 1 0 1 26 / 2 x200/2 x240/2 x102
38 * 1 1 0 30 / 2 x172/2 x208/2 x106
39 * 1 1 1 30 / 2 x172/2 x208/2 x88
40 *
41 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
42 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below
43 */
44
45#define MD(nr) (1 << nr)
46
27#define CPG_BASE 0xe6150000 47#define CPG_BASE 0xe6150000
28#define CPG_LEN 0x1000 48#define CPG_LEN 0x1000
29 49
30#define SMSTPCR2 0xe6150138 50#define SMSTPCR2 0xe6150138
51#define SMSTPCR3 0xe615013c
31#define SMSTPCR7 0xe615014c 52#define SMSTPCR7 0xe615014c
32 53
54#define MODEMR 0xE6160060
55#define SDCKCR 0xE6150074
56#define SD2CKCR 0xE6150078
57#define SD3CKCR 0xE615007C
58#define MMC0CKCR 0xE6150240
59#define MMC1CKCR 0xE6150244
60#define SSPCKCR 0xE6150248
61#define SSPRSCKCR 0xE615024C
62
33static struct clk_mapping cpg_mapping = { 63static struct clk_mapping cpg_mapping = {
34 .phys = CPG_BASE, 64 .phys = CPG_BASE,
35 .len = CPG_LEN, 65 .len = CPG_LEN,
36}; 66};
37 67
38static struct clk p_clk = { 68static struct clk extal_clk = {
39 .rate = 65000000, /* shortcut for now */ 69 /* .rate will be updated on r8a7790_clock_init() */
40 .mapping = &cpg_mapping, 70 .mapping = &cpg_mapping,
41}; 71};
42 72
43static struct clk mp_clk = { 73static struct sh_clk_ops followparent_clk_ops = {
44 .rate = 52000000, /* shortcut for now */ 74 .recalc = followparent_recalc,
45 .mapping = &cpg_mapping, 75};
76
77static struct clk main_clk = {
78 /* .parent will be set r8a73a4_clock_init */
79 .ops = &followparent_clk_ops,
46}; 80};
47 81
82/*
83 * clock ratio of these clock will be updated
84 * on r8a7790_clock_init()
85 */
86SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
87SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
88SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
89SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
90
91/* fixed ratio clock */
92SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
93SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
94
95SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
96SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
97SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
98SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
99SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
100SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
101SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
102SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
103SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
104SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
105SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
106SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
107SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
108
109SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
110SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
111SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
112SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
113
48static struct clk *main_clks[] = { 114static struct clk *main_clks[] = {
115 &extal_clk,
116 &extal_div2_clk,
117 &main_clk,
118 &pll1_clk,
119 &pll1_div2_clk,
120 &pll3_clk,
121 &lb_clk,
122 &qspi_clk,
123 &zg_clk,
124 &zx_clk,
125 &zs_clk,
126 &hp_clk,
127 &i_clk,
128 &b_clk,
49 &p_clk, 129 &p_clk,
130 &cl_clk,
131 &m2_clk,
132 &imp_clk,
133 &rclk_clk,
134 &oscclk_clk,
135 &zb3_clk,
136 &zb3d2_clk,
137 &ddr_clk,
50 &mp_clk, 138 &mp_clk,
139 &cp_clk,
140};
141
142/* SDHI (DIV4) clock */
143static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
144
145static struct clk_div_mult_table div4_div_mult_table = {
146 .divisors = divisors,
147 .nr_divisors = ARRAY_SIZE(divisors),
148};
149
150static struct clk_div4_table div4_table = {
151 .div_mult_table = &div4_div_mult_table,
152};
153
154enum {
155 DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
156};
157
158static struct clk div4_clks[DIV4_NR] = {
159 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
160 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
161 [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
162};
163
164/* DIV6 clocks */
165enum {
166 DIV6_SD2, DIV6_SD3,
167 DIV6_MMC0, DIV6_MMC1,
168 DIV6_SSP, DIV6_SSPRS,
169 DIV6_NR
170};
171
172static struct clk div6_clks[DIV6_NR] = {
173 [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
174 [DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
175 [DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
176 [DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
177 [DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
178 [DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
179};
180
181/* MSTP */
182enum {
183 MSTP721, MSTP720,
184 MSTP304,
185 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
186 MSTP_NR
51}; 187};
52 188
53enum { MSTP721, MSTP720,
54 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
55static struct clk mstp_clks[MSTP_NR] = { 189static struct clk mstp_clks[MSTP_NR] = {
56 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ 190 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
57 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 191 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
192 [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
58 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ 193 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
59 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ 194 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
60 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ 195 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
@@ -64,6 +199,48 @@ static struct clk mstp_clks[MSTP_NR] = {
64}; 199};
65 200
66static struct clk_lookup lookups[] = { 201static struct clk_lookup lookups[] = {
202
203 /* main clocks */
204 CLKDEV_CON_ID("extal", &extal_clk),
205 CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
206 CLKDEV_CON_ID("main", &main_clk),
207 CLKDEV_CON_ID("pll1", &pll1_clk),
208 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
209 CLKDEV_CON_ID("pll3", &pll3_clk),
210 CLKDEV_CON_ID("zg", &zg_clk),
211 CLKDEV_CON_ID("zx", &zx_clk),
212 CLKDEV_CON_ID("zs", &zs_clk),
213 CLKDEV_CON_ID("hp", &hp_clk),
214 CLKDEV_CON_ID("i", &i_clk),
215 CLKDEV_CON_ID("b", &b_clk),
216 CLKDEV_CON_ID("lb", &lb_clk),
217 CLKDEV_CON_ID("p", &p_clk),
218 CLKDEV_CON_ID("cl", &cl_clk),
219 CLKDEV_CON_ID("m2", &m2_clk),
220 CLKDEV_CON_ID("imp", &imp_clk),
221 CLKDEV_CON_ID("rclk", &rclk_clk),
222 CLKDEV_CON_ID("oscclk", &oscclk_clk),
223 CLKDEV_CON_ID("zb3", &zb3_clk),
224 CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
225 CLKDEV_CON_ID("ddr", &ddr_clk),
226 CLKDEV_CON_ID("mp", &mp_clk),
227 CLKDEV_CON_ID("qspi", &qspi_clk),
228 CLKDEV_CON_ID("cp", &cp_clk),
229
230 /* DIV4 */
231 CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
232 CLKDEV_CON_ID("sd0", &div4_clks[DIV4_SD0]),
233 CLKDEV_CON_ID("sd1", &div4_clks[DIV4_SD1]),
234
235 /* DIV6 */
236 CLKDEV_CON_ID("sd2", &div6_clks[DIV6_SD2]),
237 CLKDEV_CON_ID("sd3", &div6_clks[DIV6_SD3]),
238 CLKDEV_CON_ID("mmc0", &div6_clks[DIV6_MMC0]),
239 CLKDEV_CON_ID("mmc1", &div6_clks[DIV6_MMC1]),
240 CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
241 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
242
243 /* MSTP */
67 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), 244 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
68 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), 245 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
69 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), 246 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -74,14 +251,61 @@ static struct clk_lookup lookups[] = {
74 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), 251 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
75}; 252};
76 253
254#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
255 extal_clk.rate = e * 1000 * 1000; \
256 main_clk.parent = m; \
257 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
258 if (mode & MD(19)) \
259 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
260 else \
261 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
262
263
77void __init r8a7790_clock_init(void) 264void __init r8a7790_clock_init(void)
78{ 265{
266 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
267 u32 mode;
79 int k, ret = 0; 268 int k, ret = 0;
80 269
270 BUG_ON(!modemr);
271 mode = ioread32(modemr);
272 iounmap(modemr);
273
274 switch (mode & (MD(14) | MD(13))) {
275 case 0:
276 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
277 break;
278 case MD(13):
279 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
280 break;
281 case MD(14):
282 R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
283 break;
284 case MD(13) | MD(14):
285 R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
286 break;
287 }
288
289 if (mode & (MD(18)))
290 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
291 else
292 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
293
294 if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
295 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
296 else
297 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
298
81 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 299 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
82 ret = clk_register(main_clks[k]); 300 ret = clk_register(main_clks[k]);
83 301
84 if (!ret) 302 if (!ret)
303 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
304
305 if (!ret)
306 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
307
308 if (!ret)
85 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 309 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
86 310
87 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 311 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 784fbaa4cc55..d9fd0336b910 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
228 228
229static struct clk div4_clks[DIV4_NR] = { 229static struct clk div4_clks[DIV4_NR] = {
230 [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), 230 [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
231 /*
232 * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to
233 * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and
234 * 239.2MHz for VDD_DVFS=1.315V.
235 */
231 [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), 236 [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
232 [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), 237 [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
233 [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), 238 [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
@@ -252,6 +257,101 @@ static struct clk twd_clk = {
252 .ops = &twd_clk_ops, 257 .ops = &twd_clk_ops,
253}; 258};
254 259
260static struct sh_clk_ops zclk_ops, kicker_ops;
261static const struct sh_clk_ops *div4_clk_ops;
262
263static int zclk_set_rate(struct clk *clk, unsigned long rate)
264{
265 int ret;
266
267 if (!clk->parent || !__clk_get(clk->parent))
268 return -ENODEV;
269
270 if (readl(FRQCRB) & (1 << 31))
271 return -EBUSY;
272
273 if (rate == clk_get_rate(clk->parent)) {
274 /* 1:1 - switch off divider */
275 __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB);
276 /* nullify the divider to prepare for the next time */
277 ret = div4_clk_ops->set_rate(clk, rate / 2);
278 if (!ret)
279 ret = frqcr_kick();
280 if (ret > 0)
281 ret = 0;
282 } else {
283 /* Enable the divider */
284 __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB);
285
286 ret = frqcr_kick();
287 if (ret >= 0)
288 /*
289 * set the divider - call the DIV4 method, it will kick
290 * FRQCRB too
291 */
292 ret = div4_clk_ops->set_rate(clk, rate);
293 if (ret < 0)
294 goto esetrate;
295 }
296
297esetrate:
298 __clk_put(clk->parent);
299 return ret;
300}
301
302static long zclk_round_rate(struct clk *clk, unsigned long rate)
303{
304 unsigned long div_freq = div4_clk_ops->round_rate(clk, rate),
305 parent_freq = clk_get_rate(clk->parent);
306
307 if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq)
308 return parent_freq;
309
310 return div_freq;
311}
312
313static unsigned long zclk_recalc(struct clk *clk)
314{
315 /*
316 * Must recalculate frequencies in case PLL0 has been changed, even if
317 * the divisor is unused ATM!
318 */
319 unsigned long div_freq = div4_clk_ops->recalc(clk);
320
321 if (__raw_readl(FRQCRB) & (1 << 28))
322 return div_freq;
323
324 return clk_get_rate(clk->parent);
325}
326
327static int kicker_set_rate(struct clk *clk, unsigned long rate)
328{
329 if (__raw_readl(FRQCRB) & (1 << 31))
330 return -EBUSY;
331
332 return div4_clk_ops->set_rate(clk, rate);
333}
334
335static void div4_clk_extend(void)
336{
337 int i;
338
339 div4_clk_ops = div4_clks[0].ops;
340
341 /* Add a kicker-busy check before changing the rate */
342 kicker_ops = *div4_clk_ops;
343 /* We extend the DIV4 clock with a 1:1 pass-through case */
344 zclk_ops = *div4_clk_ops;
345
346 kicker_ops.set_rate = kicker_set_rate;
347 zclk_ops.set_rate = zclk_set_rate;
348 zclk_ops.round_rate = zclk_round_rate;
349 zclk_ops.recalc = zclk_recalc;
350
351 for (i = 0; i < DIV4_NR; i++)
352 div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops;
353}
354
255enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, 355enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
256 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, 356 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
257 DIV6_FSIA, DIV6_FSIB, DIV6_SUB, 357 DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -450,7 +550,7 @@ static struct clk *late_main_clks[] = {
450}; 550};
451 551
452enum { MSTP001, 552enum { MSTP001,
453 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, 553 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100,
454 MSTP219, MSTP218, MSTP217, 554 MSTP219, MSTP218, MSTP217,
455 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 555 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
456 MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322, 556 MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
@@ -471,6 +571,7 @@ static struct clk mstp_clks[MSTP_NR] = {
471 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ 571 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
472 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */ 572 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
473 [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ 573 [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
574 [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */
474 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ 575 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
475 [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ 576 [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
476 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */ 577 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
@@ -513,6 +614,9 @@ static struct clk_lookup lookups[] = {
513 CLKDEV_CON_ID("r_clk", &r_clk), 614 CLKDEV_CON_ID("r_clk", &r_clk),
514 CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ 615 CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
515 616
617 /* DIV4 clocks */
618 CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]),
619
516 /* DIV6 clocks */ 620 /* DIV6 clocks */
517 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), 621 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
518 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), 622 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
@@ -604,8 +708,11 @@ void __init sh73a0_clock_init(void)
604 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 708 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
605 ret = clk_register(main_clks[k]); 709 ret = clk_register(main_clks[k]);
606 710
607 if (!ret) 711 if (!ret) {
608 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 712 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
713 if (!ret)
714 div4_clk_extend();
715 }
609 716
610 if (!ret) 717 if (!ret)
611 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); 718 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
index 76ac61292e48..03e56074928c 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -24,16 +24,16 @@ struct clk name = { \
24} 24}
25 25
26#define SH_FIXED_RATIO_CLK(name, p, r) \ 26#define SH_FIXED_RATIO_CLK(name, p, r) \
27static SH_FIXED_RATIO_CLKg(name, p, r); 27static SH_FIXED_RATIO_CLKg(name, p, r)
28 28
29#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \ 29#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \
30 SH_CLK_RATIO(name, m, d); \ 30 SH_CLK_RATIO(name, m, d); \
31 SH_FIXED_RATIO_CLK(name, p, name); 31 SH_FIXED_RATIO_CLK(name, p, name)
32 32
33#define SH_CLK_SET_RATIO(p, m, d) \ 33#define SH_CLK_SET_RATIO(p, m, d) \
34{ \ 34do { \
35 (p)->mul = m; \ 35 (p)->mul = m; \
36 (p)->div = d; \ 36 (p)->div = d; \
37} 37} while (0)
38 38
39#endif 39#endif
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 68053fc4d9dc..ae65b459483f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -18,6 +18,7 @@
18#ifndef __ASM_R8A7778_H__ 18#ifndef __ASM_R8A7778_H__
19#define __ASM_R8A7778_H__ 19#define __ASM_R8A7778_H__
20 20
21#include <linux/mmc/sh_mobile_sdhi.h>
21#include <linux/sh_eth.h> 22#include <linux/sh_eth.h>
22 23
23extern void r8a7778_add_standard_devices(void); 24extern void r8a7778_add_standard_devices(void);
@@ -29,5 +30,6 @@ extern void r8a7778_init_irq_dt(void);
29extern void r8a7778_clock_init(void); 30extern void r8a7778_clock_init(void);
30extern void r8a7778_init_irq_extpin(int irlm); 31extern void r8a7778_init_irq_extpin(int irlm);
31extern void r8a7778_pinmux_init(void); 32extern void r8a7778_pinmux_init(void);
33extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info);
32 34
33#endif /* __ASM_R8A7778_H__ */ 35#endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 1f36ecc322a3..1b9b7f2a5016 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -81,12 +81,6 @@ static struct sh_timer_config sh_tmu1_platform_data = {
81 .clocksource_rating = 200, 81 .clocksource_rating = 200,
82}; 82};
83 83
84/* Ether */
85static struct resource ether_resources[] = {
86 DEFINE_RES_MEM(0xfde00000, 0x400),
87 DEFINE_RES_IRQ(gic_iid(0x89)),
88};
89
90#define r8a7778_register_tmu(idx) \ 84#define r8a7778_register_tmu(idx) \
91 platform_device_register_resndata( \ 85 platform_device_register_resndata( \
92 &platform_bus, "sh_tmu", idx, \ 86 &platform_bus, "sh_tmu", idx, \
@@ -95,6 +89,20 @@ static struct resource ether_resources[] = {
95 &sh_tmu##idx##_platform_data, \ 89 &sh_tmu##idx##_platform_data, \
96 sizeof(sh_tmu##idx##_platform_data)) 90 sizeof(sh_tmu##idx##_platform_data))
97 91
92/* Ether */
93static struct resource ether_resources[] = {
94 DEFINE_RES_MEM(0xfde00000, 0x400),
95 DEFINE_RES_IRQ(gic_iid(0x89)),
96};
97
98void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
99{
100 platform_device_register_resndata(&platform_bus, "sh_eth", -1,
101 ether_resources,
102 ARRAY_SIZE(ether_resources),
103 pdata, sizeof(*pdata));
104}
105
98/* PFC/GPIO */ 106/* PFC/GPIO */
99static struct resource pfc_resources[] = { 107static struct resource pfc_resources[] = {
100 DEFINE_RES_MEM(0xfffc0000, 0x118), 108 DEFINE_RES_MEM(0xfffc0000, 0x118),
@@ -139,6 +147,30 @@ void __init r8a7778_pinmux_init(void)
139 r8a7778_register_gpio(2); 147 r8a7778_register_gpio(2);
140 r8a7778_register_gpio(3); 148 r8a7778_register_gpio(3);
141 r8a7778_register_gpio(4); 149 r8a7778_register_gpio(4);
150};
151
152/* SDHI */
153static struct resource sdhi_resources[] = {
154 /* SDHI0 */
155 DEFINE_RES_MEM(0xFFE4C000, 0x100),
156 DEFINE_RES_IRQ(gic_iid(0x77)),
157 /* SDHI1 */
158 DEFINE_RES_MEM(0xFFE4D000, 0x100),
159 DEFINE_RES_IRQ(gic_iid(0x78)),
160 /* SDHI2 */
161 DEFINE_RES_MEM(0xFFE4F000, 0x100),
162 DEFINE_RES_IRQ(gic_iid(0x76)),
163};
164
165void __init r8a7778_sdhi_init(int id,
166 struct sh_mobile_sdhi_info *info)
167{
168 BUG_ON(id < 0 || id > 2);
169
170 platform_device_register_resndata(
171 &platform_bus, "sh_mobile_sdhi", id,
172 sdhi_resources + (2 * id), 2,
173 info, sizeof(*info));
142} 174}
143 175
144void __init r8a7778_add_standard_devices(void) 176void __init r8a7778_add_standard_devices(void)
@@ -165,14 +197,6 @@ void __init r8a7778_add_standard_devices(void)
165 r8a7778_register_tmu(1); 197 r8a7778_register_tmu(1);
166} 198}
167 199
168void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
169{
170 platform_device_register_resndata(&platform_bus, "sh_eth", -1,
171 ether_resources,
172 ARRAY_SIZE(ether_resources),
173 pdata, sizeof(*pdata));
174}
175
176static struct renesas_intc_irqpin_config irqpin_platform_data = { 200static struct renesas_intc_irqpin_config irqpin_platform_data = {
177 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 201 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
178 .sense_bitfield_width = 2, 202 .sense_bitfield_width = 2,
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 9696f3646864..96e7ca1e4e11 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -288,12 +288,7 @@ static struct sh_timer_config tmu00_platform_data = {
288}; 288};
289 289
290static struct resource tmu00_resources[] = { 290static struct resource tmu00_resources[] = {
291 [0] = { 291 [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
292 .name = "TMU00",
293 .start = 0xfff60008,
294 .end = 0xfff60013,
295 .flags = IORESOURCE_MEM,
296 },
297 [1] = { 292 [1] = {
298 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ 293 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
299 .flags = IORESOURCE_IRQ, 294 .flags = IORESOURCE_IRQ,
@@ -318,12 +313,7 @@ static struct sh_timer_config tmu01_platform_data = {
318}; 313};
319 314
320static struct resource tmu01_resources[] = { 315static struct resource tmu01_resources[] = {
321 [0] = { 316 [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
322 .name = "TMU01",
323 .start = 0xfff60014,
324 .end = 0xfff6001f,
325 .flags = IORESOURCE_MEM,
326 },
327 [1] = { 317 [1] = {
328 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ 318 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
329 .flags = IORESOURCE_IRQ, 319 .flags = IORESOURCE_IRQ,
@@ -341,12 +331,7 @@ static struct platform_device tmu01_device = {
341}; 331};
342 332
343static struct resource i2c0_resources[] = { 333static struct resource i2c0_resources[] = {
344 [0] = { 334 [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
345 .name = "IIC0",
346 .start = 0xe6820000,
347 .end = 0xe6820425 - 1,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = { 335 [1] = {
351 .start = gic_spi(167), 336 .start = gic_spi(167),
352 .end = gic_spi(170), 337 .end = gic_spi(170),
@@ -355,12 +340,7 @@ static struct resource i2c0_resources[] = {
355}; 340};
356 341
357static struct resource i2c1_resources[] = { 342static struct resource i2c1_resources[] = {
358 [0] = { 343 [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
359 .name = "IIC1",
360 .start = 0xe6822000,
361 .end = 0xe6822425 - 1,
362 .flags = IORESOURCE_MEM,
363 },
364 [1] = { 344 [1] = {
365 .start = gic_spi(51), 345 .start = gic_spi(51),
366 .end = gic_spi(54), 346 .end = gic_spi(54),
@@ -369,12 +349,7 @@ static struct resource i2c1_resources[] = {
369}; 349};
370 350
371static struct resource i2c2_resources[] = { 351static struct resource i2c2_resources[] = {
372 [0] = { 352 [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
373 .name = "IIC2",
374 .start = 0xe6824000,
375 .end = 0xe6824425 - 1,
376 .flags = IORESOURCE_MEM,
377 },
378 [1] = { 353 [1] = {
379 .start = gic_spi(171), 354 .start = gic_spi(171),
380 .end = gic_spi(174), 355 .end = gic_spi(174),
@@ -383,12 +358,7 @@ static struct resource i2c2_resources[] = {
383}; 358};
384 359
385static struct resource i2c3_resources[] = { 360static struct resource i2c3_resources[] = {
386 [0] = { 361 [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
387 .name = "IIC3",
388 .start = 0xe6826000,
389 .end = 0xe6826425 - 1,
390 .flags = IORESOURCE_MEM,
391 },
392 [1] = { 362 [1] = {
393 .start = gic_spi(183), 363 .start = gic_spi(183),
394 .end = gic_spi(186), 364 .end = gic_spi(186),
@@ -397,12 +367,7 @@ static struct resource i2c3_resources[] = {
397}; 367};
398 368
399static struct resource i2c4_resources[] = { 369static struct resource i2c4_resources[] = {
400 [0] = { 370 [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
401 .name = "IIC4",
402 .start = 0xe6828000,
403 .end = 0xe6828425 - 1,
404 .flags = IORESOURCE_MEM,
405 },
406 [1] = { 371 [1] = {
407 .start = gic_spi(187), 372 .start = gic_spi(187),
408 .end = gic_spi(190), 373 .end = gic_spi(190),
@@ -623,12 +588,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
623}; 588};
624 589
625static struct resource sh73a0_dmae_resources[] = { 590static struct resource sh73a0_dmae_resources[] = {
626 { 591 DEFINE_RES_MEM(0xfe000020, 0x89e0),
627 /* Registers including DMAOR and channels including DMARSx */
628 .start = 0xfe000020,
629 .end = 0xfe008a00 - 1,
630 .flags = IORESOURCE_MEM,
631 },
632 { 592 {
633 .name = "error_irq", 593 .name = "error_irq",
634 .start = gic_spi(129), 594 .start = gic_spi(129),
@@ -727,18 +687,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
727 687
728/* Resource order important! */ 688/* Resource order important! */
729static struct resource sh73a0_mpdma_resources[] = { 689static struct resource sh73a0_mpdma_resources[] = {
730 { 690 /* Channel registers and DMAOR */
731 /* Channel registers and DMAOR */ 691 DEFINE_RES_MEM(0xec618020, 0x270),
732 .start = 0xec618020, 692 /* DMARSx */
733 .end = 0xec61828f, 693 DEFINE_RES_MEM(0xec619000, 0xc),
734 .flags = IORESOURCE_MEM,
735 },
736 {
737 /* DMARSx */
738 .start = 0xec619000,
739 .end = 0xec61900b,
740 .flags = IORESOURCE_MEM,
741 },
742 { 694 {
743 .name = "error_irq", 695 .name = "error_irq",
744 .start = gic_spi(181), 696 .start = gic_spi(181),
@@ -785,12 +737,7 @@ static struct platform_device pmu_device = {
785 737
786/* an IPMMU module for ICB */ 738/* an IPMMU module for ICB */
787static struct resource ipmmu_resources[] = { 739static struct resource ipmmu_resources[] = {
788 [0] = { 740 DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
789 .name = "IPMMU",
790 .start = 0xfe951000,
791 .end = 0xfe9510ff,
792 .flags = IORESOURCE_MEM,
793 },
794}; 741};
795 742
796static const char * const ipmmu_dev_names[] = { 743static const char * const ipmmu_dev_names[] = {
@@ -982,11 +929,17 @@ void __init sh73a0_add_standard_devices(void)
982 ARRAY_SIZE(sh73a0_late_devices)); 929 ARRAY_SIZE(sh73a0_late_devices));
983} 930}
984 931
932void __init sh73a0_init_delay(void)
933{
934 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
935}
936
985/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 937/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
986void __init __weak sh73a0_register_twd(void) { } 938void __init __weak sh73a0_register_twd(void) { }
987 939
988void __init sh73a0_earlytimer_init(void) 940void __init sh73a0_earlytimer_init(void)
989{ 941{
942 sh73a0_init_delay();
990 sh73a0_clock_init(); 943 sh73a0_clock_init();
991 shmobile_earlytimer_init(); 944 shmobile_earlytimer_init();
992 sh73a0_register_twd(); 945 sh73a0_register_twd();
@@ -1005,17 +958,14 @@ void __init sh73a0_add_early_devices(void)
1005 958
1006#ifdef CONFIG_USE_OF 959#ifdef CONFIG_USE_OF
1007 960
1008void __init sh73a0_init_delay(void)
1009{
1010 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
1011}
1012
1013static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { 961static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
1014 {}, 962 {},
1015}; 963};
1016 964
1017void __init sh73a0_add_standard_devices_dt(void) 965void __init sh73a0_add_standard_devices_dt(void)
1018{ 966{
967 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
968
1019 /* clocks are setup late during boot in the case of DT */ 969 /* clocks are setup late during boot in the case of DT */
1020 sh73a0_clock_init(); 970 sh73a0_clock_init();
1021 971
@@ -1023,6 +973,9 @@ void __init sh73a0_add_standard_devices_dt(void)
1023 ARRAY_SIZE(sh73a0_devices_dt)); 973 ARRAY_SIZE(sh73a0_devices_dt));
1024 of_platform_populate(NULL, of_default_bus_match_table, 974 of_platform_populate(NULL, of_default_bus_match_table,
1025 sh73a0_auxdata_lookup, NULL); 975 sh73a0_auxdata_lookup, NULL);
976
977 /* Instantiate cpufreq-cpu0 */
978 platform_device_register_full(&devinfo);
1026} 979}
1027 980
1028static const char *sh73a0_boards_compat_dt[] __initdata = { 981static const char *sh73a0_boards_compat_dt[] __initdata = {
generated by cgit v1.2.2 (git 2.25.0) at 2026-07-07 22:34:19 -0400