diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-06-09 21:01:45 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-06-09 21:01:45 -0400 |
| commit | ae75d84f3e29a1832b35cd342ac471bbf30bce4c (patch) | |
| tree | 930825162814ee91e8fa52a871d9b80c5951d6da | |
| parent | 0b52a3c89c8f44d7a936da8b374789dc0f43b188 (diff) | |
| parent | b11ae95100f7061b39a15e5c1ecbf862464ac4b4 (diff) | |
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc fixes from Benjamin Herrenschmidt:
"This is purely regressions (though not all recent ones) or stable
material"
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
powerpc: Partial revert of "Context switch more PMU related SPRs"
powerpc/perf: Fix deadlock caused by calling printk() in PMU exception
powerpc/hw_breakpoints: Add DABRX cpu feature to fix 32-bit regression
powerpc/power8: Update denormalization handler
powerpc/pseries: Simplify denormalization handler
powerpc/power8: Fix oprofile and perf
powerpc/eeh: Don't check RTAS token to get PE addr
powerpc/pci: Check the bus address instead of resource address in pcibios_fixup_resources
| -rw-r--r-- | arch/powerpc/include/asm/cputable.h | 17 | ||||
| -rw-r--r-- | arch/powerpc/kernel/cputable.c | 8 | ||||
| -rw-r--r-- | arch/powerpc/kernel/entry_64.S | 28 | ||||
| -rw-r--r-- | arch/powerpc/kernel/exceptions-64s.S | 90 | ||||
| -rw-r--r-- | arch/powerpc/kernel/pci-common.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/kernel/process.c | 3 | ||||
| -rw-r--r-- | arch/powerpc/perf/core-book3s.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/platforms/pseries/eeh_pseries.c | 12 |
8 files changed, 51 insertions, 113 deletions
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 26807e5aff51..6f3887d884d2 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h | |||
| @@ -176,6 +176,7 @@ extern const char *powerpc_base_platform; | |||
| 176 | #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000) | 176 | #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000) |
| 177 | #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) | 177 | #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) |
| 178 | #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) | 178 | #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) |
| 179 | #define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000) | ||
| 179 | 180 | ||
| 180 | #ifndef __ASSEMBLY__ | 181 | #ifndef __ASSEMBLY__ |
| 181 | 182 | ||
| @@ -394,19 +395,20 @@ extern const char *powerpc_base_platform; | |||
| 394 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \ | 395 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \ |
| 395 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ | 396 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ |
| 396 | CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ | 397 | CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ |
| 397 | CPU_FTR_HVMODE) | 398 | CPU_FTR_HVMODE | CPU_FTR_DABRX) |
| 398 | #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 399 | #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 399 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 400 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 400 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 401 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 401 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ | 402 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ |
| 402 | CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB) | 403 | CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) |
| 403 | #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 404 | #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 404 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 405 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 405 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 406 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 406 | CPU_FTR_COHERENT_ICACHE | \ | 407 | CPU_FTR_COHERENT_ICACHE | \ |
| 407 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ | 408 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
| 408 | CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ | 409 | CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ |
| 409 | CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR) | 410 | CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ |
| 411 | CPU_FTR_DABRX) | ||
| 410 | #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 412 | #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 411 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ | 413 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ |
| 412 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 414 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| @@ -415,7 +417,7 @@ extern const char *powerpc_base_platform; | |||
| 415 | CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ | 417 | CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ |
| 416 | CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ | 418 | CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ |
| 417 | CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \ | 419 | CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \ |
| 418 | CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR) | 420 | CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX) |
| 419 | #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 421 | #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 420 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ | 422 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ |
| 421 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 423 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| @@ -430,14 +432,15 @@ extern const char *powerpc_base_platform; | |||
| 430 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 432 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 431 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 433 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 432 | CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ | 434 | CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ |
| 433 | CPU_FTR_UNALIGNED_LD_STD) | 435 | CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) |
| 434 | #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 436 | #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 435 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ | 437 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ |
| 436 | CPU_FTR_PURR | CPU_FTR_REAL_LE) | 438 | CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) |
| 437 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) | 439 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) |
| 438 | 440 | ||
| 439 | #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ | 441 | #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ |
| 440 | CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX) | 442 | CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \ |
| 443 | CPU_FTR_ICSWX | CPU_FTR_DABRX ) | ||
| 441 | 444 | ||
| 442 | #ifdef __powerpc64__ | 445 | #ifdef __powerpc64__ |
| 443 | #ifdef CONFIG_PPC_BOOK3E | 446 | #ifdef CONFIG_PPC_BOOK3E |
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 1f0937d7d4b5..2a45d0f04385 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c | |||
| @@ -452,8 +452,8 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
| 452 | .mmu_features = MMU_FTRS_POWER8, | 452 | .mmu_features = MMU_FTRS_POWER8, |
| 453 | .icache_bsize = 128, | 453 | .icache_bsize = 128, |
| 454 | .dcache_bsize = 128, | 454 | .dcache_bsize = 128, |
| 455 | .oprofile_type = PPC_OPROFILE_POWER4, | 455 | .oprofile_type = PPC_OPROFILE_INVALID, |
| 456 | .oprofile_cpu_type = 0, | 456 | .oprofile_cpu_type = "ppc64/ibm-compat-v1", |
| 457 | .cpu_setup = __setup_cpu_power8, | 457 | .cpu_setup = __setup_cpu_power8, |
| 458 | .cpu_restore = __restore_cpu_power8, | 458 | .cpu_restore = __restore_cpu_power8, |
| 459 | .platform = "power8", | 459 | .platform = "power8", |
| @@ -506,8 +506,8 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
| 506 | .dcache_bsize = 128, | 506 | .dcache_bsize = 128, |
| 507 | .num_pmcs = 6, | 507 | .num_pmcs = 6, |
| 508 | .pmc_type = PPC_PMC_IBM, | 508 | .pmc_type = PPC_PMC_IBM, |
| 509 | .oprofile_cpu_type = 0, | 509 | .oprofile_cpu_type = "ppc64/power8", |
| 510 | .oprofile_type = PPC_OPROFILE_POWER4, | 510 | .oprofile_type = PPC_OPROFILE_INVALID, |
| 511 | .cpu_setup = __setup_cpu_power8, | 511 | .cpu_setup = __setup_cpu_power8, |
| 512 | .cpu_restore = __restore_cpu_power8, | 512 | .cpu_restore = __restore_cpu_power8, |
| 513 | .platform = "power8", | 513 | .platform = "power8", |
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 246b11c4fe7e..8741c854e03d 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S | |||
| @@ -465,20 +465,6 @@ BEGIN_FTR_SECTION | |||
| 465 | std r0, THREAD_EBBHR(r3) | 465 | std r0, THREAD_EBBHR(r3) |
| 466 | mfspr r0, SPRN_EBBRR | 466 | mfspr r0, SPRN_EBBRR |
| 467 | std r0, THREAD_EBBRR(r3) | 467 | std r0, THREAD_EBBRR(r3) |
| 468 | |||
| 469 | /* PMU registers made user read/(write) by EBB */ | ||
| 470 | mfspr r0, SPRN_SIAR | ||
| 471 | std r0, THREAD_SIAR(r3) | ||
| 472 | mfspr r0, SPRN_SDAR | ||
| 473 | std r0, THREAD_SDAR(r3) | ||
| 474 | mfspr r0, SPRN_SIER | ||
| 475 | std r0, THREAD_SIER(r3) | ||
| 476 | mfspr r0, SPRN_MMCR0 | ||
| 477 | std r0, THREAD_MMCR0(r3) | ||
| 478 | mfspr r0, SPRN_MMCR2 | ||
| 479 | std r0, THREAD_MMCR2(r3) | ||
| 480 | mfspr r0, SPRN_MMCRA | ||
| 481 | std r0, THREAD_MMCRA(r3) | ||
| 482 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | 468 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
| 483 | #endif | 469 | #endif |
| 484 | 470 | ||
| @@ -581,20 +567,6 @@ BEGIN_FTR_SECTION | |||
| 581 | ld r0, THREAD_EBBRR(r4) | 567 | ld r0, THREAD_EBBRR(r4) |
| 582 | mtspr SPRN_EBBRR, r0 | 568 | mtspr SPRN_EBBRR, r0 |
| 583 | 569 | ||
| 584 | /* PMU registers made user read/(write) by EBB */ | ||
| 585 | ld r0, THREAD_SIAR(r4) | ||
| 586 | mtspr SPRN_SIAR, r0 | ||
| 587 | ld r0, THREAD_SDAR(r4) | ||
| 588 | mtspr SPRN_SDAR, r0 | ||
| 589 | ld r0, THREAD_SIER(r4) | ||
| 590 | mtspr SPRN_SIER, r0 | ||
| 591 | ld r0, THREAD_MMCR0(r4) | ||
| 592 | mtspr SPRN_MMCR0, r0 | ||
| 593 | ld r0, THREAD_MMCR2(r4) | ||
| 594 | mtspr SPRN_MMCR2, r0 | ||
| 595 | ld r0, THREAD_MMCRA(r4) | ||
| 596 | mtspr SPRN_MMCRA, r0 | ||
| 597 | |||
| 598 | ld r0,THREAD_TAR(r4) | 570 | ld r0,THREAD_TAR(r4) |
| 599 | mtspr SPRN_TAR,r0 | 571 | mtspr SPRN_TAR,r0 |
| 600 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | 572 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index e6eba1bf61ad..e783453f910d 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S | |||
| @@ -454,38 +454,14 @@ BEGIN_FTR_SECTION | |||
| 454 | xori r10,r10,(MSR_FE0|MSR_FE1) | 454 | xori r10,r10,(MSR_FE0|MSR_FE1) |
| 455 | mtmsrd r10 | 455 | mtmsrd r10 |
| 456 | sync | 456 | sync |
| 457 | fmr 0,0 | 457 | |
| 458 | fmr 1,1 | 458 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 |
| 459 | fmr 2,2 | 459 | #define FMR4(n) FMR2(n) ; FMR2(n+2) |
| 460 | fmr 3,3 | 460 | #define FMR8(n) FMR4(n) ; FMR4(n+4) |
| 461 | fmr 4,4 | 461 | #define FMR16(n) FMR8(n) ; FMR8(n+8) |
| 462 | fmr 5,5 | 462 | #define FMR32(n) FMR16(n) ; FMR16(n+16) |
| 463 | fmr 6,6 | 463 | FMR32(0) |
| 464 | fmr 7,7 | 464 | |
| 465 | fmr 8,8 | ||
| 466 | fmr 9,9 | ||
| 467 | fmr 10,10 | ||
| 468 | fmr 11,11 | ||
| 469 | fmr 12,12 | ||
| 470 | fmr 13,13 | ||
| 471 | fmr 14,14 | ||
| 472 | fmr 15,15 | ||
| 473 | fmr 16,16 | ||
| 474 | fmr 17,17 | ||
| 475 | fmr 18,18 | ||
| 476 | fmr 19,19 | ||
| 477 | fmr 20,20 | ||
| 478 | fmr 21,21 | ||
| 479 | fmr 22,22 | ||
| 480 | fmr 23,23 | ||
| 481 | fmr 24,24 | ||
| 482 | fmr 25,25 | ||
| 483 | fmr 26,26 | ||
| 484 | fmr 27,27 | ||
| 485 | fmr 28,28 | ||
| 486 | fmr 29,29 | ||
| 487 | fmr 30,30 | ||
| 488 | fmr 31,31 | ||
| 489 | FTR_SECTION_ELSE | 465 | FTR_SECTION_ELSE |
| 490 | /* | 466 | /* |
| 491 | * To denormalise we need to move a copy of the register to itself. | 467 | * To denormalise we need to move a copy of the register to itself. |
| @@ -495,39 +471,25 @@ FTR_SECTION_ELSE | |||
| 495 | oris r10,r10,MSR_VSX@h | 471 | oris r10,r10,MSR_VSX@h |
| 496 | mtmsrd r10 | 472 | mtmsrd r10 |
| 497 | sync | 473 | sync |
| 498 | XVCPSGNDP(0,0,0) | 474 | |
| 499 | XVCPSGNDP(1,1,1) | 475 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) |
| 500 | XVCPSGNDP(2,2,2) | 476 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) |
| 501 | XVCPSGNDP(3,3,3) | 477 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) |
| 502 | XVCPSGNDP(4,4,4) | 478 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) |
| 503 | XVCPSGNDP(5,5,5) | 479 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) |
| 504 | XVCPSGNDP(6,6,6) | 480 | XVCPSGNDP32(0) |
| 505 | XVCPSGNDP(7,7,7) | 481 | |
| 506 | XVCPSGNDP(8,8,8) | ||
| 507 | XVCPSGNDP(9,9,9) | ||
| 508 | XVCPSGNDP(10,10,10) | ||
| 509 | XVCPSGNDP(11,11,11) | ||
| 510 | XVCPSGNDP(12,12,12) | ||
| 511 | XVCPSGNDP(13,13,13) | ||
| 512 | XVCPSGNDP(14,14,14) | ||
| 513 | XVCPSGNDP(15,15,15) | ||
| 514 | XVCPSGNDP(16,16,16) | ||
| 515 | XVCPSGNDP(17,17,17) | ||
| 516 | XVCPSGNDP(18,18,18) | ||
| 517 | XVCPSGNDP(19,19,19) | ||
| 518 | XVCPSGNDP(20,20,20) | ||
| 519 | XVCPSGNDP(21,21,21) | ||
| 520 | XVCPSGNDP(22,22,22) | ||
| 521 | XVCPSGNDP(23,23,23) | ||
| 522 | XVCPSGNDP(24,24,24) | ||
| 523 | XVCPSGNDP(25,25,25) | ||
| 524 | XVCPSGNDP(26,26,26) | ||
| 525 | XVCPSGNDP(27,27,27) | ||
| 526 | XVCPSGNDP(28,28,28) | ||
| 527 | XVCPSGNDP(29,29,29) | ||
| 528 | XVCPSGNDP(30,30,30) | ||
| 529 | XVCPSGNDP(31,31,31) | ||
| 530 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) | 482 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
| 483 | |||
| 484 | BEGIN_FTR_SECTION | ||
| 485 | b denorm_done | ||
| 486 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | ||
| 487 | /* | ||
| 488 | * To denormalise we need to move a copy of the register to itself. | ||
| 489 | * For POWER8 we need to do that for all 64 VSX registers | ||
| 490 | */ | ||
| 491 | XVCPSGNDP32(32) | ||
| 492 | denorm_done: | ||
| 531 | mtspr SPRN_HSRR0,r11 | 493 | mtspr SPRN_HSRR0,r11 |
| 532 | mtcrf 0x80,r9 | 494 | mtcrf 0x80,r9 |
| 533 | ld r9,PACA_EXGEN+EX_R9(r13) | 495 | ld r9,PACA_EXGEN+EX_R9(r13) |
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 7f2273cc3c7d..eabeec991016 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c | |||
| @@ -827,6 +827,7 @@ static void pcibios_fixup_resources(struct pci_dev *dev) | |||
| 827 | } | 827 | } |
| 828 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | 828 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
| 829 | struct resource *res = dev->resource + i; | 829 | struct resource *res = dev->resource + i; |
| 830 | struct pci_bus_region reg; | ||
| 830 | if (!res->flags) | 831 | if (!res->flags) |
| 831 | continue; | 832 | continue; |
| 832 | 833 | ||
| @@ -835,8 +836,9 @@ static void pcibios_fixup_resources(struct pci_dev *dev) | |||
| 835 | * at 0 as unset as well, except if PCI_PROBE_ONLY is also set | 836 | * at 0 as unset as well, except if PCI_PROBE_ONLY is also set |
| 836 | * since in that case, we don't want to re-assign anything | 837 | * since in that case, we don't want to re-assign anything |
| 837 | */ | 838 | */ |
| 839 | pcibios_resource_to_bus(dev, ®, res); | ||
| 838 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || | 840 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || |
| 839 | (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { | 841 | (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { |
| 840 | /* Only print message if not re-assigning */ | 842 | /* Only print message if not re-assigning */ |
| 841 | if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) | 843 | if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) |
| 842 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " | 844 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " |
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index a902723fdc69..b0f3e3f77e72 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c | |||
| @@ -399,7 +399,8 @@ static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) | |||
| 399 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) | 399 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
| 400 | { | 400 | { |
| 401 | mtspr(SPRN_DABR, dabr); | 401 | mtspr(SPRN_DABR, dabr); |
| 402 | mtspr(SPRN_DABRX, dabrx); | 402 | if (cpu_has_feature(CPU_FTR_DABRX)) |
| 403 | mtspr(SPRN_DABRX, dabrx); | ||
| 403 | return 0; | 404 | return 0; |
| 404 | } | 405 | } |
| 405 | #else | 406 | #else |
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 845c867444e6..29c6482890c8 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c | |||
| @@ -1758,7 +1758,7 @@ static void perf_event_interrupt(struct pt_regs *regs) | |||
| 1758 | } | 1758 | } |
| 1759 | } | 1759 | } |
| 1760 | } | 1760 | } |
| 1761 | if ((!found) && printk_ratelimit()) | 1761 | if (!found && !nmi && printk_ratelimit()) |
| 1762 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); | 1762 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); |
| 1763 | 1763 | ||
| 1764 | /* | 1764 | /* |
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c index 19506f935737..b456b157d33d 100644 --- a/arch/powerpc/platforms/pseries/eeh_pseries.c +++ b/arch/powerpc/platforms/pseries/eeh_pseries.c | |||
| @@ -83,7 +83,11 @@ static int pseries_eeh_init(void) | |||
| 83 | ibm_configure_pe = rtas_token("ibm,configure-pe"); | 83 | ibm_configure_pe = rtas_token("ibm,configure-pe"); |
| 84 | ibm_configure_bridge = rtas_token("ibm,configure-bridge"); | 84 | ibm_configure_bridge = rtas_token("ibm,configure-bridge"); |
| 85 | 85 | ||
| 86 | /* necessary sanity check */ | 86 | /* |
| 87 | * Necessary sanity check. We needn't check "get-config-addr-info" | ||
| 88 | * and its variant since the old firmware probably support address | ||
| 89 | * of domain/bus/slot/function for EEH RTAS operations. | ||
| 90 | */ | ||
| 87 | if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) { | 91 | if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) { |
| 88 | pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n", | 92 | pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n", |
| 89 | __func__); | 93 | __func__); |
| @@ -102,12 +106,6 @@ static int pseries_eeh_init(void) | |||
| 102 | pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n", | 106 | pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n", |
| 103 | __func__); | 107 | __func__); |
| 104 | return -EINVAL; | 108 | return -EINVAL; |
| 105 | } else if (ibm_get_config_addr_info2 == RTAS_UNKNOWN_SERVICE && | ||
| 106 | ibm_get_config_addr_info == RTAS_UNKNOWN_SERVICE) { | ||
| 107 | pr_warning("%s: RTAS service <ibm,get-config-addr-info2> and " | ||
| 108 | "<ibm,get-config-addr-info> invalid\n", | ||
| 109 | __func__); | ||
| 110 | return -EINVAL; | ||
| 111 | } else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE && | 109 | } else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE && |
| 112 | ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) { | 110 | ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) { |
| 113 | pr_warning("%s: RTAS service <ibm,configure-pe> and " | 111 | pr_warning("%s: RTAS service <ibm,configure-pe> and " |
