diff options
| author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2015-02-16 00:19:53 -0500 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2015-03-03 07:55:13 -0500 |
| commit | ae55099f5b6f79ec88a91af3dae3f6cdfec92303 (patch) | |
| tree | f0db0607f36282cd17e2a31bc89b7b985ea3aa2c | |
| parent | ff5e56859d3887eca6479d2868521126a83ceda1 (diff) | |
ath9k: Move MCI registers to reg_mci.h
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.h | 1 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/reg.h | 275 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/reg_mci.h | 300 |
3 files changed, 301 insertions, 275 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index e82e570de330..29a25d92add7 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include "eeprom.h" | 27 | #include "eeprom.h" |
| 28 | #include "calib.h" | 28 | #include "calib.h" |
| 29 | #include "reg.h" | 29 | #include "reg.h" |
| 30 | #include "reg_mci.h" | ||
| 30 | #include "phy.h" | 31 | #include "phy.h" |
| 31 | #include "btcoex.h" | 32 | #include "btcoex.h" |
| 32 | #include "dynack.h" | 33 | #include "dynack.h" |
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index 9587ec655680..1234399a43dd 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h | |||
| @@ -2044,279 +2044,4 @@ enum { | |||
| 2044 | #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 | 2044 | #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 |
| 2045 | #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 | 2045 | #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 |
| 2046 | 2046 | ||
| 2047 | /* MCI Registers */ | ||
| 2048 | |||
| 2049 | #define AR_MCI_COMMAND0 0x1800 | ||
| 2050 | #define AR_MCI_COMMAND0_HEADER 0xFF | ||
| 2051 | #define AR_MCI_COMMAND0_HEADER_S 0 | ||
| 2052 | #define AR_MCI_COMMAND0_LEN 0x1f00 | ||
| 2053 | #define AR_MCI_COMMAND0_LEN_S 8 | ||
| 2054 | #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000 | ||
| 2055 | #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13 | ||
| 2056 | |||
| 2057 | #define AR_MCI_COMMAND1 0x1804 | ||
| 2058 | |||
| 2059 | #define AR_MCI_COMMAND2 0x1808 | ||
| 2060 | #define AR_MCI_COMMAND2_RESET_TX 0x01 | ||
| 2061 | #define AR_MCI_COMMAND2_RESET_TX_S 0 | ||
| 2062 | #define AR_MCI_COMMAND2_RESET_RX 0x02 | ||
| 2063 | #define AR_MCI_COMMAND2_RESET_RX_S 1 | ||
| 2064 | #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC | ||
| 2065 | #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2 | ||
| 2066 | #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400 | ||
| 2067 | #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10 | ||
| 2068 | |||
| 2069 | #define AR_MCI_RX_CTRL 0x180c | ||
| 2070 | |||
| 2071 | #define AR_MCI_TX_CTRL 0x1810 | ||
| 2072 | /* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */ | ||
| 2073 | #define AR_MCI_TX_CTRL_CLK_DIV 0x03 | ||
| 2074 | #define AR_MCI_TX_CTRL_CLK_DIV_S 0 | ||
| 2075 | #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04 | ||
| 2076 | #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2 | ||
| 2077 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8 | ||
| 2078 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3 | ||
| 2079 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000 | ||
| 2080 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24 | ||
| 2081 | |||
| 2082 | #define AR_MCI_MSG_ATTRIBUTES_TABLE 0x1814 | ||
| 2083 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF | ||
| 2084 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0 | ||
| 2085 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000 | ||
| 2086 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16 | ||
| 2087 | |||
| 2088 | #define AR_MCI_SCHD_TABLE_0 0x1818 | ||
| 2089 | #define AR_MCI_SCHD_TABLE_1 0x181c | ||
| 2090 | #define AR_MCI_GPM_0 0x1820 | ||
| 2091 | #define AR_MCI_GPM_1 0x1824 | ||
| 2092 | #define AR_MCI_GPM_WRITE_PTR 0xFFFF0000 | ||
| 2093 | #define AR_MCI_GPM_WRITE_PTR_S 16 | ||
| 2094 | #define AR_MCI_GPM_BUF_LEN 0x0000FFFF | ||
| 2095 | #define AR_MCI_GPM_BUF_LEN_S 0 | ||
| 2096 | |||
| 2097 | #define AR_MCI_INTERRUPT_RAW 0x1828 | ||
| 2098 | #define AR_MCI_INTERRUPT_EN 0x182c | ||
| 2099 | #define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 | ||
| 2100 | #define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0 | ||
| 2101 | #define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 | ||
| 2102 | #define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1 | ||
| 2103 | #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004 | ||
| 2104 | #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2 | ||
| 2105 | #define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 | ||
| 2106 | #define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3 | ||
| 2107 | #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 | ||
| 2108 | #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4 | ||
| 2109 | #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 | ||
| 2110 | #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5 | ||
| 2111 | #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 | ||
| 2112 | #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7 | ||
| 2113 | #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 | ||
| 2114 | #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8 | ||
| 2115 | #define AR_MCI_INTERRUPT_RX_MSG 0x00000200 | ||
| 2116 | #define AR_MCI_INTERRUPT_RX_MSG_S 9 | ||
| 2117 | #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 | ||
| 2118 | #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10 | ||
| 2119 | #define AR_MCI_INTERRUPT_BT_PRI 0x07fff800 | ||
| 2120 | #define AR_MCI_INTERRUPT_BT_PRI_S 11 | ||
| 2121 | #define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000 | ||
| 2122 | #define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27 | ||
| 2123 | #define AR_MCI_INTERRUPT_BT_FREQ 0x10000000 | ||
| 2124 | #define AR_MCI_INTERRUPT_BT_FREQ_S 28 | ||
| 2125 | #define AR_MCI_INTERRUPT_BT_STOMP 0x20000000 | ||
| 2126 | #define AR_MCI_INTERRUPT_BT_STOMP_S 29 | ||
| 2127 | #define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000 | ||
| 2128 | #define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30 | ||
| 2129 | #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 | ||
| 2130 | #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31 | ||
| 2131 | |||
| 2132 | #define AR_MCI_INTERRUPT_DEFAULT (AR_MCI_INTERRUPT_SW_MSG_DONE | \ | ||
| 2133 | AR_MCI_INTERRUPT_RX_INVALID_HDR | \ | ||
| 2134 | AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ | ||
| 2135 | AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ | ||
| 2136 | AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ | ||
| 2137 | AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \ | ||
| 2138 | AR_MCI_INTERRUPT_RX_MSG | \ | ||
| 2139 | AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \ | ||
| 2140 | AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT) | ||
| 2141 | |||
| 2142 | #define AR_MCI_INTERRUPT_MSG_FAIL_MASK (AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ | ||
| 2143 | AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ | ||
| 2144 | AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ | ||
| 2145 | AR_MCI_INTERRUPT_TX_SW_MSG_FAIL) | ||
| 2146 | |||
| 2147 | #define AR_MCI_REMOTE_CPU_INT 0x1830 | ||
| 2148 | #define AR_MCI_REMOTE_CPU_INT_EN 0x1834 | ||
| 2149 | #define AR_MCI_INTERRUPT_RX_MSG_RAW 0x1838 | ||
| 2150 | #define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c | ||
| 2151 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 | ||
| 2152 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 | ||
| 2153 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 | ||
| 2154 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 | ||
| 2155 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 | ||
| 2156 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 | ||
| 2157 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 | ||
| 2158 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 | ||
| 2159 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 | ||
| 2160 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 | ||
| 2161 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 | ||
| 2162 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 | ||
| 2163 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 | ||
| 2164 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 | ||
| 2165 | #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 | ||
| 2166 | #define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 | ||
| 2167 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 | ||
| 2168 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 | ||
| 2169 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 | ||
| 2170 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 | ||
| 2171 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 | ||
| 2172 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 | ||
| 2173 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 | ||
| 2174 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 | ||
| 2175 | #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ | ||
| 2176 | AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL| \ | ||
| 2177 | AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ | ||
| 2178 | AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ | ||
| 2179 | AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ | ||
| 2180 | AR_MCI_INTERRUPT_RX_MSG_CONT_RST) | ||
| 2181 | |||
| 2182 | #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT (AR_MCI_INTERRUPT_RX_MSG_GPM | \ | ||
| 2183 | AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET| \ | ||
| 2184 | AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ | ||
| 2185 | AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING| \ | ||
| 2186 | AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) | ||
| 2187 | |||
| 2188 | #define AR_MCI_CPU_INT 0x1840 | ||
| 2189 | |||
| 2190 | #define AR_MCI_RX_STATUS 0x1844 | ||
| 2191 | #define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00 | ||
| 2192 | #define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8 | ||
| 2193 | #define AR_MCI_RX_REMOTE_SLEEP 0x00001000 | ||
| 2194 | #define AR_MCI_RX_REMOTE_SLEEP_S 12 | ||
| 2195 | #define AR_MCI_RX_MCI_CLK_REQ 0x00002000 | ||
| 2196 | #define AR_MCI_RX_MCI_CLK_REQ_S 13 | ||
| 2197 | |||
| 2198 | #define AR_MCI_CONT_STATUS 0x1848 | ||
| 2199 | #define AR_MCI_CONT_RSSI_POWER 0x000000FF | ||
| 2200 | #define AR_MCI_CONT_RSSI_POWER_S 0 | ||
| 2201 | #define AR_MCI_CONT_PRIORITY 0x0000FF00 | ||
| 2202 | #define AR_MCI_CONT_PRIORITY_S 8 | ||
| 2203 | #define AR_MCI_CONT_TXRX 0x00010000 | ||
| 2204 | #define AR_MCI_CONT_TXRX_S 16 | ||
| 2205 | |||
| 2206 | #define AR_MCI_BT_PRI0 0x184c | ||
| 2207 | #define AR_MCI_BT_PRI1 0x1850 | ||
| 2208 | #define AR_MCI_BT_PRI2 0x1854 | ||
| 2209 | #define AR_MCI_BT_PRI3 0x1858 | ||
| 2210 | #define AR_MCI_BT_PRI 0x185c | ||
| 2211 | #define AR_MCI_WL_FREQ0 0x1860 | ||
| 2212 | #define AR_MCI_WL_FREQ1 0x1864 | ||
| 2213 | #define AR_MCI_WL_FREQ2 0x1868 | ||
| 2214 | #define AR_MCI_GAIN 0x186c | ||
| 2215 | #define AR_MCI_WBTIMER1 0x1870 | ||
| 2216 | #define AR_MCI_WBTIMER2 0x1874 | ||
| 2217 | #define AR_MCI_WBTIMER3 0x1878 | ||
| 2218 | #define AR_MCI_WBTIMER4 0x187c | ||
| 2219 | #define AR_MCI_MAXGAIN 0x1880 | ||
| 2220 | #define AR_MCI_HW_SCHD_TBL_CTL 0x1884 | ||
| 2221 | #define AR_MCI_HW_SCHD_TBL_D0 0x1888 | ||
| 2222 | #define AR_MCI_HW_SCHD_TBL_D1 0x188c | ||
| 2223 | #define AR_MCI_HW_SCHD_TBL_D2 0x1890 | ||
| 2224 | #define AR_MCI_HW_SCHD_TBL_D3 0x1894 | ||
| 2225 | #define AR_MCI_TX_PAYLOAD0 0x1898 | ||
| 2226 | #define AR_MCI_TX_PAYLOAD1 0x189c | ||
| 2227 | #define AR_MCI_TX_PAYLOAD2 0x18a0 | ||
| 2228 | #define AR_MCI_TX_PAYLOAD3 0x18a4 | ||
| 2229 | #define AR_BTCOEX_WBTIMER 0x18a8 | ||
| 2230 | |||
| 2231 | #define AR_BTCOEX_CTRL 0x18ac | ||
| 2232 | #define AR_BTCOEX_CTRL_AR9462_MODE 0x00000001 | ||
| 2233 | #define AR_BTCOEX_CTRL_AR9462_MODE_S 0 | ||
| 2234 | #define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002 | ||
| 2235 | #define AR_BTCOEX_CTRL_WBTIMER_EN_S 1 | ||
| 2236 | #define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004 | ||
| 2237 | #define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2 | ||
| 2238 | #define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008 | ||
| 2239 | #define AR_BTCOEX_CTRL_LNA_SHARED_S 3 | ||
| 2240 | #define AR_BTCOEX_CTRL_PA_SHARED 0x00000010 | ||
| 2241 | #define AR_BTCOEX_CTRL_PA_SHARED_S 4 | ||
| 2242 | #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020 | ||
| 2243 | #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5 | ||
| 2244 | #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040 | ||
| 2245 | #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6 | ||
| 2246 | #define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180 | ||
| 2247 | #define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7 | ||
| 2248 | #define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00 | ||
| 2249 | #define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9 | ||
| 2250 | #define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000 | ||
| 2251 | #define AR_BTCOEX_CTRL_AGGR_THRESH_S 12 | ||
| 2252 | #define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000 | ||
| 2253 | #define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19 | ||
| 2254 | #define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000 | ||
| 2255 | #define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20 | ||
| 2256 | #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000 | ||
| 2257 | #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28 | ||
| 2258 | #define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000 | ||
| 2259 | #define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29 | ||
| 2260 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000 | ||
| 2261 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30 | ||
| 2262 | #define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 | ||
| 2263 | #define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 | ||
| 2264 | |||
| 2265 | #define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2)) | ||
| 2266 | #define AR_BTCOEX_WL_LNA 0x1940 | ||
| 2267 | #define AR_BTCOEX_RFGAIN_CTRL 0x1944 | ||
| 2268 | #define AR_BTCOEX_WL_LNA_TIMEOUT 0x003FFFFF | ||
| 2269 | #define AR_BTCOEX_WL_LNA_TIMEOUT_S 0 | ||
| 2270 | |||
| 2271 | #define AR_BTCOEX_CTRL2 0x1948 | ||
| 2272 | #define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800 | ||
| 2273 | #define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11 | ||
| 2274 | #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000 | ||
| 2275 | #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19 | ||
| 2276 | #define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000 | ||
| 2277 | #define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22 | ||
| 2278 | #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000 | ||
| 2279 | #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23 | ||
| 2280 | #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000 | ||
| 2281 | #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24 | ||
| 2282 | #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000 | ||
| 2283 | #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25 | ||
| 2284 | |||
| 2285 | #define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001 | ||
| 2286 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0 | ||
| 2287 | #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002 | ||
| 2288 | #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1 | ||
| 2289 | #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004 | ||
| 2290 | #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2 | ||
| 2291 | #define AR_GLB_WLAN_UART_INTF_EN 0x00020000 | ||
| 2292 | #define AR_GLB_WLAN_UART_INTF_EN_S 17 | ||
| 2293 | #define AR_GLB_DS_JTAG_DISABLE 0x00040000 | ||
| 2294 | #define AR_GLB_DS_JTAG_DISABLE_S 18 | ||
| 2295 | |||
| 2296 | #define AR_BTCOEX_RC 0x194c | ||
| 2297 | #define AR_BTCOEX_MAX_RFGAIN(_x) (0x1950 + ((_x) << 2)) | ||
| 2298 | #define AR_BTCOEX_DBG 0x1a50 | ||
| 2299 | #define AR_MCI_LAST_HW_MSG_HDR 0x1a54 | ||
| 2300 | #define AR_MCI_LAST_HW_MSG_BDY 0x1a58 | ||
| 2301 | |||
| 2302 | #define AR_MCI_SCHD_TABLE_2 0x1a5c | ||
| 2303 | #define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001 | ||
| 2304 | #define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0 | ||
| 2305 | #define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002 | ||
| 2306 | #define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1 | ||
| 2307 | |||
| 2308 | #define AR_BTCOEX_CTRL3 0x1a60 | ||
| 2309 | #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000fff | ||
| 2310 | #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0 | ||
| 2311 | |||
| 2312 | #define AR_GLB_SWREG_DISCONT_MODE 0x2002c | ||
| 2313 | #define AR_GLB_SWREG_DISCONT_EN_BT_WLAN 0x3 | ||
| 2314 | |||
| 2315 | #define AR_MCI_MISC 0x1a74 | ||
| 2316 | #define AR_MCI_MISC_HW_FIX_EN 0x00000001 | ||
| 2317 | #define AR_MCI_MISC_HW_FIX_EN_S 0 | ||
| 2318 | #define AR_MCI_DBG_CNT_CTRL 0x1a78 | ||
| 2319 | #define AR_MCI_DBG_CNT_CTRL_ENABLE 0x00000001 | ||
| 2320 | #define AR_MCI_DBG_CNT_CTRL_ENABLE_S 0 | ||
| 2321 | |||
| 2322 | #endif | 2047 | #endif |
diff --git a/drivers/net/wireless/ath/ath9k/reg_mci.h b/drivers/net/wireless/ath/ath9k/reg_mci.h new file mode 100644 index 000000000000..8d1572dcc05a --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/reg_mci.h | |||
| @@ -0,0 +1,300 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2015 Qualcomm Atheros Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_MCI_H | ||
| 18 | #define REG_MCI_H | ||
| 19 | |||
| 20 | #define AR_MCI_COMMAND0 0x1800 | ||
| 21 | #define AR_MCI_COMMAND0_HEADER 0xFF | ||
| 22 | #define AR_MCI_COMMAND0_HEADER_S 0 | ||
| 23 | #define AR_MCI_COMMAND0_LEN 0x1f00 | ||
| 24 | #define AR_MCI_COMMAND0_LEN_S 8 | ||
| 25 | #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000 | ||
| 26 | #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13 | ||
| 27 | |||
| 28 | #define AR_MCI_COMMAND1 0x1804 | ||
| 29 | |||
| 30 | #define AR_MCI_COMMAND2 0x1808 | ||
| 31 | #define AR_MCI_COMMAND2_RESET_TX 0x01 | ||
| 32 | #define AR_MCI_COMMAND2_RESET_TX_S 0 | ||
| 33 | #define AR_MCI_COMMAND2_RESET_RX 0x02 | ||
| 34 | #define AR_MCI_COMMAND2_RESET_RX_S 1 | ||
| 35 | #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC | ||
| 36 | #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2 | ||
| 37 | #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400 | ||
| 38 | #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10 | ||
| 39 | |||
| 40 | #define AR_MCI_RX_CTRL 0x180c | ||
| 41 | |||
| 42 | #define AR_MCI_TX_CTRL 0x1810 | ||
| 43 | /* | ||
| 44 | * 0 = no division, | ||
| 45 | * 1 = divide by 2, | ||
| 46 | * 2 = divide by 4, | ||
| 47 | * 3 = divide by 8 | ||
| 48 | */ | ||
| 49 | #define AR_MCI_TX_CTRL_CLK_DIV 0x03 | ||
| 50 | #define AR_MCI_TX_CTRL_CLK_DIV_S 0 | ||
| 51 | #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04 | ||
| 52 | #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2 | ||
| 53 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8 | ||
| 54 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3 | ||
| 55 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000 | ||
| 56 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24 | ||
| 57 | |||
| 58 | #define AR_MCI_MSG_ATTRIBUTES_TABLE 0x1814 | ||
| 59 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF | ||
| 60 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0 | ||
| 61 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000 | ||
| 62 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16 | ||
| 63 | |||
| 64 | #define AR_MCI_SCHD_TABLE_0 0x1818 | ||
| 65 | #define AR_MCI_SCHD_TABLE_1 0x181c | ||
| 66 | #define AR_MCI_GPM_0 0x1820 | ||
| 67 | #define AR_MCI_GPM_1 0x1824 | ||
| 68 | #define AR_MCI_GPM_WRITE_PTR 0xFFFF0000 | ||
| 69 | #define AR_MCI_GPM_WRITE_PTR_S 16 | ||
| 70 | #define AR_MCI_GPM_BUF_LEN 0x0000FFFF | ||
| 71 | #define AR_MCI_GPM_BUF_LEN_S 0 | ||
| 72 | |||
| 73 | #define AR_MCI_INTERRUPT_RAW 0x1828 | ||
| 74 | |||
| 75 | #define AR_MCI_INTERRUPT_EN 0x182c | ||
| 76 | #define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 | ||
| 77 | #define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0 | ||
| 78 | #define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 | ||
| 79 | #define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1 | ||
| 80 | #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004 | ||
| 81 | #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2 | ||
| 82 | #define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 | ||
| 83 | #define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3 | ||
| 84 | #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 | ||
| 85 | #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4 | ||
| 86 | #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 | ||
| 87 | #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5 | ||
| 88 | #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 | ||
| 89 | #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7 | ||
| 90 | #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 | ||
| 91 | #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8 | ||
| 92 | #define AR_MCI_INTERRUPT_RX_MSG 0x00000200 | ||
| 93 | #define AR_MCI_INTERRUPT_RX_MSG_S 9 | ||
| 94 | #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 | ||
| 95 | #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10 | ||
| 96 | #define AR_MCI_INTERRUPT_BT_PRI 0x07fff800 | ||
| 97 | #define AR_MCI_INTERRUPT_BT_PRI_S 11 | ||
| 98 | #define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000 | ||
| 99 | #define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27 | ||
| 100 | #define AR_MCI_INTERRUPT_BT_FREQ 0x10000000 | ||
| 101 | #define AR_MCI_INTERRUPT_BT_FREQ_S 28 | ||
| 102 | #define AR_MCI_INTERRUPT_BT_STOMP 0x20000000 | ||
| 103 | #define AR_MCI_INTERRUPT_BT_STOMP_S 29 | ||
| 104 | #define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000 | ||
| 105 | #define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30 | ||
| 106 | #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 | ||
| 107 | #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31 | ||
| 108 | |||
| 109 | #define AR_MCI_REMOTE_CPU_INT 0x1830 | ||
| 110 | #define AR_MCI_REMOTE_CPU_INT_EN 0x1834 | ||
| 111 | #define AR_MCI_INTERRUPT_RX_MSG_RAW 0x1838 | ||
| 112 | #define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c | ||
| 113 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 | ||
| 114 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 | ||
| 115 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 | ||
| 116 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 | ||
| 117 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 | ||
| 118 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 | ||
| 119 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 | ||
| 120 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 | ||
| 121 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 | ||
| 122 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 | ||
| 123 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 | ||
| 124 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 | ||
| 125 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 | ||
| 126 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 | ||
| 127 | #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 | ||
| 128 | #define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 | ||
| 129 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 | ||
| 130 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 | ||
| 131 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 | ||
| 132 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 | ||
| 133 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 | ||
| 134 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 | ||
| 135 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 | ||
| 136 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 | ||
| 137 | |||
| 138 | #define AR_MCI_CPU_INT 0x1840 | ||
| 139 | |||
| 140 | #define AR_MCI_RX_STATUS 0x1844 | ||
| 141 | #define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00 | ||
| 142 | #define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8 | ||
| 143 | #define AR_MCI_RX_REMOTE_SLEEP 0x00001000 | ||
| 144 | #define AR_MCI_RX_REMOTE_SLEEP_S 12 | ||
| 145 | #define AR_MCI_RX_MCI_CLK_REQ 0x00002000 | ||
| 146 | #define AR_MCI_RX_MCI_CLK_REQ_S 13 | ||
| 147 | |||
| 148 | #define AR_MCI_CONT_STATUS 0x1848 | ||
| 149 | #define AR_MCI_CONT_RSSI_POWER 0x000000FF | ||
| 150 | #define AR_MCI_CONT_RSSI_POWER_S 0 | ||
| 151 | #define AR_MCI_CONT_PRIORITY 0x0000FF00 | ||
| 152 | #define AR_MCI_CONT_PRIORITY_S 8 | ||
| 153 | #define AR_MCI_CONT_TXRX 0x00010000 | ||
| 154 | #define AR_MCI_CONT_TXRX_S 16 | ||
| 155 | |||
| 156 | #define AR_MCI_BT_PRI0 0x184c | ||
| 157 | #define AR_MCI_BT_PRI1 0x1850 | ||
| 158 | #define AR_MCI_BT_PRI2 0x1854 | ||
| 159 | #define AR_MCI_BT_PRI3 0x1858 | ||
| 160 | #define AR_MCI_BT_PRI 0x185c | ||
| 161 | #define AR_MCI_WL_FREQ0 0x1860 | ||
| 162 | #define AR_MCI_WL_FREQ1 0x1864 | ||
| 163 | #define AR_MCI_WL_FREQ2 0x1868 | ||
| 164 | #define AR_MCI_GAIN 0x186c | ||
| 165 | #define AR_MCI_WBTIMER1 0x1870 | ||
| 166 | #define AR_MCI_WBTIMER2 0x1874 | ||
| 167 | #define AR_MCI_WBTIMER3 0x1878 | ||
| 168 | #define AR_MCI_WBTIMER4 0x187c | ||
| 169 | #define AR_MCI_MAXGAIN 0x1880 | ||
| 170 | #define AR_MCI_HW_SCHD_TBL_CTL 0x1884 | ||
| 171 | #define AR_MCI_HW_SCHD_TBL_D0 0x1888 | ||
| 172 | #define AR_MCI_HW_SCHD_TBL_D1 0x188c | ||
| 173 | #define AR_MCI_HW_SCHD_TBL_D2 0x1890 | ||
| 174 | #define AR_MCI_HW_SCHD_TBL_D3 0x1894 | ||
| 175 | #define AR_MCI_TX_PAYLOAD0 0x1898 | ||
| 176 | #define AR_MCI_TX_PAYLOAD1 0x189c | ||
| 177 | #define AR_MCI_TX_PAYLOAD2 0x18a0 | ||
| 178 | #define AR_MCI_TX_PAYLOAD3 0x18a4 | ||
| 179 | #define AR_BTCOEX_WBTIMER 0x18a8 | ||
| 180 | |||
| 181 | #define AR_BTCOEX_CTRL 0x18ac | ||
| 182 | #define AR_BTCOEX_CTRL_AR9462_MODE 0x00000001 | ||
| 183 | #define AR_BTCOEX_CTRL_AR9462_MODE_S 0 | ||
| 184 | #define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002 | ||
| 185 | #define AR_BTCOEX_CTRL_WBTIMER_EN_S 1 | ||
| 186 | #define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004 | ||
| 187 | #define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2 | ||
| 188 | #define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008 | ||
| 189 | #define AR_BTCOEX_CTRL_LNA_SHARED_S 3 | ||
| 190 | #define AR_BTCOEX_CTRL_PA_SHARED 0x00000010 | ||
| 191 | #define AR_BTCOEX_CTRL_PA_SHARED_S 4 | ||
| 192 | #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020 | ||
| 193 | #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5 | ||
| 194 | #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040 | ||
| 195 | #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6 | ||
| 196 | #define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180 | ||
| 197 | #define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7 | ||
| 198 | #define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00 | ||
| 199 | #define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9 | ||
| 200 | #define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000 | ||
| 201 | #define AR_BTCOEX_CTRL_AGGR_THRESH_S 12 | ||
| 202 | #define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000 | ||
| 203 | #define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19 | ||
| 204 | #define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000 | ||
| 205 | #define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20 | ||
| 206 | #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000 | ||
| 207 | #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28 | ||
| 208 | #define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000 | ||
| 209 | #define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29 | ||
| 210 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000 | ||
| 211 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30 | ||
| 212 | #define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 | ||
| 213 | #define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 | ||
| 214 | |||
| 215 | #define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2)) | ||
| 216 | #define AR_BTCOEX_WL_LNA 0x1940 | ||
| 217 | #define AR_BTCOEX_RFGAIN_CTRL 0x1944 | ||
| 218 | #define AR_BTCOEX_WL_LNA_TIMEOUT 0x003FFFFF | ||
| 219 | #define AR_BTCOEX_WL_LNA_TIMEOUT_S 0 | ||
| 220 | |||
| 221 | #define AR_BTCOEX_CTRL2 0x1948 | ||
| 222 | #define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800 | ||
| 223 | #define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11 | ||
| 224 | #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000 | ||
| 225 | #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19 | ||
| 226 | #define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000 | ||
| 227 | #define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22 | ||
| 228 | #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000 | ||
| 229 | #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23 | ||
| 230 | #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000 | ||
| 231 | #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24 | ||
| 232 | #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000 | ||
| 233 | #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25 | ||
| 234 | |||
| 235 | #define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001 | ||
| 236 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0 | ||
| 237 | #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002 | ||
| 238 | #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1 | ||
| 239 | #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004 | ||
| 240 | #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2 | ||
| 241 | #define AR_GLB_WLAN_UART_INTF_EN 0x00020000 | ||
| 242 | #define AR_GLB_WLAN_UART_INTF_EN_S 17 | ||
| 243 | #define AR_GLB_DS_JTAG_DISABLE 0x00040000 | ||
| 244 | #define AR_GLB_DS_JTAG_DISABLE_S 18 | ||
| 245 | |||
| 246 | #define AR_BTCOEX_RC 0x194c | ||
| 247 | #define AR_BTCOEX_MAX_RFGAIN(_x) (0x1950 + ((_x) << 2)) | ||
| 248 | #define AR_BTCOEX_DBG 0x1a50 | ||
| 249 | #define AR_MCI_LAST_HW_MSG_HDR 0x1a54 | ||
| 250 | #define AR_MCI_LAST_HW_MSG_BDY 0x1a58 | ||
| 251 | |||
| 252 | #define AR_MCI_SCHD_TABLE_2 0x1a5c | ||
| 253 | #define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001 | ||
| 254 | #define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0 | ||
| 255 | #define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002 | ||
| 256 | #define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1 | ||
| 257 | |||
| 258 | #define AR_BTCOEX_CTRL3 0x1a60 | ||
| 259 | #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000fff | ||
| 260 | #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0 | ||
| 261 | |||
| 262 | #define AR_GLB_SWREG_DISCONT_MODE 0x2002c | ||
| 263 | #define AR_GLB_SWREG_DISCONT_EN_BT_WLAN 0x3 | ||
| 264 | |||
| 265 | #define AR_MCI_MISC 0x1a74 | ||
| 266 | #define AR_MCI_MISC_HW_FIX_EN 0x00000001 | ||
| 267 | #define AR_MCI_MISC_HW_FIX_EN_S 0 | ||
| 268 | #define AR_MCI_DBG_CNT_CTRL 0x1a78 | ||
| 269 | #define AR_MCI_DBG_CNT_CTRL_ENABLE 0x00000001 | ||
| 270 | #define AR_MCI_DBG_CNT_CTRL_ENABLE_S 0 | ||
| 271 | |||
| 272 | #define AR_MCI_INTERRUPT_DEFAULT (AR_MCI_INTERRUPT_SW_MSG_DONE | \ | ||
| 273 | AR_MCI_INTERRUPT_RX_INVALID_HDR | \ | ||
| 274 | AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ | ||
| 275 | AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ | ||
| 276 | AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ | ||
| 277 | AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \ | ||
| 278 | AR_MCI_INTERRUPT_RX_MSG | \ | ||
| 279 | AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \ | ||
| 280 | AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT) | ||
| 281 | |||
| 282 | #define AR_MCI_INTERRUPT_MSG_FAIL_MASK (AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ | ||
| 283 | AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ | ||
| 284 | AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ | ||
| 285 | AR_MCI_INTERRUPT_TX_SW_MSG_FAIL) | ||
| 286 | |||
| 287 | #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ | ||
| 288 | AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ | ||
| 289 | AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ | ||
| 290 | AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ | ||
| 291 | AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ | ||
| 292 | AR_MCI_INTERRUPT_RX_MSG_CONT_RST) | ||
| 293 | |||
| 294 | #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT (AR_MCI_INTERRUPT_RX_MSG_GPM | \ | ||
| 295 | AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \ | ||
| 296 | AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ | ||
| 297 | AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \ | ||
| 298 | AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) | ||
| 299 | |||
| 300 | #endif /* REG_MCI_H */ | ||