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authorLinus Walleij <linus.walleij@linaro.org>2012-10-15 04:17:15 -0400
committerLinus Walleij <linus.walleij@linaro.org>2012-10-15 04:17:15 -0400
commitae0407e137ebea3c573b47246b3ca0e7076b07e8 (patch)
treefa453f69f2dcce1ba8a708f605a7f16de72024df
parentddffeb8c4d0331609ef2581d84de4d763607bd37 (diff)
parent251e783ad0375470fa4fd3848645a38c5d3ee6c3 (diff)
Merge branch 'j/pinctrl' of http://github.com/at91linux/linux-at91 into at91
Diffstat
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio_atmel.txt5
-rw-r--r--Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt136
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/Makefile44
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi187
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi173
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts1
-rw-r--r--arch/arm/boot/dts/at91sam9g15.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g15ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_common.dtsi6
-rw-r--r--arch/arm/boot/dts/at91sam9g25.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts49
-rw-r--r--arch/arm/boot/dts/at91sam9g35.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g35ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi189
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts1
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi180
-rw-r--r--arch/arm/boot/dts/at91sam9x25.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9x25ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9x35.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9x35ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi178
-rw-r--r--arch/arm/boot/dts/at91sam9x5ek.dtsi59
-rw-r--r--arch/arm/configs/at91_dt_defconfig1
-rw-r--r--arch/arm/mach-at91/at91rm9200.c4
-rw-r--r--arch/arm/mach-at91/at91sam9260.c7
-rw-r--r--arch/arm/mach-at91/at91sam9261.c4
-rw-r--r--arch/arm/mach-at91/at91sam9263.c9
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c10
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c15
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c4
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c19
-rw-r--r--arch/arm/mach-at91/board-dt.c2
-rw-r--r--arch/arm/mach-at91/gpio.c190
-rw-r--r--arch/arm/mach-at91/setup.c6
-rw-r--r--arch/arm/mach-at91/soc.h12
-rw-r--r--drivers/mtd/nand/atmel_nand.c9
-rw-r--r--drivers/pinctrl/Kconfig9
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/pinctrl-at91.c1490
-rw-r--r--drivers/tty/serial/atmel_serial.c8
41 files changed, 2768 insertions, 446 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
index 66efc804806a..85f8c0d084fa 100644
--- a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
@@ -9,6 +9,10 @@ Required properties:
9 unused). 9 unused).
10- gpio-controller: Marks the device node as a GPIO controller. 10- gpio-controller: Marks the device node as a GPIO controller.
11 11
12optional properties:
13- #gpio-lines: Number of gpio if absent 32.
14
15
12Example: 16Example:
13 pioA: gpio@fffff200 { 17 pioA: gpio@fffff200 {
14 compatible = "atmel,at91rm9200-gpio"; 18 compatible = "atmel,at91rm9200-gpio";
@@ -16,5 +20,6 @@ Example:
16 interrupts = <2 4>; 20 interrupts = <2 4>;
17 #gpio-cells = <2>; 21 #gpio-cells = <2>;
18 gpio-controller; 22 gpio-controller;
23 #gpio-lines = <19>;
19 }; 24 };
20 25
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
new file mode 100644
index 000000000000..20a987e55a28
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -0,0 +1,136 @@
1* Atmel AT91 Pinmux Controller
2
3The AT91 Pinmux Controler, enables the IC
4to share one PAD to several functional blocks. The sharing is done by
5multiplexing the PAD input/output signals. For each PAD there are up to
68 muxing options (called periph modes). Since different modules require
7different PAD settings (like pull up, keeper, etc) the contoller controls
8also the PAD settings parameters.
9
10Please refer to pinctrl-bindings.txt in this directory for details of the
11common pinctrl bindings used by client devices, including the meaning of the
12phrase "pin configuration node".
13
14Atmel AT91 pin configuration node is a node of a group of pins which can be
15used for a specific device or function. This node represents both mux and config
16of the pins in that group. The 'pins' selects the function mode(also named pin
17mode) this pin can work on and the 'config' configures various pad settings
18such as pull-up, multi drive, etc.
19
20Required properties for iomux controller:
21- compatible: "atmel,at91rm9200-pinctrl"
22- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
23 configured in this periph mode. All the periph and bank need to be describe.
24
25How to create such array:
26
27Each column will represent the possible peripheral of the pinctrl
28Each line will represent a pio bank
29
30Take an example on the 9260
31Peripheral: 2 ( A and B)
32Bank: 3 (A, B and C)
33=>
34
35 /* A B */
36 0xffffffff 0xffc00c3b /* pioA */
37 0xffffffff 0x7fff3ccf /* pioB */
38 0xffffffff 0x007fffff /* pioC */
39
40For each peripheral/bank we will descibe in a u32 if a pin can can be
41configured in it by putting 1 to the pin bit (1 << pin)
42
43Let's take the pioA on peripheral B
44From the datasheet Table 10-2.
45Peripheral B
46PA0 MCDB0
47PA1 MCCDB
48PA2
49PA3 MCDB3
50PA4 MCDB2
51PA5 MCDB1
52PA6
53PA7
54PA8
55PA9
56PA10 ETX2
57PA11 ETX3
58PA12
59PA13
60PA14
61PA15
62PA16
63PA17
64PA18
65PA19
66PA20
67PA21
68PA22 ETXER
69PA23 ETX2
70PA24 ETX3
71PA25 ERX2
72PA26 ERX3
73PA27 ERXCK
74PA28 ECRS
75PA29 ECOL
76PA30 RXD4
77PA31 TXD4
78
79=> 0xffc00c3b
80
81Required properties for pin configuration node:
82- atmel,pins: 4 integers array, represents a group of pins mux and config
83 setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
84 The PERIPH 0 means gpio.
85
86Bits used for CONFIG:
87PULL_UP(1 << 0): indicate this pin need a pull up.
88MULTIDRIVE(1 << 1): indicate this pin need to be configured as multidrive.
89
90NOTE:
91Some requirements for using atmel,at91rm9200-pinctrl binding:
921. We have pin function node defined under at91 controller node to represent
93 what pinmux functions this SoC supports.
942. The driver can use the function node's name and pin configuration node's
95 name describe the pin function and group hierarchy.
96 For example, Linux at91 pinctrl driver takes the function node's name
97 as the function name and pin configuration node's name as group name to
98 create the map table.
993. Each pin configuration node should have a phandle, devices can set pins
100 configurations by referring to the phandle of that pin configuration node.
1014. The gpio controller must be describe in the pinctrl simple-bus.
102
103Examples:
104
105pinctrl@fffff400 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges;
109 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
110 reg = <0xfffff400 0x600>;
111
112 atmel,mux-mask = <
113 /* A B */
114 0xffffffff 0xffc00c3b /* pioA */
115 0xffffffff 0x7fff3ccf /* pioB */
116 0xffffffff 0x007fffff /* pioC */
117 >;
118
119 /* shared pinctrl settings */
120 dbgu {
121 pinctrl_dbgu: dbgu-0 {
122 atmel,pins =
123 <1 14 0x1 0x0 /* PB14 periph A */
124 1 15 0x1 0x1>; /* PB15 periph with pullup */
125 };
126 };
127};
128
129dbgu: serial@fffff200 {
130 compatible = "atmel,at91sam9260-usart";
131 reg = <0xfffff200 0x200>;
132 interrupts = <1 4 7>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_dbgu>;
135 status = "disabled";
136};
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 73067efd4845..7c3b522a20f5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -330,6 +330,8 @@ config ARCH_AT91
330 select IRQ_DOMAIN 330 select IRQ_DOMAIN
331 select NEED_MACH_GPIO_H 331 select NEED_MACH_GPIO_H
332 select NEED_MACH_IO_H if PCCARD 332 select NEED_MACH_IO_H if PCCARD
333 select PINCTRL
334 select PINCTRL_AT91 if USE_OF
333 help 335 help
334 This enables support for systems based on Atmel 336 This enables support for systems based on Atmel
335 AT91RM9200 and AT91SAM9* processors. 337 AT91RM9200 and AT91SAM9* processors.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c1ce813fcc4a..a9b051a8f70e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,21 +1,33 @@
1ifeq ($(CONFIG_OF),y) 1ifeq ($(CONFIG_OF),y)
2 2
3dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \ 3# Keep at91 dtb files sorted alphabetically for each SoC
4 at91sam9263ek.dtb \ 4# sam9260
5 at91sam9g20ek_2mmc.dtb \ 5dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
6 at91sam9g20ek.dtb \ 6dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
7 at91sam9g25ek.dtb \ 7dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
8 at91sam9m10g45ek.dtb \ 8dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
9 at91sam9n12ek.dtb \ 9dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
10 ethernut5.dtb \ 10# sam9263
11 evk-pro3.dtb \ 11dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
12 kizbox.dtb \ 12dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
13 tny_a9260.dtb \ 13dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
14 tny_a9263.dtb \ 14# sam9g20
15 tny_a9g20.dtb \ 15dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
16 usb_a9260.dtb \ 16dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
17 usb_a9263.dtb \ 17dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
18 usb_a9g20.dtb 18dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
19dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
20# sam9g45
21dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
22# sam9n12
23dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
24# sam9x5
25dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
26dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
27dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
28dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
29dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
30
19dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 31dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
20dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ 32dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
21 dove-cubox.dtb \ 33 dove-cubox.dtb \
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index d410581a5a85..9a24ffbb7231 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -98,40 +98,161 @@
98 interrupts = <26 4 0 27 4 0 28 4 0>; 98 interrupts = <26 4 0 27 4 0 28 4 0>;
99 }; 99 };
100 100
101 pioA: gpio@fffff400 { 101 pinctrl@fffff400 {
102 compatible = "atmel,at91rm9200-gpio"; 102 #address-cells = <1>;
103 reg = <0xfffff400 0x100>; 103 #size-cells = <1>;
104 interrupts = <2 4 1>; 104 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
105 #gpio-cells = <2>; 105 ranges = <0xfffff400 0xfffff400 0x600>;
106 gpio-controller; 106
107 interrupt-controller; 107 atmel,mux-mask = <
108 #interrupt-cells = <2>; 108 /* A B */
109 }; 109 0xffffffff 0xffc00c3b /* pioA */
110 0xffffffff 0x7fff3ccf /* pioB */
111 0xffffffff 0x007fffff /* pioC */
112 >;
113
114 /* shared pinctrl settings */
115 dbgu {
116 pinctrl_dbgu: dbgu-0 {
117 atmel,pins =
118 <1 14 0x1 0x0 /* PB14 periph A */
119 1 15 0x1 0x1>; /* PB15 periph with pullup */
120 };
121 };
110 122
111 pioB: gpio@fffff600 { 123 uart0 {
112 compatible = "atmel,at91rm9200-gpio"; 124 pinctrl_uart0: uart0-0 {
113 reg = <0xfffff600 0x100>; 125 atmel,pins =
114 interrupts = <3 4 1>; 126 <1 4 0x1 0x0 /* PB4 periph A */
115 #gpio-cells = <2>; 127 1 5 0x1 0x0>; /* PB5 periph A */
116 gpio-controller; 128 };
117 interrupt-controller; 129
118 #interrupt-cells = <2>; 130 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
119 }; 131 atmel,pins =
132 <1 26 0x1 0x0 /* PB26 periph A */
133 1 27 0x1 0x0>; /* PB27 periph A */
134 };
135
136 pinctrl_uart0_dtr_dsr: uart0_dtr_dsr-0 {
137 atmel,pins =
138 <1 24 0x1 0x0 /* PB24 periph A */
139 1 22 0x1 0x0>; /* PB22 periph A */
140 };
141
142 pinctrl_uart0_dcd: uart0_dcd-0 {
143 atmel,pins =
144 <1 23 0x1 0x0>; /* PB23 periph A */
145 };
146
147 pinctrl_uart0_ri: uart0_ri-0 {
148 atmel,pins =
149 <1 25 0x1 0x0>; /* PB25 periph A */
150 };
151 };
120 152
121 pioC: gpio@fffff800 { 153 uart1 {
122 compatible = "atmel,at91rm9200-gpio"; 154 pinctrl_uart1: uart1-0 {
123 reg = <0xfffff800 0x100>; 155 atmel,pins =
124 interrupts = <4 4 1>; 156 <2 6 0x1 0x1 /* PB6 periph A with pullup */
125 #gpio-cells = <2>; 157 2 7 0x1 0x0>; /* PB7 periph A */
126 gpio-controller; 158 };
127 interrupt-controller; 159
128 #interrupt-cells = <2>; 160 pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
161 atmel,pins =
162 <1 28 0x1 0x0 /* PB28 periph A */
163 1 29 0x1 0x0>; /* PB29 periph A */
164 };
165 };
166
167 uart2 {
168 pinctrl_uart2: uart2-0 {
169 atmel,pins =
170 <1 8 0x1 0x1 /* PB8 periph A with pullup */
171 1 9 0x1 0x0>; /* PB9 periph A */
172 };
173
174 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
175 atmel,pins =
176 <0 4 0x1 0x0 /* PA4 periph A */
177 0 5 0x1 0x0>; /* PA5 periph A */
178 };
179 };
180
181 uart3 {
182 pinctrl_uart3: uart3-0 {
183 atmel,pins =
184 <2 10 0x1 0x1 /* PB10 periph A with pullup */
185 2 11 0x1 0x0>; /* PB11 periph A */
186 };
187
188 pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
189 atmel,pins =
190 <3 8 0x2 0x0 /* PB8 periph B */
191 3 10 0x2 0x0>; /* PB10 periph B */
192 };
193 };
194
195 uart4 {
196 pinctrl_uart4: uart4-0 {
197 atmel,pins =
198 <0 31 0x2 0x1 /* PA31 periph B with pullup */
199 0 30 0x2 0x0>; /* PA30 periph B */
200 };
201 };
202
203 uart5 {
204 pinctrl_uart5: uart5-0 {
205 atmel,pins =
206 <2 12 0x1 0x1 /* PB12 periph A with pullup */
207 2 13 0x1 0x0>; /* PB13 periph A */
208 };
209 };
210
211 nand {
212 pinctrl_nand: nand-0 {
213 atmel,pins =
214 <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
215 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
216 };
217 };
218
219 pioA: gpio@fffff400 {
220 compatible = "atmel,at91rm9200-gpio";
221 reg = <0xfffff400 0x200>;
222 interrupts = <2 4 1>;
223 #gpio-cells = <2>;
224 gpio-controller;
225 interrupt-controller;
226 #interrupt-cells = <2>;
227 };
228
229 pioB: gpio@fffff600 {
230 compatible = "atmel,at91rm9200-gpio";
231 reg = <0xfffff600 0x200>;
232 interrupts = <3 4 1>;
233 #gpio-cells = <2>;
234 gpio-controller;
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 };
238
239 pioC: gpio@fffff800 {
240 compatible = "atmel,at91rm9200-gpio";
241 reg = <0xfffff800 0x200>;
242 interrupts = <4 4 1>;
243 #gpio-cells = <2>;
244 gpio-controller;
245 interrupt-controller;
246 #interrupt-cells = <2>;
247 };
129 }; 248 };
130 249
131 dbgu: serial@fffff200 { 250 dbgu: serial@fffff200 {
132 compatible = "atmel,at91sam9260-usart"; 251 compatible = "atmel,at91sam9260-usart";
133 reg = <0xfffff200 0x200>; 252 reg = <0xfffff200 0x200>;
134 interrupts = <1 4 7>; 253 interrupts = <1 4 7>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_dbgu>;
135 status = "disabled"; 256 status = "disabled";
136 }; 257 };
137 258
@@ -141,6 +262,8 @@
141 interrupts = <6 4 5>; 262 interrupts = <6 4 5>;
142 atmel,use-dma-rx; 263 atmel,use-dma-rx;
143 atmel,use-dma-tx; 264 atmel,use-dma-tx;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart0>;
144 status = "disabled"; 267 status = "disabled";
145 }; 268 };
146 269
@@ -150,6 +273,8 @@
150 interrupts = <7 4 5>; 273 interrupts = <7 4 5>;
151 atmel,use-dma-rx; 274 atmel,use-dma-rx;
152 atmel,use-dma-tx; 275 atmel,use-dma-tx;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_uart1>;
153 status = "disabled"; 278 status = "disabled";
154 }; 279 };
155 280
@@ -159,6 +284,8 @@
159 interrupts = <8 4 5>; 284 interrupts = <8 4 5>;
160 atmel,use-dma-rx; 285 atmel,use-dma-rx;
161 atmel,use-dma-tx; 286 atmel,use-dma-tx;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_uart2>;
162 status = "disabled"; 289 status = "disabled";
163 }; 290 };
164 291
@@ -168,6 +295,8 @@
168 interrupts = <23 4 5>; 295 interrupts = <23 4 5>;
169 atmel,use-dma-rx; 296 atmel,use-dma-rx;
170 atmel,use-dma-tx; 297 atmel,use-dma-tx;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_uart3>;
171 status = "disabled"; 300 status = "disabled";
172 }; 301 };
173 302
@@ -177,6 +306,8 @@
177 interrupts = <24 4 5>; 306 interrupts = <24 4 5>;
178 atmel,use-dma-rx; 307 atmel,use-dma-rx;
179 atmel,use-dma-tx; 308 atmel,use-dma-tx;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_uart4>;
180 status = "disabled"; 311 status = "disabled";
181 }; 312 };
182 313
@@ -186,6 +317,8 @@
186 interrupts = <25 4 5>; 317 interrupts = <25 4 5>;
187 atmel,use-dma-rx; 318 atmel,use-dma-rx;
188 atmel,use-dma-tx; 319 atmel,use-dma-tx;
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_uart5>;
189 status = "disabled"; 322 status = "disabled";
190 }; 323 };
191 324
@@ -257,6 +390,8 @@
257 >; 390 >;
258 atmel,nand-addr-offset = <21>; 391 atmel,nand-addr-offset = <21>;
259 atmel,nand-cmd-offset = <22>; 392 atmel,nand-cmd-offset = <22>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_nand>;
260 gpios = <&pioC 13 0 395 gpios = <&pioC 13 0
261 &pioC 14 0 396 &pioC 14 0
262 0 397 0
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 3e6e5c1abbf3..251ccec430a4 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -89,60 +89,137 @@
89 reg = <0xfffffd10 0x10>; 89 reg = <0xfffffd10 0x10>;
90 }; 90 };
91 91
92 pioA: gpio@fffff200 { 92 pinctrl@fffff200 {
93 compatible = "atmel,at91rm9200-gpio"; 93 #address-cells = <1>;
94 reg = <0xfffff200 0x100>; 94 #size-cells = <1>;
95 interrupts = <2 4 1>; 95 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
96 #gpio-cells = <2>; 96 ranges = <0xfffff200 0xfffff200 0xa00>;
97 gpio-controller;
98 interrupt-controller;
99 #interrupt-cells = <2>;
100 };
101 97
102 pioB: gpio@fffff400 { 98 atmel,mux-mask = <
103 compatible = "atmel,at91rm9200-gpio"; 99 /* A B */
104 reg = <0xfffff400 0x100>; 100 0xfffffffb 0xffffe07f /* pioA */
105 interrupts = <3 4 1>; 101 0x0007ffff 0x39072fff /* pioB */
106 #gpio-cells = <2>; 102 0xffffffff 0x3ffffff8 /* pioC */
107 gpio-controller; 103 0xfffffbff 0xffffffff /* pioD */
108 interrupt-controller; 104 0xffe00fff 0xfbfcff00 /* pioE */
109 #interrupt-cells = <2>; 105 >;
110 };
111 106
112 pioC: gpio@fffff600 { 107 /* shared pinctrl settings */
113 compatible = "atmel,at91rm9200-gpio"; 108 dbgu {
114 reg = <0xfffff600 0x100>; 109 pinctrl_dbgu: dbgu-0 {
115 interrupts = <4 4 1>; 110 atmel,pins =
116 #gpio-cells = <2>; 111 <2 30 0x1 0x0 /* PC30 periph A */
117 gpio-controller; 112 2 31 0x1 0x1>; /* PC31 periph with pullup */
118 interrupt-controller; 113 };
119 #interrupt-cells = <2>; 114 };
120 };
121 115
122 pioD: gpio@fffff800 { 116 uart0 {
123 compatible = "atmel,at91rm9200-gpio"; 117 pinctrl_uart0: uart0-0 {
124 reg = <0xfffff800 0x100>; 118 atmel,pins =
125 interrupts = <4 4 1>; 119 <0 26 0x1 0x1 /* PA26 periph A with pullup */
126 #gpio-cells = <2>; 120 0 27 0x1 0x0>; /* PA27 periph A */
127 gpio-controller; 121 };
128 interrupt-controller;
129 #interrupt-cells = <2>;
130 };
131 122
132 pioE: gpio@fffffa00 { 123 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
133 compatible = "atmel,at91rm9200-gpio"; 124 atmel,pins =
134 reg = <0xfffffa00 0x100>; 125 <0 28 0x1 0x0 /* PA28 periph A */
135 interrupts = <4 4 1>; 126 0 29 0x1 0x0>; /* PA29 periph A */
136 #gpio-cells = <2>; 127 };
137 gpio-controller; 128 };
138 interrupt-controller; 129
139 #interrupt-cells = <2>; 130 uart1 {
131 pinctrl_uart1: uart1-0 {
132 atmel,pins =
133 <3 0 0x1 0x1 /* PD0 periph A with pullup */
134 3 1 0x1 0x0>; /* PD1 periph A */
135 };
136
137 pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
138 atmel,pins =
139 <3 7 0x2 0x0 /* PD7 periph B */
140 3 8 0x2 0x0>; /* PD8 periph B */
141 };
142 };
143
144 uart2 {
145 pinctrl_uart2: uart2-0 {
146 atmel,pins =
147 <3 2 0x1 0x1 /* PD2 periph A with pullup */
148 3 3 0x1 0x0>; /* PD3 periph A */
149 };
150
151 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
152 atmel,pins =
153 <3 5 0x2 0x0 /* PD5 periph B */
154 4 6 0x2 0x0>; /* PD6 periph B */
155 };
156 };
157
158 nand {
159 pinctrl_nand: nand-0 {
160 atmel,pins =
161 <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
162 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
163 };
164 };
165
166 pioA: gpio@fffff200 {
167 compatible = "atmel,at91rm9200-gpio";
168 reg = <0xfffff200 0x200>;
169 interrupts = <2 4 1>;
170 #gpio-cells = <2>;
171 gpio-controller;
172 interrupt-controller;
173 #interrupt-cells = <2>;
174 };
175
176 pioB: gpio@fffff400 {
177 compatible = "atmel,at91rm9200-gpio";
178 reg = <0xfffff400 0x200>;
179 interrupts = <3 4 1>;
180 #gpio-cells = <2>;
181 gpio-controller;
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 };
185
186 pioC: gpio@fffff600 {
187 compatible = "atmel,at91rm9200-gpio";
188 reg = <0xfffff600 0x200>;
189 interrupts = <4 4 1>;
190 #gpio-cells = <2>;
191 gpio-controller;
192 interrupt-controller;
193 #interrupt-cells = <2>;
194 };
195
196 pioD: gpio@fffff800 {
197 compatible = "atmel,at91rm9200-gpio";
198 reg = <0xfffff800 0x200>;
199 interrupts = <4 4 1>;
200 #gpio-cells = <2>;
201 gpio-controller;
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 };
205
206 pioE: gpio@fffffa00 {
207 compatible = "atmel,at91rm9200-gpio";
208 reg = <0xfffffa00 0x200>;
209 interrupts = <4 4 1>;
210 #gpio-cells = <2>;
211 gpio-controller;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
140 }; 215 };
141 216
142 dbgu: serial@ffffee00 { 217 dbgu: serial@ffffee00 {
143 compatible = "atmel,at91sam9260-usart"; 218 compatible = "atmel,at91sam9260-usart";
144 reg = <0xffffee00 0x200>; 219 reg = <0xffffee00 0x200>;
145 interrupts = <1 4 7>; 220 interrupts = <1 4 7>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_dbgu>;
146 status = "disabled"; 223 status = "disabled";
147 }; 224 };
148 225
@@ -152,6 +229,8 @@
152 interrupts = <7 4 5>; 229 interrupts = <7 4 5>;
153 atmel,use-dma-rx; 230 atmel,use-dma-rx;
154 atmel,use-dma-tx; 231 atmel,use-dma-tx;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart0>;
155 status = "disabled"; 234 status = "disabled";
156 }; 235 };
157 236
@@ -161,6 +240,8 @@
161 interrupts = <8 4 5>; 240 interrupts = <8 4 5>;
162 atmel,use-dma-rx; 241 atmel,use-dma-rx;
163 atmel,use-dma-tx; 242 atmel,use-dma-tx;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_uart1>;
164 status = "disabled"; 245 status = "disabled";
165 }; 246 };
166 247
@@ -170,6 +251,8 @@
170 interrupts = <9 4 5>; 251 interrupts = <9 4 5>;
171 atmel,use-dma-rx; 252 atmel,use-dma-rx;
172 atmel,use-dma-tx; 253 atmel,use-dma-tx;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart2>;
173 status = "disabled"; 256 status = "disabled";
174 }; 257 };
175 258
@@ -206,6 +289,8 @@
206 >; 289 >;
207 atmel,nand-addr-offset = <21>; 290 atmel,nand-addr-offset = <21>;
208 atmel,nand-cmd-offset = <22>; 291 atmel,nand-cmd-offset = <22>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_nand>;
209 gpios = <&pioA 22 0 294 gpios = <&pioA 22 0
210 &pioD 15 0 295 &pioD 15 0
211 0 296 0
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index f86ac4b609fc..7cfe9d521f12 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -38,6 +38,7 @@
38 }; 38 };
39 39
40 usart0: serial@fff8c000 { 40 usart0: serial@fff8c000 {
41 pinctrl-0 = <&pinctrl_uart0 &pinctrl_uart0_rts_cts>;
41 status = "okay"; 42 status = "okay";
42 }; 43 };
43 44
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
new file mode 100644
index 000000000000..fbe7a7089c2a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G15 SoC";
13 compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0x00000000 /* pioA */
21 0x00040000 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
new file mode 100644
index 000000000000..86dd3f6d938f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g15.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index b06c0db273b1..e33ab0a88d04 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -35,6 +35,12 @@
35 }; 35 };
36 36
37 usart0: serial@fffb0000 { 37 usart0: serial@fffb0000 {
38 pinctrl-0 =
39 <&pinctrl_uart0
40 &pinctrl_uart0_rts_cts
41 &pinctrl_uart0_dtr_dsr
42 &pinctrl_uart0_dcd
43 &pinctrl_uart0_ri>;
38 status = "okay"; 44 status = "okay";
39 }; 45 };
40 46
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
new file mode 100644
index 000000000000..05a718fb83c4
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G25 SoC";
13 compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0xc000001c /* pioA */
21 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */
22 0x80000000 0x07c0ffff 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 877c08f06763..c5ab16fba059 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -7,55 +7,10 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10/include/ "at91sam9x5.dtsi" 10/include/ "at91sam9g25.dtsi"
11/include/ "at91sam9x5cm.dtsi" 11/include/ "at91sam9x5ek.dtsi"
12 12
13/ { 13/ {
14 model = "Atmel AT91SAM9G25-EK"; 14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; 15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16
17 chosen {
18 bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
19 };
20
21 ahb {
22 apb {
23 dbgu: serial@fffff200 {
24 status = "okay";
25 };
26
27 usart0: serial@f801c000 {
28 status = "okay";
29 };
30
31 macb0: ethernet@f802c000 {
32 phy-mode = "rmii";
33 status = "okay";
34 };
35
36 i2c0: i2c@f8010000 {
37 status = "okay";
38 };
39
40 i2c1: i2c@f8014000 {
41 status = "okay";
42 };
43
44 i2c2: i2c@f8018000 {
45 status = "okay";
46 };
47 };
48
49 usb0: ohci@00600000 {
50 status = "okay";
51 num-ports = <2>;
52 atmel,vbus-gpio = <&pioD 19 1
53 &pioD 20 1
54 >;
55 };
56
57 usb1: ehci@00700000 {
58 status = "okay";
59 };
60 };
61}; 16};
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
new file mode 100644
index 000000000000..f9d14a722794
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G35 SoC";
13 compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0xc000000c /* pioA */
21 0x000406ff 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
new file mode 100644
index 000000000000..95944bdd798d
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g35.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G35-EK";
15 compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 3add030d61f8..c340f6635d81 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -108,60 +108,151 @@
108 interrupts = <21 4 0>; 108 interrupts = <21 4 0>;
109 }; 109 };
110 110
111 pioA: gpio@fffff200 { 111 pinctrl@fffff200 {
112 compatible = "atmel,at91rm9200-gpio"; 112 #address-cells = <1>;
113 reg = <0xfffff200 0x100>; 113 #size-cells = <1>;
114 interrupts = <2 4 1>; 114 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
115 #gpio-cells = <2>; 115 ranges = <0xfffff200 0xfffff200 0xa00>;
116 gpio-controller; 116
117 interrupt-controller; 117 atmel,mux-mask = <
118 #interrupt-cells = <2>; 118 /* A B */
119 }; 119 0xffffffff 0xffc003ff /* pioA */
120 0xffffffff 0x800f8f00 /* pioB */
121 0xffffffff 0x00000e00 /* pioC */
122 0xffffffff 0xff0c1381 /* pioD */
123 0xffffffff 0x81ffff81 /* pioE */
124 >;
125
126 /* shared pinctrl settings */
127 dbgu {
128 pinctrl_dbgu: dbgu-0 {
129 atmel,pins =
130 <1 12 0x1 0x0 /* PB12 periph A */
131 1 13 0x1 0x0>; /* PB13 periph A */
132 };
133 };
120 134
121 pioB: gpio@fffff400 { 135 uart0 {
122 compatible = "atmel,at91rm9200-gpio"; 136 pinctrl_uart0: uart0-0 {
123 reg = <0xfffff400 0x100>; 137 atmel,pins =
124 interrupts = <3 4 1>; 138 <1 19 0x1 0x1 /* PB19 periph A with pullup */
125 #gpio-cells = <2>; 139 1 18 0x1 0x0>; /* PB18 periph A */
126 gpio-controller; 140 };
127 interrupt-controller; 141
128 #interrupt-cells = <2>; 142 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
129 }; 143 atmel,pins =
144 <1 17 0x2 0x0 /* PB17 periph B */
145 1 15 0x2 0x0>; /* PB15 periph B */
146 };
147 };
130 148
131 pioC: gpio@fffff600 { 149 uart1 {
132 compatible = "atmel,at91rm9200-gpio"; 150 pinctrl_uart1: uart1-0 {
133 reg = <0xfffff600 0x100>; 151 atmel,pins =
134 interrupts = <4 4 1>; 152 <1 4 0x1 0x1 /* PB4 periph A with pullup */
135 #gpio-cells = <2>; 153 1 5 0x1 0x0>; /* PB5 periph A */
136 gpio-controller; 154 };
137 interrupt-controller; 155
138 #interrupt-cells = <2>; 156 pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
139 }; 157 atmel,pins =
158 <3 16 0x1 0x0 /* PD16 periph A */
159 3 17 0x1 0x0>; /* PD17 periph A */
160 };
161 };
140 162
141 pioD: gpio@fffff800 { 163 uart2 {
142 compatible = "atmel,at91rm9200-gpio"; 164 pinctrl_uart2: uart2-0 {
143 reg = <0xfffff800 0x100>; 165 atmel,pins =
144 interrupts = <5 4 1>; 166 <1 6 0x1 0x1 /* PB6 periph A with pullup */
145 #gpio-cells = <2>; 167 1 7 0x1 0x0>; /* PB7 periph A */
146 gpio-controller; 168 };
147 interrupt-controller; 169
148 #interrupt-cells = <2>; 170 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
149 }; 171 atmel,pins =
172 <2 9 0x2 0x0 /* PC9 periph B */
173 2 11 0x2 0x0>; /* PC11 periph B */
174 };
175 };
150 176
151 pioE: gpio@fffffa00 { 177 uart3 {
152 compatible = "atmel,at91rm9200-gpio"; 178 pinctrl_uart3: uart3-0 {
153 reg = <0xfffffa00 0x100>; 179 atmel,pins =
154 interrupts = <5 4 1>; 180 <1 8 0x1 0x1 /* PB9 periph A with pullup */
155 #gpio-cells = <2>; 181 1 9 0x1 0x0>; /* PB8 periph A */
156 gpio-controller; 182 };
157 interrupt-controller; 183
158 #interrupt-cells = <2>; 184 pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
185 atmel,pins =
186 <0 23 0x2 0x0 /* PA23 periph B */
187 0 24 0x2 0x0>; /* PA24 periph B */
188 };
189 };
190
191 nand {
192 pinctrl_nand: nand-0 {
193 atmel,pins =
194 <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
195 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
196 };
197 };
198
199 pioA: gpio@fffff200 {
200 compatible = "atmel,at91rm9200-gpio";
201 reg = <0xfffff200 0x200>;
202 interrupts = <2 4 1>;
203 #gpio-cells = <2>;
204 gpio-controller;
205 interrupt-controller;
206 #interrupt-cells = <2>;
207 };
208
209 pioB: gpio@fffff400 {
210 compatible = "atmel,at91rm9200-gpio";
211 reg = <0xfffff400 0x200>;
212 interrupts = <3 4 1>;
213 #gpio-cells = <2>;
214 gpio-controller;
215 interrupt-controller;
216 #interrupt-cells = <2>;
217 };
218
219 pioC: gpio@fffff600 {
220 compatible = "atmel,at91rm9200-gpio";
221 reg = <0xfffff600 0x200>;
222 interrupts = <4 4 1>;
223 #gpio-cells = <2>;
224 gpio-controller;
225 interrupt-controller;
226 #interrupt-cells = <2>;
227 };
228
229 pioD: gpio@fffff800 {
230 compatible = "atmel,at91rm9200-gpio";
231 reg = <0xfffff800 0x200>;
232 interrupts = <5 4 1>;
233 #gpio-cells = <2>;
234 gpio-controller;
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 };
238
239 pioE: gpio@fffffa00 {
240 compatible = "atmel,at91rm9200-gpio";
241 reg = <0xfffffa00 0x200>;
242 interrupts = <5 4 1>;
243 #gpio-cells = <2>;
244 gpio-controller;
245 interrupt-controller;
246 #interrupt-cells = <2>;
247 };
159 }; 248 };
160 249
161 dbgu: serial@ffffee00 { 250 dbgu: serial@ffffee00 {
162 compatible = "atmel,at91sam9260-usart"; 251 compatible = "atmel,at91sam9260-usart";
163 reg = <0xffffee00 0x200>; 252 reg = <0xffffee00 0x200>;
164 interrupts = <1 4 7>; 253 interrupts = <1 4 7>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_dbgu>;
165 status = "disabled"; 256 status = "disabled";
166 }; 257 };
167 258
@@ -171,6 +262,8 @@
171 interrupts = <7 4 5>; 262 interrupts = <7 4 5>;
172 atmel,use-dma-rx; 263 atmel,use-dma-rx;
173 atmel,use-dma-tx; 264 atmel,use-dma-tx;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart0>;
174 status = "disabled"; 267 status = "disabled";
175 }; 268 };
176 269
@@ -180,6 +273,8 @@
180 interrupts = <8 4 5>; 273 interrupts = <8 4 5>;
181 atmel,use-dma-rx; 274 atmel,use-dma-rx;
182 atmel,use-dma-tx; 275 atmel,use-dma-tx;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_uart1>;
183 status = "disabled"; 278 status = "disabled";
184 }; 279 };
185 280
@@ -189,6 +284,8 @@
189 interrupts = <9 4 5>; 284 interrupts = <9 4 5>;
190 atmel,use-dma-rx; 285 atmel,use-dma-rx;
191 atmel,use-dma-tx; 286 atmel,use-dma-tx;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_uart2>;
192 status = "disabled"; 289 status = "disabled";
193 }; 290 };
194 291
@@ -198,6 +295,8 @@
198 interrupts = <10 4 5>; 295 interrupts = <10 4 5>;
199 atmel,use-dma-rx; 296 atmel,use-dma-rx;
200 atmel,use-dma-tx; 297 atmel,use-dma-tx;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_uart3>;
201 status = "disabled"; 300 status = "disabled";
202 }; 301 };
203 302
@@ -273,6 +372,8 @@
273 >; 372 >;
274 atmel,nand-addr-offset = <21>; 373 atmel,nand-addr-offset = <21>;
275 atmel,nand-cmd-offset = <22>; 374 atmel,nand-cmd-offset = <22>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_nand>;
276 gpios = <&pioC 8 0 377 gpios = <&pioC 8 0
277 &pioC 14 0 378 &pioC 14 0
278 0 379 0
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 15e1dd43f625..6aa28b941907 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -39,6 +39,7 @@
39 }; 39 };
40 40
41 usart1: serial@fff90000 { 41 usart1: serial@fff90000 {
42 pinctrl-0 = <&pinctrl_uart0 &pinctrl_uart1_rts_cts>;
42 status = "okay"; 43 status = "okay";
43 }; 44 };
44 45
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 82508d68aa7e..7b644c5b0bed 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -102,50 +102,150 @@
102 interrupts = <20 4 0>; 102 interrupts = <20 4 0>;
103 }; 103 };
104 104
105 pioA: gpio@fffff400 { 105 pinctrl@fffff400 {
106 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 106 #address-cells = <1>;
107 reg = <0xfffff400 0x100>; 107 #size-cells = <1>;
108 interrupts = <2 4 1>; 108 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
109 #gpio-cells = <2>; 109 ranges = <0xfffff400 0xfffff400 0x800>;
110 gpio-controller;
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 };
114 110
115 pioB: gpio@fffff600 { 111 atmel,mux-mask = <
116 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 112 /* A B C */
117 reg = <0xfffff600 0x100>; 113 0xffffffff 0xffe07983 0x00000000 /* pioA */
118 interrupts = <2 4 1>; 114 0x00040000 0x00047e0f 0x00000000 /* pioB */
119 #gpio-cells = <2>; 115 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
120 gpio-controller; 116 0x003fffff 0x003f8000 0x00000000 /* pioD */
121 interrupt-controller; 117 >;
122 #interrupt-cells = <2>;
123 };
124 118
125 pioC: gpio@fffff800 { 119 /* shared pinctrl settings */
126 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 120 dbgu {
127 reg = <0xfffff800 0x100>; 121 pinctrl_dbgu: dbgu-0 {
128 interrupts = <3 4 1>; 122 atmel,pins =
129 #gpio-cells = <2>; 123 <0 9 0x1 0x0 /* PA9 periph A */
130 gpio-controller; 124 0 10 0x1 0x1>; /* PA10 periph with pullup */
131 interrupt-controller; 125 };
132 #interrupt-cells = <2>; 126 };
133 };
134 127
135 pioD: gpio@fffffa00 { 128 uart0 {
136 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 129 pinctrl_uart0: uart0-0 {
137 reg = <0xfffffa00 0x100>; 130 atmel,pins =
138 interrupts = <3 4 1>; 131 <0 1 0x1 0x1 /* PA1 periph A with pullup */
139 #gpio-cells = <2>; 132 0 0 0x1 0x0>; /* PA0 periph A */
140 gpio-controller; 133 };
141 interrupt-controller; 134
142 #interrupt-cells = <2>; 135 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
136 atmel,pins =
137 <0 2 0x1 0x0 /* PA2 periph A */
138 0 3 0x1 0x0>; /* PA3 periph A */
139 };
140 };
141
142 uart1 {
143 pinctrl_uart1: uart1-0 {
144 atmel,pins =
145 <0 6 0x1 0x1 /* PA6 periph A with pullup */
146 0 5 0x1 0x0>; /* PA5 periph A */
147 };
148 };
149
150 uart2 {
151 pinctrl_uart2: uart2-0 {
152 atmel,pins =
153 <0 8 0x1 0x1 /* PA8 periph A with pullup */
154 0 7 0x1 0x0>; /* PA7 periph A */
155 };
156
157 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
158 atmel,pins =
159 <1 0 0x2 0x0 /* PB0 periph B */
160 1 1 0x2 0x0>; /* PB1 periph B */
161 };
162 };
163
164 uart3 {
165 pinctrl_uart3: uart3-0 {
166 atmel,pins =
167 <2 23 0x2 0x1 /* PC23 periph B with pullup */
168 2 22 0x2 0x0>; /* PC22 periph B */
169 };
170
171 pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
172 atmel,pins =
173 <2 24 0x2 0x0 /* PC24 periph B */
174 2 25 0x2 0x0>; /* PC25 periph B */
175 };
176 };
177
178 usart0 {
179 pinctrl_usart0: usart0-0 {
180 atmel,pins =
181 <2 9 0x3 0x1 /* PC9 periph C with pullup */
182 2 8 0x3 0x0>; /* PC8 periph C */
183 };
184 };
185
186 usart1 {
187 pinctrl_usart1: usart1-0 {
188 atmel,pins =
189 <2 16 0x3 0x1 /* PC17 periph C with pullup */
190 2 17 0x3 0x0>; /* PC16 periph C */
191 };
192 };
193
194 nand {
195 pinctrl_nand: nand-0 {
196 atmel,pins =
197 <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
198 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
199 };
200 };
201
202 pioA: gpio@fffff400 {
203 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
204 reg = <0xfffff400 0x200>;
205 interrupts = <2 4 1>;
206 #gpio-cells = <2>;
207 gpio-controller;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 };
211
212 pioB: gpio@fffff600 {
213 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
214 reg = <0xfffff600 0x200>;
215 interrupts = <2 4 1>;
216 #gpio-cells = <2>;
217 gpio-controller;
218 interrupt-controller;
219 #interrupt-cells = <2>;
220 };
221
222 pioC: gpio@fffff800 {
223 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
224 reg = <0xfffff800 0x200>;
225 interrupts = <3 4 1>;
226 #gpio-cells = <2>;
227 gpio-controller;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 };
231
232 pioD: gpio@fffffa00 {
233 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
234 reg = <0xfffffa00 0x200>;
235 interrupts = <3 4 1>;
236 #gpio-cells = <2>;
237 gpio-controller;
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 };
143 }; 241 };
144 242
145 dbgu: serial@fffff200 { 243 dbgu: serial@fffff200 {
146 compatible = "atmel,at91sam9260-usart"; 244 compatible = "atmel,at91sam9260-usart";
147 reg = <0xfffff200 0x200>; 245 reg = <0xfffff200 0x200>;
148 interrupts = <1 4 7>; 246 interrupts = <1 4 7>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_dbgu>;
149 status = "disabled"; 249 status = "disabled";
150 }; 250 };
151 251
@@ -155,6 +255,8 @@
155 interrupts = <5 4 5>; 255 interrupts = <5 4 5>;
156 atmel,use-dma-rx; 256 atmel,use-dma-rx;
157 atmel,use-dma-tx; 257 atmel,use-dma-tx;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_uart0>;
158 status = "disabled"; 260 status = "disabled";
159 }; 261 };
160 262
@@ -164,6 +266,8 @@
164 interrupts = <6 4 5>; 266 interrupts = <6 4 5>;
165 atmel,use-dma-rx; 267 atmel,use-dma-rx;
166 atmel,use-dma-tx; 268 atmel,use-dma-tx;
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart1>;
167 status = "disabled"; 271 status = "disabled";
168 }; 272 };
169 273
@@ -173,6 +277,8 @@
173 interrupts = <7 4 5>; 277 interrupts = <7 4 5>;
174 atmel,use-dma-rx; 278 atmel,use-dma-rx;
175 atmel,use-dma-tx; 279 atmel,use-dma-tx;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_uart2>;
176 status = "disabled"; 282 status = "disabled";
177 }; 283 };
178 284
@@ -182,6 +288,8 @@
182 interrupts = <8 4 5>; 288 interrupts = <8 4 5>;
183 atmel,use-dma-rx; 289 atmel,use-dma-rx;
184 atmel,use-dma-tx; 290 atmel,use-dma-tx;
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_uart3>;
185 status = "disabled"; 293 status = "disabled";
186 }; 294 };
187 295
@@ -215,6 +323,8 @@
215 >; 323 >;
216 atmel,nand-addr-offset = <21>; 324 atmel,nand-addr-offset = <21>;
217 atmel,nand-cmd-offset = <22>; 325 atmel,nand-cmd-offset = <22>;
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_nand>;
218 gpios = <&pioD 5 0 328 gpios = <&pioD 5 0
219 &pioD 4 0 329 &pioD 4 0
220 0 330 0
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
new file mode 100644
index 000000000000..956c65f7c39f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X25 SoC";
13 compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe03fff 0xc000001c /* pioA */
21 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
22 0x80000000 0xfffd0000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
new file mode 100644
index 000000000000..af907eaa1f25
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x25.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
new file mode 100644
index 000000000000..fb102d6126ce
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -0,0 +1,28 @@
1/*
2 * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X35 SoC";
13 compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe03fff 0xc000000c /* pioA */
21 0x000406ff 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
new file mode 100644
index 000000000000..5ccb607b5414
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -0,0 +1,16 @@
1/*
2 * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x35.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9X35-EK";
15 compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 03fc136421c5..6a40b777ea4c 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -111,50 +111,150 @@
111 interrupts = <21 4 0>; 111 interrupts = <21 4 0>;
112 }; 112 };
113 113
114 pioA: gpio@fffff400 { 114 pinctrl@fffff400 {
115 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 115 #address-cells = <1>;
116 reg = <0xfffff400 0x100>; 116 #size-cells = <1>;
117 interrupts = <2 4 1>; 117 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
118 #gpio-cells = <2>; 118 ranges = <0xfffff400 0xfffff400 0x800>;
119 gpio-controller; 119
120 interrupt-controller; 120 /* shared pinctrl settings */
121 #interrupt-cells = <2>; 121 dbgu {
122 }; 122 pinctrl_dbgu: dbgu-0 {
123 atmel,pins =
124 <0 9 0x1 0x0 /* PA9 periph A */
125 0 10 0x1 0x1>; /* PA10 periph A with pullup */
126 };
127 };
123 128
124 pioB: gpio@fffff600 { 129 uart0 {
125 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 130 pinctrl_uart0: uart0-0 {
126 reg = <0xfffff600 0x100>; 131 atmel,pins =
127 interrupts = <2 4 1>; 132 <0 0 0x1 0x1 /* PA0 periph A with pullup */
128 #gpio-cells = <2>; 133 0 1 0x1 0x0>; /* PA1 periph A */
129 gpio-controller; 134 };
130 interrupt-controller; 135
131 #interrupt-cells = <2>; 136 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
132 }; 137 atmel,pins =
138 <0 2 0x1 0x0 /* PA2 periph A */
139 0 3 0x1 0x0>; /* PA3 periph A */
140 };
141 };
133 142
134 pioC: gpio@fffff800 { 143 uart1 {
135 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 144 pinctrl_uart1: uart1-0 {
136 reg = <0xfffff800 0x100>; 145 atmel,pins =
137 interrupts = <3 4 1>; 146 <0 5 0x1 0x1 /* PA5 periph A with pullup */
138 #gpio-cells = <2>; 147 0 6 0x1 0x0>; /* PA6 periph A */
139 gpio-controller; 148 };
140 interrupt-controller; 149
141 #interrupt-cells = <2>; 150 pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
142 }; 151 atmel,pins =
152 <3 27 0x3 0x0 /* PC27 periph C */
153 3 28 0x3 0x0>; /* PC28 periph C */
154 };
155 };
143 156
144 pioD: gpio@fffffa00 { 157 uart2 {
145 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 158 pinctrl_uart2: uart2-0 {
146 reg = <0xfffffa00 0x100>; 159 atmel,pins =
147 interrupts = <3 4 1>; 160 <0 7 0x1 0x1 /* PA7 periph A with pullup */
148 #gpio-cells = <2>; 161 0 8 0x1 0x0>; /* PA8 periph A */
149 gpio-controller; 162 };
150 interrupt-controller; 163
151 #interrupt-cells = <2>; 164 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
165 atmel,pins =
166 <0 0 0x2 0x0 /* PB0 periph B */
167 0 1 0x2 0x0>; /* PB1 periph B */
168 };
169 };
170
171 uart3 {
172 pinctrl_uart3: uart3-0 {
173 atmel,pins =
174 <3 23 0x2 0x1 /* PC22 periph B with pullup */
175 3 23 0x2 0x0>; /* PC23 periph B */
176 };
177
178 pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
179 atmel,pins =
180 <3 24 0x2 0x0 /* PC24 periph B */
181 3 25 0x2 0x0>; /* PC25 periph B */
182 };
183 };
184
185 usart0 {
186 pinctrl_usart0: usart0-0 {
187 atmel,pins =
188 <3 8 0x3 0x0 /* PC8 periph C */
189 3 9 0x3 0x1>; /* PC9 periph C with pullup */
190 };
191 };
192
193 usart1 {
194 pinctrl_usart1: usart1-0 {
195 atmel,pins =
196 <3 16 0x3 0x0 /* PC16 periph C */
197 3 17 0x3 0x1>; /* PC17 periph C with pullup */
198 };
199 };
200
201 nand {
202 pinctrl_nand: nand-0 {
203 atmel,pins =
204 <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
205 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
206 };
207 };
208
209 pioA: gpio@fffff400 {
210 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
211 reg = <0xfffff400 0x200>;
212 interrupts = <2 4 1>;
213 #gpio-cells = <2>;
214 gpio-controller;
215 interrupt-controller;
216 #interrupt-cells = <2>;
217 };
218
219 pioB: gpio@fffff600 {
220 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
221 reg = <0xfffff600 0x200>;
222 interrupts = <2 4 1>;
223 #gpio-cells = <2>;
224 gpio-controller;
225 #gpio-lines = <19>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 };
229
230 pioC: gpio@fffff800 {
231 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
232 reg = <0xfffff800 0x200>;
233 interrupts = <3 4 1>;
234 #gpio-cells = <2>;
235 gpio-controller;
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 };
239
240 pioD: gpio@fffffa00 {
241 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
242 reg = <0xfffffa00 0x200>;
243 interrupts = <3 4 1>;
244 #gpio-cells = <2>;
245 gpio-controller;
246 #gpio-lines = <22>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 };
152 }; 250 };
153 251
154 dbgu: serial@fffff200 { 252 dbgu: serial@fffff200 {
155 compatible = "atmel,at91sam9260-usart"; 253 compatible = "atmel,at91sam9260-usart";
156 reg = <0xfffff200 0x200>; 254 reg = <0xfffff200 0x200>;
157 interrupts = <1 4 7>; 255 interrupts = <1 4 7>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_dbgu>;
158 status = "disabled"; 258 status = "disabled";
159 }; 259 };
160 260
@@ -164,6 +264,8 @@
164 interrupts = <5 4 5>; 264 interrupts = <5 4 5>;
165 atmel,use-dma-rx; 265 atmel,use-dma-rx;
166 atmel,use-dma-tx; 266 atmel,use-dma-tx;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_uart0>;
167 status = "disabled"; 269 status = "disabled";
168 }; 270 };
169 271
@@ -173,6 +275,8 @@
173 interrupts = <6 4 5>; 275 interrupts = <6 4 5>;
174 atmel,use-dma-rx; 276 atmel,use-dma-rx;
175 atmel,use-dma-tx; 277 atmel,use-dma-tx;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_uart1>;
176 status = "disabled"; 280 status = "disabled";
177 }; 281 };
178 282
@@ -182,6 +286,8 @@
182 interrupts = <7 4 5>; 286 interrupts = <7 4 5>;
183 atmel,use-dma-rx; 287 atmel,use-dma-rx;
184 atmel,use-dma-tx; 288 atmel,use-dma-tx;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_uart2>;
185 status = "disabled"; 291 status = "disabled";
186 }; 292 };
187 293
@@ -273,6 +379,8 @@
273 >; 379 >;
274 atmel,nand-addr-offset = <21>; 380 atmel,nand-addr-offset = <21>;
275 atmel,nand-cmd-offset = <22>; 381 atmel,nand-cmd-offset = <22>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_nand>;
276 gpios = <&pioD 5 0 384 gpios = <&pioD 5 0
277 &pioD 4 0 385 &pioD 4 0
278 0 386 0
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
new file mode 100644
index 000000000000..cc9730c60180
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -0,0 +1,59 @@
1/*
2 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/include/ "at91sam9x5cm.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X5-EK";
13 compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
17 };
18
19 ahb {
20 apb {
21 dbgu: serial@fffff200 {
22 status = "okay";
23 };
24
25 usart0: serial@f801c000 {
26 status = "okay";
27 };
28
29 macb0: ethernet@f802c000 {
30 phy-mode = "rmii";
31 status = "okay";
32 };
33
34 i2c0: i2c@f8010000 {
35 status = "okay";
36 };
37
38 i2c1: i2c@f8014000 {
39 status = "okay";
40 };
41
42 i2c2: i2c@f8018000 {
43 status = "okay";
44 };
45 };
46
47 usb0: ohci@00600000 {
48 status = "okay";
49 num-ports = <2>;
50 atmel,vbus-gpio = <&pioD 19 1
51 &pioD 20 1
52 >;
53 };
54
55 usb1: ehci@00700000 {
56 status = "okay";
57 };
58 };
59};
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 67bc571ed0c3..b175577d7abb 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -111,6 +111,7 @@ CONFIG_I2C=y
111CONFIG_I2C_GPIO=y 111CONFIG_I2C_GPIO=y
112CONFIG_SPI=y 112CONFIG_SPI=y
113CONFIG_SPI_ATMEL=y 113CONFIG_SPI_ATMEL=y
114CONFIG_PINCTRL_AT91=y
114# CONFIG_HWMON is not set 115# CONFIG_HWMON is not set
115CONFIG_WATCHDOG=y 116CONFIG_WATCHDOG=y
116CONFIG_AT91SAM9X_WATCHDOG=y 117CONFIG_AT91SAM9X_WATCHDOG=y
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index b4f0565aff63..a45473425f5e 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -361,10 +361,10 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
361 0 /* Advanced Interrupt Controller (IRQ6) */ 361 0 /* Advanced Interrupt Controller (IRQ6) */
362}; 362};
363 363
364struct at91_init_soc __initdata at91rm9200_soc = { 364AT91_SOC_START(rm9200)
365 .map_io = at91rm9200_map_io, 365 .map_io = at91rm9200_map_io,
366 .default_irq_priority = at91rm9200_default_irq_priority, 366 .default_irq_priority = at91rm9200_default_irq_priority,
367 .ioremap_registers = at91rm9200_ioremap_registers, 367 .ioremap_registers = at91rm9200_ioremap_registers,
368 .register_clocks = at91rm9200_register_clocks, 368 .register_clocks = at91rm9200_register_clocks,
369 .init = at91rm9200_initialize, 369 .init = at91rm9200_initialize,
370}; 370AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index ad29f93f20ca..46d30831c9a8 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -235,6 +235,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
235 CLKDEV_CON_ID("pioA", &pioA_clk), 235 CLKDEV_CON_ID("pioA", &pioA_clk),
236 CLKDEV_CON_ID("pioB", &pioB_clk), 236 CLKDEV_CON_ID("pioB", &pioB_clk),
237 CLKDEV_CON_ID("pioC", &pioC_clk), 237 CLKDEV_CON_ID("pioC", &pioC_clk),
238 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
239 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
240 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
238}; 241};
239 242
240static struct clk_lookup usart_clocks_lookups[] = { 243static struct clk_lookup usart_clocks_lookups[] = {
@@ -390,10 +393,10 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
390 0, /* Advanced Interrupt Controller */ 393 0, /* Advanced Interrupt Controller */
391}; 394};
392 395
393struct at91_init_soc __initdata at91sam9260_soc = { 396AT91_SOC_START(sam9260)
394 .map_io = at91sam9260_map_io, 397 .map_io = at91sam9260_map_io,
395 .default_irq_priority = at91sam9260_default_irq_priority, 398 .default_irq_priority = at91sam9260_default_irq_priority,
396 .ioremap_registers = at91sam9260_ioremap_registers, 399 .ioremap_registers = at91sam9260_ioremap_registers,
397 .register_clocks = at91sam9260_register_clocks, 400 .register_clocks = at91sam9260_register_clocks,
398 .init = at91sam9260_initialize, 401 .init = at91sam9260_initialize,
399}; 402AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 8d999eb1a137..93a24e921aff 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -334,10 +334,10 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
334 0, /* Advanced Interrupt Controller */ 334 0, /* Advanced Interrupt Controller */
335}; 335};
336 336
337struct at91_init_soc __initdata at91sam9261_soc = { 337AT91_SOC_START(sam9261)
338 .map_io = at91sam9261_map_io, 338 .map_io = at91sam9261_map_io,
339 .default_irq_priority = at91sam9261_default_irq_priority, 339 .default_irq_priority = at91sam9261_default_irq_priority,
340 .ioremap_registers = at91sam9261_ioremap_registers, 340 .ioremap_registers = at91sam9261_ioremap_registers,
341 .register_clocks = at91sam9261_register_clocks, 341 .register_clocks = at91sam9261_register_clocks,
342 .init = at91sam9261_initialize, 342 .init = at91sam9261_initialize,
343}; 343AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 6a01d0360dfb..f8ea00136234 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -212,6 +212,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
212 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk), 212 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
213 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk), 213 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
214 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk), 214 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
215 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
216 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
217 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
218 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
219 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
215}; 220};
216 221
217static struct clk_lookup usart_clocks_lookups[] = { 222static struct clk_lookup usart_clocks_lookups[] = {
@@ -365,10 +370,10 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
365 0, /* Advanced Interrupt Controller (IRQ1) */ 370 0, /* Advanced Interrupt Controller (IRQ1) */
366}; 371};
367 372
368struct at91_init_soc __initdata at91sam9263_soc = { 373AT91_SOC_START(sam9263)
369 .map_io = at91sam9263_map_io, 374 .map_io = at91sam9263_map_io,
370 .default_irq_priority = at91sam9263_default_irq_priority, 375 .default_irq_priority = at91sam9263_default_irq_priority,
371 .ioremap_registers = at91sam9263_ioremap_registers, 376 .ioremap_registers = at91sam9263_ioremap_registers,
372 .register_clocks = at91sam9263_register_clocks, 377 .register_clocks = at91sam9263_register_clocks,
373 .init = at91sam9263_initialize, 378 .init = at91sam9263_initialize,
374}; 379AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 84af1b506d92..e6dd371d9f56 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -260,6 +260,12 @@ static struct clk_lookup periph_clocks_lookups[] = {
260 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk), 260 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
261 /* fake hclk clock */ 261 /* fake hclk clock */
262 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), 262 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
263 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
264 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
265 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
266 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
267 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
268
263 CLKDEV_CON_ID("pioA", &pioA_clk), 269 CLKDEV_CON_ID("pioA", &pioA_clk),
264 CLKDEV_CON_ID("pioB", &pioB_clk), 270 CLKDEV_CON_ID("pioB", &pioB_clk),
265 CLKDEV_CON_ID("pioC", &pioC_clk), 271 CLKDEV_CON_ID("pioC", &pioC_clk),
@@ -409,10 +415,10 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
409 0, /* Advanced Interrupt Controller (IRQ0) */ 415 0, /* Advanced Interrupt Controller (IRQ0) */
410}; 416};
411 417
412struct at91_init_soc __initdata at91sam9g45_soc = { 418AT91_SOC_START(sam9g45)
413 .map_io = at91sam9g45_map_io, 419 .map_io = at91sam9g45_map_io,
414 .default_irq_priority = at91sam9g45_default_irq_priority, 420 .default_irq_priority = at91sam9g45_default_irq_priority,
415 .ioremap_registers = at91sam9g45_ioremap_registers, 421 .ioremap_registers = at91sam9g45_ioremap_registers,
416 .register_clocks = at91sam9g45_register_clocks, 422 .register_clocks = at91sam9g45_register_clocks,
417 .init = at91sam9g45_initialize, 423 .init = at91sam9g45_initialize,
418}; 424AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 732d3d3f4ec5..bf8a083a02ab 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -171,10 +171,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
171 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk), 171 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
172 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), 172 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
173 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), 173 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
174 CLKDEV_CON_ID("pioA", &pioAB_clk), 174 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
175 CLKDEV_CON_ID("pioB", &pioAB_clk), 175 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
176 CLKDEV_CON_ID("pioC", &pioCD_clk), 176 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
177 CLKDEV_CON_ID("pioD", &pioCD_clk), 177 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
178 /* additional fake clock for macb_hclk */ 178 /* additional fake clock for macb_hclk */
179 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk), 179 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
180 CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk), 180 CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
@@ -223,13 +223,10 @@ static void __init at91sam9n12_map_io(void)
223void __init at91sam9n12_initialize(void) 223void __init at91sam9n12_initialize(void)
224{ 224{
225 at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); 225 at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
226
227 /* Register GPIO subsystem (using DT) */
228 at91_gpio_init(NULL, 0);
229} 226}
230 227
231struct at91_init_soc __initdata at91sam9n12_soc = { 228AT91_SOC_START(sam9n12)
232 .map_io = at91sam9n12_map_io, 229 .map_io = at91sam9n12_map_io,
233 .register_clocks = at91sam9n12_register_clocks, 230 .register_clocks = at91sam9n12_register_clocks,
234 .init = at91sam9n12_initialize, 231 .init = at91sam9n12_initialize,
235}; 232AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 72e908412222..cbe72e44c13f 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -338,10 +338,10 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
338 0, /* Advanced Interrupt Controller */ 338 0, /* Advanced Interrupt Controller */
339}; 339};
340 340
341struct at91_init_soc __initdata at91sam9rl_soc = { 341AT91_SOC_START(sam9rl)
342 .map_io = at91sam9rl_map_io, 342 .map_io = at91sam9rl_map_io,
343 .default_irq_priority = at91sam9rl_default_irq_priority, 343 .default_irq_priority = at91sam9rl_default_irq_priority,
344 .ioremap_registers = at91sam9rl_ioremap_registers, 344 .ioremap_registers = at91sam9rl_ioremap_registers,
345 .register_clocks = at91sam9rl_register_clocks, 345 .register_clocks = at91sam9rl_register_clocks,
346 .init = at91sam9rl_initialize, 346 .init = at91sam9rl_initialize,
347}; 347AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e5035380dcbc..56d13a4950a7 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -234,10 +234,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
234 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), 234 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
235 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), 235 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
236 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk), 236 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
237 CLKDEV_CON_ID("pioA", &pioAB_clk), 237 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
238 CLKDEV_CON_ID("pioB", &pioAB_clk), 238 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
239 CLKDEV_CON_ID("pioC", &pioCD_clk), 239 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
240 CLKDEV_CON_ID("pioD", &pioCD_clk), 240 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
241 /* additional fake clock for macb_hclk */ 241 /* additional fake clock for macb_hclk */
242 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk), 242 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
243 CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk), 243 CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
@@ -313,18 +313,11 @@ static void __init at91sam9x5_map_io(void)
313 at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE); 313 at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
314} 314}
315 315
316void __init at91sam9x5_initialize(void)
317{
318 /* Register GPIO subsystem (using DT) */
319 at91_gpio_init(NULL, 0);
320}
321
322/* -------------------------------------------------------------------- 316/* --------------------------------------------------------------------
323 * Interrupt initialization 317 * Interrupt initialization
324 * -------------------------------------------------------------------- */ 318 * -------------------------------------------------------------------- */
325 319
326struct at91_init_soc __initdata at91sam9x5_soc = { 320AT91_SOC_START(sam9x5)
327 .map_io = at91sam9x5_map_io, 321 .map_io = at91sam9x5_map_io,
328 .register_clocks = at91sam9x5_register_clocks, 322 .register_clocks = at91sam9x5_register_clocks,
329 .init = at91sam9x5_initialize, 323AT91_SOC_END
330};
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index e8f45c4e0ea8..3b6a94820fa0 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -30,8 +30,6 @@
30static const struct of_device_id irq_of_match[] __initconst = { 30static const struct of_device_id irq_of_match[] __initconst = {
31 31
32 { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init }, 32 { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
33 { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
34 { .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
35 { /*sentinel*/ } 33 { /*sentinel*/ }
36}; 34};
37 35
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index be42cf0e74bd..c5d7e1e9d757 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -23,8 +23,6 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/irqdomain.h> 24#include <linux/irqdomain.h>
25#include <linux/of_address.h> 25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_gpio.h>
28 26
29#include <asm/mach/irq.h> 27#include <asm/mach/irq.h>
30 28
@@ -33,6 +31,8 @@
33 31
34#include "generic.h" 32#include "generic.h"
35 33
34#define MAX_NB_GPIO_PER_BANK 32
35
36struct at91_gpio_chip { 36struct at91_gpio_chip {
37 struct gpio_chip chip; 37 struct gpio_chip chip;
38 struct at91_gpio_chip *next; /* Bank sharing same clock */ 38 struct at91_gpio_chip *next; /* Bank sharing same clock */
@@ -46,6 +46,7 @@ struct at91_gpio_chip {
46 46
47#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 47#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
48 48
49static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
49static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip); 50static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
50static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val); 51static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
51static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset); 52static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
@@ -55,26 +56,27 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
55 unsigned offset); 56 unsigned offset);
56static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset); 57static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
57 58
58#define AT91_GPIO_CHIP(name, nr_gpio) \ 59#define AT91_GPIO_CHIP(name) \
59 { \ 60 { \
60 .chip = { \ 61 .chip = { \
61 .label = name, \ 62 .label = name, \
63 .request = at91_gpiolib_request, \
62 .direction_input = at91_gpiolib_direction_input, \ 64 .direction_input = at91_gpiolib_direction_input, \
63 .direction_output = at91_gpiolib_direction_output, \ 65 .direction_output = at91_gpiolib_direction_output, \
64 .get = at91_gpiolib_get, \ 66 .get = at91_gpiolib_get, \
65 .set = at91_gpiolib_set, \ 67 .set = at91_gpiolib_set, \
66 .dbg_show = at91_gpiolib_dbg_show, \ 68 .dbg_show = at91_gpiolib_dbg_show, \
67 .to_irq = at91_gpiolib_to_irq, \ 69 .to_irq = at91_gpiolib_to_irq, \
68 .ngpio = nr_gpio, \ 70 .ngpio = MAX_NB_GPIO_PER_BANK, \
69 }, \ 71 }, \
70 } 72 }
71 73
72static struct at91_gpio_chip gpio_chip[] = { 74static struct at91_gpio_chip gpio_chip[] = {
73 AT91_GPIO_CHIP("pioA", 32), 75 AT91_GPIO_CHIP("pioA"),
74 AT91_GPIO_CHIP("pioB", 32), 76 AT91_GPIO_CHIP("pioB"),
75 AT91_GPIO_CHIP("pioC", 32), 77 AT91_GPIO_CHIP("pioC"),
76 AT91_GPIO_CHIP("pioD", 32), 78 AT91_GPIO_CHIP("pioD"),
77 AT91_GPIO_CHIP("pioE", 32), 79 AT91_GPIO_CHIP("pioE"),
78}; 80};
79 81
80static int gpio_banks; 82static int gpio_banks;
@@ -89,7 +91,7 @@ static unsigned long at91_gpio_caps;
89 91
90static inline void __iomem *pin_to_controller(unsigned pin) 92static inline void __iomem *pin_to_controller(unsigned pin)
91{ 93{
92 pin /= 32; 94 pin /= MAX_NB_GPIO_PER_BANK;
93 if (likely(pin < gpio_banks)) 95 if (likely(pin < gpio_banks))
94 return gpio_chip[pin].regbase; 96 return gpio_chip[pin].regbase;
95 97
@@ -98,7 +100,7 @@ static inline void __iomem *pin_to_controller(unsigned pin)
98 100
99static inline unsigned pin_to_mask(unsigned pin) 101static inline unsigned pin_to_mask(unsigned pin)
100{ 102{
101 return 1 << (pin % 32); 103 return 1 << (pin % MAX_NB_GPIO_PER_BANK);
102} 104}
103 105
104 106
@@ -713,80 +715,6 @@ postcore_initcall(at91_gpio_debugfs_init);
713 */ 715 */
714static struct lock_class_key gpio_lock_class; 716static struct lock_class_key gpio_lock_class;
715 717
716#if defined(CONFIG_OF)
717static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
718 irq_hw_number_t hw)
719{
720 struct at91_gpio_chip *at91_gpio = h->host_data;
721
722 irq_set_lockdep_class(virq, &gpio_lock_class);
723
724 /*
725 * Can use the "simple" and not "edge" handler since it's
726 * shorter, and the AIC handles interrupts sanely.
727 */
728 irq_set_chip_and_handler(virq, &gpio_irqchip,
729 handle_simple_irq);
730 set_irq_flags(virq, IRQF_VALID);
731 irq_set_chip_data(virq, at91_gpio);
732
733 return 0;
734}
735
736static struct irq_domain_ops at91_gpio_ops = {
737 .map = at91_gpio_irq_map,
738 .xlate = irq_domain_xlate_twocell,
739};
740
741int __init at91_gpio_of_irq_setup(struct device_node *node,
742 struct device_node *parent)
743{
744 struct at91_gpio_chip *prev = NULL;
745 int alias_idx = of_alias_get_id(node, "gpio");
746 struct at91_gpio_chip *at91_gpio = &gpio_chip[alias_idx];
747
748 /* Setup proper .irq_set_type function */
749 if (has_pio3())
750 gpio_irqchip.irq_set_type = alt_gpio_irq_type;
751 else
752 gpio_irqchip.irq_set_type = gpio_irq_type;
753
754 /* Disable irqs of this PIO controller */
755 __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
756
757 /* Setup irq domain */
758 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
759 &at91_gpio_ops, at91_gpio);
760 if (!at91_gpio->domain)
761 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
762 at91_gpio->pioc_idx);
763
764 /* Setup chained handler */
765 if (at91_gpio->pioc_idx)
766 prev = &gpio_chip[at91_gpio->pioc_idx - 1];
767
768 /* The toplevel handler handles one bank of GPIOs, except
769 * on some SoC it can handles up to three...
770 * We only set up the handler for the first of the list.
771 */
772 if (prev && prev->next == at91_gpio)
773 return 0;
774
775 at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
776 at91_gpio->pioc_hwirq);
777 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
778 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
779
780 return 0;
781}
782#else
783int __init at91_gpio_of_irq_setup(struct device_node *node,
784 struct device_node *parent)
785{
786 return -EINVAL;
787}
788#endif
789
790/* 718/*
791 * irqdomain initialization: pile up irqdomains on top of AIC range 719 * irqdomain initialization: pile up irqdomains on top of AIC range
792 */ 720 */
@@ -862,6 +790,16 @@ void __init at91_gpio_irq_setup(void)
862} 790}
863 791
864/* gpiolib support */ 792/* gpiolib support */
793static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
794{
795 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
796 void __iomem *pio = at91_gpio->regbase;
797 unsigned mask = 1 << offset;
798
799 __raw_writel(mask, pio + PIO_PER);
800 return 0;
801}
802
865static int at91_gpiolib_direction_input(struct gpio_chip *chip, 803static int at91_gpiolib_direction_input(struct gpio_chip *chip,
866 unsigned offset) 804 unsigned offset)
867{ 805{
@@ -975,81 +913,11 @@ err:
975 return -EINVAL; 913 return -EINVAL;
976} 914}
977 915
978#ifdef CONFIG_OF_GPIO
979static void __init of_at91_gpio_init_one(struct device_node *np)
980{
981 int alias_idx;
982 struct at91_gpio_chip *at91_gpio;
983
984 if (!np)
985 return;
986
987 alias_idx = of_alias_get_id(np, "gpio");
988 if (alias_idx >= MAX_GPIO_BANKS) {
989 pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
990 alias_idx, MAX_GPIO_BANKS);
991 return;
992 }
993
994 at91_gpio = &gpio_chip[alias_idx];
995 at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
996
997 at91_gpio->regbase = of_iomap(np, 0);
998 if (!at91_gpio->regbase) {
999 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
1000 alias_idx);
1001 return;
1002 }
1003
1004 /* Get the interrupts property */
1005 if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
1006 pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
1007 alias_idx);
1008 goto ioremap_err;
1009 }
1010
1011 /* Get capabilities from compatibility property */
1012 if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
1013 at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
1014
1015 /* Setup clock */
1016 if (at91_gpio_setup_clk(alias_idx))
1017 goto ioremap_err;
1018
1019 at91_gpio->chip.of_node = np;
1020 gpio_banks = max(gpio_banks, alias_idx + 1);
1021 at91_gpio->pioc_idx = alias_idx;
1022 return;
1023
1024ioremap_err:
1025 iounmap(at91_gpio->regbase);
1026}
1027
1028static int __init of_at91_gpio_init(void)
1029{
1030 struct device_node *np = NULL;
1031
1032 /*
1033 * This isn't ideal, but it gets things hooked up until this
1034 * driver is converted into a platform_device
1035 */
1036 for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
1037 of_at91_gpio_init_one(np);
1038
1039 return gpio_banks > 0 ? 0 : -EINVAL;
1040}
1041#else
1042static int __init of_at91_gpio_init(void)
1043{
1044 return -EINVAL;
1045}
1046#endif
1047
1048static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq) 916static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
1049{ 917{
1050 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx]; 918 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
1051 919
1052 at91_gpio->chip.base = idx * at91_gpio->chip.ngpio; 920 at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
1053 at91_gpio->pioc_hwirq = pioc_hwirq; 921 at91_gpio->pioc_hwirq = pioc_hwirq;
1054 at91_gpio->pioc_idx = idx; 922 at91_gpio->pioc_idx = idx;
1055 923
@@ -1079,11 +947,11 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
1079 947
1080 BUG_ON(nr_banks > MAX_GPIO_BANKS); 948 BUG_ON(nr_banks > MAX_GPIO_BANKS);
1081 949
1082 if (of_at91_gpio_init() < 0) { 950 if (of_have_populated_dt())
1083 /* No GPIO controller found in device tree */ 951 return;
1084 for (i = 0; i < nr_banks; i++) 952
1085 at91_gpio_init_one(i, data[i].regbase, data[i].id); 953 for (i = 0; i < nr_banks; i++)
1086 } 954 at91_gpio_init_one(i, data[i].regbase, data[i].id);
1087 955
1088 for (i = 0; i < gpio_banks; i++) { 956 for (i = 0; i < gpio_banks; i++) {
1089 at91_gpio = &gpio_chip[i]; 957 at91_gpio = &gpio_chip[i];
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index da9881b161e1..523daa92be10 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -10,6 +10,7 @@
10#include <linux/mm.h> 10#include <linux/mm.h>
11#include <linux/pm.h> 11#include <linux/pm.h>
12#include <linux/of_address.h> 12#include <linux/of_address.h>
13#include <linux/pinctrl/machine.h>
13 14
14#include <asm/system_misc.h> 15#include <asm/system_misc.h>
15#include <asm/mach/map.h> 16#include <asm/mach/map.h>
@@ -448,7 +449,8 @@ void __init at91_dt_initialize(void)
448 /* Register the processor-specific clocks */ 449 /* Register the processor-specific clocks */
449 at91_boot_soc.register_clocks(); 450 at91_boot_soc.register_clocks();
450 451
451 at91_boot_soc.init(); 452 if (at91_boot_soc.init)
453 at91_boot_soc.init();
452} 454}
453#endif 455#endif
454 456
@@ -463,4 +465,6 @@ void __init at91_initialize(unsigned long main_clock)
463 at91_boot_soc.register_clocks(); 465 at91_boot_soc.register_clocks();
464 466
465 at91_boot_soc.init(); 467 at91_boot_soc.init();
468
469 pinctrl_provide_dummies();
466} 470}
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index a9cfeb153719..9c6d3d4f9a23 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -5,6 +5,7 @@
5 */ 5 */
6 6
7struct at91_init_soc { 7struct at91_init_soc {
8 int builtin;
8 unsigned int *default_irq_priority; 9 unsigned int *default_irq_priority;
9 void (*map_io)(void); 10 void (*map_io)(void);
10 void (*ioremap_registers)(void); 11 void (*ioremap_registers)(void);
@@ -22,9 +23,18 @@ extern struct at91_init_soc at91sam9rl_soc;
22extern struct at91_init_soc at91sam9x5_soc; 23extern struct at91_init_soc at91sam9x5_soc;
23extern struct at91_init_soc at91sam9n12_soc; 24extern struct at91_init_soc at91sam9n12_soc;
24 25
26#define AT91_SOC_START(_name) \
27struct at91_init_soc __initdata at91##_name##_soc \
28 __used \
29 = { \
30 .builtin = 1, \
31
32#define AT91_SOC_END \
33};
34
25static inline int at91_soc_is_enabled(void) 35static inline int at91_soc_is_enabled(void)
26{ 36{
27 return at91_boot_soc.init != NULL; 37 return at91_boot_soc.builtin;
28} 38}
29 39
30#if !defined(CONFIG_SOC_AT91RM9200) 40#if !defined(CONFIG_SOC_AT91RM9200)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 914455783302..92623ac2015a 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -41,6 +41,7 @@
41#include <linux/gpio.h> 41#include <linux/gpio.h>
42#include <linux/io.h> 42#include <linux/io.h>
43#include <linux/platform_data/atmel.h> 43#include <linux/platform_data/atmel.h>
44#include <linux/pinctrl/consumer.h>
44 45
45#include <mach/cpu.h> 46#include <mach/cpu.h>
46 47
@@ -1370,6 +1371,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
1370 struct resource *mem; 1371 struct resource *mem;
1371 struct mtd_part_parser_data ppdata = {}; 1372 struct mtd_part_parser_data ppdata = {};
1372 int res; 1373 int res;
1374 struct pinctrl *pinctrl;
1373 1375
1374 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1376 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1375 if (!mem) { 1377 if (!mem) {
@@ -1414,6 +1416,13 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
1414 nand_chip->IO_ADDR_W = host->io_base; 1416 nand_chip->IO_ADDR_W = host->io_base;
1415 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl; 1417 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1416 1418
1419 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1420 if (IS_ERR(pinctrl)) {
1421 dev_err(host->dev, "Failed to request pinctrl\n");
1422 res = PTR_ERR(pinctrl);
1423 goto err_ecc_ioremap;
1424 }
1425
1417 if (gpio_is_valid(host->board.rdy_pin)) { 1426 if (gpio_is_valid(host->board.rdy_pin)) {
1418 res = gpio_request(host->board.rdy_pin, "nand_rdy"); 1427 res = gpio_request(host->board.rdy_pin, "nand_rdy");
1419 if (res < 0) { 1428 if (res < 0) {
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 7bf914df6e91..4787f0e4597d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -26,6 +26,15 @@ config DEBUG_PINCTRL
26 help 26 help
27 Say Y here to add some extra checks and diagnostics to PINCTRL calls. 27 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
28 28
29config PINCTRL_AT91
30 bool "AT91 pinctrl driver"
31 depends on OF
32 depends on ARCH_AT91
33 select PINMUX
34 select PINCONF
35 help
36 Say Y here to enable the at91 pinctrl driver
37
29config PINCTRL_BCM2835 38config PINCTRL_BCM2835
30 bool 39 bool
31 select PINMUX 40 select PINMUX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f395ba5cec25..78a191c85adc 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,6 +9,7 @@ ifeq ($(CONFIG_OF),y)
9obj-$(CONFIG_PINCTRL) += devicetree.o 9obj-$(CONFIG_PINCTRL) += devicetree.o
10endif 10endif
11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o 11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
12obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 13obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
13obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o 14obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
14obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o 15obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
new file mode 100644
index 000000000000..01bf92459fdc
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -0,0 +1,1490 @@
1/*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/slab.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/irqdomain.h>
24#include <linux/pinctrl/machine.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>
28/* Since we request GPIOs from ourself */
29#include <linux/pinctrl/consumer.h>
30
31#include <asm/mach/irq.h>
32
33#include <mach/hardware.h>
34#include <mach/at91_pio.h>
35
36#include "core.h"
37
38#define MAX_NB_GPIO_PER_BANK 32
39
40struct at91_pinctrl_mux_ops;
41
42struct at91_gpio_chip {
43 struct gpio_chip chip;
44 struct pinctrl_gpio_range range;
45 struct at91_gpio_chip *next; /* Bank sharing same clock */
46 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
47 int pioc_virq; /* PIO bank Linux virtual interrupt */
48 int pioc_idx; /* PIO bank index */
49 void __iomem *regbase; /* PIO bank virtual address */
50 struct clk *clock; /* associated clock */
51 struct irq_domain *domain; /* associated irq domain */
52 struct at91_pinctrl_mux_ops *ops; /* ops */
53};
54
55#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
56
57static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
58
59static int gpio_banks;
60
61#define PULL_UP (0 << 1)
62#define MULTI_DRIVE (1 << 1)
63
64/**
65 * struct at91_pmx_func - describes AT91 pinmux functions
66 * @name: the name of this specific function
67 * @groups: corresponding pin groups
68 * @ngroups: the number of groups
69 */
70struct at91_pmx_func {
71 const char *name;
72 const char **groups;
73 unsigned ngroups;
74};
75
76enum at91_mux {
77 AT91_MUX_GPIO = 0,
78 AT91_MUX_PERIPH_A = 1,
79 AT91_MUX_PERIPH_B = 2,
80 AT91_MUX_PERIPH_C = 3,
81 AT91_MUX_PERIPH_D = 4,
82};
83
84/**
85 * struct at91_pmx_pin - describes an At91 pin mux
86 * @bank: the bank of the pin
87 * @pin: the pin number in the @bank
88 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
89 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
90 */
91struct at91_pmx_pin {
92 uint32_t bank;
93 uint32_t pin;
94 enum at91_mux mux;
95 unsigned long conf;
96};
97
98/**
99 * struct at91_pin_group - describes an At91 pin group
100 * @name: the name of this specific pin group
101 * @pins_conf: the mux mode for each pin in this group. The size of this
102 * array is the same as pins.
103 * @pins: an array of discrete physical pins used in this group, taken
104 * from the driver-local pin enumeration space
105 * @npins: the number of pins in this group array, i.e. the number of
106 * elements in .pins so we can iterate over that array
107 */
108struct at91_pin_group {
109 const char *name;
110 struct at91_pmx_pin *pins_conf;
111 unsigned int *pins;
112 unsigned npins;
113};
114
115/**
116 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
117 * on new IP with support for periph C and D the way to mux in
118 * periph A and B has changed
119 * So provide the right call back
120 * if not present means the IP does not support it
121 * @get_periph: return the periph mode configured
122 * @mux_A_periph: mux as periph A
123 * @mux_B_periph: mux as periph B
124 * @mux_C_periph: mux as periph C
125 * @mux_D_periph: mux as periph D
126 * @irq_type: return irq type
127 */
128struct at91_pinctrl_mux_ops {
129 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
130 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
131 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
132 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
133 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
134 /* irq */
135 int (*irq_type)(struct irq_data *d, unsigned type);
136};
137
138static int gpio_irq_type(struct irq_data *d, unsigned type);
139static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
140
141struct at91_pinctrl {
142 struct device *dev;
143 struct pinctrl_dev *pctl;
144
145 int nbanks;
146
147 uint32_t *mux_mask;
148 int nmux;
149
150 struct at91_pmx_func *functions;
151 int nfunctions;
152
153 struct at91_pin_group *groups;
154 int ngroups;
155
156 struct at91_pinctrl_mux_ops *ops;
157};
158
159static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
160 const struct at91_pinctrl *info,
161 const char *name)
162{
163 const struct at91_pin_group *grp = NULL;
164 int i;
165
166 for (i = 0; i < info->ngroups; i++) {
167 if (strcmp(info->groups[i].name, name))
168 continue;
169
170 grp = &info->groups[i];
171 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
172 break;
173 }
174
175 return grp;
176}
177
178static int at91_get_groups_count(struct pinctrl_dev *pctldev)
179{
180 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
181
182 return info->ngroups;
183}
184
185static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
186 unsigned selector)
187{
188 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
189
190 return info->groups[selector].name;
191}
192
193static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
194 const unsigned **pins,
195 unsigned *npins)
196{
197 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
198
199 if (selector >= info->ngroups)
200 return -EINVAL;
201
202 *pins = info->groups[selector].pins;
203 *npins = info->groups[selector].npins;
204
205 return 0;
206}
207
208static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
209 unsigned offset)
210{
211 seq_printf(s, "%s", dev_name(pctldev->dev));
212}
213
214static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
215 struct device_node *np,
216 struct pinctrl_map **map, unsigned *num_maps)
217{
218 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
219 const struct at91_pin_group *grp;
220 struct pinctrl_map *new_map;
221 struct device_node *parent;
222 int map_num = 1;
223 int i;
224 struct at91_pmx_pin *pin;
225
226 /*
227 * first find the group of this node and check if we need create
228 * config maps for pins
229 */
230 grp = at91_pinctrl_find_group_by_name(info, np->name);
231 if (!grp) {
232 dev_err(info->dev, "unable to find group for node %s\n",
233 np->name);
234 return -EINVAL;
235 }
236
237 map_num += grp->npins;
238 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
239 if (!new_map)
240 return -ENOMEM;
241
242 *map = new_map;
243 *num_maps = map_num;
244
245 /* create mux map */
246 parent = of_get_parent(np);
247 if (!parent) {
248 kfree(new_map);
249 return -EINVAL;
250 }
251 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
252 new_map[0].data.mux.function = parent->name;
253 new_map[0].data.mux.group = np->name;
254 of_node_put(parent);
255
256 /* create config map */
257 new_map++;
258 for (i = 0; i < grp->npins; i++) {
259 pin = &grp->pins_conf[i];
260
261 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
262 new_map[i].data.configs.group_or_pin =
263 pin_get_name(pctldev, grp->pins[i]);
264 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
265 new_map[i].data.configs.num_configs = 1;
266 }
267
268 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
269 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
270
271 return 0;
272}
273
274static void at91_dt_free_map(struct pinctrl_dev *pctldev,
275 struct pinctrl_map *map, unsigned num_maps)
276{
277}
278
279static struct pinctrl_ops at91_pctrl_ops = {
280 .get_groups_count = at91_get_groups_count,
281 .get_group_name = at91_get_group_name,
282 .get_group_pins = at91_get_group_pins,
283 .pin_dbg_show = at91_pin_dbg_show,
284 .dt_node_to_map = at91_dt_node_to_map,
285 .dt_free_map = at91_dt_free_map,
286};
287
288static void __iomem * pin_to_controller(struct at91_pinctrl *info,
289 unsigned int bank)
290{
291 return gpio_chips[bank]->regbase;
292}
293
294static inline int pin_to_bank(unsigned pin)
295{
296 return pin /= MAX_NB_GPIO_PER_BANK;
297}
298
299static unsigned pin_to_mask(unsigned int pin)
300{
301 return 1 << pin;
302}
303
304static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
305{
306 writel_relaxed(mask, pio + PIO_IDR);
307}
308
309static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
310{
311 return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1;
312}
313
314static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
315{
316 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
317}
318
319static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
320{
321 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
322}
323
324static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
325{
326 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
327}
328
329static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
330{
331 writel_relaxed(mask, pio + PIO_ASR);
332}
333
334static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
335{
336 writel_relaxed(mask, pio + PIO_BSR);
337}
338
339static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
340{
341
342 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
343 pio + PIO_ABCDSR1);
344 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
345 pio + PIO_ABCDSR2);
346}
347
348static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
349{
350 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
351 pio + PIO_ABCDSR1);
352 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
353 pio + PIO_ABCDSR2);
354}
355
356static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
357{
358 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
359 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
360}
361
362static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
363{
364 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
365 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
366}
367
368static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
369{
370 unsigned select;
371
372 if (readl_relaxed(pio + PIO_PSR) & mask)
373 return AT91_MUX_GPIO;
374
375 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
376 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
377
378 return select + 1;
379}
380
381static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
382{
383 unsigned select;
384
385 if (readl_relaxed(pio + PIO_PSR) & mask)
386 return AT91_MUX_GPIO;
387
388 select = readl_relaxed(pio + PIO_ABSR) & mask;
389
390 return select + 1;
391}
392
393static struct at91_pinctrl_mux_ops at91rm9200_ops = {
394 .get_periph = at91_mux_get_periph,
395 .mux_A_periph = at91_mux_set_A_periph,
396 .mux_B_periph = at91_mux_set_B_periph,
397 .irq_type = gpio_irq_type,
398};
399
400static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
401 .get_periph = at91_mux_pio3_get_periph,
402 .mux_A_periph = at91_mux_pio3_set_A_periph,
403 .mux_B_periph = at91_mux_pio3_set_B_periph,
404 .mux_C_periph = at91_mux_pio3_set_C_periph,
405 .mux_D_periph = at91_mux_pio3_set_D_periph,
406 .irq_type = alt_gpio_irq_type,
407};
408
409static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
410{
411 if (pin->mux) {
412 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
413 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
414 } else {
415 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
416 pin->bank + 'A', pin->pin, pin->conf);
417 }
418}
419
420static int pin_check_config(struct at91_pinctrl *info, const char* name,
421 int index, const struct at91_pmx_pin *pin)
422{
423 int mux;
424
425 /* check if it's a valid config */
426 if (pin->bank >= info->nbanks) {
427 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
428 name, index, pin->bank, info->nbanks);
429 return -EINVAL;
430 }
431
432 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
433 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
434 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
435 return -EINVAL;
436 }
437
438 if (!pin->mux)
439 return 0;
440
441 mux = pin->mux - 1;
442
443 if (mux >= info->nmux) {
444 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
445 name, index, mux, info->nmux);
446 return -EINVAL;
447 }
448
449 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
450 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
451 name, index, mux, pin->bank + 'A', pin->pin);
452 return -EINVAL;
453 }
454
455 return 0;
456}
457
458static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
459{
460 writel_relaxed(mask, pio + PIO_PDR);
461}
462
463static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
464{
465 writel_relaxed(mask, pio + PIO_PER);
466 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
467}
468
469static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
470 unsigned group)
471{
472 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
473 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
474 const struct at91_pmx_pin *pin;
475 uint32_t npins = info->groups[group].npins;
476 int i, ret;
477 unsigned mask;
478 void __iomem *pio;
479
480 dev_dbg(info->dev, "enable function %s group %s\n",
481 info->functions[selector].name, info->groups[group].name);
482
483 /* first check that all the pins of the group are valid with a valid
484 * paramter */
485 for (i = 0; i < npins; i++) {
486 pin = &pins_conf[i];
487 ret = pin_check_config(info, info->groups[group].name, i, pin);
488 if (ret)
489 return ret;
490 }
491
492 for (i = 0; i < npins; i++) {
493 pin = &pins_conf[i];
494 at91_pin_dbg(info->dev, pin);
495 pio = pin_to_controller(info, pin->bank);
496 mask = pin_to_mask(pin->pin);
497 at91_mux_disable_interrupt(pio, mask);
498 switch(pin->mux) {
499 case AT91_MUX_GPIO:
500 at91_mux_gpio_enable(pio, mask, 1);
501 break;
502 case AT91_MUX_PERIPH_A:
503 info->ops->mux_A_periph(pio, mask);
504 break;
505 case AT91_MUX_PERIPH_B:
506 info->ops->mux_B_periph(pio, mask);
507 break;
508 case AT91_MUX_PERIPH_C:
509 if (!info->ops->mux_C_periph)
510 return -EINVAL;
511 info->ops->mux_C_periph(pio, mask);
512 break;
513 case AT91_MUX_PERIPH_D:
514 if (!info->ops->mux_D_periph)
515 return -EINVAL;
516 info->ops->mux_D_periph(pio, mask);
517 break;
518 }
519 if (pin->mux)
520 at91_mux_gpio_disable(pio, mask);
521 }
522
523 return 0;
524}
525
526static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
527 unsigned group)
528{
529 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
530 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
531 const struct at91_pmx_pin *pin;
532 uint32_t npins = info->groups[group].npins;
533 int i;
534 unsigned mask;
535 void __iomem *pio;
536
537 for (i = 0; i < npins; i++) {
538 pin = &pins_conf[i];
539 at91_pin_dbg(info->dev, pin);
540 pio = pin_to_controller(info, pin->bank);
541 mask = pin_to_mask(pin->pin);
542 at91_mux_gpio_enable(pio, mask, 1);
543 }
544}
545
546static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
547{
548 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
549
550 return info->nfunctions;
551}
552
553static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
554 unsigned selector)
555{
556 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
557
558 return info->functions[selector].name;
559}
560
561static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
562 const char * const **groups,
563 unsigned * const num_groups)
564{
565 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
566
567 *groups = info->functions[selector].groups;
568 *num_groups = info->functions[selector].ngroups;
569
570 return 0;
571}
572
573int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
574 struct pinctrl_gpio_range *range,
575 unsigned offset)
576{
577 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
578 struct at91_gpio_chip *at91_chip;
579 struct gpio_chip *chip;
580 unsigned mask;
581
582 if (!range) {
583 dev_err(npct->dev, "invalid range\n");
584 return -EINVAL;
585 }
586 if (!range->gc) {
587 dev_err(npct->dev, "missing GPIO chip in range\n");
588 return -EINVAL;
589 }
590 chip = range->gc;
591 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
592
593 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
594
595 mask = 1 << (offset - chip->base);
596
597 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
598 offset, 'A' + range->id, offset - chip->base, mask);
599
600 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
601
602 return 0;
603}
604
605void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
606 struct pinctrl_gpio_range *range,
607 unsigned offset)
608{
609 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
610
611 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
612 /* Set the pin to some default state, GPIO is usually default */
613}
614
615static struct pinmux_ops at91_pmx_ops = {
616 .get_functions_count = at91_pmx_get_funcs_count,
617 .get_function_name = at91_pmx_get_func_name,
618 .get_function_groups = at91_pmx_get_groups,
619 .enable = at91_pmx_enable,
620 .disable = at91_pmx_disable,
621 .gpio_request_enable = at91_gpio_request_enable,
622 .gpio_disable_free = at91_gpio_disable_free,
623};
624
625static int at91_pinconf_get(struct pinctrl_dev *pctldev,
626 unsigned pin_id, unsigned long *config)
627{
628 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
629 void __iomem *pio;
630 unsigned pin;
631
632 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config);
633 pio = pin_to_controller(info, pin_to_bank(pin_id));
634 pin = pin_id % MAX_NB_GPIO_PER_BANK;
635
636 if (at91_mux_get_multidrive(pio, pin))
637 *config |= MULTI_DRIVE;
638
639 if (at91_mux_get_pullup(pio, pin))
640 *config |= PULL_UP;
641
642 return 0;
643}
644
645static int at91_pinconf_set(struct pinctrl_dev *pctldev,
646 unsigned pin_id, unsigned long config)
647{
648 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
649 unsigned mask;
650 void __iomem *pio;
651
652 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config);
653 pio = pin_to_controller(info, pin_to_bank(pin_id));
654 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
655
656 at91_mux_set_pullup(pio, mask, config & PULL_UP);
657 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
658 return 0;
659}
660
661static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
662 struct seq_file *s, unsigned pin_id)
663{
664
665}
666
667static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
668 struct seq_file *s, unsigned group)
669{
670}
671
672struct pinconf_ops at91_pinconf_ops = {
673 .pin_config_get = at91_pinconf_get,
674 .pin_config_set = at91_pinconf_set,
675 .pin_config_dbg_show = at91_pinconf_dbg_show,
676 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
677};
678
679static struct pinctrl_desc at91_pinctrl_desc = {
680 .pctlops = &at91_pctrl_ops,
681 .pmxops = &at91_pmx_ops,
682 .confops = &at91_pinconf_ops,
683 .owner = THIS_MODULE,
684};
685
686static const char *gpio_compat = "atmel,at91rm9200-gpio";
687
688static void __devinit at91_pinctrl_child_count(struct at91_pinctrl *info,
689 struct device_node *np)
690{
691 struct device_node *child;
692
693 for_each_child_of_node(np, child) {
694 if (of_device_is_compatible(child, gpio_compat)) {
695 info->nbanks++;
696 } else {
697 info->nfunctions++;
698 info->ngroups += of_get_child_count(child);
699 }
700 }
701}
702
703static int __devinit at91_pinctrl_mux_mask(struct at91_pinctrl *info,
704 struct device_node *np)
705{
706 int ret = 0;
707 int size;
708 const const __be32 *list;
709
710 list = of_get_property(np, "atmel,mux-mask", &size);
711 if (!list) {
712 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
713 return -EINVAL;
714 }
715
716 size /= sizeof(*list);
717 if (!size || size % info->nbanks) {
718 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
719 return -EINVAL;
720 }
721 info->nmux = size / info->nbanks;
722
723 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
724 if (!info->mux_mask) {
725 dev_err(info->dev, "could not alloc mux_mask\n");
726 return -ENOMEM;
727 }
728
729 ret = of_property_read_u32_array(np, "atmel,mux-mask",
730 info->mux_mask, size);
731 if (ret)
732 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
733 return ret;
734}
735
736static int __devinit at91_pinctrl_parse_groups(struct device_node *np,
737 struct at91_pin_group *grp,
738 struct at91_pinctrl *info,
739 u32 index)
740{
741 struct at91_pmx_pin *pin;
742 int size;
743 const const __be32 *list;
744 int i, j;
745
746 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
747
748 /* Initialise group */
749 grp->name = np->name;
750
751 /*
752 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
753 * do sanity check and calculate pins number
754 */
755 list = of_get_property(np, "atmel,pins", &size);
756 /* we do not check return since it's safe node passed down */
757 size /= sizeof(*list);
758 if (!size || size % 4) {
759 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
760 return -EINVAL;
761 }
762
763 grp->npins = size / 4;
764 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
765 GFP_KERNEL);
766 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
767 GFP_KERNEL);
768 if (!grp->pins_conf || !grp->pins)
769 return -ENOMEM;
770
771 for (i = 0, j = 0; i < size; i += 4, j++) {
772 pin->bank = be32_to_cpu(*list++);
773 pin->pin = be32_to_cpu(*list++);
774 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
775 pin->mux = be32_to_cpu(*list++);
776 pin->conf = be32_to_cpu(*list++);
777
778 at91_pin_dbg(info->dev, pin);
779 pin++;
780 }
781
782 return 0;
783}
784
785static int __devinit at91_pinctrl_parse_functions(struct device_node *np,
786 struct at91_pinctrl *info, u32 index)
787{
788 struct device_node *child;
789 struct at91_pmx_func *func;
790 struct at91_pin_group *grp;
791 int ret;
792 static u32 grp_index;
793 u32 i = 0;
794
795 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
796
797 func = &info->functions[index];
798
799 /* Initialise function */
800 func->name = np->name;
801 func->ngroups = of_get_child_count(np);
802 if (func->ngroups <= 0) {
803 dev_err(info->dev, "no groups defined\n");
804 return -EINVAL;
805 }
806 func->groups = devm_kzalloc(info->dev,
807 func->ngroups * sizeof(char *), GFP_KERNEL);
808 if (!func->groups)
809 return -ENOMEM;
810
811 for_each_child_of_node(np, child) {
812 func->groups[i] = child->name;
813 grp = &info->groups[grp_index++];
814 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
815 if (ret)
816 return ret;
817 }
818
819 return 0;
820}
821
822static struct of_device_id at91_pinctrl_of_match[] __devinitdata = {
823 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
824 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
825 { /* sentinel */ }
826};
827
828static int __devinit at91_pinctrl_probe_dt(struct platform_device *pdev,
829 struct at91_pinctrl *info)
830{
831 int ret = 0;
832 int i, j;
833 uint32_t *tmp;
834 struct device_node *np = pdev->dev.of_node;
835 struct device_node *child;
836
837 if (!np)
838 return -ENODEV;
839
840 info->dev = &pdev->dev;
841 info->ops =
842 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
843 at91_pinctrl_child_count(info, np);
844
845 if (info->nbanks < 1) {
846 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
847 return -EINVAL;
848 }
849
850 ret = at91_pinctrl_mux_mask(info, np);
851 if (ret)
852 return ret;
853
854 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
855
856 dev_dbg(&pdev->dev, "mux-mask\n");
857 tmp = info->mux_mask;
858 for (i = 0; i < info->nbanks; i++) {
859 for (j = 0; j < info->nmux; j++, tmp++) {
860 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
861 }
862 }
863
864 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
865 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
866 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
867 GFP_KERNEL);
868 if (!info->functions)
869 return -ENOMEM;
870
871 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
872 GFP_KERNEL);
873 if (!info->groups)
874 return -ENOMEM;
875
876 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
877 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
878 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
879
880 i = 0;
881
882 for_each_child_of_node(np, child) {
883 if (of_device_is_compatible(child, gpio_compat))
884 continue;
885 ret = at91_pinctrl_parse_functions(child, info, i++);
886 if (ret) {
887 dev_err(&pdev->dev, "failed to parse function\n");
888 return ret;
889 }
890 }
891
892 return 0;
893}
894
895static int __devinit at91_pinctrl_probe(struct platform_device *pdev)
896{
897 struct at91_pinctrl *info;
898 struct pinctrl_pin_desc *pdesc;
899 int ret, i, j ,k;
900
901 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
902 if (!info)
903 return -ENOMEM;
904
905 ret = at91_pinctrl_probe_dt(pdev, info);
906 if (ret)
907 return ret;
908
909 /*
910 * We need all the GPIO drivers to probe FIRST, or we will not be able
911 * to obtain references to the struct gpio_chip * for them, and we
912 * need this to proceed.
913 */
914 for (i = 0; i < info->nbanks; i++) {
915 if (!gpio_chips[i]) {
916 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
917 devm_kfree(&pdev->dev, info);
918 return -EPROBE_DEFER;
919 }
920 }
921
922 at91_pinctrl_desc.name = dev_name(&pdev->dev);
923 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
924 at91_pinctrl_desc.pins = pdesc =
925 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
926
927 if (!at91_pinctrl_desc.pins)
928 return -ENOMEM;
929
930 for (i = 0 , k = 0; i < info->nbanks; i++) {
931 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
932 pdesc->number = k;
933 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
934 pdesc++;
935 }
936 }
937
938 platform_set_drvdata(pdev, info);
939 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
940
941 if (!info->pctl) {
942 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
943 ret = -EINVAL;
944 goto err;
945 }
946
947 /* We will handle a range of GPIO pins */
948 for (i = 0; i < info->nbanks; i++)
949 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
950
951 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
952
953 return 0;
954
955err:
956 return ret;
957}
958
959int __devexit at91_pinctrl_remove(struct platform_device *pdev)
960{
961 struct at91_pinctrl *info = platform_get_drvdata(pdev);
962
963 pinctrl_unregister(info->pctl);
964
965 return 0;
966}
967
968static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
969{
970 /*
971 * Map back to global GPIO space and request muxing, the direction
972 * parameter does not matter for this controller.
973 */
974 int gpio = chip->base + offset;
975 int bank = chip->base / chip->ngpio;
976
977 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
978 'A' + bank, offset, gpio);
979
980 return pinctrl_request_gpio(gpio);
981}
982
983static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
984{
985 int gpio = chip->base + offset;
986
987 pinctrl_free_gpio(gpio);
988}
989
990static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
991{
992 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
993 void __iomem *pio = at91_gpio->regbase;
994 unsigned mask = 1 << offset;
995
996 writel_relaxed(mask, pio + PIO_ODR);
997 return 0;
998}
999
1000static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1001{
1002 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1003 void __iomem *pio = at91_gpio->regbase;
1004 unsigned mask = 1 << offset;
1005 u32 pdsr;
1006
1007 pdsr = readl_relaxed(pio + PIO_PDSR);
1008 return (pdsr & mask) != 0;
1009}
1010
1011static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1012 int val)
1013{
1014 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1015 void __iomem *pio = at91_gpio->regbase;
1016 unsigned mask = 1 << offset;
1017
1018 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1019}
1020
1021static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1022 int val)
1023{
1024 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1025 void __iomem *pio = at91_gpio->regbase;
1026 unsigned mask = 1 << offset;
1027
1028 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1029 writel_relaxed(mask, pio + PIO_OER);
1030
1031 return 0;
1032}
1033
1034static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1035{
1036 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1037 int virq;
1038
1039 if (offset < chip->ngpio)
1040 virq = irq_create_mapping(at91_gpio->domain, offset);
1041 else
1042 virq = -ENXIO;
1043
1044 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1045 chip->label, offset + chip->base, virq);
1046 return virq;
1047}
1048
1049#ifdef CONFIG_DEBUG_FS
1050static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1051{
1052 enum at91_mux mode;
1053 int i;
1054 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1055 void __iomem *pio = at91_gpio->regbase;
1056
1057 for (i = 0; i < chip->ngpio; i++) {
1058 unsigned pin = chip->base + i;
1059 unsigned mask = pin_to_mask(pin);
1060 const char *gpio_label;
1061 u32 pdsr;
1062
1063 gpio_label = gpiochip_is_requested(chip, i);
1064 if (!gpio_label)
1065 continue;
1066 mode = at91_gpio->ops->get_periph(pio, mask);
1067 seq_printf(s, "[%s] GPIO%s%d: ",
1068 gpio_label, chip->label, i);
1069 if (mode == AT91_MUX_GPIO) {
1070 pdsr = readl_relaxed(pio + PIO_PDSR);
1071
1072 seq_printf(s, "[gpio] %s\n",
1073 pdsr & mask ?
1074 "set" : "clear");
1075 } else {
1076 seq_printf(s, "[periph %c]\n",
1077 mode + 'A' - 1);
1078 }
1079 }
1080}
1081#else
1082#define at91_gpio_dbg_show NULL
1083#endif
1084
1085/* Several AIC controller irqs are dispatched through this GPIO handler.
1086 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1087 * at91_set_gpio_input() then maybe enable its glitch filter.
1088 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1089 * handler.
1090 * First implementation always triggers on rising and falling edges
1091 * whereas the newer PIO3 can be additionally configured to trigger on
1092 * level, edge with any polarity.
1093 *
1094 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1095 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1096 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1097 */
1098
1099static void gpio_irq_mask(struct irq_data *d)
1100{
1101 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1102 void __iomem *pio = at91_gpio->regbase;
1103 unsigned mask = 1 << d->hwirq;
1104
1105 if (pio)
1106 writel_relaxed(mask, pio + PIO_IDR);
1107}
1108
1109static void gpio_irq_unmask(struct irq_data *d)
1110{
1111 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1112 void __iomem *pio = at91_gpio->regbase;
1113 unsigned mask = 1 << d->hwirq;
1114
1115 if (pio)
1116 writel_relaxed(mask, pio + PIO_IER);
1117}
1118
1119static int gpio_irq_type(struct irq_data *d, unsigned type)
1120{
1121 switch (type) {
1122 case IRQ_TYPE_NONE:
1123 case IRQ_TYPE_EDGE_BOTH:
1124 return 0;
1125 default:
1126 return -EINVAL;
1127 }
1128}
1129
1130/* Alternate irq type for PIO3 support */
1131static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1132{
1133 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1134 void __iomem *pio = at91_gpio->regbase;
1135 unsigned mask = 1 << d->hwirq;
1136
1137 switch (type) {
1138 case IRQ_TYPE_EDGE_RISING:
1139 writel_relaxed(mask, pio + PIO_ESR);
1140 writel_relaxed(mask, pio + PIO_REHLSR);
1141 break;
1142 case IRQ_TYPE_EDGE_FALLING:
1143 writel_relaxed(mask, pio + PIO_ESR);
1144 writel_relaxed(mask, pio + PIO_FELLSR);
1145 break;
1146 case IRQ_TYPE_LEVEL_LOW:
1147 writel_relaxed(mask, pio + PIO_LSR);
1148 writel_relaxed(mask, pio + PIO_FELLSR);
1149 break;
1150 case IRQ_TYPE_LEVEL_HIGH:
1151 writel_relaxed(mask, pio + PIO_LSR);
1152 writel_relaxed(mask, pio + PIO_REHLSR);
1153 break;
1154 case IRQ_TYPE_EDGE_BOTH:
1155 /*
1156 * disable additional interrupt modes:
1157 * fall back to default behavior
1158 */
1159 writel_relaxed(mask, pio + PIO_AIMDR);
1160 return 0;
1161 case IRQ_TYPE_NONE:
1162 default:
1163 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1164 return -EINVAL;
1165 }
1166
1167 /* enable additional interrupt modes */
1168 writel_relaxed(mask, pio + PIO_AIMER);
1169
1170 return 0;
1171}
1172
1173#ifdef CONFIG_PM
1174static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1175{
1176 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1177 unsigned bank = at91_gpio->pioc_idx;
1178
1179 if (unlikely(bank >= MAX_GPIO_BANKS))
1180 return -EINVAL;
1181
1182 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1183
1184 return 0;
1185}
1186#else
1187#define gpio_irq_set_wake NULL
1188#endif
1189
1190static struct irq_chip gpio_irqchip = {
1191 .name = "GPIO",
1192 .irq_disable = gpio_irq_mask,
1193 .irq_mask = gpio_irq_mask,
1194 .irq_unmask = gpio_irq_unmask,
1195 /* .irq_set_type is set dynamically */
1196 .irq_set_wake = gpio_irq_set_wake,
1197};
1198
1199static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1200{
1201 struct irq_chip *chip = irq_desc_get_chip(desc);
1202 struct irq_data *idata = irq_desc_get_irq_data(desc);
1203 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
1204 void __iomem *pio = at91_gpio->regbase;
1205 unsigned long isr;
1206 int n;
1207
1208 chained_irq_enter(chip, desc);
1209 for (;;) {
1210 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1211 * When there none are pending, we're finished unless we need
1212 * to process multiple banks (like ID_PIOCDE on sam9263).
1213 */
1214 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1215 if (!isr) {
1216 if (!at91_gpio->next)
1217 break;
1218 at91_gpio = at91_gpio->next;
1219 pio = at91_gpio->regbase;
1220 continue;
1221 }
1222
1223 n = find_first_bit(&isr, BITS_PER_LONG);
1224 while (n < BITS_PER_LONG) {
1225 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
1226 n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
1227 }
1228 }
1229 chained_irq_exit(chip, desc);
1230 /* now it may re-trigger */
1231}
1232
1233/*
1234 * This lock class tells lockdep that GPIO irqs are in a different
1235 * category than their parents, so it won't report false recursion.
1236 */
1237static struct lock_class_key gpio_lock_class;
1238
1239static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1240 irq_hw_number_t hw)
1241{
1242 struct at91_gpio_chip *at91_gpio = h->host_data;
1243
1244 irq_set_lockdep_class(virq, &gpio_lock_class);
1245
1246 /*
1247 * Can use the "simple" and not "edge" handler since it's
1248 * shorter, and the AIC handles interrupts sanely.
1249 */
1250 irq_set_chip_and_handler(virq, &gpio_irqchip,
1251 handle_simple_irq);
1252 set_irq_flags(virq, IRQF_VALID);
1253 irq_set_chip_data(virq, at91_gpio);
1254
1255 return 0;
1256}
1257
1258static struct irq_domain_ops at91_gpio_ops = {
1259 .map = at91_gpio_irq_map,
1260 .xlate = irq_domain_xlate_twocell,
1261};
1262
1263static int at91_gpio_of_irq_setup(struct device_node *node,
1264 struct at91_gpio_chip *at91_gpio)
1265{
1266 struct at91_gpio_chip *prev = NULL;
1267 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1268
1269 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1270
1271 /* Setup proper .irq_set_type function */
1272 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1273
1274 /* Disable irqs of this PIO controller */
1275 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1276
1277 /* Setup irq domain */
1278 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
1279 &at91_gpio_ops, at91_gpio);
1280 if (!at91_gpio->domain)
1281 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1282 at91_gpio->pioc_idx);
1283
1284 /* Setup chained handler */
1285 if (at91_gpio->pioc_idx)
1286 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1287
1288 /* The toplevel handler handles one bank of GPIOs, except
1289 * on some SoC it can handles up to three...
1290 * We only set up the handler for the first of the list.
1291 */
1292 if (prev && prev->next == at91_gpio)
1293 return 0;
1294
1295 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
1296 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
1297
1298 return 0;
1299}
1300
1301/* This structure is replicated for each GPIO block allocated at probe time */
1302static struct gpio_chip at91_gpio_template = {
1303 .request = at91_gpio_request,
1304 .free = at91_gpio_free,
1305 .direction_input = at91_gpio_direction_input,
1306 .get = at91_gpio_get,
1307 .direction_output = at91_gpio_direction_output,
1308 .set = at91_gpio_set,
1309 .to_irq = at91_gpio_to_irq,
1310 .dbg_show = at91_gpio_dbg_show,
1311 .can_sleep = 0,
1312 .ngpio = MAX_NB_GPIO_PER_BANK,
1313};
1314
1315static void __devinit at91_gpio_probe_fixup(void)
1316{
1317 unsigned i;
1318 struct at91_gpio_chip *at91_gpio, *last = NULL;
1319
1320 for (i = 0; i < gpio_banks; i++) {
1321 at91_gpio = gpio_chips[i];
1322
1323 /*
1324 * GPIO controller are grouped on some SoC:
1325 * PIOC, PIOD and PIOE can share the same IRQ line
1326 */
1327 if (last && last->pioc_virq == at91_gpio->pioc_virq)
1328 last->next = at91_gpio;
1329 last = at91_gpio;
1330 }
1331}
1332
1333static struct of_device_id at91_gpio_of_match[] __devinitdata = {
1334 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1335 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1336 { /* sentinel */ }
1337};
1338
1339static int __devinit at91_gpio_probe(struct platform_device *pdev)
1340{
1341 struct device_node *np = pdev->dev.of_node;
1342 struct resource *res;
1343 struct at91_gpio_chip *at91_chip = NULL;
1344 struct gpio_chip *chip;
1345 struct pinctrl_gpio_range *range;
1346 int ret = 0;
1347 int irq;
1348 int alias_idx = of_alias_get_id(np, "gpio");
1349 uint32_t ngpio;
1350
1351 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1352 if (gpio_chips[alias_idx]) {
1353 ret = -EBUSY;
1354 goto err;
1355 }
1356
1357 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1358 if (!res) {
1359 ret = -ENOENT;
1360 goto err;
1361 }
1362
1363 irq = platform_get_irq(pdev, 0);
1364 if (irq < 0) {
1365 ret = irq;
1366 goto err;
1367 }
1368
1369 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1370 if (!at91_chip) {
1371 ret = -ENOMEM;
1372 goto err;
1373 }
1374
1375 at91_chip->regbase = devm_request_and_ioremap(&pdev->dev, res);
1376 if (!at91_chip->regbase) {
1377 dev_err(&pdev->dev, "failed to map registers, ignoring.\n");
1378 ret = -EBUSY;
1379 goto err;
1380 }
1381
1382 at91_chip->ops =
1383 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1384 at91_chip->pioc_virq = irq;
1385 at91_chip->pioc_idx = alias_idx;
1386
1387 at91_chip->clock = clk_get(&pdev->dev, NULL);
1388 if (IS_ERR(at91_chip->clock)) {
1389 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1390 goto err;
1391 }
1392
1393 if (clk_prepare(at91_chip->clock))
1394 goto clk_prep_err;
1395
1396 /* enable PIO controller's clock */
1397 if (clk_enable(at91_chip->clock)) {
1398 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1399 goto clk_err;
1400 }
1401
1402 at91_chip->chip = at91_gpio_template;
1403
1404 chip = &at91_chip->chip;
1405 chip->of_node = np;
1406 chip->label = dev_name(&pdev->dev);
1407 chip->dev = &pdev->dev;
1408 chip->owner = THIS_MODULE;
1409 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1410
1411 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1412 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1413 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1414 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1415 else
1416 chip->ngpio = ngpio;
1417 }
1418
1419 range = &at91_chip->range;
1420 range->name = chip->label;
1421 range->id = alias_idx;
1422 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1423
1424 range->npins = chip->ngpio;
1425 range->gc = chip;
1426
1427 ret = gpiochip_add(chip);
1428 if (ret)
1429 goto clk_err;
1430
1431 gpio_chips[alias_idx] = at91_chip;
1432 gpio_banks = max(gpio_banks, alias_idx + 1);
1433
1434 at91_gpio_probe_fixup();
1435
1436 at91_gpio_of_irq_setup(np, at91_chip);
1437
1438 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1439
1440 return 0;
1441
1442clk_err:
1443 clk_unprepare(at91_chip->clock);
1444clk_prep_err:
1445 clk_put(at91_chip->clock);
1446err:
1447 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1448
1449 return ret;
1450}
1451
1452static struct platform_driver at91_gpio_driver = {
1453 .driver = {
1454 .name = "gpio-at91",
1455 .owner = THIS_MODULE,
1456 .of_match_table = of_match_ptr(at91_gpio_of_match),
1457 },
1458 .probe = at91_gpio_probe,
1459};
1460
1461static struct platform_driver at91_pinctrl_driver = {
1462 .driver = {
1463 .name = "pinctrl-at91",
1464 .owner = THIS_MODULE,
1465 .of_match_table = of_match_ptr(at91_pinctrl_of_match),
1466 },
1467 .probe = at91_pinctrl_probe,
1468 .remove = __devexit_p(at91_pinctrl_remove),
1469};
1470
1471static int __init at91_pinctrl_init(void)
1472{
1473 int ret;
1474
1475 ret = platform_driver_register(&at91_gpio_driver);
1476 if (ret)
1477 return ret;
1478 return platform_driver_register(&at91_pinctrl_driver);
1479}
1480arch_initcall(at91_pinctrl_init);
1481
1482static void __exit at91_pinctrl_exit(void)
1483{
1484 platform_driver_unregister(&at91_pinctrl_driver);
1485}
1486
1487module_exit(at91_pinctrl_exit);
1488MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1489MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1490MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 3d7e1ee2fa57..65f891be12d1 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -39,6 +39,7 @@
39#include <linux/atmel_pdc.h> 39#include <linux/atmel_pdc.h>
40#include <linux/atmel_serial.h> 40#include <linux/atmel_serial.h>
41#include <linux/uaccess.h> 41#include <linux/uaccess.h>
42#include <linux/pinctrl/consumer.h>
42 43
43#include <asm/io.h> 44#include <asm/io.h>
44#include <asm/ioctls.h> 45#include <asm/ioctls.h>
@@ -1773,6 +1774,7 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev)
1773 struct atmel_uart_data *pdata = pdev->dev.platform_data; 1774 struct atmel_uart_data *pdata = pdev->dev.platform_data;
1774 void *data; 1775 void *data;
1775 int ret = -ENODEV; 1776 int ret = -ENODEV;
1777 struct pinctrl *pinctrl;
1776 1778
1777 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 1779 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1778 1780
@@ -1805,6 +1807,12 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev)
1805 1807
1806 atmel_init_port(port, pdev); 1808 atmel_init_port(port, pdev);
1807 1809
1810 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1811 if (IS_ERR(pinctrl)) {
1812 ret = PTR_ERR(pinctrl);
1813 goto err;
1814 }
1815
1808 if (!atmel_use_dma_rx(&port->uart)) { 1816 if (!atmel_use_dma_rx(&port->uart)) {
1809 ret = -ENOMEM; 1817 ret = -ENOMEM;
1810 data = kmalloc(sizeof(struct atmel_uart_char) 1818 data = kmalloc(sizeof(struct atmel_uart_char)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 06:43:59 -0500